| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,Flow_completed,0h6m41s,0h2m46s,5652.173913043478,0.46,2826.086956521739,5,561.93,1300,0,0,0,0,0,0,0,8,0,0,0,561231,17243,0.0,0.0,0.0,0.0,-0.22,0.0,0.0,0.0,0.0,-0.4,511843016,0.0,47.22,10.06,35.71,0.16,-1,1054,1627,210,783,0,0,0,1300,247,0,75,14,115,0,0,181,436,422,10,130,5454,0,5584,97.84735812133071,10.22,10,AREA 0,4,50,1,50,153.18,0.32,0,sky130_fd_sc_hd,4,4 |
