| #BUS_SORT |
| |
| #MANUAL_PLACE |
| #E |
| cpu_clk 0000 0 |
| rtc_clk 0000 1 |
| cpu_rst_n 0000 2 |
| irq_lines\[15\] 0000 3 |
| irq_lines\[14\] 0000 4 |
| irq_lines\[13\] 0000 5 |
| irq_lines\[12\] 0000 6 |
| irq_lines\[11\] 0000 7 |
| irq_lines\[10\] 0000 8 |
| irq_lines\[9\] 0000 9 |
| irq_lines\[8\] 0000 10 |
| irq_lines\[7\] 0000 11 |
| irq_lines\[6\] 0000 12 |
| irq_lines\[5\] 0000 13 |
| irq_lines\[4\] 0000 14 |
| irq_lines\[3\] 0000 15 |
| irq_lines\[2\] 0000 16 |
| irq_lines\[1\] 0000 17 |
| irq_lines\[0\] 0000 18 |
| soft_irq 0000 19 |
| fuse_mhartid\[31\] 0000 20 |
| fuse_mhartid\[30\] 0000 21 |
| fuse_mhartid\[29\] 0000 22 |
| fuse_mhartid\[28\] 0000 23 |
| fuse_mhartid\[27\] 0000 24 |
| fuse_mhartid\[26\] 0000 25 |
| fuse_mhartid\[25\] 0000 26 |
| fuse_mhartid\[24\] 0000 27 |
| fuse_mhartid\[23\] 0000 28 |
| fuse_mhartid\[22\] 0000 29 |
| fuse_mhartid\[21\] 0000 30 |
| fuse_mhartid\[20\] 0000 31 |
| fuse_mhartid\[19\] 0000 32 |
| fuse_mhartid\[18\] 0000 33 |
| fuse_mhartid\[17\] 0000 34 |
| fuse_mhartid\[16\] 0000 35 |
| fuse_mhartid\[15\] 0000 36 |
| fuse_mhartid\[14\] 0000 37 |
| fuse_mhartid\[13\] 0000 38 |
| fuse_mhartid\[12\] 0000 39 |
| fuse_mhartid\[11\] 0000 40 |
| fuse_mhartid\[10\] 0000 41 |
| fuse_mhartid\[9\] 0000 42 |
| fuse_mhartid\[8\] 0000 43 |
| fuse_mhartid\[7\] 0000 44 |
| fuse_mhartid\[6\] 0000 45 |
| fuse_mhartid\[5\] 0000 46 |
| fuse_mhartid\[4\] 0000 47 |
| fuse_mhartid\[3\] 0000 48 |
| fuse_mhartid\[2\] 0000 49 |
| fuse_mhartid\[1\] 0000 50 |
| fuse_mhartid\[0\] 0000 51 |
| |
| #N |
| mclk 0000 0 |
| reset_n 0000 1 |
| user_clock2 0000 2 |
| spi_rst_n 0000 3 |
| user_irq\[2\] 0000 4 |
| user_irq\[1\] 0000 5 |
| user_irq\[0\] 0000 6 |
| device_idcode\[31\] 0000 7 |
| device_idcode\[30\] 0000 8 |
| device_idcode\[29\] 0000 9 |
| device_idcode\[28\] 0000 10 |
| device_idcode\[27\] 0000 11 |
| device_idcode\[26\] 0000 12 |
| device_idcode\[25\] 0000 13 |
| device_idcode\[24\] 0000 14 |
| device_idcode\[23\] 0000 15 |
| device_idcode\[22\] 0000 16 |
| device_idcode\[21\] 0000 17 |
| device_idcode\[20\] 0000 18 |
| device_idcode\[19\] 0000 19 |
| device_idcode\[18\] 0000 20 |
| device_idcode\[17\] 0000 21 |
| device_idcode\[16\] 0000 22 |
| device_idcode\[15\] 0000 23 |
| device_idcode\[14\] 0000 24 |
| device_idcode\[13\] 0000 25 |
| device_idcode\[12\] 0000 26 |
| device_idcode\[11\] 0000 27 |
| device_idcode\[10\] 0000 28 |
| device_idcode\[9\] 0000 29 |
| device_idcode\[8\] 0000 30 |
| device_idcode\[7\] 0000 31 |
| device_idcode\[6\] 0000 32 |
| device_idcode\[5\] 0000 33 |
| device_idcode\[4\] 0000 34 |
| device_idcode\[3\] 0000 35 |
| device_idcode\[2\] 0000 36 |
| device_idcode\[1\] 0000 37 |
| device_idcode\[0\] 0000 38 |
| |
| #W |
| sdram_clk 0000 0 |
| sdram_rst_n 0000 1 |
| sdr_init_done 0000 2 |
| cfg_sdr_width\[1] 0000 3 |
| cfg_sdr_width\[0] 0000 4 |
| cfg_colbits\[1\] 0000 5 |
| cfg_colbits\[0\] 0000 6 |
| cfg_sdr_tras_d\[3\] 0000 7 |
| cfg_sdr_tras_d\[2\] 0000 8 |
| cfg_sdr_tras_d\[1\] 0000 9 |
| cfg_sdr_tras_d\[0\] 0000 10 |
| cfg_sdr_trp_d\[3\] 0000 11 |
| cfg_sdr_trp_d\[2\] 0000 12 |
| cfg_sdr_trp_d\[1\] 0000 13 |
| cfg_sdr_trp_d\[0\] 0000 14 |
| cfg_sdr_trcd_d\[3\] 0000 15 |
| cfg_sdr_trcd_d\[2\] 0000 16 |
| cfg_sdr_trcd_d\[1\] 0000 17 |
| cfg_sdr_trcd_d\[0\] 0000 18 |
| cfg_sdr_en 0000 19 |
| cfg_req_depth\[1\] 0000 20 |
| cfg_req_depth\[0\] 0000 21 |
| cfg_sdr_mode_reg\[12\] 0000 22 |
| cfg_sdr_mode_reg\[11\] 0000 23 |
| cfg_sdr_mode_reg\[10\] 0000 24 |
| cfg_sdr_mode_reg\[9\] 0000 25 |
| cfg_sdr_mode_reg\[8\] 0000 26 |
| cfg_sdr_mode_reg\[7\] 0000 27 |
| cfg_sdr_mode_reg\[6\] 0000 28 |
| cfg_sdr_mode_reg\[5\] 0000 29 |
| cfg_sdr_mode_reg\[4\] 0000 30 |
| cfg_sdr_mode_reg\[3\] 0000 31 |
| cfg_sdr_mode_reg\[2\] 0000 32 |
| cfg_sdr_mode_reg\[1\] 0000 33 |
| cfg_sdr_mode_reg\[0\] 0000 34 |
| cfg_sdr_cas\[2\] 0000 35 |
| cfg_sdr_cas\[1\] 0000 36 |
| cfg_sdr_cas\[0\] 0000 37 |
| cfg_sdr_trcar_d\[3\] 0000 38 |
| cfg_sdr_trcar_d\[2\] 0000 39 |
| cfg_sdr_trcar_d\[1\] 0000 40 |
| cfg_sdr_trcar_d\[0\] 0000 41 |
| cfg_sdr_twr_d\[3\] 0000 42 |
| cfg_sdr_twr_d\[2\] 0000 43 |
| cfg_sdr_twr_d\[1\] 0000 44 |
| cfg_sdr_twr_d\[0\] 0000 45 |
| cfg_sdr_rfsh\[11\] 0000 46 |
| cfg_sdr_rfsh\[10\] 0000 47 |
| cfg_sdr_rfsh\[9\] 0000 48 |
| cfg_sdr_rfsh\[8\] 0000 49 |
| cfg_sdr_rfsh\[7\] 0000 50 |
| cfg_sdr_rfsh\[6\] 0000 51 |
| cfg_sdr_rfsh\[5\] 0000 52 |
| cfg_sdr_rfsh\[4\] 0000 53 |
| cfg_sdr_rfsh\[3\] 0000 54 |
| cfg_sdr_rfsh\[2\] 0000 55 |
| cfg_sdr_rfsh\[1\] 0000 56 |
| cfg_sdr_rfsh\[0\] 0000 57 |
| cfg_sdr_rfmax\[2\] 0000 58 |
| cfg_sdr_rfmax\[1\] 0000 59 |
| cfg_sdr_rfmax\[0\] 0000 60 |
| |
| |
| #S |
| reg_cs 0000 0 |
| reg_wr 0000 1 |
| reg_addr\[7\] 0000 2 |
| reg_addr\[6\] 0000 3 |
| reg_addr\[5\] 0000 4 |
| reg_addr\[4\] 0000 5 |
| reg_addr\[3\] 0000 6 |
| reg_addr\[2\] 0000 7 |
| reg_addr\[1\] 0000 8 |
| reg_addr\[0\] 0000 9 |
| reg_be\[3\] 0000 10 |
| reg_be\[2\] 0000 11 |
| reg_be\[1\] 0000 12 |
| reg_be\[0\] 0000 13 |
| reg_wdata\[31\] 0000 14 |
| reg_wdata\[30\] 0000 15 |
| reg_wdata\[29\] 0000 16 |
| reg_wdata\[28\] 0000 17 |
| reg_wdata\[27\] 0000 18 |
| reg_wdata\[26\] 0000 19 |
| reg_wdata\[25\] 0000 20 |
| reg_wdata\[24\] 0000 21 |
| reg_wdata\[23\] 0000 22 |
| reg_wdata\[22\] 0000 23 |
| reg_wdata\[21\] 0000 24 |
| reg_wdata\[20\] 0000 25 |
| reg_wdata\[19\] 0000 26 |
| reg_wdata\[18\] 0000 27 |
| reg_wdata\[17\] 0000 28 |
| reg_wdata\[16\] 0000 29 |
| reg_wdata\[15\] 0000 30 |
| reg_wdata\[14\] 0000 31 |
| reg_wdata\[13\] 0000 32 |
| reg_wdata\[12\] 0000 33 |
| reg_wdata\[11\] 0000 34 |
| reg_wdata\[10\] 0000 35 |
| reg_wdata\[9\] 0000 36 |
| reg_wdata\[8\] 0000 37 |
| reg_wdata\[7\] 0000 38 |
| reg_wdata\[6\] 0000 39 |
| reg_wdata\[5\] 0000 40 |
| reg_wdata\[4\] 0000 41 |
| reg_wdata\[3\] 0000 42 |
| reg_wdata\[2\] 0000 43 |
| reg_wdata\[1\] 0000 44 |
| reg_wdata\[0\] 0000 45 |
| reg_rdata\[31\] 0000 46 |
| reg_rdata\[30\] 0000 47 |
| reg_rdata\[29\] 0000 48 |
| reg_rdata\[28\] 0000 49 |
| reg_rdata\[27\] 0000 50 |
| reg_rdata\[26\] 0000 51 |
| reg_rdata\[25\] 0000 52 |
| reg_rdata\[24\] 0000 53 |
| reg_rdata\[23\] 0000 54 |
| reg_rdata\[22\] 0000 55 |
| reg_rdata\[21\] 0000 56 |
| reg_rdata\[20\] 0000 57 |
| reg_rdata\[19\] 0000 58 |
| reg_rdata\[18\] 0000 59 |
| reg_rdata\[17\] 0000 60 |
| reg_rdata\[16\] 0000 61 |
| reg_rdata\[15\] 0000 62 |
| reg_rdata\[14\] 0000 63 |
| reg_rdata\[13\] 0000 64 |
| reg_rdata\[12\] 0000 65 |
| reg_rdata\[11\] 0000 66 |
| reg_rdata\[10\] 0000 67 |
| reg_rdata\[9\] 0000 68 |
| reg_rdata\[8\] 0000 69 |
| reg_rdata\[7\] 0000 70 |
| reg_rdata\[6\] 0000 71 |
| reg_rdata\[5\] 0000 72 |
| reg_rdata\[4\] 0000 73 |
| reg_rdata\[3\] 0000 74 |
| reg_rdata\[2\] 0000 75 |
| reg_rdata\[1\] 0000 76 |
| reg_rdata\[0\] 0000 77 |
| reg_ack 0000 78 |
