final gds & signoff results
diff --git a/checks/erase_box_user_analog_project_wrapper.gds.log b/checks/erase_box_user_analog_project_wrapper.gds.log
new file mode 100644
index 0000000..c6ec0d7
--- /dev/null
+++ b/checks/erase_box_user_analog_project_wrapper.gds.log
@@ -0,0 +1,50 @@
+/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/gds//user_analog_project_wrapper.gds /mnt/shuttles/mpw-two/slot-006/opencryo_testchip/checks/user_analog_project_wrapper_erased.gds user_analog_project_wrapper
+
+Magic 8.3 revision 182 - Compiled on Thu Jun 24 20:18:20 UTC 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Using technology "sky130A", version 1.0.192-0-gfa1b3ad
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+CIF input style is now "sky130(vendor)"
+Warning: Calma reading is not undoable! I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_analog_project_wrapper
+Reading "char".
+Reading "inv".
+Reading "ringosc".
+Reading "indVCO".
+Reading "user_analog_project_wrapper".
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 42.88 x 3520.00 (-42.88, 0.00 ), ( 0.00, 3520.00) 150937.59
+lambda: 4288.00 x 352000.00 (-4288.00, 0.00 ), ( 0.00, 352000.00) 1509376000.00
+internal: 8576 x 704000 ( -8576, 0 ), ( 0, 704000) 6037504000
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 42.50 x 3520.00 ( 2920.00, 0.00 ), ( 2962.50, 3520.00) 149600.00
+lambda: 4250.00 x 352000.00 ( 292000.00, 0.00 ), ( 296250.00, 352000.00) 1496000000.00
+internal: 8500 x 704000 ( 584000, 0 ), ( 592500, 704000) 5984000000
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3005.38 x 37.53 (-42.88, -37.53), ( 2962.50, 0.00 ) 112791.91
+lambda: 300538.00 x 3753.00 (-4288.00, -3753.00), ( 296250.00, 0.00 ) 1127919104.00
+internal: 601076 x 7506 ( -8576, -7506 ), ( 592500, 0 ) 4511676456
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3005.38 x 37.21 (-42.88, 3520.00), ( 2962.50, 3557.21) 111830.19
+lambda: 300538.00 x 3721.00 (-4288.00, 352000.00), ( 296250.00, 355721.00) 1118301952.00
+internal: 601076 x 7442 ( -8576, 704000), ( 592500, 711442) 4473207592
+can't read "errorCode": no such variable
+ Generating output for cell xor_target
+/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/checks/user_analog_project_wrapper_erased.gds
diff --git a/checks/erase_box_user_analog_project_wrapper_empty.gds.log b/checks/erase_box_user_analog_project_wrapper_empty.gds.log
new file mode 100644
index 0000000..c927a14
--- /dev/null
+++ b/checks/erase_box_user_analog_project_wrapper_empty.gds.log
@@ -0,0 +1,46 @@
+/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/checks/user_analog_project_wrapper_empty.gds /mnt/shuttles/mpw-two/slot-006/opencryo_testchip/checks/user_analog_project_wrapper_empty_erased.gds user_analog_project_wrapper
+
+Magic 8.3 revision 182 - Compiled on Thu Jun 24 20:18:20 UTC 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Using technology "sky130A", version 1.0.192-0-gfa1b3ad
+Input style sky130(vendor): scaleFactor=2, multiplier=2
+CIF input style is now "sky130(vendor)"
+Warning: Calma reading is not undoable! I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_analog_project_wrapper
+Reading "user_analog_project_wrapper".
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 42.88 x 3520.00 (-42.88, 0.00 ), ( 0.00, 3520.00) 150937.59
+lambda: 4288.00 x 352000.00 (-4288.00, 0.00 ), ( 0.00, 352000.00) 1509376000.00
+internal: 8576 x 704000 ( -8576, 0 ), ( 0, 704000) 6037504000
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 42.50 x 3520.00 ( 2920.00, 0.00 ), ( 2962.50, 3520.00) 149600.00
+lambda: 4250.00 x 352000.00 ( 292000.00, 0.00 ), ( 296250.00, 352000.00) 1496000000.00
+internal: 8500 x 704000 ( 584000, 0 ), ( 592500, 704000) 5984000000
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3005.38 x 37.53 (-42.88, -37.53), ( 2962.50, 0.00 ) 112791.91
+lambda: 300538.00 x 3753.00 (-4288.00, -3753.00), ( 296250.00, 0.00 ) 1127919104.00
+internal: 601076 x 7506 ( -8576, -7506 ), ( 592500, 0 ) 4511676456
+Root cell box:
+ width x height ( llx, lly ), ( urx, ury ) area (units^2)
+
+microns: 3005.38 x 37.21 (-42.88, 3520.00), ( 2962.50, 3557.21) 111830.19
+lambda: 300538.00 x 3721.00 (-4288.00, 352000.00), ( 296250.00, 355721.00) 1118301952.00
+internal: 601076 x 7442 ( -8576, 704000), ( 592500, 711442) 4473207592
+can't read "errorCode": no such variable
+ Generating output for cell xor_target
+/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/checks/user_analog_project_wrapper_empty_erased.gds
diff --git a/checks/full_log.log b/checks/full_log.log
new file mode 100644
index 0000000..013cb85
--- /dev/null
+++ b/checks/full_log.log
@@ -0,0 +1,60 @@
+FULL RUN LOG:
+ Executing Step 0 of 8: Extracting GDS Files
+Step 0 done without fatal errors.
+ Executing Step 1 of 8: Project License Check
+{{LICENSE COMPLIANCE PASSED}} Apache-2.0 LICENSE file was found in project root
+ SPDX COMPLIANCE Found 20 non-compliant files with the SPDX Standard. Check full log for more information
+SPDX COMPLIANCE: NON-COMPLIANT FILES PREVIEW: ['/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/README.md', '/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/xschem/example_por.sch', '/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/xschem/test.data', '/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/xschem/example_por_tb.spice.orig', '/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/xschem/user_analog_project_wrapper.sch', '/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/xschem/.spiceinit', '/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/xschem/user_analog_project_wrapper.sym', '/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/xschem/xschemrc', '/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/xschem/example_por_tb.sch', '/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/xschem/example_por.sym', '/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/xschem/analog_wrapper_tb.sch', '/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/signoff/kdrc_results_offgrid.xml.summary', '/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/signoff/kdrc_results_mr_fe.xml.summary', '/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/signoff/kdrc_results_fom.xml.summary', '/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/signoff/versions', '/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/signoff/kdrc_results_met.xml.summary', '/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/mag/compose_final.tcl', '/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/mag/generate_fill.tcl', '/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/mag/generate_fill_dist.tcl', '/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/mag/generate_fill_final.tcl']
+ Executing Step 2 of 8: YAML File Check
+ YAML file valid!
+Step 2 done without fatal errors.
+ Detected Project Type is "analog"
+ Executing Step 3 of 8: Project Compliance Checks
+b'Going into /mnt/shuttles/mpw-two/caravel'
+b'Removing manifest'
+b'Fetching manifest'
+b'Running sha1sum checks'
+ Manifest Checks Failed. Please rebase your Repository to the latest Caravel master.
+verilog/rtl/DFFRAM.v: FAILED
+verilog/rtl/DFFRAMBB.v: FAILED
+verilog/rtl/__user_project_wrapper.v: FAILED
+verilog/rtl/caravan.v: FAILED
+verilog/rtl/caravan_netlists.v: FAILED
+verilog/rtl/caravel.v: FAILED
+verilog/rtl/chip_io.v: FAILED
+verilog/rtl/chip_io_alt.v: FAILED
+verilog/rtl/gpio_control_block.v: FAILED
+verilog/rtl/housekeeping_spi.v: FAILED
+verilog/rtl/mem_wb.v: FAILED
+verilog/rtl/mgmt_core.v: FAILED
+verilog/rtl/mgmt_protect.v: FAILED
+verilog/rtl/mgmt_soc.v: FAILED
+verilog/rtl/mprj_ctrl.v: FAILED
+verilog/rtl/simple_spi_master.v: FAILED
+verilog/rtl/sram_1rw1r_32_256_8_sky130.v: FAILED
+verilog/rtl/storage.v: FAILED
+scripts/generate_fill.py: FAILED
+scripts/compositor.py: FAILED
+ Makefile Checks Passed.
+ Default config checks failed because:
+The parameter organization_url in info.yaml is default
+The parameter owner in info.yaml is default
+ Documentation Checks Passed.
+ Executing Step 4 of 8: XOR Consistency Checks
+ Running XOR Checks...
+Total XOR differences = 0
+ XOR Checks on User Project GDS Passed!
+Step 4 done without fatal errors.
+ Executing Step 5 of 8: DRC Violations Checks
+ Running Magic DRC Checks...
+ DRC Checks on User Project GDS Passed!
+Step 5 done without fatal errors.
+ Executing Step 6 of 8: KLayout DRC Violations Check
+ Running Klayout DRC Checks...
+ Klayout DRC Checks on User Project GDS Passed!
+Step 6 done without fatal errors.
+ Executing Klayout off grid check.
+ Klayout offgrid Checks on User Project GDS Passed!
+Step 7 done without fatal errors.
+ Klayout metal density Checks on GDS Failed, Check /mnt/shuttles/mpw-two/slot-006/opencryo_testchip/checks/met_density_check.xml
+ SOME Checks FAILED !!!
diff --git a/checks/klayout_drc.log b/checks/klayout_drc.log
new file mode 100644
index 0000000..1f80bf9
--- /dev/null
+++ b/checks/klayout_drc.log
@@ -0,0 +1,363 @@
+"_input" in: sky130A_mr.lydrc:88
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:89
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:90
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:91
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:92
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:93
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:94
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:95
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:96
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:97
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:98
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:99
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:100
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:101
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:102
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:103
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:104
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:105
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:106
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:107
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:108
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:110
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:111
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:113
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:114
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:116
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:117
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:119
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:120
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:122
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:123
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:125
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:127
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:128
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:129
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:130
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:131
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:132
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:133
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:134
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:135
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:136
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:137
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:138
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:139
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:140
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:141
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:142
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:143
+Elapsed: 0.010s
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+Elapsed: 0.000s
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+Elapsed: 0.010s
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+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:147
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:148
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+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:150
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:151
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:152
+Elapsed: 0.010s
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+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:154
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+"_input" in: sky130A_mr.lydrc:155
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:156
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+"_input" in: sky130A_mr.lydrc:157
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+"_input" in: sky130A_mr.lydrc:158
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+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:160
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+"_input" in: sky130A_mr.lydrc:162
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:163
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:164
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:165
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:166
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:167
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:168
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:169
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:170
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:171
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:172
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:173
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:174
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:175
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:176
+Elapsed: 0.010s
+"_input" in: sky130A_mr.lydrc:177
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:178
+Elapsed: 0.000s
+"_input" in: sky130A_mr.lydrc:179
+Elapsed: 0.010s
+{{ DRC section }}
+{{ FEOL section }}
+"&" in: sky130A_mr.lydrc:203
+Elapsed: 0.010s
+{{ dnwell }}
+"width_check" in: sky130A_mr.lydrc:207
+Elapsed: 0.000s
+"_output" in: sky130A_mr.lydrc:207
+Elapsed: 0.010s
+{{ nwell }}
+"width_check" in: sky130A_mr.lydrc:215
+Elapsed: 0.000s
+"_output" in: sky130A_mr.lydrc:215
+Elapsed: 0.010s
+"isolated_check" in: sky130A_mr.lydrc:216
+Elapsed: 0.000s
+"_output" in: sky130A_mr.lydrc:216
+Elapsed: 0.010s
+{{ hvtp }}
+"width_check" in: sky130A_mr.lydrc:235
+Elapsed: 0.000s
+"_output" in: sky130A_mr.lydrc:235
+Elapsed: 0.010s
+"isolated_check" in: sky130A_mr.lydrc:236
+Elapsed: 0.000s
+"_output" in: sky130A_mr.lydrc:236
+Elapsed: 0.010s
+{{ htvr }}
+"width_check" in: sky130A_mr.lydrc:243
+Elapsed: 0.000s
+"_output" in: sky130A_mr.lydrc:243
+Elapsed: 0.010s
+"isolated_check" in: sky130A_mr.lydrc:244
+Elapsed: 0.000s
+"_output" in: sky130A_mr.lydrc:244
+Elapsed: 0.010s
+{{ lvtn }}
+"isolated_check" in: sky130A_mr.lydrc:249
+Elapsed: 0.000s
+"_output" in: sky130A_mr.lydrc:249
+Elapsed: 0.010s
+{{ ncm }}
+"width_check" in: sky130A_mr.lydrc:261
+Elapsed: 0.000s
+"_output" in: sky130A_mr.lydrc:261
+Elapsed: 0.010s
+{{ diff-tap }}
+"+" in: sky130A_mr.lydrc:270
+Elapsed: 0.000s
+"width_check" in: sky130A_mr.lydrc:271
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:271
+Elapsed: 0.000s
+"isolated_check" in: sky130A_mr.lydrc:276
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:276
+Elapsed: 0.000s
+{{ tunm }}
+"width_check" in: sky130A_mr.lydrc:289
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:289
+Elapsed: 0.000s
+"isolated_check" in: sky130A_mr.lydrc:290
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:290
+Elapsed: 0.000s
+{{ poly }}
+"width_check" in: sky130A_mr.lydrc:299
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:299
+Elapsed: 0.000s
+"isolated_check" in: sky130A_mr.lydrc:301
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:301
+Elapsed: 0.000s
+{{ rpm }}
+"width_check" in: sky130A_mr.lydrc:318
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:318
+Elapsed: 0.000s
+"isolated_check" in: sky130A_mr.lydrc:319
+Elapsed: 0.020s
+"_output" in: sky130A_mr.lydrc:319
+Elapsed: 0.000s
+{{ npc }}
+"width_check" in: sky130A_mr.lydrc:352
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:352
+Elapsed: 0.000s
+"isolated_check" in: sky130A_mr.lydrc:353
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:353
+Elapsed: 0.000s
+{{ licon }}
+"interacting" in: sky130A_mr.lydrc:374
+Elapsed: 0.010s
+"-" in: sky130A_mr.lydrc:374
+Elapsed: 0.000s
+"edges" in: sky130A_mr.lydrc:374
+Elapsed: 0.010s
+"with_length" in: sky130A_mr.lydrc:374
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:374
+Elapsed: 0.000s
+"interacting" in: sky130A_mr.lydrc:375
+Elapsed: 0.010s
+"&" in: sky130A_mr.lydrc:375
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+"interacting" in: sky130A_mr.lydrc:375
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+"&" in: sky130A_mr.lydrc:375
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+"edges" in: sky130A_mr.lydrc:375
+Elapsed: 0.010s
+"with_length" in: sky130A_mr.lydrc:375
+Elapsed: 0.000s
+"interacting" in: sky130A_mr.lydrc:375
+Elapsed: 0.010s
+"&" in: sky130A_mr.lydrc:375
+Elapsed: 0.000s
+"edges" in: sky130A_mr.lydrc:375
+Elapsed: 0.010s
+"with_length" in: sky130A_mr.lydrc:375
+Elapsed: 0.000s
+"|" in: sky130A_mr.lydrc:375
+Elapsed: 0.010s
+"not_interacting" in: sky130A_mr.lydrc:375
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:375
+Elapsed: 0.000s
+"|" in: sky130A_mr.lydrc:403
+Elapsed: 0.010s
+"&" in: sky130A_mr.lydrc:403
+Elapsed: 0.000s
+"separation_check" in: sky130A_mr.lydrc:403
+Elapsed: 0.000s
+"_output" in: sky130A_mr.lydrc:403
+Elapsed: 0.000s
+"&" in: sky130A_mr.lydrc:409
+Elapsed: 0.010s
+"edges" in: sky130A_mr.lydrc:409
+Elapsed: 0.000s
+"edges" in: sky130A_mr.lydrc:409
+Elapsed: 0.010s
+"-" in: sky130A_mr.lydrc:409
+Elapsed: 0.000s
+"_output" in: sky130A_mr.lydrc:409
+Elapsed: 0.010s
+{{ vpp }}
+{{ capm }}
+"width_check" in: sky130A_mr.lydrc:434
+Elapsed: 0.000s
+"_output" in: sky130A_mr.lydrc:434
+Elapsed: 0.010s
+"isolated_check" in: sky130A_mr.lydrc:435
+Elapsed: 0.000s
+"_output" in: sky130A_mr.lydrc:435
+Elapsed: 0.010s
+"interacting" in: sky130A_mr.lydrc:436
+Elapsed: 0.010s
+"isolated_check" in: sky130A_mr.lydrc:436
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:436
+Elapsed: 0.000s
+"enclosing_check" in: sky130A_mr.lydrc:437
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:437
+Elapsed: 0.000s
+"enclosing_check" in: sky130A_mr.lydrc:438
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:438
+Elapsed: 0.000s
+"separation_check" in: sky130A_mr.lydrc:439
+Elapsed: 0.010s
+"_output" in: sky130A_mr.lydrc:439
+Elapsed: 0.010s
+{{ FEOL section }}
+{{ hvi }}
+"width_check" in: sky130A_mr.lydrc:753
+Elapsed: 0.000s
+"_output" in: sky130A_mr.lydrc:753
+Elapsed: 0.010s
+{{ hvntm }}
+"width_check" in: sky130A_mr.lydrc:779
+Elapsed: 0.000s
+"_output" in: sky130A_mr.lydrc:779
+Elapsed: 0.010s
+"isolated_check" in: sky130A_mr.lydrc:780
+Elapsed: 0.000s
+"_output" in: sky130A_mr.lydrc:780
+Elapsed: 0.010s
+Writing report database: /mnt/shuttles/mpw-two/slot-006/opencryo_testchip/checks/user_analog_project_wrapper_klayout.lydrc ..
+Total run time: 0.920s
diff --git a/checks/magic_drc.log b/checks/magic_drc.log
new file mode 100644
index 0000000..6ebfbc2
--- /dev/null
+++ b/checks/magic_drc.log
@@ -0,0 +1,30 @@
+
+Magic 8.3 revision 182 - Compiled on Thu Jun 24 20:18:20 UTC 2021.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/usr/local/bin/drc_checks/magic_drc_check.tcl" from command line.
+Warning: Calma reading is not undoable! I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_analog_project_wrapper
+Reading "char".
+Reading "inv".
+Reading "ringosc".
+Reading "indVCO".
+Reading "user_analog_project_wrapper".
+[INFO]: Loading user_analog_project_wrapper
+
+DRC style is now "drc(full)"
+Loading DRC CIF style.
+No errors found.
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+[INFO]: DRC Checking DONE (/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/checks/user_analog_project_wrapper.magic.drc)
+[INFO]: Saving mag view with DRC errors(/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/checks/user_analog_project_wrapper.magic.drc.mag)
+[INFO]: Saved
diff --git a/checks/manifest_check.log b/checks/manifest_check.log
new file mode 100644
index 0000000..7e6b925
--- /dev/null
+++ b/checks/manifest_check.log
@@ -0,0 +1,47 @@
+verilog/rtl/DFFRAM.v: FAILED
+verilog/rtl/DFFRAMBB.v: FAILED
+verilog/rtl/__uprj_analog_netlists.v: OK
+verilog/rtl/__uprj_netlists.v: OK
+verilog/rtl/__user_analog_project_wrapper.v: OK
+verilog/rtl/__user_project_wrapper.v: FAILED
+verilog/rtl/caravan.v: FAILED
+verilog/rtl/caravan_netlists.v: FAILED
+verilog/rtl/caravel.v: FAILED
+verilog/rtl/caravel_clocking.v: OK
+verilog/rtl/chip_io.v: FAILED
+verilog/rtl/chip_io_alt.v: FAILED
+verilog/rtl/clock_div.v: OK
+verilog/rtl/convert_gpio_sigs.v: OK
+verilog/rtl/counter_timer_high.v: OK
+verilog/rtl/counter_timer_low.v: OK
+verilog/rtl/digital_pll.v: OK
+verilog/rtl/digital_pll_controller.v: OK
+verilog/rtl/gpio_control_block.v: FAILED
+verilog/rtl/gpio_wb.v: OK
+verilog/rtl/housekeeping_spi.v: FAILED
+verilog/rtl/la_wb.v: OK
+verilog/rtl/mem_wb.v: FAILED
+verilog/rtl/mgmt_core.v: FAILED
+verilog/rtl/mgmt_protect.v: FAILED
+verilog/rtl/mgmt_protect_hv.v: OK
+verilog/rtl/mgmt_soc.v: FAILED
+verilog/rtl/mprj2_logic_high.v: OK
+verilog/rtl/mprj_ctrl.v: FAILED
+verilog/rtl/mprj_io.v: OK
+verilog/rtl/mprj_logic_high.v: OK
+verilog/rtl/pads.v: OK
+verilog/rtl/picorv32.v: OK
+verilog/rtl/ring_osc2x13.v: OK
+verilog/rtl/simple_por.v: OK
+verilog/rtl/simple_spi_master.v: FAILED
+verilog/rtl/simpleuart.v: OK
+verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v: OK
+verilog/rtl/spimemio.v: OK
+verilog/rtl/sram_1rw1r_32_256_8_sky130.v: FAILED
+verilog/rtl/storage.v: FAILED
+verilog/rtl/storage_bridge_wb.v: OK
+verilog/rtl/sysctrl.v: OK
+verilog/rtl/wb_intercon.v: OK
+scripts/set_user_id.py: OK
+scripts/generate_fill.py: FAILED
+scripts/compositor.py: FAILED
diff --git a/checks/met_density_check.xml b/checks/met_density_check.xml
new file mode 100644
index 0000000..6928d4f
--- /dev/null
+++ b/checks/met_density_check.xml
@@ -0,0 +1,123 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>Density Checks</description>
+ <original-file/>
+ <generator>drc: script='/usr/local/bin/klayout_drc_checks/met_density.lydrc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>li1.pd.1e</name>
+ <description>0.65 max li1 ca pattern density</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1.pd.1e</name>
+ <description>0.65 max m1 ca pattern density</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2.pd.1e</name>
+ <description>0.65 max m2 ca pattern density</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3.pd.1e</name>
+ <description>0.65 max m3 ca pattern density</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4.pd.1e</name>
+ <description>0.65 max m4 ca pattern density</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5.pd.1e</name>
+ <description>0.55 max m5 ca pattern density</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ <item>
+ <tags/>
+ <category>'li1.pd.1e'</category>
+ <cell>user_analog_project_wrapper</cell>
+ <visited>false</visited>
+ <multiplicity>1</multiplicity>
+ <image/>
+ <values>
+ <value>polygon: (0,0;0,3520;2920,3520;2920,0)</value>
+ </values>
+ </item>
+ <item>
+ <tags/>
+ <category>'m1.pd.1e'</category>
+ <cell>user_analog_project_wrapper</cell>
+ <visited>false</visited>
+ <multiplicity>1</multiplicity>
+ <image/>
+ <values>
+ <value>polygon: (0,0;0,3520;2920,3520;2920,0)</value>
+ </values>
+ </item>
+ <item>
+ <tags/>
+ <category>'m2.pd.1e'</category>
+ <cell>user_analog_project_wrapper</cell>
+ <visited>false</visited>
+ <multiplicity>1</multiplicity>
+ <image/>
+ <values>
+ <value>polygon: (0,0;0,3520;2920,3520;2920,0)</value>
+ </values>
+ </item>
+ <item>
+ <tags/>
+ <category>'m3.pd.1e'</category>
+ <cell>user_analog_project_wrapper</cell>
+ <visited>false</visited>
+ <multiplicity>1</multiplicity>
+ <image/>
+ <values>
+ <value>polygon: (0,0;0,3520;2920,3520;2920,0)</value>
+ </values>
+ </item>
+ <item>
+ <tags/>
+ <category>'m4.pd.1e'</category>
+ <cell>user_analog_project_wrapper</cell>
+ <visited>false</visited>
+ <multiplicity>1</multiplicity>
+ <image/>
+ <values>
+ <value>polygon: (0,0;0,3520;2920,3520;2920,0)</value>
+ </values>
+ </item>
+ <item>
+ <tags/>
+ <category>'m5.pd.1e'</category>
+ <cell>user_analog_project_wrapper</cell>
+ <visited>false</visited>
+ <multiplicity>1</multiplicity>
+ <image/>
+ <values>
+ <value>polygon: (0,0;0,3520;2920,3520;2920,0)</value>
+ </values>
+ </item>
+ </items>
+</report-database>
diff --git a/checks/met_density_check.xml.summary b/checks/met_density_check.xml.summary
new file mode 100644
index 0000000..a289d3c
--- /dev/null
+++ b/checks/met_density_check.xml.summary
@@ -0,0 +1,7 @@
+ 1 0.55 max m5 ca pattern density
+ 1 0.65 max li1 ca pattern density
+ 1 0.65 max m1 ca pattern density
+ 1 0.65 max m2 ca pattern density
+ 1 0.65 max m3 ca pattern density
+ 1 0.65 max m4 ca pattern density
+ 6 total error(s) among 6 error type(s), 6 non-zero type(s)
diff --git a/checks/offgrid_check.xml b/checks/offgrid_check.xml
new file mode 100644
index 0000000..b4d3510
--- /dev/null
+++ b/checks/offgrid_check.xml
@@ -0,0 +1,483 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/usr/local/bin/klayout_drc_checks/offgrid.lydrc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>dnwell_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>dnwell_angle</name>
+ <description>x.3a : non 45 degree angle dnwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell_angle</name>
+ <description>x.3a : non 45 degree angle nwell</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwbm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwbm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwbm_angle</name>
+ <description>x.3a : non 45 degree angle pwbm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwde_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwde</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwde_angle</name>
+ <description>x.3a : non 45 degree angle pwde</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp_angle</name>
+ <description>x.3a : non 45 degree angle hvtp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvtr</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr_angle</name>
+ <description>x.3a : non 45 degree angle hvtr</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on lvtn</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn_angle</name>
+ <description>x.3a : non 45 degree angle lvtn</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on ncm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm_angle</name>
+ <description>x.3a : non 45 degree angle ncm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_angle</name>
+ <description>x.2 : non 90 degree angle diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>diff_angle</name>
+ <description>x.2c : non 45 degree angle diff</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_angle</name>
+ <description>x.2 : non 90 degree angle tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tap_angle</name>
+ <description>x.2c : non 45 degree angle tap</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on tunm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm_angle</name>
+ <description>x.3a : non 45 degree angle tunm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on poly</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly_angle</name>
+ <description>x.2 : non 90 degree angle poly</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on rpm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm_angle</name>
+ <description>x.3a : non 45 degree angle rpm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc_angle</name>
+ <description>x.3a : non 45 degree angle npc</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsdm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nsdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsdm_angle</name>
+ <description>x.3a : non 45 degree angle nsdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psdm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on psdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>psdm_angle</name>
+ <description>x.3a : non 45 degree angle psdm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on licon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon_angle</name>
+ <description>x.2 : non 90 degree angle licon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>li_angle</name>
+ <description>x.3a : non 45 degree angle li</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on mcon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ct_angle</name>
+ <description>x.2 : non 90 degree angle mcon</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vpp_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on vpp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vpp_angle</name>
+ <description>x.3a : non 45 degree angle vpp</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m1_angle</name>
+ <description>x.3a : non 45 degree angle m1</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via_angle</name>
+ <description>x.2 : non 90 degree angle via</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m2_angle</name>
+ <description>x.3a : non 45 degree angle m2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via2_angle</name>
+ <description>x.2 : non 90 degree angle via2</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m3_angle</name>
+ <description>x.3a : non 45 degree angle m3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via3_angle</name>
+ <description>x.2 : non 90 degree angle via3</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on nsm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nsm_angle</name>
+ <description>x.3a : non 45 degree angle nsm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m4_angle</name>
+ <description>x.3a : non 45 degree angle m4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>via4_angle</name>
+ <description>x.2 : non 90 degree angle via4</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>m5_angle</name>
+ <description>x.3a : non 45 degree angle m5</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pad</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pad_angle</name>
+ <description>x.3a : non 45 degree angle pad</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mf_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on mf</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>mf_angle</name>
+ <description>x.2 : non 90 degree angle mf</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi_angle</name>
+ <description>x.3a : non 45 degree angle hvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on hvntm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm_angle</name>
+ <description>x.3a : non 45 degree angle hvntm</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vhvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on vhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>vhvi_angle</name>
+ <description>x.3a : non 45 degree angle vhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>uhvi_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on uhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>uhvi_angle</name>
+ <description>x.3a : non 45 degree angle uhvi</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwell_rs_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on pwell_rs</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>pwell_rs_angle</name>
+ <description>x.3a : non 45 degree angle pwell_rs</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>areaid_re_OFFGRID</name>
+ <description>x.1b : OFFGRID vertex on areaid.re</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/checks/spdx_compliance_report.log b/checks/spdx_compliance_report.log
new file mode 100644
index 0000000..bb127e8
--- /dev/null
+++ b/checks/spdx_compliance_report.log
@@ -0,0 +1,22 @@
+FULL RUN LOG:
+SPDX NON-COMPLIANT FILES
+/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/README.md
+/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/xschem/example_por.sch
+/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/xschem/test.data
+/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/xschem/example_por_tb.spice.orig
+/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/xschem/user_analog_project_wrapper.sch
+/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/xschem/.spiceinit
+/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/xschem/user_analog_project_wrapper.sym
+/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/xschem/xschemrc
+/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/xschem/example_por_tb.sch
+/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/xschem/example_por.sym
+/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/xschem/analog_wrapper_tb.sch
+/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/signoff/kdrc_results_offgrid.xml.summary
+/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/signoff/kdrc_results_mr_fe.xml.summary
+/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/signoff/kdrc_results_fom.xml.summary
+/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/signoff/versions
+/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/signoff/kdrc_results_met.xml.summary
+/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/mag/compose_final.tcl
+/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/mag/generate_fill.tcl
+/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/mag/generate_fill_dist.tcl
+/mnt/shuttles/mpw-two/slot-006/opencryo_testchip/mag/generate_fill_final.tcl
diff --git a/checks/user_analog_project_wrapper.magic.drc b/checks/user_analog_project_wrapper.magic.drc
new file mode 100644
index 0000000..829b9d5
--- /dev/null
+++ b/checks/user_analog_project_wrapper.magic.drc
@@ -0,0 +1,5 @@
+user_analog_project_wrapper
+----------------------------------------
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+
diff --git a/checks/user_analog_project_wrapper.magic.drc.mag b/checks/user_analog_project_wrapper.magic.drc.mag
new file mode 100644
index 0000000..5751a12
--- /dev/null
+++ b/checks/user_analog_project_wrapper.magic.drc.mag
@@ -0,0 +1,4437 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1626418305
+<< checkpaint >>
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+flabel metal3 s 583520 24002 584800 24114 0 FreeSans 1400 0 0 0 io_oeb[4]
+flabel metal3 s 583520 50460 584800 50572 0 FreeSans 1400 0 0 0 io_oeb[5]
+flabel metal3 s 583520 95118 584800 95230 0 FreeSans 1400 0 0 0 io_oeb[6]
+flabel metal3 s 583520 275140 584800 275252 0 FreeSans 1400 0 0 0 io_oeb[7]
+flabel metal3 s 583520 319562 584800 319674 0 FreeSans 1400 0 0 0 io_oeb[8]
+flabel metal3 s 583520 364784 584800 364896 0 FreeSans 1400 0 0 0 io_oeb[9]
+flabel metal3 s 583520 3908 584800 4020 0 FreeSans 1400 0 0 0 io_out[0]
+flabel metal3 s 583520 410024 584800 410136 0 FreeSans 1400 0 0 0 io_out[10]
+flabel metal3 s 583520 454446 584800 454558 0 FreeSans 1400 0 0 0 io_out[11]
+flabel metal3 s 583520 498868 584800 498980 0 FreeSans 1400 0 0 0 io_out[12]
+flabel metal3 s 583520 588290 584800 588402 0 FreeSans 1400 0 0 0 io_out[13]
+flabel metal3 s -800 506802 480 506914 0 FreeSans 1400 0 0 0 io_out[14]
+flabel metal3 s -800 463580 480 463692 0 FreeSans 1400 0 0 0 io_out[15]
+flabel metal3 s -800 420358 480 420470 0 FreeSans 1400 0 0 0 io_out[16]
+flabel metal3 s -800 377136 480 377248 0 FreeSans 1400 0 0 0 io_out[17]
+flabel metal3 s -800 333914 480 334026 0 FreeSans 1400 0 0 0 io_out[18]
+flabel metal3 s -800 290692 480 290804 0 FreeSans 1400 0 0 0 io_out[19]
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+flabel metal3 s -800 120048 480 120160 0 FreeSans 1400 0 0 0 io_out[21]
+flabel metal3 s -800 76826 480 76938 0 FreeSans 1400 0 0 0 io_out[22]
+flabel metal3 s -800 33604 480 33716 0 FreeSans 1400 0 0 0 io_out[23]
+flabel metal3 s -800 12182 480 12294 0 FreeSans 1400 0 0 0 io_out[24]
+flabel metal3 s -800 7454 480 7566 0 FreeSans 1400 0 0 0 io_out[25]
+flabel metal3 s -800 2726 480 2838 0 FreeSans 1400 0 0 0 io_out[26]
+flabel metal3 s 583520 13364 584800 13476 0 FreeSans 1400 0 0 0 io_out[2]
+flabel metal3 s 583520 18092 584800 18204 0 FreeSans 1400 0 0 0 io_out[3]
+flabel metal3 s 583520 22820 584800 22932 0 FreeSans 1400 0 0 0 io_out[4]
+flabel metal3 s 583520 49278 584800 49390 0 FreeSans 1400 0 0 0 io_out[5]
+flabel metal3 s 583520 93936 584800 94048 0 FreeSans 1400 0 0 0 io_out[6]
+flabel metal3 s 583520 273958 584800 274070 0 FreeSans 1400 0 0 0 io_out[7]
+flabel metal3 s 583520 318380 584800 318492 0 FreeSans 1400 0 0 0 io_out[8]
+flabel metal3 s 583520 363602 584800 363714 0 FreeSans 1400 0 0 0 io_out[9]
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+flabel metal2 s 38348 -800 38460 480 0 FreeSans 1400 90 0 0 wbs_dat_i[7]
+flabel metal2 s 41894 -800 42006 480 0 FreeSans 1400 90 0 0 wbs_dat_i[8]
+flabel metal2 s 45440 -800 45552 480 0 FreeSans 1400 90 0 0 wbs_dat_i[9]
+flabel metal2 s 9980 -800 10092 480 0 FreeSans 1400 90 0 0 wbs_dat_o[0]
+flabel metal2 s 50168 -800 50280 480 0 FreeSans 1400 90 0 0 wbs_dat_o[10]
+flabel metal2 s 53714 -800 53826 480 0 FreeSans 1400 90 0 0 wbs_dat_o[11]
+flabel metal2 s 57260 -800 57372 480 0 FreeSans 1400 90 0 0 wbs_dat_o[12]
+flabel metal2 s 60806 -800 60918 480 0 FreeSans 1400 90 0 0 wbs_dat_o[13]
+flabel metal2 s 64352 -800 64464 480 0 FreeSans 1400 90 0 0 wbs_dat_o[14]
+flabel metal2 s 67898 -800 68010 480 0 FreeSans 1400 90 0 0 wbs_dat_o[15]
+flabel metal2 s 71444 -800 71556 480 0 FreeSans 1400 90 0 0 wbs_dat_o[16]
+flabel metal2 s 74990 -800 75102 480 0 FreeSans 1400 90 0 0 wbs_dat_o[17]
+flabel metal2 s 78536 -800 78648 480 0 FreeSans 1400 90 0 0 wbs_dat_o[18]
+flabel metal2 s 82082 -800 82194 480 0 FreeSans 1400 90 0 0 wbs_dat_o[19]
+flabel metal2 s 14708 -800 14820 480 0 FreeSans 1400 90 0 0 wbs_dat_o[1]
+flabel metal2 s 85628 -800 85740 480 0 FreeSans 1400 90 0 0 wbs_dat_o[20]
+flabel metal2 s 89174 -800 89286 480 0 FreeSans 1400 90 0 0 wbs_dat_o[21]
+flabel metal2 s 92720 -800 92832 480 0 FreeSans 1400 90 0 0 wbs_dat_o[22]
+flabel metal2 s 96266 -800 96378 480 0 FreeSans 1400 90 0 0 wbs_dat_o[23]
+flabel metal2 s 99812 -800 99924 480 0 FreeSans 1400 90 0 0 wbs_dat_o[24]
+flabel metal2 s 103358 -800 103470 480 0 FreeSans 1400 90 0 0 wbs_dat_o[25]
+flabel metal2 s 106904 -800 107016 480 0 FreeSans 1400 90 0 0 wbs_dat_o[26]
+flabel metal2 s 110450 -800 110562 480 0 FreeSans 1400 90 0 0 wbs_dat_o[27]
+flabel metal2 s 113996 -800 114108 480 0 FreeSans 1400 90 0 0 wbs_dat_o[28]
+flabel metal2 s 117542 -800 117654 480 0 FreeSans 1400 90 0 0 wbs_dat_o[29]
+flabel metal2 s 19436 -800 19548 480 0 FreeSans 1400 90 0 0 wbs_dat_o[2]
+flabel metal2 s 121088 -800 121200 480 0 FreeSans 1400 90 0 0 wbs_dat_o[30]
+flabel metal2 s 124634 -800 124746 480 0 FreeSans 1400 90 0 0 wbs_dat_o[31]
+flabel metal2 s 24164 -800 24276 480 0 FreeSans 1400 90 0 0 wbs_dat_o[3]
+flabel metal2 s 28892 -800 29004 480 0 FreeSans 1400 90 0 0 wbs_dat_o[4]
+flabel metal2 s 32438 -800 32550 480 0 FreeSans 1400 90 0 0 wbs_dat_o[5]
+flabel metal2 s 35984 -800 36096 480 0 FreeSans 1400 90 0 0 wbs_dat_o[6]
+flabel metal2 s 39530 -800 39642 480 0 FreeSans 1400 90 0 0 wbs_dat_o[7]
+flabel metal2 s 43076 -800 43188 480 0 FreeSans 1400 90 0 0 wbs_dat_o[8]
+flabel metal2 s 46622 -800 46734 480 0 FreeSans 1400 90 0 0 wbs_dat_o[9]
+flabel metal2 s 11162 -800 11274 480 0 FreeSans 1400 90 0 0 wbs_sel_i[0]
+flabel metal2 s 15890 -800 16002 480 0 FreeSans 1400 90 0 0 wbs_sel_i[1]
+flabel metal2 s 20618 -800 20730 480 0 FreeSans 1400 90 0 0 wbs_sel_i[2]
+flabel metal2 s 25346 -800 25458 480 0 FreeSans 1400 90 0 0 wbs_sel_i[3]
+flabel metal2 s 5252 -800 5364 480 0 FreeSans 1400 90 0 0 wbs_stb_i
+flabel metal2 s 6434 -800 6546 480 0 FreeSans 1400 90 0 0 wbs_we_i
+<< properties >>
+string FIXED_BBOX 0 0 584000 704000
+<< end >>
diff --git a/checks/user_analog_project_wrapper.xor.gds b/checks/user_analog_project_wrapper.xor.gds
new file mode 100644
index 0000000..ca9c9c1
--- /dev/null
+++ b/checks/user_analog_project_wrapper.xor.gds
Binary files differ
diff --git a/checks/user_analog_project_wrapper_empty.gds b/checks/user_analog_project_wrapper_empty.gds
new file mode 100644
index 0000000..6bb65fc
--- /dev/null
+++ b/checks/user_analog_project_wrapper_empty.gds
Binary files differ
diff --git a/checks/user_analog_project_wrapper_empty_erased.gds b/checks/user_analog_project_wrapper_empty_erased.gds
new file mode 100644
index 0000000..e793e55
--- /dev/null
+++ b/checks/user_analog_project_wrapper_empty_erased.gds
Binary files differ
diff --git a/checks/user_analog_project_wrapper_erased.gds b/checks/user_analog_project_wrapper_erased.gds
new file mode 100644
index 0000000..acefe3f
--- /dev/null
+++ b/checks/user_analog_project_wrapper_erased.gds
Binary files differ
diff --git a/checks/user_analog_project_wrapper_klayout.lydrc b/checks/user_analog_project_wrapper_klayout.lydrc
new file mode 100644
index 0000000..f7bd1ec
--- /dev/null
+++ b/checks/user_analog_project_wrapper_klayout.lydrc
@@ -0,0 +1,213 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/usr/local/bin/drc_checks/../tech-files/sky130A_mr.lydrc'</generator>
+ <top-cell>user_analog_project_wrapper</top-cell>
+ <tags>
+ </tags>
+ <categories>
+ <category>
+ <name>dnwell.2</name>
+ <description>dnwell.2 : min. dnwell width : 3.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.1</name>
+ <description>nwell.1 : min. nwell width : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>nwell.2a</name>
+ <description>nwell.2a : min. nwell spacing (merged if less) : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.1</name>
+ <description>hvtp.1 : min. hvtp width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtp.2</name>
+ <description>hvtp.2 : min. hvtp spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.1</name>
+ <description>hvtr.1 : min. hvtr width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvtr.2</name>
+ <description>hvtr.2 : min. hvtr spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>lvtn.2</name>
+ <description>lvtn.2 : min. lvtn spacing : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>ncm.1</name>
+ <description>ncm.1 : min. ncm width : 0.38um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.1</name>
+ <description>difftap.1 : min. difftap width : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>difftap.3</name>
+ <description>difftap.3 : min. difftap spacing : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm.1</name>
+ <description>tunm.1 : min. tunm width : 0.41um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>tunm.2</name>
+ <description>tunm.2 : min. tunm spacing : 0.5um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly.1a</name>
+ <description>poly.1a : min. poly width : 0.15um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>poly.2</name>
+ <description>poly.2 : min. poly spacing : 0.21um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm.1a</name>
+ <description>rpm.1a : min. rpm width : 1.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>rpm.2</name>
+ <description>rpm.2 : min. rpm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc.1</name>
+ <description>npc.1 : min. npc width : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>npc.2</name>
+ <description>npc.2 : min. npc spacing, should be mnually merge if less : 0.27um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.1</name>
+ <description>licon.1 : minimum/maximum width of licon : 0.17um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.1b/c</name>
+ <description>licon.1b/c : minimum/maximum width/length of licon inside poly resistor : 2.0/0.19um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.13</name>
+ <description>licon.13 : min. difftap licon spacing to npc : 0.09um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>licon.17</name>
+ <description>licon.17 : tap must not straddle poly</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.1</name>
+ <description>capm.1 : min. capm width : 1.0um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2a</name>
+ <description>capm.2a : min. capm spacing : 0.84um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.2b</name>
+ <description>capm.2b : min. capm spacing : 1.2um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.3</name>
+ <description>capm.3 : min. m2 enclosure of capm : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.4</name>
+ <description>capm.4 : min. capm enclosure of via2 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>capm.5</name>
+ <description>capm.5 : min. capm spacing to via2 : 0.14um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvi.1</name>
+ <description>hvi.1 : min. hvi width : 0.6um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm.1</name>
+ <description>hvntm.1 : min. hvntm width : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ <category>
+ <name>hvntm.2</name>
+ <description>hvntm.2 : min. hvntm spacing : 0.7um</description>
+ <categories>
+ </categories>
+ </category>
+ </categories>
+ <cells>
+ <cell>
+ <name>user_analog_project_wrapper</name>
+ <variant/>
+ <references>
+ </references>
+ </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>
diff --git a/checks/xor.log b/checks/xor.log
new file mode 100644
index 0000000..04f36d3
--- /dev/null
+++ b/checks/xor.log
@@ -0,0 +1,38 @@
+First Layout: /mnt/shuttles/mpw-two/slot-006/opencryo_testchip/checks/user_analog_project_wrapper_empty_erased.gds
+Second Layout: /mnt/shuttles/mpw-two/slot-006/opencryo_testchip/checks/user_analog_project_wrapper_erased.gds
+Design Name: xor_target
+Output GDS will be: /mnt/shuttles/mpw-two/slot-006/opencryo_testchip/checks/user_analog_project_wrapper.xor.gds
+Reading /mnt/shuttles/mpw-two/slot-006/opencryo_testchip/checks/user_analog_project_wrapper_empty_erased.gds ..
+Reading /mnt/shuttles/mpw-two/slot-006/opencryo_testchip/checks/user_analog_project_wrapper_erased.gds ..
+--- Running XOR for 69/20 ---
+"_input" in: xor.drc:38
+Elapsed: 0.010s
+"_input" in: xor.drc:38
+Elapsed: 0.000s
+"^" in: xor.drc:38
+Elapsed: 0.010s
+XOR differences: 0
+"_output" in: xor.drc:41
+Elapsed: 0.010s
+--- Running XOR for 70/20 ---
+"_input" in: xor.drc:38
+Elapsed: 0.000s
+"_input" in: xor.drc:38
+Elapsed: 0.010s
+"^" in: xor.drc:38
+Elapsed: 0.000s
+XOR differences: 0
+"_output" in: xor.drc:41
+Elapsed: 0.010s
+--- Running XOR for 81/14 ---
+"_input" in: xor.drc:38
+Elapsed: 0.000s
+"_input" in: xor.drc:38
+Elapsed: 0.010s
+"^" in: xor.drc:38
+Elapsed: 0.000s
+XOR differences: 0
+"_output" in: xor.drc:41
+Elapsed: 0.010s
+Writing layout file: /mnt/shuttles/mpw-two/slot-006/opencryo_testchip/checks/user_analog_project_wrapper.xor.gds ..
+Total run time: 0.080s
diff --git a/checks/xor_total.txt b/checks/xor_total.txt
new file mode 100644
index 0000000..05b29a4
--- /dev/null
+++ b/checks/xor_total.txt
@@ -0,0 +1 @@
+Total XOR differences = 0
\ No newline at end of file
diff --git a/gds/caravan.gds.gz b/gds/caravan.gds.gz
new file mode 100644
index 0000000..5616c9a
--- /dev/null
+++ b/gds/caravan.gds.gz
Binary files differ
diff --git a/gds/caravel_00020006.gds.gz.00.split b/gds/caravel_00020006.gds.gz.00.split
new file mode 100644
index 0000000..ddd47e1
--- /dev/null
+++ b/gds/caravel_00020006.gds.gz.00.split
Binary files differ
diff --git a/gds/caravel_00020006.gds.gz.01.split b/gds/caravel_00020006.gds.gz.01.split
new file mode 100644
index 0000000..6b04c5e
--- /dev/null
+++ b/gds/caravel_00020006.gds.gz.01.split
Binary files differ
diff --git a/gds/caravel_00020006.gds.gz.02.split b/gds/caravel_00020006.gds.gz.02.split
new file mode 100644
index 0000000..b222aa1
--- /dev/null
+++ b/gds/caravel_00020006.gds.gz.02.split
Binary files differ
diff --git a/gds/caravel_00020006.gds.gz.03.split b/gds/caravel_00020006.gds.gz.03.split
new file mode 100644
index 0000000..0c80a6c
--- /dev/null
+++ b/gds/caravel_00020006.gds.gz.03.split
Binary files differ
diff --git a/gds/caravel_00020006.gds.gz.04.split b/gds/caravel_00020006.gds.gz.04.split
new file mode 100644
index 0000000..c38fceb
--- /dev/null
+++ b/gds/caravel_00020006.gds.gz.04.split
Binary files differ
diff --git a/gds/caravel_00020006_fill_pattern.gds.gz.00.split b/gds/caravel_00020006_fill_pattern.gds.gz.00.split
new file mode 100644
index 0000000..41c2da5
--- /dev/null
+++ b/gds/caravel_00020006_fill_pattern.gds.gz.00.split
Binary files differ
diff --git a/gds/caravel_00020006_fill_pattern.gds.gz.01.split b/gds/caravel_00020006_fill_pattern.gds.gz.01.split
new file mode 100644
index 0000000..c62e1ba
--- /dev/null
+++ b/gds/caravel_00020006_fill_pattern.gds.gz.01.split
Binary files differ
diff --git a/gds/caravel_00020006_fill_pattern.gds.gz.02.split b/gds/caravel_00020006_fill_pattern.gds.gz.02.split
new file mode 100644
index 0000000..38a1253
--- /dev/null
+++ b/gds/caravel_00020006_fill_pattern.gds.gz.02.split
Binary files differ
diff --git a/gds/caravel_00020006_fill_pattern.gds.gz.03.split b/gds/caravel_00020006_fill_pattern.gds.gz.03.split
new file mode 100644
index 0000000..47b85df
--- /dev/null
+++ b/gds/caravel_00020006_fill_pattern.gds.gz.03.split
Binary files differ
diff --git a/gds/caravel_00020006_fill_pattern.gds.gz.04.split b/gds/caravel_00020006_fill_pattern.gds.gz.04.split
new file mode 100644
index 0000000..615e4d5
--- /dev/null
+++ b/gds/caravel_00020006_fill_pattern.gds.gz.04.split
Binary files differ
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds
deleted file mode 100644
index 5788fd8..0000000
--- a/gds/user_analog_project_wrapper.gds
+++ /dev/null
Binary files differ
diff --git a/gds/user_analog_project_wrapper.gds.gz b/gds/user_analog_project_wrapper.gds.gz
new file mode 100644
index 0000000..7b81f9d
--- /dev/null
+++ b/gds/user_analog_project_wrapper.gds.gz
Binary files differ
diff --git a/gds/user_id_prog_zero.gds.gz b/gds/user_id_prog_zero.gds.gz
new file mode 100644
index 0000000..fd7f8c8
--- /dev/null
+++ b/gds/user_id_prog_zero.gds.gz
Binary files differ
diff --git a/gds/user_id_programming.gds.gz b/gds/user_id_programming.gds.gz
new file mode 100644
index 0000000..e18d938
--- /dev/null
+++ b/gds/user_id_programming.gds.gz
Binary files differ
diff --git a/info.yaml b/info.yaml
index 8ba8660..15c8369 100644
--- a/info.yaml
+++ b/info.yaml
@@ -1,19 +1,20 @@
----
project:
- description: "An analog project for Google sponsored Open MPW shuttles for SKY130."
- foundry: "SkyWater"
- git_url: "https://github.com/efabless/caravel_analog_user.git"
- organization: "Efabless"
- organization_url: "http://efabless.com"
- owner: "Tim Edwards"
- process: "SKY130"
- project_name: "Caravel Analog User"
- project_id: "00000000"
+ category: Test Harness
+ cover_image: docs/source/_static/caravel_harness.png
+ description: An analog project for Google sponsored Open MPW shuttles for SKY130.
+ foundry: SkyWater
+ git_url: https://github.com/efabless/caravel_analog_user.git
+ layout_image: ./gds/caravan.png
+ organization: Efabless
+ organization_url: http://efabless.com
+ owner: Tim Edwards
+ process: SKY130
+ project_id: '00020006'
+ project_name: Caravel Analog User
+ shuttle_url: https://foss-eda-tools.googlesource.com/third_party/shuttle/mpw-two/slot-006.git
tags:
- - "Open MPW"
- - "Test Harness"
- category: "Test Harness"
- top_level_netlist: "caravel/verilog/gl/caravan.v"
- user_level_netlist: "verilog/rtl/user_analog_project_wrapper.v"
- version: "1.00"
- cover_image: "docs/source/_static/caravel_harness.png"
+ - Open MPW
+ - Test Harness
+ top_level_netlist: caravel/verilog/gl/caravan.v
+ user_level_netlist: verilog/rtl/user_analog_project_wrapper.v
+ version: '1.00'
diff --git a/mag/.magicrc b/mag/.magicrc
new file mode 100644
index 0000000..12328c6
--- /dev/null
+++ b/mag/.magicrc
@@ -0,0 +1,97 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+puts stdout "Sourcing design .magicrc for technology sky130A ..."
+
+# Put grid on 0.005 pitch. This is important, as some commands don't
+# rescale the grid automatically (such as lef read?).
+
+set scalefac [tech lambda]
+if {[lindex $scalefac 1] < 2} {
+ scalegrid 1 2
+}
+
+drc off
+drc euclidean on
+
+# Allow override of PDK path from environment variable PDKPATH
+if {[catch {set PDKPATH $env(PDKPATH)}]} {
+ set PDKPATH "$::env(PDK_ROOT)/sky130A"
+}
+
+# loading technology
+tech load $PDKPATH/libs.tech/magic/sky130A.tech
+
+# load device generator
+source $PDKPATH/libs.tech/magic/sky130A.tcl
+
+# load bind keys (optional)
+# source $PDKPATH/libs.tech/magic/sky130A-BindKeys
+
+# set units to lambda grid
+snap lambda
+
+# set sky130 standard power, ground, and substrate names
+set VDD VPWR
+set GND VGND
+set SUB VSUBS
+
+# Allow override of type of magic library views used, "mag" or "maglef",
+# from environment variable MAGTYPE
+
+if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
+ set MAGTYPE maglef
+}
+
+ path search [concat "../$MAGTYPE" [path search]]
+
+
+# add path to reference cells
+if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} {
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms
+ addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc
+ addpath ${PDKPATH}/libs.ref/mag/sky130_ml_xx_hd
+} else {
+ addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE}
+ addpath ${PDKPATH}/libs.ref/sky130_ml_xx_hd/mag
+}
+
+addpath hexdigits
+addpath ../subcells/simple_por/mag
+
+# add path to GDS cells
+
+# add path to IP from catalog. This procedure defined in the PDK script.
+catch {magic::query_mylib_ip}
+# add path to local IP from user design space. Defined in the PDK script.
+catch {magic::query_my_projects}
diff --git a/mag/compose_final.tcl b/mag/compose_final.tcl
new file mode 100644
index 0000000..dd0dda8
--- /dev/null
+++ b/mag/compose_final.tcl
@@ -0,0 +1,28 @@
+#!/bin/env wish
+drc off
+random seed 131078
+load caravan -dereference
+property GDS_FILE /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/gds/caravan.gds
+property GDS_START 0
+select top cell
+set bbox [box values]
+load caravel_00020006_fill_pattern -quiet
+snap internal
+box values {*}$bbox
+paint comment
+property GDS_FILE /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/gds/caravel_00020006_fill_pattern.gds
+property GDS_START 0
+property FIXED_BBOX "$bbox"
+load caravel_00020006 -quiet
+box values 0 0 0 0
+box position 6um 6um
+getcell caravan child 0 0
+getcell caravel_00020006_fill_pattern child 0 0
+box position 0 0
+getcell advSeal_6um_gen
+puts stdout "Writing final GDS. . . "
+flush stdout
+gds undefined allow
+cif *hier write disable
+gds write /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/gds/caravel_00020006.gds
+quit -noprompt
diff --git a/mag/core.365 b/mag/core.365
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mag/core.365
diff --git a/mag/core.387 b/mag/core.387
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mag/core.387
diff --git a/mag/user_id_programming.mag b/mag/user_id_programming.mag
new file mode 100644
index 0000000..12006b5
--- /dev/null
+++ b/mag/user_id_programming.mag
@@ -0,0 +1,3159 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1606755340
+<< nwell >>
+rect 2304 2369 2397 2389
+<< viali >>
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+<< metal1 >>
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+<< metal4 >>
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+<< via4 >>
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+rect 2611 4186 2847 4422
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+<< metal5 >>
+rect 1104 5238 5980 5280
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+rect 5285 1738 5980 1974
+rect 1104 1696 5980 1738
+use sky130_fd_sc_hd__decap_3 PHY_0 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1606755340
+transform 1 0 1104 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_2
+timestamp 1606755340
+transform 1 0 1104 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 FILLER_1_6
+timestamp 1606755340
+transform 1 0 1656 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[27\] $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1606755340
+transform 1 0 1472 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[28\]
+timestamp 1606755340
+transform 1 0 1932 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[3\]
+timestamp 1606755340
+transform 1 0 1380 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_1 FILLER_0_3 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1606755340
+transform 1 0 1380 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_8 FILLER_0_7 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1606755340
+transform 1 0 1748 0 -1 1632
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_2 FILLER_1_12 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1606755340
+transform 1 0 2208 0 1 1632
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_3 FILLER_0_15
+timestamp 1606755340
+transform 1 0 2484 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[0\]
+timestamp 1606755340
+transform 1 0 2392 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[11\]
+timestamp 1606755340
+transform 1 0 2668 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[1\]
+timestamp 1606755340
+transform 1 0 3036 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[20\]
+timestamp 1606755340
+transform 1 0 2760 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_1 FILLER_1_20
+timestamp 1606755340
+transform 1 0 2944 0 1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_8 FILLER_0_21
+timestamp 1606755340
+transform 1 0 3036 0 -1 1632
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_6 FILLER_1_24 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1606755340
+transform 1 0 3312 0 1 1632
+box -38 -48 590 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[15\]
+timestamp 1606755340
+transform 1 0 4416 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[7\]
+timestamp 1606755340
+transform 1 0 3864 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_18 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1606755340
+transform 1 0 3956 0 -1 1632
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_2 FILLER_0_29
+timestamp 1606755340
+transform 1 0 3772 0 -1 1632
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4 FILLER_0_32 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1606755340
+transform 1 0 4048 0 -1 1632
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_12 FILLER_1_33 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
+timestamp 1606755340
+transform 1 0 4140 0 1 1632
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_3 PHY_1
+timestamp 1606755340
+transform -1 0 5980 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_3
+timestamp 1606755340
+transform -1 0 5980 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 FILLER_0_47
+timestamp 1606755340
+transform 1 0 5428 0 -1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[4\]
+timestamp 1606755340
+transform 1 0 5428 0 1 1632
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_8 FILLER_0_39
+timestamp 1606755340
+transform 1 0 4692 0 -1 1632
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_2 FILLER_1_45
+timestamp 1606755340
+transform 1 0 5244 0 1 1632
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_3 PHY_4
+timestamp 1606755340
+transform 1 0 1104 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12 FILLER_2_3
+timestamp 1606755340
+transform 1 0 1380 0 -1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12 FILLER_2_15
+timestamp 1606755340
+transform 1 0 2484 0 -1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[13\]
+timestamp 1606755340
+transform 1 0 4600 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_19
+timestamp 1606755340
+transform 1 0 3956 0 -1 2720
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4 FILLER_2_27
+timestamp 1606755340
+transform 1 0 3588 0 -1 2720
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_6 FILLER_2_32
+timestamp 1606755340
+transform 1 0 4048 0 -1 2720
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_3 PHY_5
+timestamp 1606755340
+transform -1 0 5980 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[9\]
+timestamp 1606755340
+transform 1 0 4876 0 -1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_6 FILLER_2_44
+timestamp 1606755340
+transform 1 0 5152 0 -1 2720
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_3 PHY_6
+timestamp 1606755340
+transform 1 0 1104 0 1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[31\]
+timestamp 1606755340
+transform 1 0 1380 0 1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12 FILLER_3_6
+timestamp 1606755340
+transform 1 0 1656 0 1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12 FILLER_3_18
+timestamp 1606755340
+transform 1 0 2760 0 1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12 FILLER_3_30
+timestamp 1606755340
+transform 1 0 3864 0 1 2720
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_3 PHY_7
+timestamp 1606755340
+transform -1 0 5980 0 1 2720
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_8 FILLER_3_42
+timestamp 1606755340
+transform 1 0 4968 0 1 2720
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_3 PHY_8
+timestamp 1606755340
+transform 1 0 1104 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[17\]
+timestamp 1606755340
+transform 1 0 1472 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[24\]
+timestamp 1606755340
+transform 1 0 1748 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_1 FILLER_4_3
+timestamp 1606755340
+transform 1 0 1380 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4 FILLER_4_10
+timestamp 1606755340
+transform 1 0 2024 0 -1 3808
+box -38 -48 406 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[14\]
+timestamp 1606755340
+transform 1 0 2484 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[25\]
+timestamp 1606755340
+transform 1 0 2944 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[8\]
+timestamp 1606755340
+transform 1 0 3220 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_1 FILLER_4_14
+timestamp 1606755340
+transform 1 0 2392 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_2 FILLER_4_18
+timestamp 1606755340
+transform 1 0 2760 0 -1 3808
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_3 FILLER_4_35
+timestamp 1606755340
+transform 1 0 4324 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[16\]
+timestamp 1606755340
+transform 1 0 4600 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[22\]
+timestamp 1606755340
+transform 1 0 4048 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_1 FILLER_4_30
+timestamp 1606755340
+transform 1 0 3864 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_20
+timestamp 1606755340
+transform 1 0 3956 0 -1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4 FILLER_4_26
+timestamp 1606755340
+transform 1 0 3496 0 -1 3808
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_3 PHY_9
+timestamp 1606755340
+transform -1 0 5980 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[26\]
+timestamp 1606755340
+transform 1 0 5060 0 -1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2 FILLER_4_41
+timestamp 1606755340
+transform 1 0 4876 0 -1 3808
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4 FILLER_4_46
+timestamp 1606755340
+transform 1 0 5336 0 -1 3808
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_3 PHY_10
+timestamp 1606755340
+transform 1 0 1104 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[2\]
+timestamp 1606755340
+transform 1 0 1840 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[6\]
+timestamp 1606755340
+transform 1 0 1380 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_2 FILLER_5_6
+timestamp 1606755340
+transform 1 0 1656 0 1 3808
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_12 FILLER_5_11
+timestamp 1606755340
+transform 1 0 2116 0 1 3808
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_8 FILLER_5_23
+timestamp 1606755340
+transform 1 0 3220 0 1 3808
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_3 FILLER_5_31
+timestamp 1606755340
+transform 1 0 3956 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[10\]
+timestamp 1606755340
+transform 1 0 4232 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[18\]
+timestamp 1606755340
+transform 1 0 4508 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_11
+timestamp 1606755340
+transform -1 0 5980 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[29\]
+timestamp 1606755340
+transform 1 0 5336 0 1 3808
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_1 FILLER_5_49
+timestamp 1606755340
+transform 1 0 5612 0 1 3808
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_6 FILLER_5_40
+timestamp 1606755340
+transform 1 0 4784 0 1 3808
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_3 PHY_12
+timestamp 1606755340
+transform 1 0 1104 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_14
+timestamp 1606755340
+transform 1 0 1104 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[19\]
+timestamp 1606755340
+transform 1 0 1932 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_8 FILLER_6_12
+timestamp 1606755340
+transform 1 0 2208 0 -1 4896
+box -38 -48 774 592
+use sky130_fd_sc_hd__decap_6 FILLER_6_3
+timestamp 1606755340
+transform 1 0 1380 0 -1 4896
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_12 FILLER_7_3
+timestamp 1606755340
+transform 1 0 1380 0 1 4896
+box -38 -48 1142 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[21\]
+timestamp 1606755340
+transform 1 0 3404 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[30\]
+timestamp 1606755340
+transform 1 0 3036 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_1 FILLER_6_20
+timestamp 1606755340
+transform 1 0 2944 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__fill_1 FILLER_6_24
+timestamp 1606755340
+transform 1 0 3312 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_12 FILLER_7_15
+timestamp 1606755340
+transform 1 0 2484 0 1 4896
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_3 FILLER_6_28
+timestamp 1606755340
+transform 1 0 3680 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[12\]
+timestamp 1606755340
+transform 1 0 4508 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[5\]
+timestamp 1606755340
+transform 1 0 4140 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_1 FILLER_6_36
+timestamp 1606755340
+transform 1 0 4416 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_21
+timestamp 1606755340
+transform 1 0 3956 0 -1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4 FILLER_6_32
+timestamp 1606755340
+transform 1 0 4048 0 -1 4896
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_6 FILLER_7_27
+timestamp 1606755340
+transform 1 0 3588 0 1 4896
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_6 FILLER_7_36
+timestamp 1606755340
+transform 1 0 4416 0 1 4896
+box -38 -48 590 592
+use sky130_fd_sc_hd__decap_3 PHY_13
+timestamp 1606755340
+transform -1 0 5980 0 -1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_3 PHY_15
+timestamp 1606755340
+transform -1 0 5980 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__conb_1 mask_rev_value\[23\]
+timestamp 1606755340
+transform 1 0 5060 0 1 4896
+box -38 -48 314 592
+use sky130_fd_sc_hd__fill_1 FILLER_7_42
+timestamp 1606755340
+transform 1 0 4968 0 1 4896
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_8 FILLER_6_40
+timestamp 1606755340
+transform 1 0 4784 0 -1 4896
+box -38 -48 774 592
+use sky130_fd_sc_hd__fill_2 FILLER_6_48
+timestamp 1606755340
+transform 1 0 5520 0 -1 4896
+box -38 -48 222 592
+use sky130_fd_sc_hd__decap_4 FILLER_7_46
+timestamp 1606755340
+transform 1 0 5336 0 1 4896
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_3 PHY_16
+timestamp 1606755340
+transform 1 0 1104 0 -1 5984
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_12 FILLER_8_3
+timestamp 1606755340
+transform 1 0 1380 0 -1 5984
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_12 FILLER_8_15
+timestamp 1606755340
+transform 1 0 2484 0 -1 5984
+box -38 -48 1142 592
+use sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_22
+timestamp 1606755340
+transform 1 0 3956 0 -1 5984
+box -38 -48 130 592
+use sky130_fd_sc_hd__decap_4 FILLER_8_27
+timestamp 1606755340
+transform 1 0 3588 0 -1 5984
+box -38 -48 406 592
+use sky130_fd_sc_hd__decap_12 FILLER_8_32
+timestamp 1606755340
+transform 1 0 4048 0 -1 5984
+box -38 -48 1142 592
+use sky130_fd_sc_hd__decap_3 PHY_17
+timestamp 1606755340
+transform -1 0 5980 0 -1 5984
+box -38 -48 314 592
+use sky130_fd_sc_hd__decap_6 FILLER_8_44
+timestamp 1606755340
+transform 1 0 5152 0 -1 5984
+box -38 -48 590 592
+<< labels >>
+rlabel metal2 s 4066 6277 4122 7077 4 mask_rev[0]
+port 1 nsew
+rlabel metal2 s 4066 0 4122 800 4 mask_rev[10]
+port 2 nsew
+rlabel metal2 s 1122 0 1178 800 4 mask_rev[11]
+port 3 nsew
+rlabel metal2 s 570 0 626 800 4 mask_rev[12]
+port 4 nsew
+rlabel metal2 s 5354 6277 5410 7077 4 mask_rev[13]
+port 5 nsew
+rlabel metal2 s 5906 0 5962 800 4 mask_rev[14]
+port 6 nsew
+rlabel metal3 s 6309 1640 7109 1760 4 mask_rev[15]
+port 7 nsew
+rlabel metal2 s 2226 0 2282 800 4 mask_rev[16]
+port 8 nsew
+rlabel metal2 s 1674 6277 1730 7077 4 mask_rev[17]
+port 9 nsew
+rlabel metal3 s 0 5176 800 5296 4 mask_rev[18]
+port 10 nsew
+rlabel metal2 s 2962 6277 3018 7077 4 mask_rev[19]
+port 11 nsew
+rlabel metal3 s 0 3272 800 3392 4 mask_rev[1]
+port 12 nsew
+rlabel metal3 s 6309 2456 7109 2576 4 mask_rev[20]
+port 13 nsew
+rlabel metal3 s 6309 824 7109 944 4 mask_rev[21]
+port 14 nsew
+rlabel metal3 s 0 5992 800 6112 4 mask_rev[22]
+port 15 nsew
+rlabel metal2 s 1674 0 1730 800 4 mask_rev[23]
+port 16 nsew
+rlabel metal2 s 5906 6277 5962 7077 4 mask_rev[24]
+port 17 nsew
+rlabel metal3 s 0 1640 800 1760 4 mask_rev[25]
+port 18 nsew
+rlabel metal2 s 4802 6277 4858 7077 4 mask_rev[26]
+port 19 nsew
+rlabel metal2 s 1122 6277 1178 7077 4 mask_rev[27]
+port 20 nsew
+rlabel metal2 s 6458 6277 6514 7077 4 mask_rev[28]
+port 21 nsew
+rlabel metal2 s 5354 0 5410 800 4 mask_rev[29]
+port 22 nsew
+rlabel metal3 s 0 2456 800 2576 4 mask_rev[2]
+port 23 nsew
+rlabel metal3 s 6309 5176 7109 5296 4 mask_rev[30]
+port 24 nsew
+rlabel metal2 s 2962 0 3018 800 4 mask_rev[31]
+port 25 nsew
+rlabel metal2 s 3514 0 3570 800 4 mask_rev[3]
+port 26 nsew
+rlabel metal3 s 6309 3544 7109 3664 4 mask_rev[4]
+port 27 nsew
+rlabel metal3 s 6309 4360 7109 4480 4 mask_rev[5]
+port 28 nsew
+rlabel metal3 s 0 4360 800 4480 4 mask_rev[6]
+port 29 nsew
+rlabel metal2 s 3514 6277 3570 7077 4 mask_rev[7]
+port 30 nsew
+rlabel metal2 s 4802 0 4858 800 4 mask_rev[8]
+port 31 nsew
+rlabel metal2 s 2226 6277 2282 7077 4 mask_rev[9]
+port 32 nsew
+rlabel metal5 s 1104 1696 5980 2016 4 VPWR
+port 33 nsew
+rlabel metal5 s 1104 2512 5980 2832 4 VGND
+port 34 nsew
+<< properties >>
+string FIXED_BBOX 0 0 7109 7077
+string GDS_FILE ../gds/user_id_programming.gds
+string GDS_START 0
+<< end >>
diff --git a/mag/user_id_textblock.mag b/mag/user_id_textblock.mag
new file mode 100644
index 0000000..8917f0a
--- /dev/null
+++ b/mag/user_id_textblock.mag
@@ -0,0 +1,43 @@
+magic
+tech sky130A
+timestamp 1608324878
+<< checkpaint >>
+rect 1495 5490 6500 6570
+rect -630 428 19262 5490
+rect -630 -630 6210 428
+rect 16092 356 18972 428
+<< fillblock >>
+rect -328 754 16860 5172
+use alpha_0 alphaX_7 hexdigits
+timestamp 1598786981
+transform 1 0 0 0 1 1080
+box 0 0 1620 3780
+use alpha_0 alphaX_6 hexdigits
+timestamp 1598786981
+transform 1 0 2125 0 1 1080
+box 0 0 1620 3780
+use alpha_0 alphaX_5 hexdigits
+timestamp 1598786981
+transform 1 0 4250 0 1 1080
+box 0 0 1620 3780
+use alpha_2 alphaX_4 hexdigits
+timestamp 1598786981
+transform 1 0 6375 0 1 1080
+box 0 0 1620 3780
+use alpha_0 alphaX_3 hexdigits
+timestamp 1598786981
+transform 1 0 8500 0 1 1080
+box 0 0 1620 3780
+use alpha_0 alphaX_2 hexdigits
+timestamp 1598786981
+transform 1 0 10625 0 1 1080
+box 0 0 1620 3780
+use alpha_0 alphaX_1 hexdigits
+timestamp 1598786981
+transform 1 0 12750 0 1 1080
+box 0 0 1620 3780
+use alpha_6 alphaX_0 hexdigits
+timestamp 1598786981
+transform 1 0 14887 0 1 1080
+box 0 0 1620 3780
+<< end >>
diff --git a/signoff/.gitignore b/signoff/.gitignore
new file mode 100644
index 0000000..6407046
--- /dev/null
+++ b/signoff/.gitignore
@@ -0,0 +1 @@
+cdrcpost/*
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
new file mode 100644
index 0000000..5761ac9
--- /dev/null
+++ b/verilog/rtl/caravel.v
@@ -0,0 +1,817 @@
+// `default_nettype none
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+/*--------------------------------------------------------------*/
+/* caravel, a project harness for the Google/SkyWater sky130 */
+/* fabrication process and open source PDK */
+/* */
+/* Copyright 2020 efabless, Inc. */
+/* Written by Tim Edwards, December 2019 */
+/* and Mohamed Shalan, August 2020 */
+/* This file is open source hardware released under the */
+/* Apache 2.0 license. See file LICENSE. */
+/* */
+/*--------------------------------------------------------------*/
+
+module caravel (
+ inout vddio, // Common 3.3V padframe/ESD power
+ inout vddio_2, // Common 3.3V padframe/ESD power
+ inout vssio, // Common padframe/ESD ground
+ inout vssio_2, // Common padframe/ESD ground
+ inout vdda, // Management 3.3V power
+ inout vssa, // Common analog ground
+ inout vccd, // Management/Common 1.8V power
+ inout vssd, // Common digital ground
+ inout vdda1, // User area 1 3.3V power
+ inout vdda1_2, // User area 1 3.3V power
+ inout vdda2, // User area 2 3.3V power
+ inout vssa1, // User area 1 analog ground
+ inout vssa1_2, // User area 1 analog ground
+ inout vssa2, // User area 2 analog ground
+ inout vccd1, // User area 1 1.8V power
+ inout vccd2, // User area 2 1.8V power
+ inout vssd1, // User area 1 digital ground
+ inout vssd2, // User area 2 digital ground
+
+ inout gpio, // Used for external LDO control
+ inout [`MPRJ_IO_PADS-1:0] mprj_io,
+ output [`MPRJ_PWR_PADS-1:0] pwr_ctrl_out,
+ input clock, // CMOS core clock input, not a crystal
+ input resetb,
+
+ // Note that only two pins are available on the flash so dual and
+ // quad flash modes are not available.
+
+ output flash_csb,
+ output flash_clk,
+ output flash_io0,
+ output flash_io1
+);
+
+ //------------------------------------------------------------
+ // This value is uniquely defined for each user project.
+ //------------------------------------------------------------
+ parameter USER_PROJECT_ID = 32'h00020006;
+
+ // These pins are overlaid on mprj_io space. They have the function
+ // below when the management processor is in reset, or in the default
+ // configuration. They are assigned to uses in the user space by the
+ // configuration program running off of the SPI flash. Note that even
+ // when the user has taken control of these pins, they can be restored
+ // to the original use by setting the resetb pin low. The SPI pins and
+ // UART pins can be connected directly to an FTDI chip as long as the
+ // FTDI chip sets these lines to high impedence (input function) at
+ // all times except when holding the chip in reset.
+
+ // JTAG = mprj_io[0] (inout)
+ // SDO = mprj_io[1] (output)
+ // SDI = mprj_io[2] (input)
+ // CSB = mprj_io[3] (input)
+ // SCK = mprj_io[4] (input)
+ // ser_rx = mprj_io[5] (input)
+ // ser_tx = mprj_io[6] (output)
+ // irq = mprj_io[7] (input)
+
+ // These pins are reserved for any project that wants to incorporate
+ // its own processor and flash controller. While a user project can
+ // technically use any available I/O pins for the purpose, these
+ // four pins connect to a pass-through mode from the SPI slave (pins
+ // 1-4 above) so that any SPI flash connected to these specific pins
+ // can be accessed through the SPI slave even when the processor is in
+ // reset.
+
+ // user_flash_csb = mprj_io[8]
+ // user_flash_sck = mprj_io[9]
+ // user_flash_io0 = mprj_io[10]
+ // user_flash_io1 = mprj_io[11]
+
+ // One-bit GPIO dedicated to management SoC (outside of user control)
+ wire gpio_out_core;
+ wire gpio_in_core;
+ wire gpio_mode0_core;
+ wire gpio_mode1_core;
+ wire gpio_outenb_core;
+ wire gpio_inenb_core;
+
+ // User Project Control (pad-facing)
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_oeb;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_vtrip_sel;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_slow_sel;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_holdover;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_en;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol;
+ wire [`MPRJ_IO_PADS*3-1:0] mprj_io_dm;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_in;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_out;
+
+ // User Project Control (user-facing)
+ wire [`MPRJ_IO_PADS-1:0] user_io_oeb;
+ wire [`MPRJ_IO_PADS-1:0] user_io_in;
+ wire [`MPRJ_IO_PADS-1:0] user_io_out;
+ wire [`MPRJ_IO_PADS-10:0] user_analog_io;
+
+ /* Padframe control signals */
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_serial_link_1;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_serial_link_2;
+ wire mprj_io_loader_resetn;
+ wire mprj_io_loader_clock;
+ wire mprj_io_loader_data_1; /* user1 side serial loader */
+ wire mprj_io_loader_data_2; /* user2 side serial loader */
+
+ // User Project Control management I/O
+ // There are two types of GPIO connections:
+ // (1) Full Bidirectional: Management connects to in, out, and oeb
+ // Uses: JTAG and SDO
+ // (2) Selectable bidirectional: Management connects to in and out,
+ // which are tied together. oeb is grounded (oeb from the
+ // configuration is used)
+
+ // SDI = mprj_io[2] (input)
+ // CSB = mprj_io[3] (input)
+ // SCK = mprj_io[4] (input)
+ // ser_rx = mprj_io[5] (input)
+ // ser_tx = mprj_io[6] (output)
+ // irq = mprj_io[7] (input)
+
+ wire [`MPRJ_IO_PADS-1:0] mgmt_io_in;
+ wire jtag_out, sdo_out;
+ wire jtag_outenb, sdo_outenb;
+ wire gpio_flash_io2_out, gpio_flash_io3_out;
+
+ wire [1:0] mgmt_io_nc; /* no-connects */
+
+ wire clock_core;
+
+ // Power-on-reset signal. The reset pad generates the sense-inverted
+ // reset at 3.3V. The 1.8V signal and the inverted 1.8V signal are
+ // derived.
+
+ wire porb_h;
+ wire porb_l;
+ wire por_l;
+
+ wire rstb_h;
+ wire rstb_l;
+
+ wire flash_clk_core, flash_csb_core;
+ wire flash_clk_oeb_core, flash_csb_oeb_core;
+ wire flash_clk_ieb_core, flash_csb_ieb_core;
+ wire flash_io0_oeb_core, flash_io1_oeb_core;
+ wire flash_io2_oeb_core, flash_io3_oeb_core;
+ wire flash_io0_ieb_core, flash_io1_ieb_core;
+ wire flash_io0_do_core, flash_io1_do_core;
+ wire flash_io0_di_core, flash_io1_di_core;
+
+ chip_io padframe(
+ `ifndef TOP_ROUTING
+ // Package Pins
+ .vddio_pad (vddio), // Common padframe/ESD supply
+ .vddio_pad2 (vddio_2),
+ .vssio_pad (vssio), // Common padframe/ESD ground
+ .vssio_pad2 (vssio_2),
+ .vccd_pad (vccd), // Common 1.8V supply
+ .vssd_pad (vssd), // Common digital ground
+ .vdda_pad (vdda), // Management analog 3.3V supply
+ .vssa_pad (vssa), // Management analog ground
+ .vdda1_pad (vdda1), // User area 1 3.3V supply
+ .vdda1_pad2 (vdda1_2),
+ .vdda2_pad (vdda2), // User area 2 3.3V supply
+ .vssa1_pad (vssa1), // User area 1 analog ground
+ .vssa1_pad2 (vssa1_2),
+ .vssa2_pad (vssa2), // User area 2 analog ground
+ .vccd1_pad (vccd1), // User area 1 1.8V supply
+ .vccd2_pad (vccd2), // User area 2 1.8V supply
+ .vssd1_pad (vssd1), // User area 1 digital ground
+ .vssd2_pad (vssd2), // User area 2 digital ground
+ `endif
+ // Core Side Pins
+ .vddio (vddio_core),
+ .vssio (vssio_core),
+ .vdda (vdda_core),
+ .vssa (vssa_core),
+ .vccd (vccd_core),
+ .vssd (vssd_core),
+ .vdda1 (vdda1_core),
+ .vdda2 (vdda2_core),
+ .vssa1 (vssa1_core),
+ .vssa2 (vssa2_core),
+ .vccd1 (vccd1_core),
+ .vccd2 (vccd2_core),
+ .vssd1 (vssd1_core),
+ .vssd2 (vssd2_core),
+
+ .gpio(gpio),
+ .mprj_io(mprj_io),
+ .clock(clock),
+ .resetb(resetb),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ // SoC Core Interface
+ .porb_h(porb_h),
+ .por(por_l),
+ .resetb_core_h(rstb_h),
+ .clock_core(clock_core),
+ .gpio_out_core(gpio_out_core),
+ .gpio_in_core(gpio_in_core),
+ .gpio_mode0_core(gpio_mode0_core),
+ .gpio_mode1_core(gpio_mode1_core),
+ .gpio_outenb_core(gpio_outenb_core),
+ .gpio_inenb_core(gpio_inenb_core),
+ .flash_csb_core(flash_csb_core),
+ .flash_clk_core(flash_clk_core),
+ .flash_csb_oeb_core(flash_csb_oeb_core),
+ .flash_clk_oeb_core(flash_clk_oeb_core),
+ .flash_io0_oeb_core(flash_io0_oeb_core),
+ .flash_io1_oeb_core(flash_io1_oeb_core),
+ .flash_csb_ieb_core(flash_csb_ieb_core),
+ .flash_clk_ieb_core(flash_clk_ieb_core),
+ .flash_io0_ieb_core(flash_io0_ieb_core),
+ .flash_io1_ieb_core(flash_io1_ieb_core),
+ .flash_io0_do_core(flash_io0_do_core),
+ .flash_io1_do_core(flash_io1_do_core),
+ .flash_io0_di_core(flash_io0_di_core),
+ .flash_io1_di_core(flash_io1_di_core),
+ .mprj_io_in(mprj_io_in),
+ .mprj_io_out(mprj_io_out),
+ .mprj_io_oeb(mprj_io_oeb),
+ .mprj_io_inp_dis(mprj_io_inp_dis),
+ .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
+ .mprj_io_vtrip_sel(mprj_io_vtrip_sel),
+ .mprj_io_slow_sel(mprj_io_slow_sel),
+ .mprj_io_holdover(mprj_io_holdover),
+ .mprj_io_analog_en(mprj_io_analog_en),
+ .mprj_io_analog_sel(mprj_io_analog_sel),
+ .mprj_io_analog_pol(mprj_io_analog_pol),
+ .mprj_io_dm(mprj_io_dm),
+ .mprj_analog_io(user_analog_io)
+ );
+
+ // SoC core
+ wire caravel_clk;
+ wire caravel_clk2;
+ wire caravel_rstn;
+
+ wire [7:0] spi_ro_config_core;
+
+ // LA signals
+ wire [127:0] la_data_in_user; // From CPU to MPRJ
+ wire [127:0] la_data_in_mprj; // From MPRJ to CPU
+ wire [127:0] la_data_out_mprj; // From CPU to MPRJ
+ wire [127:0] la_data_out_user; // From MPRJ to CPU
+ wire [127:0] la_oenb_user; // From CPU to MPRJ
+ wire [127:0] la_oenb_mprj; // From CPU to MPRJ
+ wire [127:0] la_iena_mprj; // From CPU only
+ wire [2:0] user_irq; // From MRPJ to CPU
+ wire [2:0] user_irq_core;
+ wire [2:0] user_irq_ena;
+
+ // WB MI A (User Project)
+ wire mprj_cyc_o_core;
+ wire mprj_stb_o_core;
+ wire mprj_we_o_core;
+ wire [3:0] mprj_sel_o_core;
+ wire [31:0] mprj_adr_o_core;
+ wire [31:0] mprj_dat_o_core;
+ wire mprj_ack_i_core;
+ wire [31:0] mprj_dat_i_core;
+
+ // WB MI B (xbar)
+ wire xbar_cyc_o_core;
+ wire xbar_stb_o_core;
+ wire xbar_we_o_core;
+ wire [3:0] xbar_sel_o_core;
+ wire [31:0] xbar_adr_o_core;
+ wire [31:0] xbar_dat_o_core;
+ wire xbar_ack_i_core;
+ wire [31:0] xbar_dat_i_core;
+
+ // Mask revision
+ wire [31:0] mask_rev;
+
+ wire mprj_clock;
+ wire mprj_clock2;
+ wire mprj_reset;
+ wire mprj_cyc_o_user;
+ wire mprj_stb_o_user;
+ wire mprj_we_o_user;
+ wire [3:0] mprj_sel_o_user;
+ wire [31:0] mprj_adr_o_user;
+ wire [31:0] mprj_dat_o_user;
+ wire mprj_vcc_pwrgood;
+ wire mprj2_vcc_pwrgood;
+ wire mprj_vdd_pwrgood;
+ wire mprj2_vdd_pwrgood;
+
+ // Storage area
+ // Management R/W interface
+ wire [`RAM_BLOCKS-1:0] mgmt_ena;
+ wire [`RAM_BLOCKS-1:0] mgmt_wen;
+ wire [(`RAM_BLOCKS*4)-1:0] mgmt_wen_mask;
+ wire [7:0] mgmt_addr;
+ wire [31:0] mgmt_wdata;
+ wire [(`RAM_BLOCKS*32)-1:0] mgmt_rdata;
+ // Management RO interface
+ wire mgmt_ena_ro;
+ wire [7:0] mgmt_addr_ro;
+ wire [31:0] mgmt_rdata_ro;
+
+ mgmt_core soc (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ // GPIO (1 pin)
+ .gpio_out_pad(gpio_out_core),
+ .gpio_in_pad(gpio_in_core),
+ .gpio_mode0_pad(gpio_mode0_core),
+ .gpio_mode1_pad(gpio_mode1_core),
+ .gpio_outenb_pad(gpio_outenb_core),
+ .gpio_inenb_pad(gpio_inenb_core),
+ // Primary SPI flash controller
+ .flash_csb(flash_csb_core),
+ .flash_clk(flash_clk_core),
+ .flash_csb_oeb(flash_csb_oeb_core),
+ .flash_clk_oeb(flash_clk_oeb_core),
+ .flash_io0_oeb(flash_io0_oeb_core),
+ .flash_io1_oeb(flash_io1_oeb_core),
+ .flash_csb_ieb(flash_csb_ieb_core),
+ .flash_clk_ieb(flash_clk_ieb_core),
+ .flash_io0_ieb(flash_io0_ieb_core),
+ .flash_io1_ieb(flash_io1_ieb_core),
+ .flash_io0_do(flash_io0_do_core),
+ .flash_io1_do(flash_io1_do_core),
+ .flash_io0_di(flash_io0_di_core),
+ .flash_io1_di(flash_io1_di_core),
+ // Master Reset
+ .resetb(rstb_l),
+ .porb(porb_l),
+ // Clocks and reset
+ .clock(clock_core),
+ .core_clk(caravel_clk),
+ .user_clk(caravel_clk2),
+ .core_rstn(caravel_rstn),
+ // IRQ
+ .user_irq(user_irq),
+ .user_irq_ena(user_irq_ena),
+ // Logic Analyzer
+ .la_input(la_data_in_mprj),
+ .la_output(la_data_out_mprj),
+ .la_oenb(la_oenb_mprj),
+ .la_iena(la_iena_mprj),
+ // User Project IO Control
+ .mprj_vcc_pwrgood(mprj_vcc_pwrgood),
+ .mprj2_vcc_pwrgood(mprj2_vcc_pwrgood),
+ .mprj_vdd_pwrgood(mprj_vdd_pwrgood),
+ .mprj2_vdd_pwrgood(mprj2_vdd_pwrgood),
+ .mprj_io_loader_resetn(mprj_io_loader_resetn),
+ .mprj_io_loader_clock(mprj_io_loader_clock),
+ .mprj_io_loader_data_1(mprj_io_loader_data_1),
+ .mprj_io_loader_data_2(mprj_io_loader_data_2),
+ .mgmt_in_data(mgmt_io_in),
+ .mgmt_out_data({gpio_flash_io3_out, gpio_flash_io2_out,
+ mgmt_io_in[(`MPRJ_IO_PADS-3):2], mgmt_io_nc}),
+ .pwr_ctrl_out(pwr_ctrl_out),
+ .sdo_out(sdo_out),
+ .sdo_outenb(sdo_outenb),
+ .jtag_out(jtag_out),
+ .jtag_outenb(jtag_outenb),
+ .flash_io2_oeb(flash_io2_oeb_core),
+ .flash_io3_oeb(flash_io3_oeb_core),
+ // User Project Slave ports (WB MI A)
+ .mprj_cyc_o(mprj_cyc_o_core),
+ .mprj_stb_o(mprj_stb_o_core),
+ .mprj_we_o(mprj_we_o_core),
+ .mprj_sel_o(mprj_sel_o_core),
+ .mprj_adr_o(mprj_adr_o_core),
+ .mprj_dat_o(mprj_dat_o_core),
+ .mprj_ack_i(mprj_ack_i_core),
+ .mprj_dat_i(mprj_dat_i_core),
+ // mask data
+ .mask_rev(mask_rev),
+ // MGMT area R/W interface
+ .mgmt_ena(mgmt_ena),
+ .mgmt_wen_mask(mgmt_wen_mask),
+ .mgmt_wen(mgmt_wen),
+ .mgmt_addr(mgmt_addr),
+ .mgmt_wdata(mgmt_wdata),
+ .mgmt_rdata(mgmt_rdata),
+ // MGMT area RO interface
+ .mgmt_ena_ro(mgmt_ena_ro),
+ .mgmt_addr_ro(mgmt_addr_ro),
+ .mgmt_rdata_ro(mgmt_rdata_ro)
+ );
+
+ /* Clock and reset to user space are passed through a tristate */
+ /* buffer like the above, but since they are intended to be */
+ /* always active, connect the enable to the logic-1 output from */
+ /* the vccd1 domain. */
+
+ mgmt_protect mgmt_buffers (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ .vccd2(vccd2_core),
+ .vssd2(vssd2_core),
+ .vdda1(vdda1_core),
+ .vssa1(vssa1_core),
+ .vdda2(vdda2_core),
+ .vssa2(vssa2_core),
+ `endif
+ .caravel_clk(caravel_clk),
+ .caravel_clk2(caravel_clk2),
+ .caravel_rstn(caravel_rstn),
+ .mprj_cyc_o_core(mprj_cyc_o_core),
+ .mprj_stb_o_core(mprj_stb_o_core),
+ .mprj_we_o_core(mprj_we_o_core),
+ .mprj_sel_o_core(mprj_sel_o_core),
+ .mprj_adr_o_core(mprj_adr_o_core),
+ .mprj_dat_o_core(mprj_dat_o_core),
+ .user_irq_core(user_irq_core),
+ .la_data_out_core(la_data_out_user),
+ .la_data_out_mprj(la_data_out_mprj),
+ .la_data_in_core(la_data_in_user),
+ .la_data_in_mprj(la_data_in_mprj),
+ .la_oenb_mprj(la_oenb_mprj),
+ .la_oenb_core(la_oenb_user),
+ .la_iena_mprj(la_iena_mprj),
+ .user_irq_ena(user_irq_ena),
+
+ .user_clock(mprj_clock),
+ .user_clock2(mprj_clock2),
+ .user_reset(mprj_reset),
+ .mprj_cyc_o_user(mprj_cyc_o_user),
+ .mprj_stb_o_user(mprj_stb_o_user),
+ .mprj_we_o_user(mprj_we_o_user),
+ .mprj_sel_o_user(mprj_sel_o_user),
+ .mprj_adr_o_user(mprj_adr_o_user),
+ .mprj_dat_o_user(mprj_dat_o_user),
+ .user_irq(user_irq),
+ .user1_vcc_powergood(mprj_vcc_pwrgood),
+ .user2_vcc_powergood(mprj2_vcc_pwrgood),
+ .user1_vdd_powergood(mprj_vdd_pwrgood),
+ .user2_vdd_powergood(mprj2_vdd_pwrgood)
+ );
+
+
+ /*----------------------------------------------*/
+ /* Wrapper module around the user project */
+ /*----------------------------------------------*/
+
+ user_project_wrapper mprj (
+ `ifdef USE_POWER_PINS
+ .vdda1(vdda1_core), // User area 1 3.3V power
+ .vdda2(vdda2_core), // User area 2 3.3V power
+ .vssa1(vssa1_core), // User area 1 analog ground
+ .vssa2(vssa2_core), // User area 2 analog ground
+ .vccd1(vccd1_core), // User area 1 1.8V power
+ .vccd2(vccd2_core), // User area 2 1.8V power
+ .vssd1(vssd1_core), // User area 1 digital ground
+ .vssd2(vssd2_core), // User area 2 digital ground
+ `endif
+
+ .wb_clk_i(mprj_clock),
+ .wb_rst_i(mprj_reset),
+ // MGMT SoC Wishbone Slave
+ .wbs_cyc_i(mprj_cyc_o_user),
+ .wbs_stb_i(mprj_stb_o_user),
+ .wbs_we_i(mprj_we_o_user),
+ .wbs_sel_i(mprj_sel_o_user),
+ .wbs_adr_i(mprj_adr_o_user),
+ .wbs_dat_i(mprj_dat_o_user),
+ .wbs_ack_o(mprj_ack_i_core),
+ .wbs_dat_o(mprj_dat_i_core),
+ // Logic Analyzer
+ .la_data_in(la_data_in_user),
+ .la_data_out(la_data_out_user),
+ .la_oenb(la_oenb_user),
+ // IO Pads
+ .io_in (user_io_in),
+ .io_out(user_io_out),
+ .io_oeb(user_io_oeb),
+ .analog_io(user_analog_io),
+ // Independent clock
+ .user_clock2(mprj_clock2),
+ // IRQ
+ .user_irq(user_irq_core)
+ );
+
+ /*--------------------------------------*/
+ /* End user project instantiation */
+ /*--------------------------------------*/
+
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_serial_link_1_shifted;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_serial_link_2_shifted;
+
+ assign gpio_serial_link_1_shifted = {gpio_serial_link_1[`MPRJ_IO_PADS_1-2:0],
+ mprj_io_loader_data_1};
+ // Note that serial_link_2 is backwards compared to serial_link_1, so it
+ // shifts in the other direction.
+ assign gpio_serial_link_2_shifted = {mprj_io_loader_data_2,
+ gpio_serial_link_2[`MPRJ_IO_PADS_2-1:1]};
+
+ // Propagating clock and reset to mitigate timing and fanout issues
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_clock_1;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_clock_2;
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_resetn_1;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_resetn_2;
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_clock_1_shifted;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_clock_2_shifted;
+ wire [`MPRJ_IO_PADS_1-1:0] gpio_resetn_1_shifted;
+ wire [`MPRJ_IO_PADS_2-1:0] gpio_resetn_2_shifted;
+
+ assign gpio_clock_1_shifted = {gpio_clock_1[`MPRJ_IO_PADS_1-2:0],
+ mprj_io_loader_clock};
+ assign gpio_clock_2_shifted = {mprj_io_loader_clock,
+ gpio_clock_2[`MPRJ_IO_PADS_2-1:1]};
+ assign gpio_resetn_1_shifted = {gpio_resetn_1[`MPRJ_IO_PADS_1-2:0],
+ mprj_io_loader_resetn};
+ assign gpio_resetn_2_shifted = {mprj_io_loader_resetn,
+ gpio_resetn_2[`MPRJ_IO_PADS_2-1:1]};
+
+ // Each control block sits next to an I/O pad in the user area.
+ // It gets input through a serial chain from the previous control
+ // block and passes it to the next control block. Due to the nature
+ // of the shift register, bits are presented in reverse, as the first
+ // bit in ends up as the last bit of the last I/O pad control block.
+
+ // There are two types of block; the first two and the last two
+ // are configured to be full bidirectional under control of the
+ // management Soc (JTAG and SDO for the first two; flash_io2 and
+ // flash_io3 for the last two). The rest are configured to be default
+ // (input). Note that the first two and last two are the ones closest
+ // to the management SoC on either side, which minimizes the wire length
+ // of the extra signals those pads need.
+
+ /* First two GPIOs (JTAG and SDO) */
+ gpio_control_block #(
+ .DM_INIT(`DM_INIT), // Mode = output, strong up/down
+ .OENB_INIT(`OENB_INIT) // Enable output signaling from wire
+ ) gpio_control_bidir_1 [1:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_1_shifted[1:0]),
+ .serial_clock(gpio_clock_1_shifted[1:0]),
+
+ .resetn_out(gpio_resetn_1[1:0]),
+ .serial_clock_out(gpio_clock_1[1:0]),
+
+ .mgmt_gpio_in(mgmt_io_in[1:0]),
+ .mgmt_gpio_out({sdo_out, jtag_out}),
+ .mgmt_gpio_oeb({sdo_outenb, jtag_outenb}),
+
+ .one(),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_1_shifted[1:0]),
+ .serial_data_out(gpio_serial_link_1[1:0]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[1:0]),
+ .user_gpio_oeb(user_io_oeb[1:0]),
+ .user_gpio_in(user_io_in[1:0]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[1:0]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[1:0]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[1:0]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[1:0]),
+ .pad_gpio_holdover(mprj_io_holdover[1:0]),
+ .pad_gpio_ana_en(mprj_io_analog_en[1:0]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[1:0]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[1:0]),
+ .pad_gpio_dm(mprj_io_dm[5:0]),
+ .pad_gpio_outenb(mprj_io_oeb[1:0]),
+ .pad_gpio_out(mprj_io_out[1:0]),
+ .pad_gpio_in(mprj_io_in[1:0])
+ );
+
+ /* Section 1 GPIOs (GPIO 0 to 18) */
+ wire [`MPRJ_IO_PADS_1-1:2] one_loop1;
+ gpio_control_block gpio_control_in_1 [`MPRJ_IO_PADS_1-3:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_1_shifted[(`MPRJ_IO_PADS_1-1):2]),
+ .serial_clock(gpio_clock_1_shifted[(`MPRJ_IO_PADS_1-1):2]),
+
+ .resetn_out(gpio_resetn_1[(`MPRJ_IO_PADS_1-1):2]),
+ .serial_clock_out(gpio_clock_1[(`MPRJ_IO_PADS_1-1):2]),
+
+ .mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS_1-1):2]),
+ .mgmt_gpio_out(mgmt_io_in[(`MPRJ_IO_PADS_1-1):2]),
+ .mgmt_gpio_oeb(one_loop1),
+
+ .one(one_loop1),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_1_shifted[(`MPRJ_IO_PADS_1-1):2]),
+ .serial_data_out(gpio_serial_link_1[(`MPRJ_IO_PADS_1-1):2]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[(`MPRJ_IO_PADS_1-1):2]),
+ .user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS_1-1):2]),
+ .user_gpio_in(user_io_in[(`MPRJ_IO_PADS_1-1):2]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS_1-1):2]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS_1-1):2]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS_1-1):2]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS_1-1):2]),
+ .pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS_1-1):2]),
+ .pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS_1-1):2]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS_1-1):2]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS_1-1):2]),
+ .pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS_1*3-1):6]),
+ .pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS_1-1):2]),
+ .pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS_1-1):2]),
+ .pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS_1-1):2])
+ );
+
+ /* Last two GPIOs (flash_io2 and flash_io3) */
+ gpio_control_block #(
+ .DM_INIT(`DM_INIT), // Mode = output, strong up/down
+ .OENB_INIT(`OENB_INIT) // Enable output signaling from wire
+ ) gpio_control_bidir_2 [1:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_1_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-2)]),
+ .serial_clock(gpio_clock_1_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-2)]),
+
+ .resetn_out(gpio_resetn_1[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-2)]),
+ .serial_clock_out(gpio_clock_1[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-2)]),
+
+ .mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)]),
+ .mgmt_gpio_out({gpio_flash_io3_out, gpio_flash_io2_out}),
+ .mgmt_gpio_oeb({flash_io3_oeb_core, flash_io2_oeb_core}),
+
+ .one(),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_2_shifted[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-2)]),
+ .serial_data_out(gpio_serial_link_2[(`MPRJ_IO_PADS_2-1):(`MPRJ_IO_PADS_2-2)]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)]),
+ .user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)]),
+ .user_gpio_in(user_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)]),
+ .pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)]),
+ .pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)]),
+ .pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS*3-1):(`MPRJ_IO_PADS*3-6)]),
+ .pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)]),
+ .pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)]),
+ .pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS-1):(`MPRJ_IO_PADS-2)])
+ );
+
+ /* Section 2 GPIOs (GPIO 19 to 37) */
+ wire [`MPRJ_IO_PADS_2-3:0] one_loop2;
+ gpio_control_block gpio_control_in_2 [`MPRJ_IO_PADS_2-3:0] (
+ `ifdef USE_POWER_PINS
+ .vccd(vccd_core),
+ .vssd(vssd_core),
+ .vccd1(vccd1_core),
+ .vssd1(vssd1_core),
+ `endif
+
+ // Management Soc-facing signals
+
+ .resetn(gpio_resetn_1_shifted[(`MPRJ_IO_PADS_2-3):0]),
+ .serial_clock(gpio_clock_1_shifted[(`MPRJ_IO_PADS_2-3):0]),
+
+ .resetn_out(gpio_resetn_1[(`MPRJ_IO_PADS_2-3):0]),
+ .serial_clock_out(gpio_clock_1[(`MPRJ_IO_PADS_2-3):0]),
+
+ .mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+ .mgmt_gpio_out(mgmt_io_in[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+ .mgmt_gpio_oeb(one_loop2),
+
+ .one(one_loop2),
+ .zero(),
+
+ // Serial data chain for pad configuration
+ .serial_data_in(gpio_serial_link_2_shifted[(`MPRJ_IO_PADS_2-3):0]),
+ .serial_data_out(gpio_serial_link_2[(`MPRJ_IO_PADS_2-3):0]),
+
+ // User-facing signals
+ .user_gpio_out(user_io_out[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+ .user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+ .user_gpio_in(user_io_in[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+
+ // Pad-facing signals (Pad GPIOv2)
+ .pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS*3-7):(`MPRJ_IO_PADS_1*3)]),
+ .pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)]),
+ .pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS-3):(`MPRJ_IO_PADS_1)])
+ );
+
+ user_id_programming #(
+ .USER_PROJECT_ID(USER_PROJECT_ID)
+ ) user_id_value (
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .mask_rev(mask_rev)
+ );
+
+ // Power-on-reset circuit
+ simple_por por (
+ `ifdef USE_POWER_PINS
+ .vdd3v3(vddio_core),
+ .vdd1v8(vccd_core),
+ .vss(vssio_core),
+ `endif
+ .porb_h(porb_h),
+ .porb_l(porb_l),
+ .por_l(por_l)
+ );
+
+ // XRES (chip input pin reset) reset level converter
+ sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped rstb_level (
+ `ifdef USE_POWER_PINS
+ .VPWR(vddio_core),
+ .LVPWR(vccd_core),
+ .VGND(vssio_core),
+ `endif
+ .A(rstb_h),
+ .X(rstb_l)
+ );
+
+ // Storage area
+ storage storage(
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd_core),
+ .VGND(vssd_core),
+ `endif
+ .mgmt_clk(caravel_clk),
+ .mgmt_ena(mgmt_ena),
+ .mgmt_wen(mgmt_wen),
+ .mgmt_wen_mask(mgmt_wen_mask),
+ .mgmt_addr(mgmt_addr),
+ .mgmt_wdata(mgmt_wdata),
+ .mgmt_rdata(mgmt_rdata),
+ // Management RO interface
+ .mgmt_ena_ro(mgmt_ena_ro),
+ .mgmt_addr_ro(mgmt_addr_ro),
+ .mgmt_rdata_ro(mgmt_rdata_ro)
+ );
+
+endmodule
+// `default_nettype wire
