signoff/build/gpio_defaults.out - third_party/shuttle/sky130/mpw-002/slot-006 - Git at Google

 Step 1:  Create new cells for new GPIO default vectors.
 Creating new layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag
 Creating new gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
 Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
 Step 2:  Modify top-level layouts to use the specified defaults.
 Done.
	Step 1: Create new cells for new GPIO default vectors.
	Creating new layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag
	Creating new gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Layout file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/mag/gpio_defaults_block_1800.mag already exists and does not need to be generated.
	Gate-level verilog file /mnt/shuttles/shuttle/mpw-two/slot-006/opencryo_testchip/verilog/gl/gpio_defaults_block_1800.v already exists and does not need to be generated.
	Step 2: Modify top-level layouts to use the specified defaults.
	Done.