| commit | d0db2ab1c38ab9328dc4be9db8f17b5d8de4fd50 | [log] [tgz] |
|---|---|---|
| author | nguyendao-uom <nguyen.dao@manchester.ac.uk> | Wed Dec 08 10:46:11 2021 +0000 |
| committer | nguyendao-uom <nguyen.dao@manchester.ac.uk> | Wed Dec 08 10:46:11 2021 +0000 |
| tree | 250e612f08d12cbf62559fa1b15ff2b3c042ee87 | |
| parent | 0e69303f0440fb9bf144fb71beacd6b2e4e47c48 [diff] |
update BRAM
Demonstration of the Fabulous FPGA design flow using the Skywater 130 process.
This repo experiments an implementation of an FPGA from RTL to GDS with open Skywater-130 PDK. The design RTL was generated by FABulous framework. The fabric consists of 896 LUT4s (16x7 CLBs), 64 LUT5s (16x1 RegFiles), 8 DSPs and 8 BRAMs (8x1KB) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g. to RISC-V core) were also implemented in this version.
Refer to README for this sample project documentation.