| commit | 0e69303f0440fb9bf144fb71beacd6b2e4e47c48 | [log] [tgz] |
|---|---|---|
| author | nguyendao-uom <nguyen.dao@manchester.ac.uk> | Mon Dec 06 22:27:40 2021 +0000 |
| committer | nguyendao-uom <nguyen.dao@manchester.ac.uk> | Mon Dec 06 22:27:40 2021 +0000 |
| tree | 1f8e8bd7346e91df616d5afdb9f0a4fe5f22f9c7 | |
| parent | 0d35122d70bbf0b7cf00bd9ed6dc116b8a91e38b [diff] |
update gds
Demonstration of the Fabulous FPGA design flow using the Skywater 130 process.
This repo experiments an implementation of an FPGA from RTL to GDS with open Skywater-130 PDK. The design RTL was generated by FABulous framework. The fabric consists of 896 LUT4s (16x7 CLBs), 64 LUT5s (16x1 RegFiles), 8 DSPs and 8 BRAMs (8x1KB) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g. to RISC-V core) were also implemented in this version.
Refer to README for this sample project documentation.