| commit | 05a1d444b7f4a87bd5d7d8ecffd5054b0c185405 | [log] [tgz] |
|---|---|---|
| author | Jeff DiCorpo <jeffdi@efabless.com> | Fri Dec 10 03:58:34 2021 +0000 |
| committer | Jeff DiCorpo <jeffdi@efabless.com> | Fri Dec 10 03:58:34 2021 +0000 |
| tree | eefd0642846265524eef7dac7e3071b2093ef4c7 | |
| parent | 449eac864ec254feaf2d4bf7147c950db806b0e4 [diff] |
final gds oasis
Demonstration of the Fabulous FPGA design flow using the Skywater 130 process.
This repo experiments an implementation of an FPGA from RTL to GDS with open Skywater-130 PDK. The design RTL was generated by FABulous framework. The fabric consists of 896 LUT4s (16x7 CLBs), 64 LUT5s (16x1 RegFiles), 8 DSPs and 8 BRAMs (8x1KB) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g. to RISC-V core) were also implemented in this version.
Refer to README for this sample project documentation.