commit: 91d7c5ec826ad7c0c29ada3b13ee4cd11c3963db
[log]
author: Jeff DiCorpo <jeffdi@efabless.com>
Sun Jul 18 01:32:04 2021 +0000
committer: Jeff DiCorpo <jeffdi@efabless.com>
Sun Jul 18 01:32:04 2021 +0000
tree: fcaa4b3d74fbfb841c235f36397c811ed6ea784a
parent: 4fcec816a37e08eb6876a290a456b7c131c7514f [diff]

final gds & signoff results

gds/caravel.gds.gz[Added - diff]
gds/caravel_00020004.gds.gz.00.split[Added - diff]
gds/caravel_00020004.gds.gz.01.split[Added - diff]
gds/caravel_00020004.gds.gz.02.split[Added - diff]
gds/caravel_00020004.gds.gz.03.split[Added - diff]
gds/caravel_00020004.gds.gz.04.split[Added - diff]
gds/caravel_00020004.gds.gz.05.split[Added - diff]
gds/caravel_00020004_fill_pattern.gds.gz.00.split[Added - diff]
gds/caravel_00020004_fill_pattern.gds.gz.01.split[Added - diff]
gds/caravel_00020004_fill_pattern.gds.gz.02.split[Added - diff]
gds/caravel_00020004_fill_pattern.gds.gz.03.split[Added - diff]
gds/caravel_00020004_fill_pattern.gds.gz.04.split[Added - diff]
gds/caravel_00020004_fill_pattern.gds.gz.05.split[Added - diff]
gds/user_id_prog_zero.gds.gz[Added - diff]
gds/user_id_programming.gds.gz[Added - diff]
gds/user_proj_example.gds[Deleted - diff]
gds/user_proj_example.gds.gz[diff]
gds/user_project_wrapper.gds[Deleted - diff]
gds/user_project_wrapper.gds.gz[diff]
info.yaml[diff]
mag/.magicrc[Added - diff]
mag/compose_final.tcl[Added - diff]
mag/user_id_programming.mag[Added - diff]
mag/user_id_textblock.mag[Added - diff]
signoff/.gitignore[Added - diff]
verilog/dv/Makefile[Deleted - diff]
verilog/dv/README.md[Deleted - diff]
verilog/dv/io_ports/Makefile[Deleted - diff]
verilog/dv/io_ports/io_ports.c[Deleted - diff]
verilog/dv/io_ports/io_ports_tb.v[Deleted - diff]
verilog/dv/la_test1/Makefile[Deleted - diff]
verilog/dv/la_test1/la_test1.c[Deleted - diff]
verilog/dv/la_test1/la_test1_tb.v[Deleted - diff]
verilog/dv/la_test2/Makefile[Deleted - diff]
verilog/dv/la_test2/la_test2.c[Deleted - diff]
verilog/dv/la_test2/la_test2_tb.v[Deleted - diff]
verilog/dv/mprj_stimulus/Makefile[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus.c[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus_tb.v[Deleted - diff]
verilog/dv/wb_port/Makefile[Deleted - diff]
verilog/dv/wb_port/wb_port.c[Deleted - diff]
verilog/dv/wb_port/wb_port_tb.v[Deleted - diff]
verilog/gl/user_proj_example.v[Deleted - diff]
verilog/gl/user_project_wrapper.v[Deleted - diff]
verilog/rtl/caravel.v[Added - diff]
verilog/rtl/fpu/except.v[Deleted - diff]
verilog/rtl/fpu/fpu.v[Deleted - diff]
verilog/rtl/fpu/post_norm.v[Deleted - diff]
verilog/rtl/fpu/pre_norm.v[Deleted - diff]
verilog/rtl/fpu/pre_norm_fmul.v[Deleted - diff]
verilog/rtl/fpu/primitives.v[Deleted - diff]
verilog/rtl/i2c/i2c_master_bit_ctrl.v[Deleted - diff]
verilog/rtl/i2c/i2c_master_byte_ctrl.v[Deleted - diff]
verilog/rtl/i2c/i2c_master_defines.v[Deleted - diff]
verilog/rtl/i2c/i2c_master_top.v[Deleted - diff]
verilog/rtl/i2c/timescale.v[Deleted - diff]
verilog/rtl/ptc/ptc_defines.v[Deleted - diff]
verilog/rtl/ptc/ptc_top.v[Deleted - diff]
verilog/rtl/rtc/hexmap.v[Deleted - diff]
verilog/rtl/rtc/rtcclock.v[Deleted - diff]
verilog/rtl/rtc/rtcdate.v[Deleted - diff]
verilog/rtl/rtc/rtcgps.v[Deleted - diff]
verilog/rtl/rtc/rtclight.v[Deleted - diff]
verilog/rtl/uprj_netlists.v[Deleted - diff]
verilog/rtl/user_proj_example.v[Deleted - diff]
verilog/rtl/user_project_wrapper.v[Deleted - diff]

66 files changed

tree: fcaa4b3d74fbfb841c235f36397c811ed6ea784a

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.