| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/user_proj_example,user_proj_example,user_proj_example,Flow_completed,1h2m13s,0h7m45s,101091.47609147607,0.8658,20218.295218295214,20,1279.33,17505,0,0,0,0,0,0,0,135,0,-1,-1,871844,139596,-398.85,-398.85,-377.2,-429.19,-384.25,-31302.95,-31302.95,-29817.71,-29817.71,-30579.61,722296673,0.0,26.34,22.83,0.69,0.03,-1,17282,17872,1146,1736,0,0,0,17505,774,653,397,1358,3270,3457,778,446,2890,3310,520,672,11659,0,12331,2.5364616360177554,394.25,10,AREA 0,6,20,1,153.6,153.18,0.24,0,sky130_fd_sc_hd,4,0 |
