commit 4ad3dbf9e92f42fc9425b74fb8c57aabc209e0a4
author Baburaj <teche.raj2019@gmail.com> Wed Jun 23 08:33:56 2021 +0530
committer Baburaj <teche.raj2019@gmail.com> Wed Jun 23 08:33:56 2021 +0530
tree ca151e062260da32e726fd540359c1f6098aed5e
parent 33c2bda22df1a06258b805c49281000b421d9858

changed FP_CORE_UTIL to 20 to solve routing congestion issue

openlane/user_proj_example/config.tcl

diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index 7e11034..49f26b3 100755
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -25,11 +25,6 @@
         $script_dir/../../verilog/rtl/i2c/i2c_master_bit_ctrl.v \
         $script_dir/../../verilog/rtl/i2c/i2c_master_byte_ctrl.v \
         $script_dir/../../verilog/rtl/i2c/i2c_master_top.v \
-        $script_dir/../../verilog/rtl/rtc/hexmap.v \
-        $script_dir/../../verilog/rtl/rtc/rtcdate.v \ 
-        $script_dir/../../verilog/rtl/rtc/rtcgps.v \
-        $script_dir/../../verilog/rtl/rtc/rtclight.v \
-        $script_dir/../../verilog/rtl/rtc/rtcclock.v \
         $script_dir/../../verilog/rtl/fpu/except.v \
         $script_dir/../../verilog/rtl/fpu/post_norm.v \
         $script_dir/../../verilog/rtl/fpu/pre_norm_fmul.v \
@@ -40,7 +35,7 @@
 	
 set ::env(CLOCK_PORT) "wb_clk_i"
 set ::env(CLOCK_NET) "wb_clk_i"
-set ::env(CLOCK_PERIOD) "100"
+set ::env(CLOCK_PERIOD) "10"
 
 set ::env(DESIGN_IS_CORE) 0
 set ::env(FP_PDN_CORE_RING) 0
@@ -51,7 +46,7 @@
 set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
 
 set ::env(SYNTH_MAX_FANOUT) 6
-set ::env(FP_CORE_UTIL) 24
+set ::env(FP_CORE_UTIL) 20
 set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+4) / 100.0 ]
 set ::env(CELL_PAD) 4