commit	302883d5c10dcd3d0da9cb44b0aa362afda21c53	[log] [tgz]
author	Baburaj <teche.raj2019@gmail.com>	Fri Jun 18 21:01:45 2021 +0530
committer	Baburaj <teche.raj2019@gmail.com>	Fri Jun 18 21:01:45 2021 +0530
tree	04a31da69741a186698f80910ebcfe37f8bcd833
parent	d3e050539b229d532a45c37a645482e081e344cc [diff]

FPU , I2C , PTC and RTC RTL added to user project area

verilog/rtl/fpu/except.v[Added - diff]
verilog/rtl/fpu/fpu.v[Added - diff]
verilog/rtl/fpu/post_norm.v[Added - diff]
verilog/rtl/fpu/pre_norm.v[Added - diff]
verilog/rtl/fpu/pre_norm_fmul.v[Added - diff]
verilog/rtl/fpu/primitives.v[Added - diff]
verilog/rtl/i2c/i2c_master_bit_ctrl.v[Added - diff]
verilog/rtl/i2c/i2c_master_byte_ctrl.v[Added - diff]
verilog/rtl/i2c/i2c_master_defines.v[Added - diff]
verilog/rtl/i2c/i2c_master_top.v[Added - diff]
verilog/rtl/i2c/timescale.v[Added - diff]
verilog/rtl/ptc/ptc_defines.v[Added - diff]
verilog/rtl/ptc/ptc_top.v[Added - diff]
verilog/rtl/rtc/hexmap.v[Added - diff]
verilog/rtl/rtc/rtcclock.v[Added - diff]
verilog/rtl/rtc/rtcdate.v[Added - diff]
verilog/rtl/rtc/rtcgps.v[Added - diff]
verilog/rtl/rtc/rtclight.v[Added - diff]
verilog/rtl/user_proj_example.v[diff]

19 files changed

tree: 04a31da69741a186698f80910ebcfe37f8bcd833

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.