commit | f51dd08a1f4716df0cca0a0ebe28f99544cc611c | [log] [tgz] |
---|---|---|
author | Tim Edwards <tim@opencircuitdesign.com> | Mon Oct 05 16:30:24 2020 -0400 |
committer | Tim Edwards <tim@opencircuitdesign.com> | Mon Oct 05 16:30:24 2020 -0400 |
tree | 8a3fae4fb6ced7f0ec68ce1a4f401364927e9812 | |
parent | 89f09245bc3e3669420ed982c7f18f365b9f5e15 [diff] |
Added a simple power-on-reset circuit with schmitt trigger output, and decoupled the reset pin from the porb/porb_h. The reset for the housekeeping SPI remains connected to porb and not the reset pin, so that the processor can be put in reset but the housekeeping SPI can be accessed in that state. That prevents the user from bricking the system by having a program override the housekeeping SPI and then get into an erroneous state.
A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.
The managment SoC runs firmware taht can be used to:
The memory map of the management SoC is given below
This is the user space. It has limitted silicon area (???) as well as a fixed number of I/O pads (???). The repoo contains a sample mega project that contains a binary 32-bit up counter.
The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided: