commit	ef8312e0e966922a17c0d76b5a1e1f608703c6f3	[log] [tgz]
author	Tim Edwards <tim@opencircuitdesign.com>	Tue Sep 22 17:20:06 2020 -0400
committer	Tim Edwards <tim@opencircuitdesign.com>	Tue Sep 22 17:20:06 2020 -0400
tree	a7de20612c380d9c0832e0d60b7b6f6b06458cf0
parent	12a9a1dec1ddb922693bab112800362c566d5c60 [diff]

Caravel 2nd phase (branch phase2):  First pass at removing the analog
signals left over from Raven/Ravenna but not used on StriVe.  Reduced
the GPIO for the management area to 2 bits.  Removed additional unused
signals, removed the controls to the deleted analog signals, and
reduced the remaining controls.  Renamed the digital libraries for
the sky130 Google/SkyWater naming conventions.  Work in progress;  much
more left to do.

verilog/dv/caravel/defs.h[Renamed from verilog/dv/harness/defs.h - diff]
verilog/dv/caravel/mgmt_soc/Makefile[Renamed from verilog/dv/harness/mgmt_soc/Makefile - diff]
verilog/dv/caravel/mgmt_soc/gpio/Makefile[Renamed from verilog/dv/harness/mgmt_soc/gpio/Makefile - diff]
verilog/dv/caravel/mgmt_soc/gpio/gpio.c[Renamed from verilog/dv/harness/mgmt_soc/gpio/gpio.c - diff]
verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v[Renamed from verilog/dv/harness/mgmt_soc/gpio/gpio_tb.v - diff]
verilog/dv/caravel/mgmt_soc/hkspi/Makefile[Renamed from verilog/dv/harness/mgmt_soc/hkspi/Makefile - diff]
verilog/dv/caravel/mgmt_soc/hkspi/hkspi.c[Renamed from verilog/dv/harness/mgmt_soc/hkspi/hkspi.c - diff]
verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v[Renamed from verilog/dv/harness/mgmt_soc/hkspi/hkspi_tb.v - diff]
verilog/dv/caravel/mgmt_soc/mem/Makefile[Renamed from verilog/dv/harness/mgmt_soc/mem/Makefile - diff]
verilog/dv/caravel/mgmt_soc/mem/mem.c[Renamed from verilog/dv/harness/mgmt_soc/mem/mem.c - diff]
verilog/dv/caravel/mgmt_soc/mem/mem_tb.v[Renamed from verilog/dv/harness/mgmt_soc/mem/mem_tb.v - diff]
verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile[Renamed from verilog/dv/harness/mgmt_soc/mprj_ctrl/Makefile - diff]
verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c[Renamed from verilog/dv/harness/mgmt_soc/mprj_ctrl/mprj_ctrl.c - diff]
verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v[Renamed from verilog/dv/harness/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v - diff]
verilog/dv/caravel/mgmt_soc/perf/Makefile[Renamed from verilog/dv/harness/mgmt_soc/perf/Makefile - diff]
verilog/dv/caravel/mgmt_soc/perf/perf.c[Renamed from verilog/dv/harness/mgmt_soc/perf/perf.c - diff]
verilog/dv/caravel/mgmt_soc/perf/perf_tb.v[Renamed from verilog/dv/harness/mgmt_soc/perf/perf_tb.v - diff]
verilog/dv/caravel/mgmt_soc/sysctrl/Makefile[Renamed from verilog/dv/harness/mgmt_soc/sysctrl/Makefile - diff]
verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl.c[Renamed from verilog/dv/harness/mgmt_soc/sysctrl/sysctrl.c - diff]
verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v[Renamed from verilog/dv/harness/mgmt_soc/sysctrl/sysctrl_tb.v - diff]
verilog/dv/caravel/mgmt_soc/uart/Makefile[Renamed from verilog/dv/harness/mgmt_soc/uart/Makefile - diff]
verilog/dv/caravel/mgmt_soc/uart/uart.c[Renamed from verilog/dv/harness/mgmt_soc/uart/uart.c - diff]
verilog/dv/caravel/mgmt_soc/uart/uart_tb.v[Renamed from verilog/dv/harness/mgmt_soc/uart/uart_tb.v - diff]
verilog/dv/caravel/mprj_counter/Makefile[Renamed from verilog/dv/harness/mprj_counter/Makefile - diff]
verilog/dv/caravel/mprj_counter/README.md[Renamed from verilog/dv/harness/mprj_counter/README.md - diff]
verilog/dv/caravel/mprj_counter/io_ports/Makefile[Renamed from verilog/dv/harness/mprj_counter/io_ports/Makefile - diff]
verilog/dv/caravel/mprj_counter/io_ports/io_ports.c[Renamed from verilog/dv/harness/mprj_counter/io_ports/io_ports.c - diff]
verilog/dv/caravel/mprj_counter/io_ports/io_ports_tb.v[Renamed from verilog/dv/harness/mprj_counter/io_ports/io_ports_tb.v - diff]
verilog/dv/caravel/mprj_counter/la_test1/Makefile[Renamed from verilog/dv/harness/mprj_counter/la_test1/Makefile - diff]
verilog/dv/caravel/mprj_counter/la_test1/la_test1.c[Renamed from verilog/dv/harness/mprj_counter/la_test1/la_test1.c - diff]
verilog/dv/caravel/mprj_counter/la_test1/la_test1_tb.v[Renamed from verilog/dv/harness/mprj_counter/la_test1/la_test1_tb.v - diff]
verilog/dv/caravel/mprj_counter/la_test2/Makefile[Renamed from verilog/dv/harness/mprj_counter/la_test2/Makefile - diff]
verilog/dv/caravel/mprj_counter/la_test2/la_test2.c[Renamed from verilog/dv/harness/mprj_counter/la_test2/la_test2.c - diff]
verilog/dv/caravel/mprj_counter/la_test2/la_test2_tb.v[Renamed from verilog/dv/harness/mprj_counter/la_test2/la_test2_tb.v - diff]
verilog/dv/caravel/sections.lds[Renamed from verilog/dv/harness/sections.lds - diff]
verilog/dv/caravel/spiflash.v[Renamed from verilog/dv/harness/spiflash.v - diff]
verilog/dv/caravel/start.s[Renamed from verilog/dv/harness/start.s - diff]
verilog/dv/caravel/stub.c[Renamed from verilog/dv/harness/stub.c - diff]
verilog/dv/caravel/tbuart.v[Renamed from verilog/dv/harness/tbuart.v - diff]
verilog/dv/harness/verify.log[Deleted - diff]
verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v[diff]
verilog/rtl/caravel.v[Added - diff]
verilog/rtl/chip_io.v[diff]
verilog/rtl/digital_pll.v[diff]
verilog/rtl/harness_chip.v[Deleted - diff]
verilog/rtl/lvlshiftdown.v[Deleted - diff]
verilog/rtl/mgmt_core.v[diff]
verilog/rtl/mgmt_soc.v[diff]
verilog/rtl/pads.v[diff]
verilog/rtl/ring_osc2x13.v[diff]
verilog/rtl/sysctrl.v[diff]

51 files changed

tree: a7de20612c380d9c0832e0d60b7b6f6b06458cf0

README.md

CIIC Harness (Phase 1)

A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.

Managment SoC

The managment SoC runs firmware taht can be used to:

Configure Mega Project I/O pads
Observe and control Mega Project signals (through on-chip logic analyzer probes)
Control the Mega Project power supply

The memory map of the management SoC is given below

Mega Project Area

This is the user space. It has limitted silicon area (???) as well as a fixed number of I/O pads (???). The repoo contains a sample mega project that contains a binary 32-bit up counter.

The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:

Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: IO_Ports Test.
Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: LA_Test1.
Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: LA_Test2.