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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-040 / 8115320f43c8069cbf52bdc6deb34b44bf520a5b
commit8115320f43c8069cbf52bdc6deb34b44bf520a5b[log] [tgz]
authorTim Edwards <tim@opencircuitdesign.com>Fri Oct 09 19:57:04 2020 -0400
committerTim Edwards <tim@opencircuitdesign.com>Fri Oct 09 19:57:04 2020 -0400
tree0df07176e0d6816dc4216f84bf779eb5c252084c
parent856b092898d166106f28702cf979f7fa74cb3c47 [diff]
Modified code to let SPI master control the housekeeping SPI through
a configuration bit setting in the SPI master.  Revised the "sysctrl"
testbench to work with the SPI master controlling the housekeeping
SPI.
6 files changed
tree: 0df07176e0d6816dc4216f84bf779eb5c252084c
  1. doc/
  2. verilog/
  3. README.md
README.md

CIIC Harness (Phase 1)

A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.

Managment SoC

The managment SoC runs firmware taht can be used to:

  • Configure Mega Project I/O pads
  • Observe and control Mega Project signals (through on-chip logic analyzer probes)
  • Control the Mega Project power supply

The memory map of the management SoC is given below

Mega Project Area

This is the user space. It has limitted silicon area (???) as well as a fixed number of I/O pads (???). The repoo contains a sample mega project that contains a binary 32-bit up counter.

The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:

  1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: IO_Ports Test.
  2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: LA_Test1.
  3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: LA_Test2.