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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-040 / 61bfc1f4c75fbb9a2c915bcd539f7e01c5978a55
commit61bfc1f4c75fbb9a2c915bcd539f7e01c5978a55[log] [tgz]
authorTim Edwards <tim@opencircuitdesign.com>Sat Oct 03 11:51:17 2020 -0400
committerTim Edwards <tim@opencircuitdesign.com>Sat Oct 03 11:51:17 2020 -0400
treeb7d5960f853d8a0f8363dbd9b05446e9c1467794
parentc18c474118be6020a759267525f5df7c62ce7ee4 [diff]
Corrected the primary issue with simulation, which was the failure
to change the "vdd" connection of vddio to "vdd3v3", leaving it as
an isolated net.
4 files changed
tree: b7d5960f853d8a0f8363dbd9b05446e9c1467794
  1. doc/
  2. verilog/
  3. README.md
README.md

CIIC Harness (Phase 1)

A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.

Managment SoC

The managment SoC runs firmware taht can be used to:

  • Configure Mega Project I/O pads
  • Observe and control Mega Project signals (through on-chip logic analyzer probes)
  • Control the Mega Project power supply

The memory map of the management SoC is given below

Mega Project Area

This is the user space. It has limitted silicon area (???) as well as a fixed number of I/O pads (???). The repoo contains a sample mega project that contains a binary 32-bit up counter.

The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:

  1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: IO_Ports Test.
  2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: LA_Test1.
  3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: LA_Test2.