Vast and substantial changes: Removed the old GPIO control with the new one
that implements a shift register around the perimeter of the chip, to control
most aspects of each GPIO pad locally to avoid excessive wiring. Added modules
for the metal-programmed user ID, two counter-timers, and a general-purpose SPI
master. The SPI master can be internally directly connected to the SPI slave,
so the processor can access the housekeeping SPI in the same way as an external
host. Most signals other than 1 GPIO pin and the SPI flash controller pins were
remapped to pads in the user area, where they are active on startup and until
they are programmed for user use from the management processor. There are
several known syntax issues that need to be fixed; this is a work in progress.
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
index 41856ac..f8cd3ca 100644
--- a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
@@ -50,20 +50,17 @@
$finish;
end
- wire [1:0] gpio;
+ wire gpio;
reg gpio_lo;
reg gpio_hi;
- assign gpio[0] = gpio_lo;
- assign gpio[1] = gpio_hi;
+ assign gpio = gpio_lo;
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
- wire flash_io2;
- wire flash_io3;
reg SDI, CSB, SCK, RSTB;
wire SDO;
@@ -86,15 +83,15 @@
// Monitor
initial begin
wait(gpio_hi == 1'b0);
- wait(gpio == 2'b0);
+ wait(gpio == 1'b0);
wait(gpio_hi== 1'b1);
- wait(gpio == 2'b0);
+ wait(gpio == 1'b0);
wait(gpio_hi== 1'b1);
- wait(gpio == 2'b0);
+ wait(gpio == 1'b0);
wait(gpio_hi== 1'b0);
- wait(gpio == 2'b01);
+ wait(gpio == 1'b1);
wait(gpio_hi== 1'b0);
- wait(gpio == 2'b0);
+ wait(gpio == 1'b0);
wait(gpio_hi== 1'b1);
$display("Monitor: Test GPIO (RTL) Passed");
$finish;
@@ -122,26 +119,35 @@
assign VSS = 1'b0;
assign VDD1V8 = 1'b1;
+ // These are the mappings of mprj_io GPIO pads that are set to
+ // specific functions on startup:
+ //
+ // JTAG = mgmt_gpio_io[0] (inout)
+ // SDO = mgmt_gpio_io[1] (output)
+ // SDI = mgmt_gpio_io[2] (input)
+ // CSB = mgmt_gpio_io[3] (input)
+ // SCK = mgmt_gpio_io[4] (input)
+ // ser_rx = mgmt_gpio_io[5] (input)
+ // ser_tx = mgmt_gpio_io[6] (output)
+ // irq = mgmt_gpio_io[7] (input)
+ //
+ // Therefore to connect SDO, SDI, CSB, and SCK,
+ // apply {27'bz, SCK, CSB, SDI, SDO, 1'bz} to mprj_io (32 bits)
+
+ wire [27:0] noconnect;
+
caravel uut (
.vdd3v3 (VDD3V3),
.vdd1v8 (VDD1V8),
.vss (VSS),
.clock (clock),
- .SDI (SDI),
- .SDO (SDO),
- .CSB (CSB),
- .SCK (SCK),
- .ser_rx (1'b0),
- .ser_tx (),
- .irq (1'b0),
.gpio (gpio),
+ .mprj_io ({noconnect[27:1], SCK, CSB, SDI, SDO, noconnect[0]}),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
- .flash_io2(flash_io2),
- .flash_io3(flash_io3),
- .RSTB (RSTB)
+ .resetb (RSTB)
);
spiflash #(
@@ -151,8 +157,8 @@
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
- .io2(flash_io2),
- .io3(flash_io3)
+ .io2(), // not used
+ .io3() // not used
);
endmodule
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/make.log b/verilog/dv/caravel/mgmt_soc/gpio/make.log
deleted file mode 100644
index 9a0520b..0000000
--- a/verilog/dv/caravel/mgmt_soc/gpio/make.log
+++ /dev/null
@@ -1,976 +0,0 @@
-iverilog -I ../../ -I ../../../../ip -I ../../../../rtl \
-gpio_tb.v -o gpio.vvp
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:903: warning: choosing typ expression.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:903: warning: choosing typ expression.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:904: warning: choosing typ expression.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:904: warning: choosing typ expression.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:1839: warning: choosing typ expression.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:1839: warning: choosing typ expression.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:1840: warning: choosing typ expression.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:1840: warning: choosing typ expression.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:2884: warning: choosing typ expression.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:2884: warning: choosing typ expression.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:12: error: 's8iom0_vccd_hvc_pad' has already been declared in this scope.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:12: : It was declared here as a module.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:52: Module s8iom0_vccd_hvc_pad was already declared here: /home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:12
-
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:54: error: 's8iom0_vccd_lvc_pad' has already been declared in this scope.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:54: : It was declared here as a module.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:101: Module s8iom0_vccd_lvc_pad was already declared here: /home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:54
-
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:103: error: 's8iom0_vdda_lvc_pad' has already been declared in this scope.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:103: : It was declared here as a module.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:150: Module s8iom0_vdda_lvc_pad was already declared here: /home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:103
-
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:152: error: 's8iom0_vdda_hvc_pad' has already been declared in this scope.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:152: : It was declared here as a module.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:192: Module s8iom0_vdda_hvc_pad was already declared here: /home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:152
-
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:194: error: 's8iom0_vddio_lvc_pad' has already been declared in this scope.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:194: : It was declared here as a module.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:243: Module s8iom0_vddio_lvc_pad was already declared here: /home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:194
-
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:245: error: 's8iom0_vddio_hvc_pad' has already been declared in this scope.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:245: : It was declared here as a module.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:287: Module s8iom0_vddio_hvc_pad was already declared here: /home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:245
-
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:289: error: 's8iom0_vssd_lvc_pad' has already been declared in this scope.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:289: : It was declared here as a module.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:336: Module s8iom0_vssd_lvc_pad was already declared here: /home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:289
-
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:338: error: 's8iom0_vssd_hvc_pad' has already been declared in this scope.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:338: : It was declared here as a module.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:378: Module s8iom0_vssd_hvc_pad was already declared here: /home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:338
-
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:380: error: 's8iom0_vssio_lvc_pad' has already been declared in this scope.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:380: : It was declared here as a module.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:429: Module s8iom0_vssio_lvc_pad was already declared here: /home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:380
-
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:432: error: 's8iom0_vssio_hvc_pad' has already been declared in this scope.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:432: : It was declared here as a module.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:474: Module s8iom0_vssio_hvc_pad was already declared here: /home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:432
-
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:476: error: 's8iom0_vssa_lvc_pad' has already been declared in this scope.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:476: : It was declared here as a module.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:523: Module s8iom0_vssa_lvc_pad was already declared here: /home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:476
-
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:525: error: 's8iom0_vssa_hvc_pad' has already been declared in this scope.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:525: : It was declared here as a module.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:565: Module s8iom0_vssa_hvc_pad was already declared here: /home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:525
-
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:567: error: 's8iom0_corner_pad' has already been declared in this scope.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:567: : It was declared here as a module.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:585: Module s8iom0_corner_pad was already declared here: /home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:567
-
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:587: error: 's8iom0s8_com_bus_slice' has already been declared in this scope.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:587: : It was declared here as a module.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:605: Module s8iom0s8_com_bus_slice was already declared here: /home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:587
-
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:607: error: 's8iom0s8_com_bus_slice_1um' has already been declared in this scope.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:607: : It was declared here as a module.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:625: Module s8iom0s8_com_bus_slice_1um was already declared here: /home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:607
-
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:627: error: 's8iom0_gpiov2_pad' has already been declared in this scope.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:627: : It was declared here as a module.
-/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v:714: Module s8iom0_gpiov2_pad was already declared here: /home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v:627
-
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:588: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:588: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:717: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:717: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:1195: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:1195: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:1324: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:1324: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:1453: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:1453: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:1910: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:1910: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:2033: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:2033: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:2156: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:2156: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:2620: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:2620: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:2743: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:2743: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:2866: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:2866: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:2989: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:2989: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:3439: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:3439: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:3561: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:3561: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:3683: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:3683: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:4133: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:4133: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:4255: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:4255: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:4377: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:4377: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:4848: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:4848: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:4976: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:4976: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:5104: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:5104: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:5576: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:5576: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:5704: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:5704: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:5832: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:5832: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:6296: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:6296: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:6424: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:6424: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:6552: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:6552: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:7016: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:7016: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:7144: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:7144: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:7272: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:7272: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:7763: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:7763: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:7898: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:7898: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:8033: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:8033: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:8525: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:8525: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:8660: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:8660: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:8795: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:8795: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:9273: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:9273: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:9407: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:9407: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:9541: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:9541: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:10019: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:10019: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:10153: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:10153: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:10287: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:10287: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:10752: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:10752: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:10880: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:10880: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:11008: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:11008: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:11472: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:11472: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:11600: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:11600: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:11728: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:11728: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:12213: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:12213: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:12347: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:12347: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:12481: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:12481: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:12967: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:12967: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:13101: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:13101: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:13235: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:13235: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:13742: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:13742: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:14221: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:14221: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:14355: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:14355: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:14489: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:14489: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:14967: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:14967: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:15101: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:15101: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:15235: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:15235: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:15713: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:15713: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:15847: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:15847: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:15981: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:15981: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:16459: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:16459: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:16593: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:16593: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:16727: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:16727: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:16861: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:16861: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:17280: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:17280: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:17394: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:17394: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:17508: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:17508: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:17622: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:17622: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:18046: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:18046: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:18160: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:18160: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:18274: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:18274: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:18703: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:18703: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:18823: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:18823: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:18943: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:18943: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:19381: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:19381: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:19501: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:19501: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:19621: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:19621: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:20064: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:20064: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:20190: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:20190: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:20316: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:20316: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:20768: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:20768: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:20894: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:20894: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:21020: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:21020: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:21472: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:21472: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:21598: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:21598: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:21724: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:21724: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:22129: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:22129: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:22237: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:22237: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:22345: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:22345: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:22453: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:22453: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:22561: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:22561: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:22669: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:22669: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:22777: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:22777: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:23179: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:23179: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:23287: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:23287: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:23689: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:23689: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:23797: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:23797: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:24199: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:24199: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:24307: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:24307: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:24415: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:24415: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:29444: warning: macro UNIT_DELAY undefined (and assumed null) at this point.
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:24523: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:24523: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:24631: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:24631: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:25039: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:25039: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:25148: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:25148: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:30089: warning: macro UNIT_DELAY undefined (and assumed null) at this point.
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:25556: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:25556: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:25665: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:25665: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:26073: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:26073: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:30579: warning: macro UNIT_DELAY undefined (and assumed null) at this point.
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:26182: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:26182: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:31182: warning: macro UNIT_DELAY undefined (and assumed null) at this point.
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:26590: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:26590: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:26699: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:26699: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:31644: warning: macro UNIT_DELAY undefined (and assumed null) at this point.
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:27101: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:27101: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:27209: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:27209: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:32350: warning: macro UNIT_DELAY undefined (and assumed null) at this point.
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:27317: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:27317: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:27425: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:27425: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:27533: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:27533: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:32944: warning: macro UNIT_DELAY undefined (and assumed null) at this point.
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:27935: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:27935: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:28043: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:28043: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:33633: warning: macro UNIT_DELAY undefined (and assumed null) at this point.
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:28441: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:28441: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:28775: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:28775: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:28870: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:28870: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:34189: warning: macro UNIT_DELAY undefined (and assumed null) at this point.
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:28965: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:28965: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:29060: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:29060: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:29155: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:29155: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:29666: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:29666: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:29799: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:29799: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:30309: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:30309: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:30784: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:35893: warning: macro UNIT_DELAY undefined (and assumed null) at this point.
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:30784: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:30910: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:30910: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:31383: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:31383: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:36506: warning: macro UNIT_DELAY undefined (and assumed null) at this point.
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:31841: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:31841: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:31961: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:31961: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:32081: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:32081: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:37111: warning: macro UNIT_DELAY undefined (and assumed null) at this point.
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:32556: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:32556: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:32682: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:32682: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:33141: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:37817: warning: macro UNIT_DELAY undefined (and assumed null) at this point.
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:33141: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:33261: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:33261: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:33381: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:33381: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:33825: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:33825: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:33945: syntax error/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:38518:
-warning: macro UNIT_DELAY undefined (and assumed null) at this point.
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:33945: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:34372: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:34372: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:34486: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:34486: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:34600: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:34600: error: Invalid module instantiation/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:39085:
-warning: macro UNIT_DELAY undefined (and assumed null) at this point.
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:34954: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:34954: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:35386: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:35386: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:35500: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:35500: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:35614: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:35614: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:36104: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:36104: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:36231: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:36231: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:36715: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:36715: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:36842: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:36842: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:37311: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:37311: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:37431: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:37431: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:37551: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:37551: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:38017: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:38017: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:38138: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:38138: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:38259: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:38259: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:38713: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:38713: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:38833: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:38833: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:39277: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:39277: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:39712: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:39712: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:39826: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:39826: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:39940: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:39940: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:43816: warning: macro UNIT_DELAY undefined (and assumed null) at this point.
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:40366: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:40366: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:40769: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:40769: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:44286: warning: macro UNIT_DELAY undefined (and assumed null) at this point.
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:41171: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:41171: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:41573: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:41573: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:41981: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:41981: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:42389: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:42389: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:42797: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:42797: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:43204: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:43204: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:43318: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:43318: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:43432: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:43432: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:43546: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:43546: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:44022: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:44022: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:44483: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:44483: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:44892: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:44892: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:45006: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:45006: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:45120: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:45120: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:45234: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:45234: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:45348: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:45348: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:45756: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:45756: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:45870: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:45870: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:45984: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:45984: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:46098: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:46098: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:46604: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:46604: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:46730: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:46730: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:46856: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:46856: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:47340: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:47340: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:47832: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:47832: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:48316: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:48316: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:48659: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:48659: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:48754: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:48754: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:48849: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:48849: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:48944: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:48944: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:49385: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:49385: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:49505: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:49505: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:49625: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:49625: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:50029: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:50029: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:50137: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:50137: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:50245: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:50245: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:50353: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:50353: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:50461: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:50461: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:50569: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:50569: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:50677: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:50677: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:50904: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:50904: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:51316: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:51316: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:51430: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:51430: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:51544: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:51544: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:51658: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:51658: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:51772: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:51772: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:52185: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:52185: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:52299: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:52299: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:52413: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:52413: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:52527: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:52527: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:52641: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:52641: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:52993: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:52993: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:53095: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:53095: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:53197: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:53197: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:53299: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:53299: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:53401: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:53401: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:53813: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:53813: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:54241: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:54241: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:54669: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:54669: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:55085: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:55085: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:55508: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:55508: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:55944: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:55944: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:56060: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:56060: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:56176: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:56176: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:56292: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:56292: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:56408: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:56408: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:56865: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:56865: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:57278: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:57278: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:57390: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:57390: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:57502: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:57502: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:57918: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:57918: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:58324: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:58324: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:58435: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:58435: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:58546: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:58546: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:59340: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:59340: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:59460: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:59460: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:59580: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:59580: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:60014: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:60014: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:60134: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:60134: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:60254: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:60254: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:60374: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:60374: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:60808: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:60808: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:60928: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:60928: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:61048: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:61048: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:61521: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:61521: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:61659: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:61659: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:61797: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:61797: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:62217: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:62217: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:62331: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:62331: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:62445: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:62445: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:62559: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:62559: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:62983: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:62983: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:63097: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:63097: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:63211: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:63211: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:63640: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:63640: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:63760: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:63760: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:63880: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:63880: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:64318: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:64318: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:64438: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:64438: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:64558: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:64558: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:65001: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:65001: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:65127: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:65127: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:65253: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:65253: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:65705: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:65705: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:65831: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:65831: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:65957: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:65957: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:66409: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:66409: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:66535: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:66535: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:66661: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:66661: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:67079: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:67079: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:67193: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:67193: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:67307: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:67307: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:67421: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:67421: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:67857: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:67857: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:67973: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:67973: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:68089: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:68089: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:68530: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:68530: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:68652: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:68652: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:68774: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:68774: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:69224: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:69224: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:69346: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:69346: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:69468: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:69468: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:69923: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:69923: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:70051: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:70051: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:70179: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:70179: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:70631: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:70631: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:70757: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:70757: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:70883: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:70883: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:71335: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:71335: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:71461: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:71461: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:71587: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:71587: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:72059: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:72059: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:72187: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:72187: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:72315: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:72315: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:72787: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:72787: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:72915: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:72915: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:73043: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:73043: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:73494: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:73494: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:73616: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:73616: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:73738: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:73738: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:74188: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:74188: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:74310: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:74310: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:74432: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:74432: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:74554: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:74554: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:75010: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:75010: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:75133: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:75133: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:75256: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:75256: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:75720: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:75720: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:75843: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:75843: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:75966: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:75966: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:76437: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:76437: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:76565: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:76565: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:76693: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:76693: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:77165: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:77165: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:77293: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:77293: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:77421: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:77421: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:77885: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:77885: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:78013: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:78013: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:78141: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:78141: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:78605: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:78605: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:78733: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:78733: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:78861: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:78861: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:79346: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:79346: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:79480: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:79480: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:79614: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:79614: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:80100: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:80100: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:80234: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:80234: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:80368: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:80368: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:80846: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:80846: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:80980: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:80980: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:81114: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:81114: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:81592: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:81592: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:81726: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:81726: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:81860: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:81860: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:82325: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:82325: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:82453: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:82453: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:82581: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:82581: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:83045: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:83045: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:83173: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:83173: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:83301: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:83301: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:83786: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:83786: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:83920: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:83920: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:84054: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:84054: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:84540: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:84540: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:84674: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:84674: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:84808: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:84808: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:85286: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:85286: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:85420: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:85420: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:85554: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:85554: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:86032: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:86032: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:86166: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:86166: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:86300: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:86300: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:86434: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:86434: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:86912: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:86912: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:87046: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:87046: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:87180: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:87180: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:87658: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:87658: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:87792: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:87792: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:87926: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:87926: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:88345: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:88345: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:88459: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:88459: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:88573: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:88573: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:88687: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:88687: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:89111: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:89111: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:89225: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:89225: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:89339: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:89339: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:89768: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:89768: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:89888: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:89888: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:90008: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:90008: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:90446: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:90446: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:90566: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:90566: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:90686: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:90686: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:91129: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:91129: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:91255: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:91255: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:91381: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:91381: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:91833: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:91833: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:91959: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:91959: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:92085: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:92085: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:92537: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:92537: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:92663: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:92663: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:92789: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:92789: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:93194: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:93194: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:93914: warning: macro UNIT_DELAY undefined (and assumed null) at this point.
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:93596: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:93596: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:94623: warning: macro UNIT_DELAY undefined (and assumed null) at this point.
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:94160: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:94160: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:94305: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:94305: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:95170: warning: macro UNIT_DELAY undefined (and assumed null) at this point.
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:94867: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:94867: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:95841: warning: macro UNIT_DELAY undefined (and assumed null) at this point.
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:95402: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:95402: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:96359: warning: macro UNIT_DELAY undefined (and assumed null) at this point.
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:95541: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:95541: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:96066: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:96066: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:97149: /home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.vwarning: macro UNIT_DELAY undefined (and assumed null) at this point.
-:96582: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:96582: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:96715: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:96715: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:96848: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:96848: /home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:97814: error: Invalid module instantiationwarning: macro UNIT_DELAY undefined (and assumed null) at this point.
-
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:97381: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:97381: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:97520: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:97520: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:98583: warning: macro UNIT_DELAY undefined (and assumed null) at this point.
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:98037: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:98037: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:98170: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:98170: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:98303: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:98303: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:99203: warning: macro UNIT_DELAY undefined (and assumed null) at this point.
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:98799: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:98799: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:98931: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:98931: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:99410: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:99410: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:99536: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:99536: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:99662: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:99662: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:100672: warning: macro UNIT_DELAY undefined (and assumed null) at this point.
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:100137: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:100137: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:100257: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:100257: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:100377: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:100377: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:101329: warning: macro UNIT_DELAY undefined (and assumed null) at this point.
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:100900: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:100900: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:101039: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:101039: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:101548: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:101548: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:101681: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:101681: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:101814: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:101814: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:102152: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:102152: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:102247: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:102247: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:102584: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:102584: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:102921: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:102921: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:103252: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:103252: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:103676: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:103676: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:103792: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:103792: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:103908: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:103908: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:104337: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:104337: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:104457: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:104457: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:104577: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:104577: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:105006: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:105006: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:105122: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:105122: error: Invalid module instantiation
-../../../../rtl/caravel.v:36: Include file /home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hvl.v not found
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:105238: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:105238: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:105679: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:105679: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:105801: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:105801: error: Invalid module instantiation
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:105923: syntax error
-/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v:105923: error: Invalid module instantiation
-make: *** [Makefile:17: gpio.vvp] Error 134
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 16d7d7d..beced01 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -38,13 +38,15 @@
`include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
`include "mgmt_soc.v"
-`include "striVe_spi.v"
+`include "caravel_spi.v"
`include "digital_pll.v"
-`include "striVe_clkrst.v"
+`include "caravel_clkrst.v"
`include "mprj_counter.v"
`include "mgmt_core.v"
`include "mprj_io.v"
`include "chip_io.v"
+`include "user_id_programming.v"
+`include "gpio_control_block.v"
`ifdef USE_OPENRAM
`include "sram_1rw1r_32_8192_8_sky130.v"
@@ -54,38 +56,79 @@
inout vdd3v3,
inout vdd1v8,
inout vss,
- inout [1:0] gpio, // Local digital only for management area
+ inout gpio, // Used for external LDO control
inout [`MPRJ_IO_PADS-1:0] mprj_io,
input clock, // CMOS core clock input, not a crystal
- input RSTB,
- input ser_rx,
- output ser_tx,
- input irq,
- output SDO,
- input SDI,
- input CSB,
- input SCK,
+ input resetb,
+
+ // Note that only two pins are available on the flash so dual and
+ // quad flash modes are not available.
+
output flash_csb,
output flash_clk,
output flash_io0,
- output flash_io1,
- output flash_io2,
- output flash_io3
+ output flash_io1
);
- wire [1:0] gpio_out_core;
- wire [1:0] gpio_in_core;
- wire [1:0] gpio_mode0_core;
- wire [1:0] gpio_mode1_core;
- wire [1:0] gpio_outenb_core;
- wire [1:0] gpio_inenb_core;
+ //------------------------------------------------------------
+ // This value is uniquely defined for each user project.
+ //------------------------------------------------------------
+ parameter USER_PROJECT_ID = 32'h0;
- // Mega-Project Control
- wire [`MPRJ_IO_PADS-1:0] mprj_io_oeb_n;
+ // These pins are overlaid on mprj_io space. They have the function
+ // below when the management processor is in reset, or in the default
+ // configuration. They are assigned to uses in the user space by the
+ // configuration program running off of the SPI flash. Note that even
+ // when the user has taken control of these pins, they can be restored
+ // to the original use by setting the resetb pin low. The SPI pins and
+ // UART pins can be connected directly to an FTDI chip as long as the
+ // FTDI chip sets these lines to high impedence (input function) at
+ // all times except when holding the chip in reset.
+
+ // JTAG = mprj_io[0] (inout)
+ // SDO = mprj_io[1] (output)
+ // SDI = mprj_io[2] (input)
+ // CSB = mprj_io[3] (input)
+ // SCK = mprj_io[4] (input)
+ // ser_rx = mprj_io[5] (input)
+ // ser_tx = mprj_io[6] (output)
+ // irq = mprj_io[7] (input)
+
+ // These pins are reserved for any project that wants to incorporate
+ // its own processor and flash controller. While a user project can
+ // technically use any available I/O pins for the purpose, these
+ // four pins connect to a pass-through mode from the SPI slave (pins
+ // 1-4 above) so that any SPI flash connected to these specific pins
+ // can be accessed through the SPI slave even when the processor is in
+ // reset.
+
+ // flash_csb = mprj_io[8]
+ // flash_sck = mprj_io[9]
+ // flash_io0 = mprj_io[10]
+ // flash_io1 = mprj_io[11]
+
+ // One-bit GPIO dedicated to management SoC (outside of user control)
+ wire gpio_out_core;
+ wire gpio_in_core;
+ wire gpio_mode0_core;
+ wire gpio_mode1_core;
+ wire gpio_outenb_core;
+ wire gpio_inenb_core;
+
+ // Mega-Project Control (pad-facing)
+ wire [`MPRJ_IO_PADS-1:0] mgmt_io_data;
+ wire mprj_io_loader_resetn;
+ wire mprj_io_loader_clock;
+ wire mprj_io_loader_data;
+
wire [`MPRJ_IO_PADS-1:0] mprj_io_hldh_n;
wire [`MPRJ_IO_PADS-1:0] mprj_io_enh;
wire [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_oeb_n;
wire [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_vtrip_sel;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_slow_sel;
+ wire [`MPRJ_IO_PADS-1:0] mprj_io_holdover;
wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_en;
wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel;
wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol;
@@ -93,14 +136,22 @@
wire [`MPRJ_IO_PADS-1:0] mprj_io_in;
wire [`MPRJ_IO_PADS-1:0] mprj_io_out;
+ // Mega-Project Control (user-facing)
+ wire [`MPRJ_IO_PADS-1:0] user_io_oeb_n;
+ wire [`MPRJ_IO_PADS-1:0] user_io_in;
+ wire [`MPRJ_IO_PADS-1:0] user_io_out;
+
+ /* Padframe control signals */
+ wire [`MPRJ_IO_PADS-1:0] gpio_serial_link;
+ wire mgmt_serial_clock;
+ wire mgmt_serial_resetn;
+
+ // Power-on-reset signal. The reset pad generates the sense-inverted
+ // reset at 3.3V. The 1.8V signal and the inverted 1.8V signal are
+ // derived.
+
wire porb_h;
wire porb_l;
- wire por;
- wire SCK_core;
- wire SDI_core;
- wire CSB_core;
- wire SDO_core;
- wire SDO_enb;
chip_io padframe(
// Package Pins
@@ -110,22 +161,12 @@
.gpio(gpio),
.mprj_io(mprj_io),
.clock(clock),
- .RSTB(RSTB),
- .ser_rx(ser_rx),
- .ser_tx(ser_tx),
- .irq(irq),
- .SDO(SDO),
- .SDI(SDI),
- .CSB(CSB),
- .SCK(SCK),
+ .resetb(resetb),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
- .flash_io2(flash_io2),
- .flash_io3(flash_io3),
// SoC Core Interface
- .por(por),
.porb_h(porb_h),
.clock_core(clock_core),
.gpio_out_core(gpio_out_core),
@@ -134,36 +175,21 @@
.gpio_mode1_core(gpio_mode1_core),
.gpio_outenb_core(gpio_outenb_core),
.gpio_inenb_core(gpio_inenb_core),
- .SCK_core(SCK_core),
- .ser_rx_core(ser_rx_core),
- .ser_tx_core(ser_tx_core),
- .irq_pin_core(irq_pin_core),
.flash_csb_core(flash_csb_core),
.flash_clk_core(flash_clk_core),
.flash_csb_oeb_core(flash_csb_oeb_core),
.flash_clk_oeb_core(flash_clk_oeb_core),
.flash_io0_oeb_core(flash_io0_oeb_core),
.flash_io1_oeb_core(flash_io1_oeb_core),
- .flash_io2_oeb_core(flash_io2_oeb_core),
- .flash_io3_oeb_core(flash_io3_oeb_core),
.flash_csb_ieb_core(flash_csb_ieb_core),
.flash_clk_ieb_core(flash_clk_ieb_core),
.flash_io0_ieb_core(flash_io0_ieb_core),
.flash_io1_ieb_core(flash_io1_ieb_core),
- .flash_io2_ieb_core(flash_io2_ieb_core),
- .flash_io3_ieb_core(flash_io3_ieb_core),
.flash_io0_do_core(flash_io0_do_core),
.flash_io1_do_core(flash_io1_do_core),
- .flash_io2_do_core(flash_io2_do_core),
- .flash_io3_do_core(flash_io3_do_core),
.flash_io0_di_core(flash_io0_di_core),
.flash_io1_di_core(flash_io1_di_core),
- .flash_io2_di_core(flash_io2_di_core),
- .flash_io3_di_core(flash_io3_di_core),
- .SDI_core(SDI_core),
- .CSB_core(CSB_core),
.pll_clk16(pll_clk16),
- .SDO_core(SDO_core),
.mprj_io_in(mprj_io_in),
.mprj_io_out(mprj_io_out),
.mprj_io_oeb_n(mprj_io_oeb_n),
@@ -171,6 +197,9 @@
.mprj_io_enh(mprj_io_enh),
.mprj_io_inp_dis(mprj_io_inp_dis),
.mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
+ .mprj_io_vtrip_sel(mprj_io_vtrip_sel),
+ .mprj_io_slow_sel(mprj_io_slow_sel),
+ .mprj_io_holdover(mprj_io_holdover),
.mprj_io_analog_en(mprj_io_analog_en),
.mprj_io_analog_sel(mprj_io_analog_sel),
.mprj_io_analog_pol(mprj_io_analog_pol),
@@ -178,8 +207,8 @@
);
// SoC core
- wire striVe_clk;
- wire striVe_rstn;
+ wire caravel_clk;
+ wire caravel_rstn;
wire [7:0] spi_ro_config_core;
@@ -210,67 +239,52 @@
wire xbar_ack_i_core;
wire [31:0] xbar_dat_i_core;
+ // Mask revision
+ wire [31:0] mask_rev;
+
mgmt_core soc (
`ifdef LVS
.vdd1v8(vdd1v8),
.vss(vss),
`endif
+ // GPIO (1 pin)
.gpio_out_pad(gpio_out_core),
.gpio_in_pad(gpio_in_core),
.gpio_mode0_pad(gpio_mode0_core),
.gpio_mode1_pad(gpio_mode1_core),
.gpio_outenb_pad(gpio_outenb_core),
.gpio_inenb_pad(gpio_inenb_core),
- .spi_ro_config(spi_ro_config_core),
- .ser_tx(ser_tx_core),
- .ser_rx(ser_rx_core),
- .irq_pin(irq_pin_core),
+ // Primary SPI flash controller
.flash_csb(flash_csb_core),
.flash_clk(flash_clk_core),
.flash_csb_oeb(flash_csb_oeb_core),
.flash_clk_oeb(flash_clk_oeb_core),
.flash_io0_oeb(flash_io0_oeb_core),
.flash_io1_oeb(flash_io1_oeb_core),
- .flash_io2_oeb(flash_io2_oeb_core),
- .flash_io3_oeb(flash_io3_oeb_core),
.flash_csb_ieb(flash_csb_ieb_core),
.flash_clk_ieb(flash_clk_ieb_core),
.flash_io0_ieb(flash_io0_ieb_core),
.flash_io1_ieb(flash_io1_ieb_core),
- .flash_io2_ieb(flash_io2_ieb_core),
- .flash_io3_ieb(flash_io3_ieb_core),
.flash_io0_do(flash_io0_do_core),
.flash_io1_do(flash_io1_do_core),
- .flash_io2_do(flash_io2_do_core),
- .flash_io3_do(flash_io3_do_core),
.flash_io0_di(flash_io0_di_core),
.flash_io1_di(flash_io1_di_core),
- .flash_io2_di(flash_io2_di_core),
- .flash_io3_di(flash_io3_di_core),
- .por(por),
- .porb_l(porb_l),
+ // Power-on Reset
+ .porb(porb_l),
+ // Clocks and reset
.clock(clock_core),
.pll_clk16(pll_clk16),
- .SDI_core(SDI_core),
- .CSB_core(CSB_core),
- .SDO_core(SDO_core),
- .SDO_enb(SDO_enb),
- .striVe_clk(striVe_clk),
- .striVe_rstn(striVe_rstn),
+ .core_clk(caravel_clk),
+ .core_rstn(caravel_rstn),
// Logic Analyzer
.la_input(la_data_out_mprj),
.la_output(la_output_core),
.la_oen(la_oen),
// Mega Project IO Control
- .mprj_io_oeb_n(mprj_io_oeb_n),
- .mprj_io_enh(mprj_io_enh),
- .mprj_io_hldh_n(mprj_io_hldh_n),
- .mprj_io_inp_dis(mprj_io_inp_dis),
- .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
- .mprj_io_analog_en(mprj_io_analog_en),
- .mprj_io_analog_sel(mprj_io_analog_sel),
- .mprj_io_analog_pol(mprj_io_analog_pol),
- .mprj_io_dm(mprj_io_dm),
+ .mprj_io_loader_resetn(mprj_io_loader_resetn),
+ .mprj_io_loader_clock(mprj_io_loader_clock),
+ .mprj_io_loader_data(mprj_io_loader_data),
+ .mgmt_io_data(mgmt_io_data),
// Mega Project Slave ports (WB MI A)
.mprj_cyc_o(mprj_cyc_o_core),
.mprj_stb_o(mprj_stb_o_core),
@@ -288,18 +302,20 @@
.xbar_adr_o(xbar_adr_o_core),
.xbar_dat_o(xbar_dat_o_core),
.xbar_ack_i(xbar_ack_i_core),
- .xbar_dat_i(xbar_dat_i_core)
+ .xbar_dat_i(xbar_dat_i_core),
+ // mask data
+ .mask_rev(mask_rev)
);
- sky130_fd_sc_hd__ebufn_8 la_buf[127:0](
+ sky130_fd_sc_hd__ebufn_8 la_buf [127:0] (
.Z(la_data_in_mprj),
.A(la_output_core),
.TE_B(la_oen)
);
mega_project mprj (
- .wb_clk_i(striVe_clk),
- .wb_rst_i(!striVe_rstn),
+ .wb_clk_i(caravel_clk),
+ .wb_rst_i(!caravel_rstn),
// MGMT SoC Wishbone Slave
.wbs_cyc_i(mprj_cyc_o_core),
.wbs_stb_i(mprj_stb_o_core),
@@ -318,6 +334,45 @@
.io_in (mprj_io_in)
);
+ wire [`MPRJ_IO_PADS-1:0] gpio_serial_link_shifted;
+
+ assign gpio_serial_link_shifted = {mprj_io_loader_data, gpio_serial_link[`MPRJ_IO_PADS-1:1]};
+
+ gpio_control_block gpio_control_inst [`MPRJ_IO_PADS-1:0] (
+ // Management Soc-facing signals
+
+ resetn(mprj_io_loader_resetn),
+ serial_clock(mprj_io_loader_clock),
+
+ mgmt_gpio_io(mgmt_io_data),
+
+ // Serial data chain for pad configuration
+ serial_data_in(gpio_serial_link_shifted),
+ serial_data_out(gpio_serial_link),
+
+ // User-facing signals
+ user_gpio_out(user_io_out),
+ user_gpio_outenb(user_io_oeb_n),
+ user_gpio_in(user_io_in),
+
+ // Pad-facing signals (Pad GPIOv2)
+ pad_gpio_holdover(mprj_io_hldh_n),
+ pad_gpio_slow(mprj_io_slow),
+ pad_gpio_vtrip_sel(mprj_io_vtrip_sel),
+ pad_gpio_inenb(mprj_io_inp_dis),
+ pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel),
+ pad_gpio_vtrip_sel(mprj_io_vtrip_sel),
+ pad_gpio_slow_sel(mprj_io_slow_sel),
+ pad_gpio_holdover(mprj_io_holdover),
+ pad_gpio_ana_en(mprj_io_analog_en),
+ pad_gpio_ana_sel(mprj_io_analog_sel),
+ pad_gpio_ana_pol(mprj_io_analog_pol),
+ pad_gpio_dm(mprj_io_dm),
+ pad_gpio_outenb(mprj_io_oen_n),
+ pad_gpio_out(mprj_io_out),
+ pad_gpio_in(mprj_io_in)
+ );
+
sky130_fd_sc_hvl__lsbufhv2lv levelshift (
`ifdef LVS
.vpwr(vdd3v3),
@@ -330,4 +385,10 @@
.X(porb_l)
);
+ user_id_programming #(
+ .USER_PROJECT_ID(USER_PROJECT_ID)
+ ) user_id_value (
+ .mask_rev(mask_rev)
+ );
+
endmodule
diff --git a/verilog/rtl/striVe_clkrst.v b/verilog/rtl/caravel_clkrst.v
similarity index 60%
rename from verilog/rtl/striVe_clkrst.v
rename to verilog/rtl/caravel_clkrst.v
index ff42831..af40b8f 100644
--- a/verilog/rtl/striVe_clkrst.v
+++ b/verilog/rtl/caravel_clkrst.v
@@ -1,4 +1,4 @@
-module striVe_clkrst(
+module caravel_clkrst(
`ifdef LVS
input vdd1v8,
input vss,
@@ -6,14 +6,14 @@
input ext_clk_sel,
input ext_clk,
input pll_clk,
- input reset,
- input ext_reset,
- output clk,
- output resetn
+ input resetb,
+ input ext_reset, // NOTE: positive sense reset
+ output core_clk,
+ output resetb_sync
);
// Clock assignment (to do: make this glitch-free)
- assign clk = (ext_clk_sel == 1'b1) ? ext_clk : pll_clk;
+ assign core_clk = (ext_clk_sel == 1'b1) ? ext_clk : pll_clk;
// Reset assignment. "reset" comes from POR, while "ext_reset"
// comes from standalone SPI (and is normally zero unless
@@ -22,14 +22,14 @@
// Staged-delay reset
reg [2:0] reset_delay;
- always @(posedge clk or posedge reset) begin
- if (reset == 1'b1) begin
+ always @(posedge core_clk or negedge resetb) begin
+ if (resetb == 1'b0) begin
reset_delay <= 3'b111;
end else begin
reset_delay <= {1'b0, reset_delay[2:1]};
end
end
- assign resetn = ~(reset_delay[0] | ext_reset);
+ assign resetb_sync = ~(reset_delay[0] | ext_reset);
endmodule
diff --git a/verilog/rtl/caravel_spi.v b/verilog/rtl/caravel_spi.v
new file mode 100644
index 0000000..3abd227
--- /dev/null
+++ b/verilog/rtl/caravel_spi.v
@@ -0,0 +1,261 @@
+//-------------------------------------
+// SPI controller for Caravel (PicoSoC)
+//-------------------------------------
+// Written by Tim Edwards
+// efabless, inc. September 27, 2020
+//-------------------------------------
+
+`include "caravel_spi_slave.v"
+
+//-----------------------------------------------------------
+// This is a standalone slave SPI for the caravel chip that is
+// intended to be independent of the picosoc and independent
+// of all IP blocks except the power-on-reset. This SPI has
+// register outputs controlling the functions that critically
+// affect operation of the picosoc and so cannot be accessed
+// from the picosoc itself. This includes the PLL enables
+// and trim, and the crystal oscillator enable. It also has
+// a general reset for the picosoc, an IRQ input, a bypass for
+// the entire crystal oscillator and PLL chain, the
+// manufacturer and product IDs and product revision number.
+// To be independent of the 1.8V regulator, the slave SPI is
+// synthesized with the 3V digital library and runs off of
+// the 3V supply.
+//
+// This module is designed to be decoupled from the chip
+// padframe and redirected to the wishbone bus under
+// register control from the management SoC, such that the
+// contents can be accessed from the management core via the
+// SPI master.
+//
+//-----------------------------------------------------------
+
+//------------------------------------------------------------
+// Caravel defined registers:
+// Register 0: SPI status and control (unused & reserved)
+// Register 1 and 2: Manufacturer ID (0x0456) (readonly)
+// Register 3: Product ID (= 2) (readonly)
+// Register 4-7: Mask revision (readonly) --- Externally programmed
+// with via programming. Via programmed with a script to match
+// each customer ID.
+//
+// Register 8: PLL enable (1 bit)
+// Register 9: PLL bypass (1 bit)
+// Register 10: IRQ (1 bit)
+// Register 11: reset (1 bit)
+// Register 12: trap (1 bit) (readonly)
+// Register 13-16: PLL trim (26 bits)
+// Register 17: PLL output select (3 bits)
+// Register 18: PLL divider (5 bits)
+//------------------------------------------------------------
+
+module caravel_spi(
+`ifdef LVS
+ vdd, vss,
+`endif
+ RSTB, SCK, SDI, CSB, SDO, sdo_enb,
+ mgmt_sck, mgmt_sdi, mgmt_csb, mgmt_sdo,
+ pll_dco_ena, pll_div, pll_sel,
+ pll_trim, pll_bypass, irq, reset, trap,
+ mask_rev_in, pass_thru_reset,
+ pass_thru_mgmt_sck, pass_thru_mgmt_csb,
+ pass_thru_mgmt_sdi, pass_thru_mgmt_sdo,
+ pass_thru_user_sck, pass_thru_user_csb,
+ pass_thru_user_sdi, pass_thru_user_sdo
+);
+
+`ifdef LVS
+ inout vdd; // 3.3V supply
+ inout vss; // common ground
+`endif
+
+ input RSTB; // from padframe
+
+ input SCK; // from padframe
+ input SDI; // from padframe
+ input CSB; // from padframe
+ output SDO; // to padframe
+ output sdo_enb; // to padframe
+
+ input mgmt_sck; // from management SoC
+ input mgmt_sdi; // from management SoC
+ input mgmt_csb; // from management SoC
+ output mgmt_sdo; // to management SoC
+
+ output pll_dco_ena;
+ output [4:0] pll_div;
+ output [2:0] pll_sel;
+ output [25:0] pll_trim;
+ output pll_bypass;
+ output irq;
+ output reset;
+ input trap;
+ input [31:0] mask_rev_in; // metal programmed; 3.3V domain
+
+ // Pass-through programming mode for management area SPI flash
+ output pass_thru_reset;
+ output pass_thru_mgmt_sck;
+ output pass_thru_mgmt_csb;
+ output pass_thru_mgmt_sdi;
+ input pass_thru_mgmt_sdo;
+
+ // Pass-through programming mode for user area SPI flash
+ output pass_thru_user_sck;
+ output pass_thru_user_csb;
+ output pass_thru_user_sdi;
+ input pass_thru_user_sdo;
+
+ reg [25:0] pll_trim;
+ reg [4:0] pll_div;
+ reg [2:0] pll_sel;
+ reg pll_dco_ena;
+ reg pll_bypass;
+ reg reset_reg;
+ reg irq;
+
+ wire [7:0] odata;
+ wire [7:0] idata;
+ wire [7:0] iaddr;
+
+ wire trap;
+ wire rdstb;
+ wire wrstb;
+ wire pass_thru_mgmt; // Mode detected by spi_slave
+ wire pass_thru_mgmt_delay;
+ wire pass_thru_user; // Mode detected by spi_slave
+ wire pass_thru_user_delay;
+
+ // Connect to management SoC SPI master when mgmt_csb is low
+
+ wire loc_sck;
+ wire loc_csb;
+ wire loc_sdi;
+ wire loc_sdo;
+ wire loc_sdoenb;
+
+ assign loc_csb = (mgmt_csb == 1'b0) ? 1'b0 : CSB;
+ assign loc_sck = (mgmt_csb == 1'b0) ? mgmt_sck : SCK;
+ assign loc_sdi = (mgmt_csb == 1'b0) ? mgmt_sdi : SDI;
+
+ assign mgmt_sdo = (mgmt_csb == 1'b0) ? loc_sdo : 1'b0;
+ assign sdo_enb = (mgmt_csb == 1'b0) ? 1'b1 : loc_sdoenb;
+
+ // Pass-through mode handling
+
+ assign pass_thru_mgmt_csb = ~pass_thru_mgmt_delay;
+ assign pass_thru_mgmt_sck = pass_thru_mgmt ? SCK : 1'b0;
+ assign pass_thru_mgmt_sdi = pass_thru_mgmt ? SDI : 1'b0;
+
+ assign pass_thru_user_csb = ~pass_thru_user_delay;
+ assign pass_thru_user_sck = pass_thru_user ? SCK : 1'b0;
+ assign pass_thru_user_sdi = pass_thru_user ? SDI : 1'b0;
+
+ assign SDO = pass_thru_mgmt ? pass_thru_mgmt_sdo :
+ pass_thru_user ? pass_thru_user_sdo : loc_sdo;
+ assign reset = pass_thru_reset ? 1'b1 : reset_reg;
+
+ // Instantiate the SPI slave module
+
+ caravel_spi_slave U1 (
+ .reset(~RSTB),
+ .SCK(loc_sck),
+ .SDI(loc_sdi),
+ .CSB(loc_csb),
+ .SDO(loc_sdo),
+ .sdoenb(loc_sdoenb),
+ .idata(odata),
+ .odata(idata),
+ .oaddr(iaddr),
+ .rdstb(rdstb),
+ .wrstb(wrstb),
+ .pass_thru_mgmt(pass_thru_mgmt),
+ .pass_thru_mgmt_delay(pass_thru_mgmt_delay),
+ .pass_thru_user(pass_thru_user),
+ .pass_thru_user_delay(pass_thru_user_delay),
+ .pass_thru_reset(pass_thru_reset)
+ );
+
+ wire [11:0] mfgr_id;
+ wire [7:0] prod_id;
+ wire [31:0] mask_rev;
+
+ assign mfgr_id = 12'h456; // Hard-coded
+ assign prod_id = 8'h10; // Hard-coded
+ assign mask_rev = mask_rev_in; // Copy in to out.
+
+ // Send register contents to odata on SPI read command
+ // All values are 1-4 bits and no shadow registers are required.
+
+ assign odata =
+ (iaddr == 8'h00) ? 8'h00 : // SPI status (fixed)
+ (iaddr == 8'h01) ? {4'h0, mfgr_id[11:8]} : // Manufacturer ID (fixed)
+ (iaddr == 8'h02) ? mfgr_id[7:0] : // Manufacturer ID (fixed)
+ (iaddr == 8'h03) ? prod_id : // Product ID (fixed)
+ (iaddr == 8'h04) ? mask_rev[31:24] : // Mask rev (metal programmed)
+ (iaddr == 8'h05) ? mask_rev[23:16] : // Mask rev (metal programmed)
+ (iaddr == 8'h06) ? mask_rev[15:8] : // Mask rev (metal programmed)
+ (iaddr == 8'h07) ? mask_rev[7:0] : // Mask rev (metal programmed)
+
+ (iaddr == 8'h08) ? {7'b0000000, pll_dco_ena} :
+ (iaddr == 8'h09) ? {7'b0000000, pll_bypass} :
+ (iaddr == 8'h0a) ? {7'b0000000, irq} :
+ (iaddr == 8'h0b) ? {7'b0000000, reset} :
+ (iaddr == 8'h0c) ? {7'b0000000, trap} :
+ (iaddr == 8'h0d) ? pll_trim[7:0] :
+ (iaddr == 8'h0e) ? pll_trim[15:8] :
+ (iaddr == 8'h0f) ? pll_trim[23:16] :
+ (iaddr == 8'h10) ? {6'b000000, pll_trim[25:24]} :
+ (iaddr == 8'h11) ? {5'b00000, pll_sel} :
+ (iaddr == 8'h12) ? {3'b000, pll_div} :
+ 8'h00; // Default
+
+ // Register mapping and I/O to slave module
+
+ always @(posedge SCK or negedge RSTB) begin
+ if (RSTB == 1'b0) begin
+ // Set trim for PLL at (almost) slowest rate (~90MHz). However,
+ // pll_trim[12] must be set to zero for proper startup.
+ pll_trim <= 26'b11111111111110111111111111;
+ pll_sel <= 3'b000;
+ pll_div <= 5'b00100; // Default divide-by-8
+ pll_dco_ena <= 1'b1; // Default free-running PLL
+ pll_bypass <= 1'b1; // NOTE: Default bypass mode (don't use PLL)
+ irq <= 1'b0;
+ reset_reg <= 1'b0;
+ end else if (wrstb == 1'b1) begin
+ case (iaddr)
+ 8'h08: begin
+ pll_dco_ena <= idata[0];
+ end
+ 8'h09: begin
+ pll_bypass <= idata[0];
+ end
+ 8'h0a: begin
+ irq <= idata[0];
+ end
+ 8'h0b: begin
+ reset_reg <= idata[0];
+ end
+ // Register 0xc is read-only
+ 8'h0d: begin
+ pll_trim[7:0] <= idata;
+ end
+ 8'h0e: begin
+ pll_trim[15:8] <= idata;
+ end
+ 8'h0f: begin
+ pll_trim[23:16] <= idata;
+ end
+ 8'h10: begin
+ pll_trim[25:24] <= idata[1:0];
+ end
+ 8'h11: begin
+ pll_sel <= idata[2:0];
+ end
+ 8'h12: begin
+ pll_div <= idata[4:0];
+ end
+ endcase // (iaddr)
+ end
+ end
+endmodule // caravel_spi
diff --git a/verilog/rtl/caravel_spi_slave.v b/verilog/rtl/caravel_spi_slave.v
new file mode 100644
index 0000000..e8a6494
--- /dev/null
+++ b/verilog/rtl/caravel_spi_slave.v
@@ -0,0 +1,221 @@
+//------------------------------------------------------
+// caravel_spi_slave.v
+//------------------------------------------------------
+// General purpose SPI slave module for the Caravel chip
+//------------------------------------------------------
+// Written by Tim Edwards
+// efabless, inc., September 28, 2020
+//------------------------------------------------
+// This file is distributed free and open source
+//------------------------------------------------
+
+// SCK --- Clock input
+// SDI --- Data input
+// SDO --- Data output
+// CSB --- Chip select (sense negative)
+// idata --- Data from chip to transmit out, in 8 bits
+// odata --- Input data to chip, in 8 bits
+// addr --- Decoded address to upstream circuits
+// rdstb --- Read strobe, tells upstream circuit to supply next byte to idata
+// wrstb --- Write strobe, tells upstream circuit to latch odata.
+
+// Data format (general purpose):
+// 8 bit format
+// 1st byte: Command word (see below)
+// 2nd byte: Address word (register 0 to 255)
+// 3rd byte: Data word (value 0 to 255)
+
+// Command format:
+// 00000000 No operation
+// 10000000 Write until CSB raised
+// 01000000 Read until CSB raised
+// 11000000 Simultaneous read/write until CSB raised
+// 11000100 Pass-through read/write to management area flash SPI until CSB raised
+// 11000101 Pass-through read/write to user area flash SPI until CSB raised
+// wrnnn000 Read/write as above, for nnn = 1 to 7 bytes, then terminate
+
+// Lower three bits are reserved for future use.
+// All serial bytes are read and written msb first.
+
+// Fixed control and status registers
+
+// Address 0 is reserved and contains flags for SPI mode. This is
+// currently undefined and is always value 0.
+// Address 1 is reserved and contains manufacturer ID low 8 bits.
+// Address 2 is reserved and contains manufacturer ID high 4 bits.
+// Address 3 is reserved and contains product ID (8 bits).
+// Addresses 4 to 7 are reserved and contain the mask ID (32 bits).
+// Addresses 8 to 255 are available for general purpose use.
+
+`define COMMAND 3'b000
+`define ADDRESS 3'b001
+`define DATA 3'b010
+`define USERPASS 3'b100
+`define MGMTPASS 3'b101
+
+module caravel_spi_slave(reset, SCK, SDI, CSB, SDO,
+ sdoenb, idata, odata, oaddr, rdstb, wrstb,
+ pass_thru_mgmt, pass_thru_mgmt_delay,
+ pass_thru_user, pass_thru_user_delay, pass_thru_reset);
+
+ input reset;
+ input SCK;
+ input SDI;
+ input CSB;
+ output SDO;
+ output sdoenb;
+ input [7:0] idata;
+ output [7:0] odata;
+ output [7:0] oaddr;
+ output rdstb;
+ output wrstb;
+ output pass_thru_mgmt;
+ output pass_thru_mgmt_delay;
+ output pass_thru_user;
+ output pass_thru_user_delay;
+ output pass_thru_reset;
+
+ reg [7:0] addr;
+ reg wrstb;
+ reg rdstb;
+ reg sdoenb;
+ reg [2:0] state;
+ reg [2:0] count;
+ reg writemode;
+ reg readmode;
+ reg [2:0] fixed;
+ wire [7:0] odata;
+ reg [6:0] predata;
+ wire [7:0] oaddr;
+ reg [7:0] ldata;
+ reg pass_thru_mgmt;
+ reg pass_thru_mgmt_delay;
+ reg pre_pass_thru_mgmt;
+ reg pass_thru_user;
+ reg pass_thru_user_delay;
+ reg pre_pass_thru_user;
+ wire csb_reset;
+
+ assign odata = {predata, SDI};
+ assign oaddr = (state == `ADDRESS) ? {addr[6:0], SDI} : addr;
+ assign SDO = ldata[7];
+ assign csb_reset = CSB | reset;
+ assign pass_thru_reset = pass_thru_mgmt_delay | pre_pass_thru_mgmt;
+
+ // Readback data is captured on the falling edge of SCK so that
+ // it is guaranteed valid at the next rising edge.
+ always @(negedge SCK or posedge CSB) begin
+ if (CSB == 1'b1) begin
+ wrstb <= 1'b0;
+ ldata <= 8'b00000000;
+ sdoenb <= 1'b1;
+ end else begin
+
+ // After CSB low, 1st SCK starts command
+
+ if (state == `DATA) begin
+ if (readmode == 1'b1) begin
+ sdoenb <= 1'b0;
+ if (count == 3'b000) begin
+ ldata <= idata;
+ end else begin
+ ldata <= {ldata[6:0], 1'b0}; // Shift out
+ end
+ end else begin
+ sdoenb <= 1'b1;
+ end
+
+ // Apply write strobe on SCK negative edge on the next-to-last
+ // data bit so that it updates data on the rising edge of SCK
+ // on the last data bit.
+
+ if (count == 3'b111) begin
+ if (writemode == 1'b1) begin
+ wrstb <= 1'b1;
+ end
+ end else begin
+ wrstb <= 1'b0;
+ end
+ end else if (state == `MGMTPASS || state == `USERPASS) begin
+ wrstb <= 1'b0;
+ sdoenb <= 1'b0;
+ end else begin
+ wrstb <= 1'b0;
+ sdoenb <= 1'b1;
+ end // ! state `DATA
+ end // ! CSB
+ end // always @ ~SCK
+
+ always @(posedge SCK or posedge CSB) begin
+ if (csb_reset == 1'b1) begin
+ // Default state on reset
+ addr <= 8'h00;
+ rdstb <= 1'b0;
+ predata <= 7'b0000000;
+ state <= `COMMAND;
+ count <= 3'b000;
+ readmode <= 1'b0;
+ writemode <= 1'b0;
+ fixed <= 3'b000;
+ pass_thru_mgmt <= 1'b0;
+ pass_thru_mgmt_delay <= 1'b0;
+ pre_pass_thru_mgmt <= 1'b0;
+ pass_thru_user = 1'b0;
+ pass_thru_user_delay <= 1'b0;
+ pre_pass_thru_user <= 1'b0;
+ end else begin
+ // After CSB low, 1st SCK starts command
+ if (state == `COMMAND) begin
+ rdstb <= 1'b0;
+ count <= count + 1;
+ if (count == 3'b000) begin
+ writemode <= SDI;
+ end else if (count == 3'b001) begin
+ readmode <= SDI;
+ end else if (count < 3'b101) begin
+ fixed <= {fixed[1:0], SDI};
+ end else if (count < 3'b110) begin
+ pass_thru_mgmt_delay <= pre_pass_thru_mgmt;
+ pass_thru_user_delay <= pre_pass_thru_user;
+ end else if (count == 3'b111) begin
+ if (pre_pass_thru_mgmt == 1'b1) begin
+ state <= `MGMTPASS;
+ pre_pass_thru_mgmt <= 1'b0;
+ end else if (pre_pass_thru_user == 1'b1) begin
+ state <= `USERPASS;
+ pre_pass_thru_user <= 1'b0;
+ end else begin
+ state <= `ADDRESS;
+ end
+ end
+ end else if (state == `ADDRESS) begin
+ count <= count + 1;
+ addr <= {addr[6:0], SDI};
+ if (count == 3'b111) begin
+ if (readmode == 1'b1) begin
+ rdstb <= 1'b1;
+ end
+ state <= `DATA;
+ end else begin
+ rdstb <= 1'b0;
+ end
+ end else if (state == `DATA) begin
+ predata <= {predata[6:0], SDI};
+ count <= count + 1;
+ if (count == 3'b111) begin
+ if (fixed == 3'b001) begin
+ state <= `COMMAND;
+ end else if (fixed != 3'b000) begin
+ fixed <= fixed - 1;
+ addr <= addr + 1; // Auto increment address (fixed)
+ end else begin
+ addr <= addr + 1; // Auto increment address (streaming)
+ end
+ end else begin
+ rdstb <= 1'b0;
+ end
+ end // ! state `DATA
+ end // ! CSB
+ end // always @ SCK
+
+endmodule // caravel_spi_slave
diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v
index f3bba5e..bd359b9 100644
--- a/verilog/rtl/chip_io.v
+++ b/verilog/rtl/chip_io.v
@@ -3,62 +3,37 @@
inout vdd3v3,
inout vdd1v8,
inout vss,
- input [1:0] gpio,
+ inout gpio,
inout clock,
- inout RSTB,
- inout ser_rx,
- output ser_tx,
- inout irq,
- output SDO,
- inout SDI,
- inout CSB,
- inout SCK,
+ inout resetb,
output flash_csb,
output flash_clk,
output flash_io0,
output flash_io1,
- output flash_io2,
- output flash_io3,
// Chip Core Interface
- input por,
output porb_h,
output clock_core,
- input [1:0] gpio_out_core,
- output [1:0] gpio_in_core,
- input [1:0] gpio_mode0_core,
- input [1:0] gpio_mode1_core,
- input [1:0] gpio_outenb_core,
- input [1:0] gpio_inenb_core,
- output SCK_core,
- output ser_rx_core,
- inout ser_tx_core,
- output irq_pin_core,
+ input gpio_out_core,
+ output gpio_in_core,
+ input gpio_mode0_core,
+ input gpio_mode1_core,
+ input gpio_outenb_core,
+ input gpio_inenb_core,
input flash_csb_core,
input flash_clk_core,
input flash_csb_oeb_core,
input flash_clk_oeb_core,
input flash_io0_oeb_core,
input flash_io1_oeb_core,
- input flash_io2_oeb_core,
- input flash_io3_oeb_core,
input flash_csb_ieb_core,
input flash_clk_ieb_core,
input flash_io0_ieb_core,
input flash_io1_ieb_core,
- input flash_io2_ieb_core,
- input flash_io3_ieb_core,
input flash_io0_do_core,
input flash_io1_do_core,
- input flash_io2_do_core,
- input flash_io3_do_core,
output flash_io0_di_core,
output flash_io1_di_core,
- output flash_io2_di_core,
- output flash_io3_di_core,
- output SDI_core,
- output CSB_core,
input pll_clk16,
- input SDO_core,
// Mega-project IOs
input [`MPRJ_IO_PADS-1:0] mprj_io,
input [`MPRJ_IO_PADS-1:0] mprj_io_out,
@@ -67,6 +42,9 @@
input [`MPRJ_IO_PADS-1:0] mprj_io_enh,
input [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis,
input [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel,
+ input [`MPRJ_IO_PADS-1:0] mprj_io_vtrip_sel,
+ input [`MPRJ_IO_PADS-1:0] mprj_io_slow_sel,
+ input [`MPRJ_IO_PADS-1:0] mprj_io_holdover,
input [`MPRJ_IO_PADS-1:0] mprj_io_analog_en,
input [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel,
input [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol,
@@ -150,22 +128,16 @@
.src_bdy_lvc2()
);
- wire [5:0] dm_all;
- assign dm_all = {gpio_mode1_core[1], gpio_mode1_core[1], gpio_mode0_core[1],
- gpio_mode1_core[0], gpio_mode1_core[0], gpio_mode0_core[0]};
-
+ wire [2:0] dm_all =
+ {gpio_mode1_core, gpio_mode1_core, gpio_mode0_core};
wire[2:0] flash_io0_mode =
{flash_io0_ieb_core, flash_io0_ieb_core, flash_io0_oeb_core};
wire[2:0] flash_io1_mode =
{flash_io1_ieb_core, flash_io1_ieb_core, flash_io1_oeb_core};
- wire[2:0] flash_io2_mode =
- {flash_io2_ieb_core, flash_io2_ieb_core, flash_io2_oeb_core};
- wire[2:0] flash_io3_mode =
- {flash_io3_ieb_core, flash_io3_ieb_core, flash_io3_oeb_core};
- // GPIO pads
- `INOUT_PAD_V(
- gpio, gpio_in_core, gpio_out_core, 2,
+ // GPIO pad
+ `INOUT_PAD(
+ gpio, gpio_in_core, gpio_out_core,
gpio_inenb_core, gpio_outenb_core, dm_all);
// Flash pads
@@ -175,35 +147,22 @@
`INOUT_PAD(
flash_io1, flash_io1_di_core, flash_io1_do_core,
flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode);
- `INOUT_PAD(
- flash_io2, flash_io2_di_core, flash_io2_do_core,
- flash_io2_ieb_core, flash_io2_oeb_core, flash_io2_mode);
- `INOUT_PAD(
- flash_io3, flash_io3_di_core, flash_io3_do_core,
- flash_io3_ieb_core, flash_io3_oeb_core, flash_io3_mode);
`INPUT_PAD(clock, clock_core);
- `INPUT_PAD(irq, irq_pin_core);
- `INPUT_PAD(SDI, SDI_core);
- `INPUT_PAD(CSB, CSB_core);
- `INPUT_PAD(SCK, SCK_core);
- `INPUT_PAD(ser_rx, ser_rx_core);
// Output Pads
- `OUTPUT_PAD(SDO, SDO_core, vdd1v8, SDO_enb);
`OUTPUT_PAD(flash_csb, flash_csb_core, flash_csb_ieb_core, flash_csb_oeb_core);
`OUTPUT_PAD(flash_clk, flash_clk_core, flash_clk_ieb_core, flash_clk_oeb_core);
- `OUTPUT_PAD(ser_tx, ser_tx_core, vdd1v8, ser_tx_ena);
// NOTE: The analog_out pad from the raven chip has been replaced by
- // the digital reset input RSTB on striVe due to the lack of an on-board
+ // the digital reset input resetb on caravel due to the lack of an on-board
// power-on-reset circuit. The XRES pad is used for providing a glitch-
// free reset.
- s8iom0s8_top_xres4v2 RSTB_pad (
+ s8iom0s8_top_xres4v2 resetb_pad (
`ABUTMENT_PINS
`ifndef TOP_ROUTING
- .pad(RSTB),
+ .pad(resetb),
`endif
.tie_weak_hi_h(xresloop), // Loop-back connection to pad through pad_a_esd_h
.tie_hi_esd(),
diff --git a/verilog/rtl/convert_gpio_sigs.v b/verilog/rtl/convert_gpio_sigs.v
new file mode 100644
index 0000000..cac5141
--- /dev/null
+++ b/verilog/rtl/convert_gpio_sigs.v
@@ -0,0 +1,35 @@
+/* Convert the standard set of GPIO signals: input, output, output_enb,
+ * pullup, and pulldown into the set needed by the s8 GPIO pads:
+ * input, output, output_enb, input_enb, mode. Note that dm[2] on
+ * thepads is always equal to dm[1] in this setup, so mode is shown as
+ * only a 2-bit signal.
+ *
+ * This module is bit-sliced. Instantiate once for each GPIO pad.
+ * (Caravel has only one GPIO pad, so bit-slicing is irrelevant.)
+ */
+
+module convert_gpio_sigs (
+ input gpio_out,
+ input gpio_outenb,
+ input gpio_pu,
+ input gpio_pd,
+ output gpio_out_pad,
+ output gpio_outenb_pad,
+ output gpio_inenb_pad,
+ output gpio_mode1_pad,
+ output gpio_mode0_pad
+);
+
+ assign gpio_out_pad = (gpio_pu == 1'b0 && gpio_pd == 1'b0) ? gpio_out :
+ (gpio_pu == 1'b1) ? 1 : 0;
+
+ assign gpio_outenb_pad = (gpio_outenb == 1'b0) ? 0 :
+ (gpio_pu == 1'b1 || gpio_pd == 1'b1) ? 0 : 1;
+
+ assign gpio_inenb_pad = ~gpio_outenb;
+
+ assign gpio_mode1_pad = ~gpio_outenb_pad;
+ assign gpio_mode0_pad = gpio_outenb;
+
+endmodule
+
diff --git a/verilog/rtl/counter_timer.v b/verilog/rtl/counter_timer.v
new file mode 100755
index 0000000..ccd1431
--- /dev/null
+++ b/verilog/rtl/counter_timer.v
@@ -0,0 +1,169 @@
+/* Simple 32-bit counter-timer for Caravel. */
+
+module counter_timer_wb # (
+ parameter BASE_ADR = 32'h2200_0000,
+ parameter CONFIG = 8'h00,
+ parameter VALUE = 8'h04,
+ parameter DATA = 8'h08
+) (
+ input wb_clk_i,
+ input wb_rst_i,
+ input [31:0] wb_adr_i,
+ input [31:0] wb_dat_i,
+ input [3:0] wb_sel_i,
+ input wb_we_i,
+ input wb_cyc_i,
+ input wb_stb_i,
+
+ output wb_ack_o,
+ output [31:0] wb_dat_o,
+ output irq
+);
+ wire [31:0] counter_timer_reg_cfg_do;
+ wire [31:0] counter_timer_reg_val_do;
+ wire [31:0] counter_timer_reg_dat_do;
+
+ wire resetn = ~wb_rst_i;
+ wire valid = wb_stb_i && wb_cyc_i;
+ wire counter_timer_reg_cfg_sel = valid && (wb_adr_i == (BASE_ADR | CONFIG));
+ wire counter_timer_reg_val_sel = valid && (wb_adr_i == (BASE_ADR | VALUE));
+ wire counter_timer_reg_dat_sel = valid && (wb_adr_i == (BASE_ADR | DATA));
+
+ wire reg_cfg_we = (counter_timer_reg_cfg_sel) ?
+ (wb_sel_i[0] & {wb_we_i}): 1'b0;
+ wire [3:0] reg_val_we = (counter_timer_reg_val_sel) ?
+ (wb_sel_i & {4{wb_we_i}}): 4'b0000;
+ wire [3:0] reg_dat_we = (counter_timer_reg_dat_sel) ?
+ (wb_sel_i & {4{wb_we_i}}): 4'b0000;
+
+ wire [31:0] mem_wdata = wb_dat_i;
+ wire reg_dat_re = counter_timer_reg_dat_sel && !wb_sel_i && ~wb_we_i;
+
+ assign wb_dat_o = (counter_timer_reg_cfg_sel) ? counter_timer_reg_cfg_do :
+ (counter_timer_reg_val_sel) ? counter_timer_reg_val_do :
+ counter_timer_reg_dat_do;
+ assign wb_ack_o = counter_timer_reg_cfg_sel || counter_timer_reg_val_sel ||
+ counter_timer_reg_dat_sel;
+
+ counter_timer counter_timer_inst (
+ .resetn(resetn),
+ .clkin(wb_clk_i),
+ .reg_val_we(reg_val_we),
+ .reg_val_di(mem_wdata),
+ .reg_val_do(counter_timer_reg_val_do),
+ .reg_cfg_we(reg_cfg_we),
+ .reg_cfg_di(mem_wdata),
+ .reg_cfg_do(counter_timer_reg_cfg_do),
+ .reg_dat_we(reg_dat_we),
+ .reg_dat_di(mem_wdata),
+ .reg_dat_do(counter_timer_reg_dat_do),
+ .irq_out(irq)
+ );
+
+endmodule
+
+module counter_timer (
+ input resetn,
+ input clkin,
+
+ input [3:0] reg_val_we,
+ input [31:0] reg_val_di,
+ output [31:0] reg_val_do,
+
+ input reg_cfg_we,
+ input [31:0] reg_cfg_di,
+ output [31:0] reg_cfg_do,
+
+ input [3:0] reg_dat_we,
+ input [31:0] reg_dat_di,
+ output [31:0] reg_dat_do,
+ output irq_out
+);
+
+reg [31:0] value_cur;
+reg [31:0] value_reset;
+reg irq_out;
+
+reg enable; // Enable (start) the counter/timer
+reg oneshot; // Set oneshot (1) mode or continuous (0) mode
+reg updown; // Count up (1) or down (0)
+reg irq_ena; // Enable interrupt on timeout
+
+// Configuration register
+
+assign reg_cfg_do = {28'd0, irq_ena, updown, oneshot, enable};
+
+always @(posedge clkin or negedge resetn) begin
+ if (resetn == 1'b0) begin
+ enable <= 1'b0;
+ oneshot <= 1'b0;
+ updown <= 1'b0;
+ irq_ena <= 1'b0;
+ end else begin
+ if (reg_cfg_we) begin
+ enable <= reg_cfg_di[0];
+ oneshot <= reg_cfg_di[1];
+ updown <= reg_cfg_di[2];
+ irq_ena <= reg_cfg_di[3];
+ end
+ end
+end
+
+// Counter/timer reset value register
+
+assign reg_val_do = value_reset;
+
+always @(posedge clkin or negedge resetn) begin
+ if (resetn == 1'b0) begin
+ value_reset <= 32'd0;
+ end else begin
+ if (reg_val_we[3]) value_reset <= reg_val_di[31:24];
+ if (reg_val_we[2]) value_reset <= reg_val_di[23:16];
+ if (reg_val_we[1]) value_reset <= reg_val_di[15:8];
+ if (reg_val_we[0]) value_reset <= reg_val_di[7:0];
+ end
+end
+
+assign reg_dat_do = value_cur;
+
+// Counter/timer current value register and timer implementation
+
+always @(posedge clkin or negedge resetn) begin
+ if (resetn == 1'b0) begin
+ value_cur <= 32'd0;
+ irq_out <= 1'b0;
+ end else begin
+ if (reg_dat_we != 4'b0000) begin
+ if (reg_dat_we[3] == 1'b1) value_cur[31:24] <= reg_dat_di[31:24];
+ if (reg_dat_we[2] == 1'b1) value_cur[23:16] <= reg_dat_di[23:16];
+ if (reg_dat_we[1] == 1'b1) value_cur[15:8] <= reg_dat_di[15:8];
+ if (reg_dat_we[0] == 1'b1) value_cur[7:0] <= reg_dat_di[7:0];
+ end else if (enable == 1'b1) begin
+ if (updown == 1'b1) begin
+ if (value_cur == value_reset) begin
+ if (oneshot != 1'b1) begin
+ value_cur <= 32'd0;
+ end
+ irq_out <= irq_ena;
+ end else begin
+ value_cur <= value_cur + 1; // count up
+ irq_out <= 1'b0;
+ end
+ end else begin
+ if (value_cur == 32'd0) begin
+ if (oneshot != 1'b1) begin
+ value_cur <= value_reset;
+ end
+ irq_out <= irq_ena;
+ end else begin
+ value_cur <= value_cur - 1; // count down
+ irq_out <= 1'b0;
+ end
+ end
+ end else begin
+ irq_out <= 1'b0;
+ end
+ end
+end
+
+endmodule
diff --git a/verilog/rtl/digital_pll.v b/verilog/rtl/digital_pll.v
index 0f22108..9754180 100644
--- a/verilog/rtl/digital_pll.v
+++ b/verilog/rtl/digital_pll.v
@@ -9,14 +9,14 @@
vdd,
vss,
`endif
- reset, extclk_sel, osc, clockc, clockp, clockd, div, sel, dco, ext_trim);
+ resetb, extclk_sel, osc, clockc, clockp, clockd, div, sel, dco, ext_trim);
`ifdef LVS
input vdd;
input vss;
`endif
- input reset; // Sense positive reset
+ input resetb; // Sense negative reset
input extclk_sel; // External clock select (acts as 2nd reset)
input osc; // Input oscillator to match
input [4:0] div; // PLL feedback division ratio
@@ -31,7 +31,8 @@
wire [25:0] itrim; // Internally generated trim bits
wire [25:0] otrim; // Trim bits applied to the ring oscillator
wire [3:0] nint; // Internal divided down clocks
- wire resetb; // Internal positivie sense reset
+ wire reset; // Internal positive sense reset
+ wire resetbb; // Internal buffered negative sense reset
wire creset; // Controller reset
wire ireset; // Internal reset (external reset OR extclk_sel)
@@ -42,17 +43,17 @@
assign creset = (dco == 1'b0) ? ireset : 1'b1;
ring_osc2x13 ringosc (
- .reset(ireset),
- .trim(itrim),
- .clockp(clockp)
+ .reset(ireset),
+ .trim(itrim),
+ .clockp(clockp)
);
digital_pll_controller pll_control (
- .reset(creset),
- .clock(clockp[0]),
- .osc(osc),
- .div(div),
- .trim(otrim)
+ .reset(creset),
+ .clock(clockp[0]),
+ .osc(osc),
+ .div(div),
+ .trim(otrim)
);
// Select core clock output
@@ -62,11 +63,11 @@
(sel == 3'b011) ? clockd[2] :
clockd[3];
- // Derive negative-sense reset from the input positive-sense reset
+ // Derive internal negative-sense reset from the input negative-sense reset
- sky130_fd_sc_hd__inv_4 irb (
- .A(reset),
- .Y(resetb)
+ sky130_fd_sc_hd__buf_8 irbb (
+ .A(resetb),
+ .X(resetbb)
);
// Create divided down clocks. The inverted output only comes
@@ -74,34 +75,34 @@
// reset has to be inverted as well.
sky130_fd_sc_hd__dfrbp_1 idiv2 (
- .CLK(clockp[1]),
- .D(clockd[0]),
- .Q(nint[0]),
- .Q_N(clockd[0]),
- .RESET_B(resetb)
+ .CLK(clockp[1]),
+ .D(clockd[0]),
+ .Q(nint[0]),
+ .Q_N(clockd[0]),
+ .RESET_B(resetbb)
);
sky130_fd_sc_hd__dfrbp_1 idiv4 (
- .CLK(clockd[0]),
- .D(clockd[1]),
- .Q(nint[1]),
- .Q_N(clockd[1]),
- .RESET_B(resetb)
+ .CLK(clockd[0]),
+ .D(clockd[1]),
+ .Q(nint[1]),
+ .Q_N(clockd[1]),
+ .RESET_B(resetbb)
);
sky130_fd_sc_hd__dfrbp_1 idiv8 (
- .CLK(clockd[1]),
- .D(clockd[2]),
- .Q(nint[2]),
- .Q_N(clockd[2]),
- .RESET_B(resetb)
+ .CLK(clockd[1]),
+ .D(clockd[2]),
+ .Q(nint[2]),
+ .Q_N(clockd[2]),
+ .RESET_B(resetbb)
);
sky130_fd_sc_hd__dfrbp_1 idiv16 (
- .CLK(clockd[2]),
- .D(clockd[3]),
- .Q(nint[3]),
- .Q_N(clockd[3]),
- .RESET_B(resetb)
+ .CLK(clockd[2]),
+ .D(clockd[3]),
+ .Q(nint[3]),
+ .Q_N(clockd[3]),
+ .RESET_B(resetbb)
);
endmodule
diff --git a/verilog/rtl/gpio_control_block.v b/verilog/rtl/gpio_control_block.v
new file mode 100644
index 0000000..1575841
--- /dev/null
+++ b/verilog/rtl/gpio_control_block.v
@@ -0,0 +1,200 @@
+/*
+ *---------------------------------------------------------------------
+ * This block interfaces between the sky130_fd_io GPIOv2 pad, the
+ * caravel management area, and the user project area.
+ *
+ * The management area has ultimate control over the setting of the
+ * pad, and can modify all core-voltage inputs to the pad and monitor
+ * the output.
+ *
+ * The user project will rely on the management SoC startup program
+ * to configure each I/O pad to a fixed configuration except for
+ * the output enable which remains under user control.
+ *
+ * This module is bit-sliced. Instantiate once for each GPIO pad.
+ *
+ *---------------------------------------------------------------------
+ */
+
+/*
+ *---------------------------------------------------------------------
+ *
+ * This module instantiates a shift register chain that passes through
+ * each gpio cell. These are connected end-to-end around the padframe
+ * periphery. The purpose is to avoid a massive number of control
+ * wires between the digital core and I/O, passing through the user area.
+ *
+ * See mprj_ctrl.v for the module that registers the data for each
+ * I/O and drives the input to the shift register.
+ *
+ *---------------------------------------------------------------------
+ */
+
+module gpio_control_block #(
+ parameter PAD_CTRL_BITS = 13
+) (
+ // Management Soc-facing signals
+ input resetn, // Global reset
+ input serial_clock,
+
+ inout mgmt_gpio_io, // Management to/from pad
+
+ // Serial data chain for pad configuration
+ input serial_data_in,
+ output serial_data_out,
+
+ // User-facing signals
+ input user_gpio_out, // User space to pad
+ input user_gpio_outenb, // Output enable (user)
+ output user_gpio_in, // Pad to user space
+
+ // Pad-facing signals (Pad GPIOv2)
+ output pad_gpio_holdover,
+ output pad_gpio_slow_sel,
+ output pad_gpio_vtrip_sel,
+ output pad_gpio_inenb,
+ output pad_gpio_ib_mode_sel,
+ output pad_gpio_ana_en,
+ output pad_gpio_ana_sel,
+ output pad_gpio_ana_pol,
+ output [2:0] pad_gpio_dm,
+ output pad_gpio_outenb,
+ output pad_gpio_out,
+ input pad_gpio_in
+);
+
+ /* Parameters defining the bit offset of each function in the chain */
+ localparam MGMT_EN = 0;
+ localparam OEB = 1;
+ localparam HLDH = 2;
+ localparam ENH = 3;
+ localparam INP_DIS = 4;
+ localparam MOD_SEL = 5;
+ localparam AN_EN = 6;
+ localparam AN_SEL = 7;
+ localparam AN_POL = 8;
+ localparam SLOW = 9;
+ localparam TRIP = 10;
+ localparam DM = 11;
+
+ /* Internally registered signals */
+ reg mgmt_ena; // Enable management SoC to access pad
+ reg gpio_holdover;
+ reg gpio_slow_sel;
+ reg gpio_vtrip_sel;
+ reg gpio_inenb;
+ reg gpio_ib_mode_sel;
+ reg gpio_outenb;
+ reg [2:0] gpio_dm;
+ reg gpio_ana_en;
+ reg gpio_ana_sel;
+ reg gpio_ana_pol;
+
+ /* Derived output values */
+ wire pad_gpio_holdover;
+ wire pad_gpio_slow_sel;
+ wire pad_gpio_vtrip_sel;
+ wire pad_gpio_inenb;
+ wire pad_gpio_ib_mode_sel;
+ wire pad_gpio_ana_en;
+ wire pad_gpio_ana_sel;
+ wire pad_gpio_ana_pol;
+ wire [2:0] pad_gpio_dm;
+ wire pad_gpio_outenb;
+ wire pad_gpio_out;
+ wire pad_gpio_in;
+
+ /* Serial shift for the above (latched) values */
+ reg [PAD_CTRL_BITS-1:0] shift_register;
+
+ /* Utilize reset and clock to encode a load operation */
+ wire load_data;
+ wire int_reset;
+
+ /* Create internal reset and load signals from input reset and clock */
+ assign serial_data_out = shift_register[PAD_CTRL_BITS-1];
+ assign int_reset = (~resetn) & (~serial_clock);
+ assign load_data = (~resetn) & serial_clock;
+
+ always @(posedge serial_clock or posedge int_reset) begin
+ if (int_reset == 1'b1) begin
+ /* Clear shift register */
+ shift_register <= 'd0;
+ end else begin
+ /* Shift data in */
+ shift_register <= {shift_register[PAD_CTRL_BITS-2:0], serial_data_in};
+ end
+ end
+
+ always @(posedge load_data or posedge int_reset) begin
+ if (int_reset == 1'b1) begin
+ /* Initial state on reset: Pad set to management input */
+ mgmt_ena <= 1'b0;
+ gpio_holdover <= 1'b0; // All signals latched in hold mode
+ gpio_slow_sel <= 1'b0; // Fast slew rate
+ gpio_vtrip_sel <= 1'b0; // CMOS mode
+ gpio_ib_mode_sel <= 1'b0; // CMOS mode
+ gpio_inenb <= 1'b0; // Input enabled
+ gpio_outenb <= 1'b1; // Output disabled
+ gpio_dm <= 3'b001; // Configured as input only
+ gpio_ana_en <= 1'b0; // Digital enabled
+ gpio_ana_sel <= 1'b0; // Don't-care when gpio_ana_en = 0
+ gpio_ana_pol <= 1'b0; // Don't-care when gpio_ana_en = 0
+ end else begin
+ /* Load data */
+ mgmt_ena <= shift_register[MGMT_EN];
+ gpio_outenb <= shift_register[OEB];
+ gpio_holdover <= shift_register[HLDH];
+ gpio_inenb <= shift_register[INP_DIS];
+ gpio_ib_mode_sel <= shift_register[MOD_SEL];
+ gpio_ana_en <= shift_register[AN_EN];
+ gpio_ana_sel <= shift_register[AN_SEL];
+ gpio_ana_pol <= shift_register[AN_POL];
+ gpio_slow_sel <= shift_register[SLOW];
+ gpio_vtrip_sel <= shift_register[TRIP];
+ gpio_dm <= shift_register[DM+2:DM];
+
+ end
+ end
+
+ /* These pad configuration signals are static and do not change */
+ /* after setup. */
+
+ assign pad_gpio_holdover = gpio_holdover;
+ assign pad_gpio_slow_sel = gpio_slow_sel;
+ assign pad_gpio_vtrip_sel = gpio_vtrip_sel;
+ assign pad_gpio_ib_mode_sel = gpio_ib_mode_sel;
+ assign pad_gpio_ana_en = gpio_ana_en;
+ assign pad_gpio_ana_sel = gpio_ana_sel;
+ assign pad_gpio_ana_pol = gpio_ana_pol;
+ assign pad_gpio_dm = gpio_dm;
+ assign pad_gpio_inenb = gpio_inenb;
+
+ /* Implement pad control behavior depending on state of mgmt_ena */
+
+ /* If pad is configured for input and dm[2:1] is 01, then pad is */
+ /* configured as pull-up or pull-down depending on dm[0], and to */
+ /* set the pullup or pulldown condition, the pad output bit must */
+ /* be set to the opposite state of dm[0]. */
+ /* dm[0] = 0 is pull-down; dm[0] = 1 is pull-up. */
+ /* Otherwise, the output
+
+ assign pad_gpio_out = (mgmt_ena) ? mgmt_gpio_io :
+ (((gpio_dm[2:1] == 2'b01) && (gpio_inenb == 1'b0)) ?
+ ~gpio_dm[0] : user_gpio_out);
+
+ /* When under user control, gpio_outenb = 1 means that the pad is */
+ /* configured as input, and the user outenb is unused. Otherwise, */
+ /* the pad outenb signal is controlled by the user. */
+
+ assign pad_gpio_outenb = (mgmt_ena) ? gpio_outenb :
+ ((gpio_outenb == 1) ? 1'b1 : user_gpio_outenb);
+
+ /* User gpio_in is grounded when the management controls the pad */
+ assign user_gpio_in = (mgmt_ena) ? 1'b0 : pad_gpio_in;
+
+ /* Management I/O line is set from the pad when the pad is */
+ /* configured for input. */
+ assign mgmt_gpio_io = (gpio_inenb == 0) ? pad_gpio_in : 1'bz;
+
+endmodule
diff --git a/verilog/rtl/gpio_wb.v b/verilog/rtl/gpio_wb.v
index 9c55047..e4e92e9 100644
--- a/verilog/rtl/gpio_wb.v
+++ b/verilog/rtl/gpio_wb.v
@@ -18,11 +18,11 @@
output [31:0] wb_dat_o,
output wb_ack_o,
- input [1:0] gpio_in_pad,
- output [1:0] gpio,
- output [1:0] gpio_oeb,
- output [1:0] gpio_pu,
- output [1:0] gpio_pd
+ input gpio_in_pad,
+ output gpio,
+ output gpio_oeb,
+ output gpio_pu,
+ output gpio_pd
);
wire resetn;
@@ -50,7 +50,7 @@
.iomem_addr(wb_adr_i),
.iomem_valid(valid),
- .iomem_wstrb(iomem_we),
+ .iomem_wstrb(iomem_we[0]),
.iomem_wdata(wb_dat_i),
.iomem_rdata(wb_dat_o),
.iomem_ready(ready),
@@ -73,25 +73,25 @@
input clk,
input resetn,
- input [1:0] gpio_in_pad,
+ input gpio_in_pad,
input [31:0] iomem_addr,
input iomem_valid,
- input [3:0] iomem_wstrb,
+ input iomem_wstrb,
input [31:0] iomem_wdata,
output reg [31:0] iomem_rdata,
output reg iomem_ready,
- output [1:0] gpio,
- output [1:0] gpio_oeb,
- output [1:0] gpio_pu,
- output [1:0] gpio_pd
+ output gpio,
+ output gpio_oeb,
+ output gpio_pu,
+ output gpio_pd
);
- reg [1:0] gpio; // GPIO output data
- reg [1:0] gpio_pu; // GPIO pull-up enable
- reg [1:0] gpio_pd; // GPIO pull-down enable
- reg [1:0] gpio_oeb; // GPIO output enable (sense negative)
+ reg gpio; // GPIO output data
+ reg gpio_pu; // GPIO pull-up enable
+ reg gpio_pd; // GPIO pull-down enable
+ reg gpio_oeb; // GPIO output enable (sense negative)
wire gpio_sel;
wire gpio_oeb_sel;
@@ -115,24 +115,20 @@
iomem_ready <= 1'b 1;
if (gpio_sel) begin
- iomem_rdata <= {14'd0, gpio, 14'd0, gpio_in_pad};
-
- if (iomem_wstrb[0]) gpio[ 1: 0] <= iomem_wdata[ 1: 0];
+ iomem_rdata <= {30'd0, gpio, gpio_in_pad};
+ if (iomem_wstrb) gpio <= iomem_wdata[0];
end else if (gpio_oeb_sel) begin
- iomem_rdata <= {30'd0, gpio_oeb};
-
- if (iomem_wstrb[0]) gpio_oeb[ 1: 0] <= iomem_wdata[ 1: 0];
+ iomem_rdata <= {31'd0, gpio_oeb};
+ if (iomem_wstrb) gpio_oeb <= iomem_wdata[0];
end else if (gpio_pu_sel) begin
- iomem_rdata <= {30'd0, gpio_pu};
-
- if (iomem_wstrb[0]) gpio_pu[ 1: 0] <= iomem_wdata[ 1: 0];
+ iomem_rdata <= {31'd0, gpio_pu};
+ if (iomem_wstrb) gpio_pu <= iomem_wdata[0];
end else if (gpio_pd_sel) begin
- iomem_rdata <= {30'd0, gpio_pd};
-
- if (iomem_wstrb[0]) gpio_pd[ 1: 0] <= iomem_wdata[ 1: 0];
+ iomem_rdata <= {31'd0, gpio_pd};
+ if (iomem_wstrb) gpio_pd <= iomem_wdata[0];
end
diff --git a/verilog/rtl/mgmt_core.v b/verilog/rtl/mgmt_core.v
index ed0c79d..26e7e55 100644
--- a/verilog/rtl/mgmt_core.v
+++ b/verilog/rtl/mgmt_core.v
@@ -1,21 +1,15 @@
module mgmt_core(
`ifdef LVS
- inout vdd3v3,
inout vdd1v8,
inout vss,
`endif
- input ext_clk,
- output[ 1:0] gpio_out_pad, // Connect to out on gpio pad
- input [1:0] gpio_in_pad, // Connect to in on gpio pad
- output [1:0] gpio_mode0_pad, // Connect to dm[0] on gpio pad
- output [1:0] gpio_mode1_pad, // Connect to dm[2] on gpio pad
- output [1:0] gpio_outenb_pad, // Connect to oe_n on gpio pad
- output [1:0] gpio_inenb_pad, // Connect to inp_dis on gpio pad
- input [7:0] spi_ro_config,
- output ser_tx,
- input ser_rx,
- // IRQ
- input irq_pin, // dedicated IRQ pin
+ // GPIO (dedicated pad)
+ output gpio_out_pad, // Connect to out on gpio pad
+ input gpio_in_pad, // Connect to in on gpio pad
+ output gpio_mode0_pad, // Connect to dm[0] on gpio pad
+ output gpio_mode1_pad, // Connect to dm[2] on gpio pad
+ output gpio_outenb_pad, // Connect to oe_n on gpio pad
+ output gpio_inenb_pad, // Connect to inp_dis on gpio pad
// Flash memory control (SPI master)
output flash_csb,
output flash_clk,
@@ -23,44 +17,29 @@
output flash_clk_oeb,
output flash_io0_oeb,
output flash_io1_oeb,
- output flash_io2_oeb,
- output flash_io3_oeb,
output flash_csb_ieb,
output flash_clk_ieb,
output flash_io0_ieb,
output flash_io1_ieb,
- output flash_io2_ieb,
- output flash_io3_ieb,
output flash_io0_do,
output flash_io1_do,
- output flash_io2_do,
- output flash_io3_do,
input flash_io0_di,
input flash_io1_di,
- input flash_io2_di,
- input flash_io3_di,
- output por,
- input porb_l,
+ // Master reset
+ input porb,
+ // Clocking
input clock,
+ input ext_clk,
output pll_clk16,
- input SDI_core,
- input CSB_core,
- output SDO_core,
- output SDO_enb,
// LA signals
input [127:0] la_input, // From Mega-Project to cpu
output [127:0] la_output, // From CPU to Mega-Project
output [127:0] la_oen, // LA output enable
// Mega-Project Control Signals
- output [`MPRJ_IO_PADS-1:0] mprj_io_oeb_n,
- output [`MPRJ_IO_PADS-1:0] mprj_io_hldh_n,
- output [`MPRJ_IO_PADS-1:0] mprj_io_enh,
- output [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis,
- output [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel,
- output [`MPRJ_IO_PADS-1:0] mprj_io_analog_en,
- output [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel,
- output [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol,
- output [`MPRJ_IO_PADS*3-1:0] mprj_io_dm,
+ inout [`MPRJ_IO_PADS-1:0] mgmt_io_data,
+ output mprj_io_loader_resetn,
+ output mprj_io_loader_clock,
+ output mprj_io_loader_data,
// WB MI A (Mega project)
input mprj_ack_i,
input [31:0] mprj_dat_i,
@@ -80,15 +59,23 @@
output [31:0] xbar_adr_o,
output [31:0] xbar_dat_o,
- output striVe_clk,
- output striVe_rstn
+ output core_clk,
+ output core_rstn,
+
+ // Metal programmed user ID / mask revision vector
+ input [31:0] mask_rev
);
wire ext_clk_sel;
wire ext_clk;
wire pll_clk;
wire ext_reset;
- striVe_clkrst clkrst(
+ wire spi_sck;
+ wire spi_csb;
+ wire spi_sdi;
+ wire spi_sdo;
+
+ caravel_clkrst clkrst(
`ifdef LVS
.vdd1v8(vdd1v8),
.vss(vss),
@@ -96,29 +83,28 @@
.ext_clk_sel(ext_clk_sel),
.ext_clk(ext_clk),
.pll_clk(pll_clk),
- .reset(por),
+ .resetb(porb),
.ext_reset(ext_reset),
- .clk(striVe_clk),
- .resetn(striVe_rstn)
+ .core_clk(core_clk),
+ .resetb_sync(core_rstn)
);
- // SoC core
- wire [9:0] adc0_data_core;
- wire [1:0] adc0_inputsrc_core;
- wire [9:0] adc1_data_core;
- wire [1:0] adc1_inputsrc_core;
- wire [9:0] dac_value_core;
- wire [1:0] comp_ninputsrc_core;
- wire [1:0] comp_pinputsrc_core;
- wire [7:0] spi_ro_config_core;
+ // The following functions are connected to specific user project
+ // area pins, when under control of the management area (during
+ // startup, and when not otherwise programmed for the user project).
- // HKSPI
- wire [11:0] spi_ro_mfgr_id;
- wire [7:0] spi_ro_prod_id;
- wire [3:0] spi_ro_mask_rev;
- wire [2:0] spi_ro_pll_sel;
- wire [4:0] spi_ro_pll_div;
- wire [25:0] spi_ro_pll_trim;
+ // JTAG = mgmt_io_data[0] (inout)
+ // SDO = mgmt_io_data[1] (output) (shared with SPI master)
+ // SDI = mgmt_io_data[2] (input) (shared with SPI master)
+ // CSB = mgmt_io_data[3] (input) (shared with SPI master)
+ // SCK = mgmt_io_data[4] (input) (shared with SPI master)
+ // ser_rx = mgmt_io_data[5] (input)
+ // ser_tx = mgmt_io_data[6] (output)
+ // irq = mgmt_io_data[7] (input)
+ // flash_csb = mgmt_io_data[8] (output) (user area flash)
+ // flash_sck = mgmt_io_data[9] (output) (user area flash)
+ // flash_io0 = mgmt_io_data[10] (output) (user area flash)
+ // flash_io1 = mgmt_io_data[11] (input) (user area flash)
mgmt_soc soc (
`ifdef LVS
@@ -128,27 +114,26 @@
.pll_clk(pll_clk),
.ext_clk(ext_clk),
.ext_clk_sel(ext_clk_sel),
- .clk(striVe_clk),
- .resetn(striVe_rstn),
+ .clk(core_clk),
+ .resetn(core_rstn),
+ .trap(trap),
+ // GPIO
.gpio_out_pad(gpio_out_pad),
.gpio_in_pad(gpio_in_pad),
.gpio_mode0_pad(gpio_mode0_pad),
.gpio_mode1_pad(gpio_mode1_pad),
.gpio_outenb_pad(gpio_outenb_pad),
.gpio_inenb_pad(gpio_inenb_pad),
- .spi_ro_config(spi_ro_config),
- .spi_ro_pll_dco_ena(spi_ro_pll_dco_ena),
- .spi_ro_pll_div(spi_ro_pll_div),
- .spi_ro_pll_sel(spi_ro_pll_sel),
- .spi_ro_pll_trim(spi_ro_pll_trim),
- .spi_ro_mfgr_id(spi_ro_mfgr_id),
- .spi_ro_prod_id(spi_ro_prod_id),
- .spi_ro_mask_rev(spi_ro_mask_rev),
- .ser_tx(ser_tx),
- .ser_rx(ser_rx),
- .irq_pin(irq_pin),
+ // UART
+ .ser_tx(mgmt_io_data[6]),
+ .ser_rx(mgmt_io_data[5]),
+ .irq_pin(mgmt_io_data[7]),
.irq_spi(irq_spi),
- .trap(trap),
+ // SPI master
+ .spi_csb(spi_csb),
+ .spi_sck(spi_sck),
+ .spi_sdi(spi_sdi),
+ .spi_sdo(spi_sdo),
// Flash
.flash_csb(flash_csb),
.flash_clk(flash_clk),
@@ -172,20 +157,22 @@
.flash_io1_di(flash_io1_di),
.flash_io2_di(flash_io2_di),
.flash_io3_di(flash_io3_di),
+ // SPI pass-through to/from SPI flash controller
+ .pass_thru_mgmt(pass_thru_reset),
+ .pass_thru_mgmt_csb(pass_thru_mgmt_csb),
+ .pass_thru_mgmt_sck(pass_thru_mgmt_sck),
+ .pass_thru_mgmt_sdi(pass_thru_mgmt_sdi),
+ .pass_thru_mgmt_sdo(pass_thru_mgmt_sdo),
// Logic Analyzer
.la_input(la_input),
.la_output(la_output),
.la_oen(la_oen),
- // Mega-Project Control
- .mprj_io_oeb_n(mprj_io_oeb_n),
- .mprj_io_hldh_n(mprj_io_hldh_n),
- .mprj_io_enh(mprj_io_enh),
- .mprj_io_inp_dis(mprj_io_inp_dis),
- .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
- .mprj_io_analog_en(mprj_io_analog_en),
- .mprj_io_analog_sel(mprj_io_analog_sel),
- .mprj_io_analog_pol(mprj_io_analog_pol),
- .mprj_io_dm(mprj_io_dm),
+ // Mega-Project I/O Configuration
+ .mprj_io_loader_resetn(mprj_io_loader_resetn),
+ .mprj_io_loader_clock(mprj_io_loader_clock),
+ .mprj_io_loader_data(mprj_io_loader_data),
+ // I/O data
+ .mgmt_io_data(mgmt_io_data),
// Mega Project Slave ports (WB MI A)
.mprj_cyc_o(mprj_cyc_o),
.mprj_stb_o(mprj_stb_o),
@@ -211,58 +198,65 @@
.vdd(vdd1v8),
.vss(vss),
`endif
- .reset(por),
+ .resetb(porb),
.extclk_sel(ext_clk_sel),
- .osc(xi),
+ .osc(clock),
.clockc(pll_clk),
.clockp({pll_clk_core0, pll_clk_core90}),
.clockd({pll_clk2, pll_clk4, pll_clk8, pll_clk16}),
- .div(spi_ro_pll_div),
- .sel(spi_ro_pll_sel),
- .dco(spi_ro_pll_dco_ena),
- .ext_trim(spi_ro_pll_trim)
+ .div(spi_pll_div),
+ .sel(spi_pll_sel),
+ .dco(spi_pll_dco_ena),
+ .ext_trim(spi_pll_trim)
);
- // For the mask revision input, use an array of digital constant logic cells
- wire [3:0] mask_rev;
- wire [3:0] no_connect;
- sky130_fd_sc_hd__conb_1 mask_rev_value [3:0] (
- `ifdef LVS
- .vpwr(vdd1v8),
- .vpb(vdd1v8),
- .vnb(vss),
- .vgnd(vss),
- `endif
- .HI({no_connect[3:1], mask_rev[0]}),
- .LO({mask_rev[3:1], no_connect[0]})
- );
+ // Housekeeping SPI vectors
+ wire [4:0] spi_pll_div;
+ wire [2:0] spi_pll_sel;
+ wire [25:0] spi_pll_trim;
- // Housekeeping SPI at 3.3V.
- striVe_spi housekeeping (
+ // Housekeeping SPI (SPI slave module)
+ caravel_spi housekeeping (
`ifdef LVS
- .vdd(vdd3v3),
+ .vdd(vdd1v8),
.vss(vss),
`endif
- .RSTB(porb_l),
- .SCK(spi_sck),
- .SDI(SDI_core),
- .CSB(CSB_core),
- .SDO(SDO_core),
- .sdo_enb(SDO_enb),
- .pll_dco_ena(spi_ro_pll_dco_ena),
- .pll_sel(spi_ro_pll_sel),
- .pll_div(spi_ro_pll_div),
- .pll_trim(spi_ro_pll_trim),
- .pll_bypass(ext_clk_sel),
- .irq(irq_spi),
- .RST(por),
- .reset(ext_reset),
- .trap(trap),
- .mfgr_id(spi_ro_mfgr_id),
- .prod_id(spi_ro_prod_id),
- .mask_rev_in(mask_rev),
- .mask_rev(spi_ro_mask_rev)
- );
+ .RSTB(porb),
+ .SCK(mgmt_io_data[4]),
+ .SDI(mgmt_io_data[2]),
+ .CSB(mgmt_io_data[3]),
+ .SDO(mgmt_io_data[1]),
+ // Note that the Soc SPI master shares pins with the housekeeping
+ // SPI but with SDI and SDO reversed, such that the CPU can
+ // access the housekeeping SPI registers directly if the
+ // SPI master is enabled.
+ .mgmt_sck(mgmt_io_data[4]),
+ .mgmt_sdi(mgmt_io_data[1]),
+ .mgmt_csb(mgmt_io_data[3]),
+ .mgmt_sdo(mgmt_io_data[2]),
+ // NOTE: SDO enable is not accessible in the current configuration.
+ // May want to have a different type of GPIO control for the several
+ // pins like SPI SDO that could benefit from it.
+ .sdo_enb(),
+ .pll_dco_ena(spi_pll_dco_ena),
+ .pll_sel(spi_pll_sel),
+ .pll_div(spi_pll_div),
+ .pll_trim(spi_pll_trim),
+ .pll_bypass(ext_clk_sel),
+ .irq(irq_spi),
+ .reset(ext_reset),
+ .trap(trap),
+ .mask_rev_in(mask_rev),
+ .pass_thru_reset(pass_thru_reset),
+ .pass_thru_mgmt_sck(pass_thru_mgmt_sck),
+ .pass_thru_mgmt_csb(pass_thru_mgmt_csb),
+ .pass_thru_mgmt_sdi(pass_thru_mgmt_sdi),
+ .pass_thru_mgmt_sdo(pass_thru_mgmt_sdo),
+ .pass_thru_user_sck(mgmt_io_data[9]),
+ .pass_thru_user_csb(mgmt_io_data[8]),
+ .pass_thru_user_sdi(mgmt_io_data[10]),
+ .pass_thru_user_sdo(mgmt_io_data[11])
+ );
endmodule
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index ab1ff53..4a3b585 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -24,21 +24,23 @@
*/
`ifdef PICORV32_V
-`error "openstriVe_soc.v must be read before picorv32.v!"
+`error "mgmt_soc.v must be read before picorv32.v!"
`endif
-`define PICORV32_REGS openstriVe_soc_regs
+`define PICORV32_REGS mgmt_soc_regs
`include "picorv32.v"
`include "spimemio.v"
`include "simpleuart.v"
+`include "simple_spi_master.v"
+`include "counter_timer.v"
`include "wb_intercon.v"
`include "mem_wb.v"
`include "gpio_wb.v"
-`include "spi_sysctrl.v"
`include "sysctrl.v"
`include "la_wb.v"
`include "mprj_ctrl.v"
+`include "convert_gpio_sigs.v"
module mgmt_soc (
`ifdef LVS
@@ -52,40 +54,37 @@
input clk,
input resetn,
- // Memory mapped I/O signals
- output [1:0] gpio_out_pad, // Connect to out on gpio pad
- input [1:0] gpio_in_pad, // Connect to in on gpio pad
- output [1:0] gpio_mode0_pad, // Connect to dm[0] on gpio pad
- output [1:0] gpio_mode1_pad, // Connect to dm[2] on gpio pad
- output [1:0] gpio_outenb_pad, // Connect to oe_n on gpio pad
- output [1:0] gpio_inenb_pad, // Connect to inp_dis on gpio pad
+ // Trap state from CPU
+ output trap,
+
+ // GPIO (one pin)
+ output gpio_out_pad, // Connect to out on gpio pad
+ input gpio_in_pad, // Connect to in on gpio pad
+ output gpio_mode0_pad, // Connect to dm[0] on gpio pad
+ output gpio_mode1_pad, // Connect to dm[2] on gpio pad
+ output gpio_outenb_pad, // Connect to oe_n on gpio pad
+ output gpio_inenb_pad, // Connect to inp_dis on gpio pad
// LA signals
input [127:0] la_input, // From Mega-Project to cpu
output [127:0] la_output, // From CPU to Mega-Project
output [127:0] la_oen, // LA output enable (active low)
- // Mega-Project Control
- output [MPRJ_IO_PADS-1:0] mprj_io_oeb_n,
- output [MPRJ_IO_PADS-1:0] mprj_io_hldh_n,
- output [MPRJ_IO_PADS-1:0] mprj_io_enh,
- output [MPRJ_IO_PADS-1:0] mprj_io_inp_dis,
- output [MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel,
- output [MPRJ_IO_PADS-1:0] mprj_io_analog_en,
- output [MPRJ_IO_PADS-1:0] mprj_io_analog_sel,
- output [MPRJ_IO_PADS-1:0] mprj_io_analog_pol,
- output [MPRJ_IO_PADS*3-1:0] mprj_io_dm,
+ // Mega-Project I/O Configuration (serial load)
+ output mprj_io_loader_resetn,
+ output mprj_io_loader_clock,
+ output mprj_io_loader_data,
- input [7:0] spi_ro_config,
- input spi_ro_pll_dco_ena,
- input [4:0] spi_ro_pll_div,
- input [2:0] spi_ro_pll_sel,
- input [25:0] spi_ro_pll_trim,
+ // Mega-Project pad data (when management SoC controls the pad)
+ inout [MPRJ_IO_PADS-1:0] mgmt_io_data,
- input [11:0] spi_ro_mfgr_id,
- input [7:0] spi_ro_prod_id,
- input [3:0] spi_ro_mask_rev,
+ // SPI master
+ output spi_csb,
+ output spi_sck,
+ output spi_sdo,
+ input spi_sdi,
+ // UART
output ser_tx,
input ser_rx,
@@ -93,9 +92,6 @@
input irq_pin, // dedicated IRQ pin
input irq_spi, // IRQ from standalone SPI
- // trap
- output trap,
-
// Flash memory control (SPI master)
output flash_csb,
output flash_clk,
@@ -126,6 +122,13 @@
input flash_io2_di,
input flash_io3_di,
+ // SPI pass-thru mode
+ input pass_thru_mgmt,
+ input pass_thru_mgmt_csb,
+ input pass_thru_mgmt_sck,
+ input pass_thru_mgmt_sdi,
+ output pass_thru_mgmt_sdo,
+
// WB MI A (Mega project)
input mprj_ack_i,
input [31:0] mprj_dat_i,
@@ -153,21 +156,37 @@
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0000;
// Slaves Base Addresses
- parameter RAM_BASE_ADR = 32'h 0000_0000;
- parameter FLASH_BASE_ADR = 32'h 1000_0000;
- parameter UART_BASE_ADR = 32'h 2000_0000;
- parameter GPIO_BASE_ADR = 32'h 2100_0000;
- parameter LA_BASE_ADR = 32'h 2200_0000;
- parameter MPRJ_CTRL_ADR = 32'h 2300_0000;
- parameter MPRJ_BASE_ADR = 32'h 3000_0000; // WB MI A
- parameter SYS_BASE_ADR = 32'h 2F00_0000;
- parameter SPI_BASE_ADR = 32'h 2E00_0000;
- parameter FLASH_CTRL_CFG = 32'h 2D00_0000;
- parameter XBAR_BASE_ADR = 32'h 8000_0000;
+ parameter RAM_BASE_ADR = 32'h 0000_0000;
+ parameter FLASH_BASE_ADR = 32'h 1000_0000;
+ parameter UART_BASE_ADR = 32'h 2000_0000;
+ parameter GPIO_BASE_ADR = 32'h 2100_0000;
+ parameter COUNTER_TIMER0_BASE_ADR = 32'h 2110_0000;
+ parameter COUNTER_TIMER1_BASE_ADR = 32'h 2120_0000;
+ parameter SPI_MASTER_BASE_ADR = 32'h 2130_0000;
+ parameter LA_BASE_ADR = 32'h 2200_0000;
+ parameter MPRJ_CTRL_ADR = 32'h 2300_0000;
+ parameter MPRJ_BASE_ADR = 32'h 3000_0000; // WB MI A
+ parameter SYS_BASE_ADR = 32'h 2F00_0000;
+ parameter FLASH_CTRL_CFG = 32'h 2D00_0000;
+ parameter XBAR_BASE_ADR = 32'h 8000_0000;
// UART
parameter UART_CLK_DIV = 8'h00;
parameter UART_DATA = 8'h04;
+
+ // SPI Master
+ parameter SPI_MASTER_CONFIG = 8'h00;
+ parameter SPI_MASTER_DATA = 8'h04;
+
+ // Counter-timer 0
+ parameter COUNTER_TIMER0_CONFIG = 8'h00;
+ parameter COUNTER_TIMER0_VALUE = 8'h04;
+ parameter COUNTER_TIMER0_DATA = 8'h08;
+
+ // Counter-timer 1
+ parameter COUNTER_TIMER1_CONFIG = 8'h00;
+ parameter COUNTER_TIMER1_VALUE = 8'h04;
+ parameter COUNTER_TIMER1_DATA = 8'h08;
// SOC GPIO
parameter GPIO_DATA = 8'h00;
@@ -189,31 +208,15 @@
parameter MPRJ_IO_PADS = 32;
parameter MPRJ_PWR_CTRL = 32;
- // SPI-Controlled Registers
- parameter SPI_CFG = 8'h00;
- parameter SPI_ENA = 8'h04;
- parameter SPI_PLL_CFG = 8'h08;
- parameter SPI_MFGR_ID = 8'h0c;
- parameter SPI_PROD_ID = 8'h10;
- parameter SPI_MASK_REV = 8'h14;
- parameter SPI_PLL_BYPASS = 8'h18;
-
// System Control Registers
- parameter OSC_ENA = 8'h00;
- parameter OSC_OUT = 8'h04;
- parameter XTAL_OUT = 8'h08;
parameter PLL_OUT = 8'h0c;
parameter TRAP_OUT = 8'h10;
parameter IRQ7_SRC = 8'h14;
- parameter IRQ8_SRC = 8'h18;
- parameter OVERTEMP_ENA = 8'h1c;
- parameter OVERTEMP_DATA = 8'h20;
- parameter OVERTEMP_OUT = 8'h24;
// Wishbone Interconnect
localparam ADR_WIDTH = 32;
localparam DAT_WIDTH = 32;
- localparam NUM_SLAVES = 11;
+ localparam NUM_SLAVES = 13;
parameter [NUM_SLAVES*ADR_WIDTH-1: 0] ADR_MASK = {
{8'h80, {ADR_WIDTH-8{1'b0}}},
@@ -226,17 +229,21 @@
{8'hFF, {ADR_WIDTH-8{1'b0}}},
{8'hFF, {ADR_WIDTH-8{1'b0}}},
{8'hFF, {ADR_WIDTH-8{1'b0}}},
+ {8'hFF, {ADR_WIDTH-8{1'b0}}},
+ {8'hFF, {ADR_WIDTH-8{1'b0}}},
{8'hFF, {ADR_WIDTH-8{1'b0}}}
};
parameter [NUM_SLAVES*ADR_WIDTH-1: 0] SLAVE_ADR = {
{XBAR_BASE_ADR},
{SYS_BASE_ADR},
- {SPI_BASE_ADR},
{FLASH_CTRL_CFG},
{MPRJ_BASE_ADR},
{MPRJ_CTRL_ADR},
{LA_BASE_ADR},
+ {SPI_MASTER_BASE_ADR},
+ {COUNTER_TIMER1_BASE_ADR},
+ {COUNTER_TIMER0_BASE_ADR},
{GPIO_BASE_ADR},
{UART_BASE_ADR},
{FLASH_BASE_ADR},
@@ -244,36 +251,31 @@
};
// memory-mapped I/O control registers
- wire [1:0] gpio_pullup; // Intermediate GPIO pullup
- wire [1:0] gpio_pulldown; // Intermediate GPIO pulldown
- wire [1:0] gpio_outenb; // Intermediate GPIO out enable (bar)
- wire [1:0] gpio_out; // Intermediate GPIO output
+ wire gpio_pullup; // Intermediate GPIO pullup
+ wire gpio_pulldown; // Intermediate GPIO pulldown
+ wire gpio_outenb; // Intermediate GPIO out enable (bar)
+ wire gpio_out; // Intermediate GPIO output
- wire [1:0] gpio; // GPIO output data
- wire [1:0] gpio_pu; // GPIO pull-up enable
- wire [1:0] gpio_pd; // GPIO pull-down enable
- wire [1:0] gpio_oeb; // GPIO output enable (sense negative)
+ wire gpio; // GPIO output data
+ wire gpio_pu; // GPIO pull-up enable
+ wire gpio_pd; // GPIO pull-down enable
+ wire gpio_oeb; // GPIO output enable (sense negative)
wire pll_output_dest; // PLL clock output destination
wire trap_output_dest; // Trap signal output destination
wire irq_7_inputsrc; // IRQ 7 source
- wire irq_8_inputsrc; // IRQ 8 source
// GPIO assignments
- assign gpio_out[0] = (pll_output_dest == 1'b1) ? pll_clk : gpio[0];
- assign gpio_out[1] = (trap_output_dest == 1'b1) ? trap : gpio[1];
+ assign gpio_out = (trap_output_dest == 1'b1) ? trap : gpio;
- assign gpio_outenb[0] = (pll_output_dest == 1'b0) ? gpio_oeb[0] : 1'b0;
- assign gpio_outenb[1] = (trap_output_dest == 1'b0) ? gpio_oeb[1] : 1'b0;
+ assign gpio_outenb = (trap_output_dest == 1'b0) ? gpio_oeb : 1'b0;
- assign gpio_pullup[0] = (pll_output_dest == 1'b0) ? gpio_pu[0] : 1'b0;
- assign gpio_pullup[1] = (trap_output_dest == 1'b0) ? gpio_pu[1] : 1'b0;
+ assign gpio_pullup = (trap_output_dest == 1'b0) ? gpio_pu : 1'b0;
- assign gpio_pulldown[0] = (pll_output_dest == 1'b0) ? gpio_pd[0] : 1'b0;
- assign gpio_pulldown[1] = (trap_output_dest == 1'b0) ? gpio_pd[1] : 1'b0;
+ assign gpio_pulldown = (trap_output_dest == 1'b0) ? gpio_pd : 1'b0;
// Convert GPIO signals to sky130_fd_io pad signals
- convert_gpio_sigs convert_gpio_bit [1:0] (
+ convert_gpio_sigs convert_gpio_bit (
.gpio_out(gpio_out),
.gpio_outenb(gpio_outenb),
.gpio_pu(gpio_pullup),
@@ -285,29 +287,16 @@
.gpio_mode0_pad(gpio_mode0_pad)
);
- wire [7:0] mprj_io_oeb;
- convert_gpio_sigs convert_io_bit [7:0] (
- .gpio_out(),
- .gpio_outenb(mprj_io_oeb),
- .gpio_pu(mprj_io_pu),
- .gpio_pd(mprj_io_pd),
- .gpio_out_pad(),
- .gpio_outenb_pad(mprj_io_outenb_pad),
- .gpio_inenb_pad(mprj_io_inenb_pad),
- .gpio_mode1_pad(mprj_io_mode1_pad),
- .gpio_mode0_pad(mprj_io_mode0_pad)
- );
-
reg [31:0] irq;
wire irq_7;
- wire irq_8;
wire irq_stall;
wire irq_uart;
+ wire irq_spi_master;
+ wire irq_counter_timer0;
+ wire irq_counter_timer1;
- assign irq_uart = 0;
assign irq_stall = 0;
- assign irq_7 = (irq_7_inputsrc == 1'b1) ? gpio_in_pad[0] : 1'b0;
- assign irq_8 = (irq_8_inputsrc == 1'b1) ? gpio_in_pad[1] : 1'b0;
+ assign irq_7 = (irq_7_inputsrc == 1'b1) ? gpio_in_pad : 1'b0;
always @* begin
irq = 0;
@@ -316,7 +305,9 @@
irq[5] = irq_pin;
irq[6] = irq_spi;
irq[7] = irq_7;
- irq[8] = irq_8;
+ irq[9] = irq_spi_master;
+ irq[10] = irq_counter_timer0;
+ irq[11] = irq_counter_timer1;
end
// Assumption : no syscon module and wb_clk is the clock coming from the chip pin ?
@@ -394,6 +385,12 @@
.wb_cfg_ack_o(spimemio_cfg_ack_o),
.wb_cfg_dat_o(spimemio_cfg_dat_o),
+ .pass_thru(pass_thru_mgmt),
+ .pass_thru_csb(pass_thru_mgmt_csb),
+ .pass_thru_sck(pass_thru_mgmt_sck),
+ .pass_thru_sdi(pass_thru_mgmt_sdi),
+ .pass_thru_sdo(pass_thru_mgmt_sdo),
+
.flash_csb (flash_csb),
.flash_clk (flash_clk),
@@ -452,6 +449,91 @@
.ser_rx(ser_rx)
);
+ // Wishbone SPI master
+ wire spi_master_stb_i;
+ wire spi_master_ack_o;
+ wire [31:0] spi_master_dat_o;
+
+ simple_spi_master_wb #(
+ .BASE_ADR(SPI_MASTER_BASE_ADR),
+ .CONFIG(SPI_MASTER_CONFIG),
+ .DATA(SPI_MASTER_DATA)
+ ) simple_spi_master_inst (
+ // Wishbone Interface
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+
+ .wb_adr_i(cpu_adr_o),
+ .wb_dat_i(cpu_dat_o),
+ .wb_sel_i(cpu_sel_o),
+ .wb_we_i(cpu_we_o),
+ .wb_cyc_i(cpu_cyc_o),
+
+ .wb_stb_i(spi_master_stb_i),
+ .wb_ack_o(spi_master_ack_o),
+ .wb_dat_o(spi_master_dat_o),
+
+ .csb(spi_csb),
+ .sck(spi_sck),
+ .sdi(spi_sdi),
+ .sdo(spi_sdo),
+ .irq(irq_spi_master)
+ );
+
+ // Wishbone Counter-timer 0
+ wire counter_timer0_stb_i;
+ wire counter_timer0_ack_o;
+ wire [31:0] counter_timer0_dat_o;
+
+ counter_timer_wb #(
+ .BASE_ADR(COUNTER_TIMER0_BASE_ADR),
+ .CONFIG(COUNTER_TIMER0_CONFIG),
+ .VALUE(COUNTER_TIMER0_VALUE),
+ .DATA(COUNTER_TIMER0_DATA)
+ ) counter_timer_0 (
+ // Wishbone Interface
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+
+ .wb_adr_i(cpu_adr_o),
+ .wb_dat_i(cpu_dat_o),
+ .wb_sel_i(cpu_sel_o),
+ .wb_we_i(cpu_we_o),
+ .wb_cyc_i(cpu_cyc_o),
+
+ .wb_stb_i(counter_timer0_stb_i),
+ .wb_ack_o(counter_timer0_ack_o),
+ .wb_dat_o(counter_timer0_dat_o),
+ .irq(irq_counter_timer0)
+ );
+
+ // Wishbone Counter-timer 1
+ wire counter_timer1_stb_i;
+ wire counter_timer1_ack_o;
+ wire [31:0] counter_timer1_dat_o;
+
+ counter_timer_wb #(
+ .BASE_ADR(COUNTER_TIMER1_BASE_ADR),
+ .CONFIG(COUNTER_TIMER1_CONFIG),
+ .VALUE(COUNTER_TIMER1_VALUE),
+ .DATA(COUNTER_TIMER1_DATA)
+ ) counter_timer_1 (
+ // Wishbone Interface
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+
+ .wb_adr_i(cpu_adr_o),
+ .wb_dat_i(cpu_dat_o),
+ .wb_sel_i(cpu_sel_o),
+ .wb_we_i(cpu_we_o),
+ .wb_cyc_i(cpu_cyc_o),
+
+ .wb_stb_i(counter_timer1_stb_i),
+ .wb_ack_o(counter_timer1_ack_o),
+ .wb_dat_o(counter_timer1_dat_o),
+ .irq(irq_counter_timer1)
+ );
+
// Wishbone Slave GPIO Registers
wire gpio_stb_i;
wire gpio_ack_o;
@@ -481,49 +563,6 @@
.gpio_pd(gpio_pd)
);
- // Wishbone SPI System Control Registers (RO)
- wire spi_sys_stb_i;
- wire spi_sys_ack_o;
- wire [31:0] spi_sys_dat_o;
-
- spi_sysctrl_wb #(
- .BASE_ADR(SPI_BASE_ADR),
- .SPI_CFG(SPI_CFG),
- .SPI_ENA(SPI_ENA),
- .SPI_PLL_CFG(SPI_PLL_CFG),
- .SPI_MFGR_ID(SPI_MFGR_ID),
- .SPI_PROD_ID(SPI_PROD_ID),
- .SPI_MASK_REV(SPI_MASK_REV),
- .SPI_PLL_BYPASS(SPI_PLL_BYPASS)
- ) spi_sysctrl (
- .wb_clk_i(wb_clk_i),
- .wb_rst_i(wb_rst_i),
-
- .wb_adr_i(cpu_adr_o),
- .wb_dat_i(cpu_dat_o),
- .wb_sel_i(cpu_sel_o),
- .wb_we_i(cpu_we_o),
- .wb_cyc_i(cpu_cyc_o),
-
- .wb_stb_i(spi_sys_stb_i),
- .wb_ack_o(spi_sys_ack_o),
- .wb_dat_o(spi_sys_dat_o),
-
- .spi_ro_config(spi_ro_config), // (verify) wire input to the core not connected to HKSPI, what should it be connected to ?
- .spi_ro_pll_div(spi_ro_pll_div),
- .spi_ro_pll_sel(spi_ro_pll_sel),
- .spi_ro_xtal_ena(spi_ro_xtal_ena),
- .spi_ro_reg_ena(spi_ro_reg_ena),
-
- .spi_ro_pll_trim(spi_ro_pll_trim),
- .spi_ro_pll_dco_ena(spi_ro_pll_dco_ena),
-
- .spi_ro_mfgr_id(spi_ro_mfgr_id),
- .spi_ro_prod_id(spi_ro_prod_id),
- .spi_ro_mask_rev(spi_ro_mask_rev),
- .pll_bypass(ext_clk_sel)
- );
-
// Wishbone Slave System Control Register
wire sys_stb_i;
wire sys_ack_o;
@@ -533,8 +572,7 @@
.BASE_ADR(SYS_BASE_ADR),
.PLL_OUT(PLL_OUT),
.TRAP_OUT(TRAP_OUT),
- .IRQ7_SRC(IRQ7_SRC),
- .IRQ8_SRC(IRQ8_SRC)
+ .IRQ7_SRC(IRQ7_SRC)
) sysctrl (
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
@@ -551,8 +589,7 @@
.pll_output_dest(pll_output_dest),
.trap_output_dest(trap_output_dest),
- .irq_7_inputsrc(irq_7_inputsrc),
- .irq_8_inputsrc(irq_8_inputsrc)
+ .irq_7_inputsrc(irq_7_inputsrc)
);
// Logic Analyzer
@@ -610,15 +647,10 @@
.wb_ack_o(mprj_ctrl_ack_o),
.wb_dat_o(mprj_ctrl_dat_o),
- .output_en_n(mprj_io_oeb_n),
- .holdh_n(mprj_io_hldh_n),
- .enableh(mprj_io_enh),
- .input_dis(mprj_io_inp_dis),
- .ib_mode_sel(mprj_io_ib_mode_sel),
- .analog_en(mprj_io_analog_en),
- .analog_sel(mprj_io_analog_sel),
- .analog_pol(mprj_io_analog_pol),
- .digital_mode(mprj_io_dm)
+ .serial_clock(mprj_io_loader_clock),
+ .serial_resetn(mprj_io_loader_resetn),
+ .serial_data_out(mprj_io_loader_data),
+ .mgmt_gpio_io(mgmt_io_data)
);
// Wishbone Slave RAM
@@ -658,52 +690,29 @@
.wbm_ack_o(cpu_ack_i),
// Slaves Interface
- .wbs_stb_o({ xbar_stb_o, sys_stb_i, spi_sys_stb_i, spimemio_cfg_stb_i, mprj_stb_o, mprj_ctrl_stb_i, la_stb_i, gpio_stb_i, uart_stb_i, spimemio_flash_stb_i, mem_stb_i }),
- .wbs_dat_i({ xbar_dat_i, sys_dat_o, spi_sys_dat_o, spimemio_cfg_dat_o, mprj_dat_i, mprj_ctrl_dat_o, la_dat_o, gpio_dat_o, uart_dat_o, spimemio_flash_dat_o, mem_dat_o }),
- .wbs_ack_i({ xbar_ack_i, sys_ack_o, spi_sys_ack_o, spimemio_cfg_ack_o, mprj_ack_i, mprj_ctrl_ack_o, la_ack_o, gpio_ack_o, uart_ack_o, spimemio_flash_ack_o, mem_ack_o })
+ .wbs_stb_o({ xbar_stb_o, sys_stb_i, spimemio_cfg_stb_i,
+ mprj_stb_o, mprj_ctrl_stb_i, la_stb_i,
+ spi_master_stb_i, counter_timer1_stb_i, counter_timer0_stb_i,
+ gpio_stb_i, uart_stb_i,
+ spimemio_flash_stb_i, mem_stb_i }),
+ .wbs_dat_i({ xbar_dat_i, sys_dat_o, spimemio_cfg_dat_o,
+ mprj_dat_i, mprj_ctrl_dat_o, la_dat_o,
+ spi_master_dat_o, counter_timer1_dat_o, counter_timer0_dat_o,
+ gpio_dat_o, uart_dat_o,
+ spimemio_flash_dat_o, mem_dat_o }),
+ .wbs_ack_i({ xbar_ack_i, sys_ack_o, spimemio_cfg_ack_o,
+ mprj_ack_i, mprj_ctrl_ack_o, la_ack_o,
+ spi_master_ack_o, counter_timer1_ack_o, counter_timer0_ack_o,
+ gpio_ack_o, uart_ack_o,
+ spimemio_flash_ack_o, mem_ack_o })
);
endmodule
-
-/* Convert the standard set of GPIO signals: input, output, output_enb,
- * pullup, and pulldown into the set needed by the s8 GPIO pads:
- * input, output, output_enb, input_enb, mode. Note that dm[2] on
- * thepads is always equal to dm[1] in this setup, so mode is shown as
- * only a 2-bit signal.
- *
- * This module is bit-sliced. Instantiate once for each GPIO pad.
- */
-
-module convert_gpio_sigs (
- input gpio_out,
- input gpio_outenb,
- input gpio_pu,
- input gpio_pd,
- output gpio_out_pad,
- output gpio_outenb_pad,
- output gpio_inenb_pad,
- output gpio_mode1_pad,
- output gpio_mode0_pad
-);
-
- assign gpio_out_pad = (gpio_pu == 1'b0 && gpio_pd == 1'b0) ? gpio_out :
- (gpio_pu == 1'b1) ? 1 : 0;
-
- assign gpio_outenb_pad = (gpio_outenb == 1'b0) ? 0 :
- (gpio_pu == 1'b1 || gpio_pd == 1'b1) ? 0 : 1;
-
- assign gpio_inenb_pad = ~gpio_outenb;
-
- assign gpio_mode1_pad = ~gpio_outenb_pad;
- assign gpio_mode0_pad = gpio_outenb;
-
-endmodule
-
// Implementation note:
// Replace the following two modules with wrappers for your SRAM cells.
-module openstriVe_soc_regs (
+module mgmt_soc_regs (
input clk, wen,
input [5:0] waddr,
input [5:0] raddr1,
diff --git a/verilog/rtl/mprj_ctrl.v b/verilog/rtl/mprj_ctrl.v
index 9236beb..66250cb 100644
--- a/verilog/rtl/mprj_ctrl.v
+++ b/verilog/rtl/mprj_ctrl.v
@@ -1,5 +1,8 @@
module mprj_ctrl_wb #(
parameter BASE_ADR = 32'h 2300_0000,
+ parameter DATA = 8'h 00,
+ parameter XFER = 8'h 04,
+ parameter CONFIG = 8'h 08,
parameter IO_PADS = 32, // Number of IO control registers
parameter PWR_CTRL = 32 // Number of power control registers
)(
@@ -16,17 +19,14 @@
output [31:0] wb_dat_o,
output wb_ack_o,
- output [IO_PADS-1:0] output_en_n,
- output [IO_PADS-1:0] holdh_n,
- output [IO_PADS-1:0] enableh,
- output [IO_PADS-1:0] input_dis,
- output [IO_PADS-1:0] ib_mode_sel,
- output [IO_PADS-1:0] analog_en,
- output [IO_PADS-1:0] analog_sel,
- output [IO_PADS-1:0] analog_pol,
- output [IO_PADS*3-1:0] digital_mode
-);
+ // Output is to serial loader
+ output serial_clock,
+ output serial_resetn,
+ output serial_data_out,
+ // Read/write data to each GPIO pad from management SoC
+ inout [IO_PADS-1:0] mgmt_gpio_io
+);
wire resetn;
wire valid;
wire ready;
@@ -40,7 +40,10 @@
mprj_ctrl #(
.BASE_ADR(BASE_ADR),
- .IO_PADS(IO_PADS),
+ .DATA(DATA),
+ .CONFIG(CONFIG),
+ .XFER(XFER),
+ .IO_PADS(IO_PADS),
.PWR_CTRL(PWR_CTRL)
) mprj_ctrl (
.clk(wb_clk_i),
@@ -51,21 +54,20 @@
.iomem_wdata(wb_dat_i),
.iomem_rdata(wb_dat_o),
.iomem_ready(ready),
- .output_en_n(output_en_n),
- .holdh_n(holdh_n),
- .enableh(enableh),
- .input_dis(input_dis),
- .ib_mode_sel(ib_mode_sel),
- .analog_en(analog_en),
- .analog_sel(analog_sel),
- .analog_pol(analog_pol),
- .digital_mode(digital_mode)
+
+ .serial_clock(serial_clock),
+ .serial_resetn(serial_resetn),
+ .serial_data_out(serial_data_out),
+ .mgmt_gpio_io(mgmt_gpio_io)
);
endmodule
module mprj_ctrl #(
parameter BASE_ADR = 32'h 2300_0000,
+ parameter DATA = 8'h 00,
+ parameter XFER = 8'h 04,
+ parameter CONFIG = 8'h 08,
parameter IO_PADS = 32,
parameter PWR_CTRL = 32
)(
@@ -76,51 +78,44 @@
input iomem_valid,
input [3:0] iomem_wstrb,
input [31:0] iomem_wdata,
-
output reg [31:0] iomem_rdata,
output reg iomem_ready,
- output [IO_PADS-1:0] output_en_n,
- output [IO_PADS-1:0] holdh_n,
- output [IO_PADS-1:0] enableh,
- output [IO_PADS-1:0] input_dis,
- output [IO_PADS-1:0] ib_mode_sel,
- output [IO_PADS-1:0] analog_en,
- output [IO_PADS-1:0] analog_sel,
- output [IO_PADS-1:0] analog_pol,
- output [IO_PADS*3-1:0] digital_mode
+ output serial_clock,
+ output serial_resetn,
+ output serial_data_out,
+ inout [IO_PADS-1:0] mgmt_gpio_io
);
- localparam PWR_BASE_ADR = BASE_ADR + IO_PADS*4;
- localparam OEB = 0;
- localparam HLDH = 1;
- localparam ENH = 2;
- localparam INP_DIS = 3;
- localparam MOD_SEL = 4;
- localparam AN_EN = 5;
- localparam AN_SEL = 6;
- localparam AN_POL = 7;
- localparam DM = 8;
+ localparam IO_BASE_ADR = (BASE_ADR | CONFIG);
+ localparam PWR_BASE_ADR = (BASE_ADR | CONFIG) + IO_PADS*4;
+ localparam OEB = 1; // Offset of OEB in shift register block.
- reg [IO_PADS*32-1:0] io_ctrl;
- reg [PWR_CTRL*32-1:0] pwr_ctrl;
+ reg [IO_PADS*32-1:0] io_ctrl; // I/O control, 1 word per gpio pad
+ reg [PWR_CTRL*32-1:0] pwr_ctrl; // Power control, 1 word per power pad
+ reg [IO_PADS-1:0] mgmt_gpio_out; // I/O read/write data, 1 bit per gpio pad
+ reg xfer_ctrl; // Transfer control (1 bit)
- wire [IO_PADS-1:0] io_ctrl_sel;
+ wire [IO_PADS-1:0] io_ctrl_sel; // wishbone selects
wire [PWR_CTRL-1:0] pwr_ctrl_sel;
+ wire io_data_sel;
+ wire xfer_sel;
+
+ assign xfer_sel = (iomem_addr[7:0] == XFER);
+ assign io_data_sel = (iomem_addr[7:0] == DATA);
+
+ // Direction of mgmt_gpio_io depends on the value of io_ctrl pad bit 1 (OEB)
+ // if OEB = 0 then mgmt_gpio_out --> mgmt_gpio_io; if OEB = 1 then
+ // mgmt_gpio_io --> mgmt_gpio_in. mgmt_gpio_in is always a copy of mgmt_gpio_io.
+
+ assign mgmt_gpio_in = mgmt_gpio_io;
genvar i;
generate
for (i=0; i<IO_PADS; i=i+1) begin
- assign io_ctrl_sel[i] = (iomem_addr[7:0] == (BASE_ADR[7:0] + i*4));
- assign output_en_n[i] = io_ctrl[i*32+OEB];
- assign holdh_n[i] = io_ctrl[i*32+HLDH];
- assign enableh[i] = io_ctrl[i*32+ENH];
- assign input_dis[i] = io_ctrl[i*32+INP_DIS];
- assign ib_mode_sel[i] = io_ctrl[i*32+MOD_SEL];
- assign analog_en[i] = io_ctrl[i*32+AN_EN];
- assign analog_sel[i] = io_ctrl[i*32+AN_SEL];
- assign analog_pol[i] = io_ctrl[i*32+AN_POL];
- assign digital_mode[(i+1)*3-1:i*3] = io_ctrl[i*32+DM+3-1:i*32+DM];
+ assign io_ctrl_sel[i] = (iomem_addr[7:0] == (IO_BASE_ADR[7:0] + i*4));
+ assign mgmt_gpio_io[i] = (io_ctrl[i*32] + OEB == 1'b0) ?
+ mgmt_gpio_out[i] : 1'bz;
end
endgenerate
@@ -130,16 +125,38 @@
end
endgenerate
+ // I/O transfer of xfer bit and gpio data to/from user project region under
+ // management SoC control
+
+ always @(posedge clk) begin
+ if (!resetn) begin
+ xfer_ctrl <= 0;
+ mgmt_gpio_out <= 'd0;
+ end else begin
+ iomem_ready <= 0;
+ if (iomem_valid && !iomem_ready && iomem_addr[31:8] == BASE_ADDR[31:8]) begin
+ iomem_ready <= 1'b 1;
+
+ if (io_data_sel) begin
+ iomem_rdata <= mgmt_gpio_in;
+ mgmt_gpio_out <= 'd0;
+ if (iomem_wstrb[0]) mgmt_gpio_out[IO_PADS-1:0] <= iomem_wdata[IO_PADS-1:0];
+
+ end else if (xfer_sel) begin
+ iomem_rdata <= {31'd0, xfer_ctrl};
+ if (iomem_wstrb[0]) xfer_ctrl <= iomem_wdata[1:0];
+ end
+ end
+ end
+ end
+
generate
for (i=0; i<IO_PADS; i=i+1) begin
always @(posedge clk) begin
if (!resetn) begin
io_ctrl[i*32+: 32] <= 0;
end else begin
- iomem_ready <= 0;
if (iomem_valid && !iomem_ready && iomem_addr[31:8] == BASE_ADR[31:8]) begin
- iomem_ready <= 1'b 1;
-
if (io_ctrl_sel[i]) begin
iomem_rdata <= io_ctrl[i*32+: 32];
if (iomem_wstrb[0])
@@ -166,10 +183,7 @@
if (!resetn) begin
pwr_ctrl[i*32+: 32] <= 0;
end else begin
- iomem_ready <= 0;
if (iomem_valid && !iomem_ready && iomem_addr[31:8] == BASE_ADR[31:8]) begin
- iomem_ready <= 1'b 1;
-
if (pwr_ctrl_sel[i]) begin
iomem_rdata <= pwr_ctrl[i*32+: 32];
if (iomem_wstrb[0])
@@ -190,4 +204,122 @@
end
endgenerate
-endmodule
\ No newline at end of file
+ // Instantiate the GPIO transfer circuit
+
+ gpio_transfer_data #(
+ .NUM_GPIO_PADS(IO_PADS),
+ .PAD_CTRL_BITS(14)
+ ) gpio_xfer (
+ .resetn(resetn),
+ .clock(clk),
+ .pad_configure(io_ctrl),
+ .serial_clock(serial_clock),
+ .serial_resetn(serial_resetn),
+ .serial_data_out(serial_data_out)
+ );
+
+endmodule
+
+/*
+ *----------------------------------------------------
+ *
+ * This module initiates a write to the shift register
+ * chain from registered data in the processor core.
+ *
+ *----------------------------------------------------
+ */
+
+`define START 2'b00
+`define XBYTE 2'b01
+`define LOAD 2'b10
+
+module gpio_transfer_data #(
+ parameter NUM_GPIO_PADS = 32,
+ parameter PAD_CTRL_BITS = 13
+) (
+ input resetn,
+ input clock,
+ input [NUM_GPIO_PADS*PAD_CTRL_BITS-1:0] pad_configure,
+
+ output serial_clock,
+ output serial_resetn,
+ output serial_data_out
+);
+ reg [3:0] xfer_count;
+ reg [5:0] pad_count;
+ reg [1:0] xfer_state;
+ reg serial_clock;
+ reg serial_resetn;
+ reg serial_data_out;
+ reg [PAD_CTRL_BITS-1:0] serial_data_staging;
+
+ integer i;
+
+ always @(posedge clock or negedge resetn) begin
+ if (resetn == 1'b0) begin
+
+ xfer_state <= `START;
+ xfer_count <= 4'd0;
+ pad_count <= 6'd0;
+ serial_resetn <= 1'b0;
+ serial_clock <= 1'b0;
+ serial_data_out <= 1'b0;
+
+ end else begin
+
+ if (xfer_state == `START) begin
+ serial_resetn <= 1'b1;
+ serial_clock <= 1'b0;
+ xfer_count <= 6'd0;
+ if (pad_count == NUM_GPIO_PADS) begin
+ xfer_state <= `LOAD;
+ end else begin
+ pad_count <= pad_count + 1;
+ xfer_state <= `XBYTE;
+
+ for (i=0; i < NUM_GPIO_PADS; i = i + 1) begin
+ if (pad_count == i)
+ serial_data_staging <=
+ pad_configure[(i+1)*PAD_CTRL_BITS-1 : i*PAD_CTRL_BITS];
+ end
+ end
+ end else if (xfer_state == `XBYTE) begin
+ serial_resetn <= 1'b1;
+ serial_clock <= ~serial_clock;
+ if (serial_clock == 1'b0) begin
+ if (xfer_count == PAD_CTRL_BITS) begin
+ xfer_state <= `START;
+ end else begin
+ xfer_count <= xfer_count + 1;
+ end
+ end else begin
+ serial_data_staging <= {serial_data_staging[PAD_CTRL_BITS-2:0], 1'b0};
+ serial_data_out <= serial_data_staging[PAD_CTRL_BITS-1];
+ end
+ end else if (xfer_state == `LOAD) begin
+ xfer_count <= xfer_count + 1;
+
+ /* Load sequence: Raise clock for final data shift in;
+ * Pulse reset low while clock is high
+ * Set clock back to zero.
+ * Return to idle mode.
+ */
+ if (xfer_count == 4'd0) begin
+ serial_clock <= 1'b1;
+ serial_resetn <= 1'b1;
+ end else if (xfer_count == 4'd1) begin
+ serial_clock <= 1'b1;
+ serial_resetn <= 1'b0;
+ end else if (xfer_count == 4'd2) begin
+ serial_clock <= 1'b1;
+ serial_resetn <= 1'b1;
+ end else if (xfer_count == 4'd3) begin
+ serial_resetn <= 1'b1;
+ serial_clock <= 1'b0;
+ xfer_state <= `START;
+ end
+ end
+ end
+ end
+
+endmodule
diff --git a/verilog/rtl/mprj_io.v b/verilog/rtl/mprj_io.v
index e168b67..0238649 100644
--- a/verilog/rtl/mprj_io.v
+++ b/verilog/rtl/mprj_io.v
@@ -1,27 +1,31 @@
module mprj_io(
- inout vdd,
- inout vdd1v8,
- inout vss,
- input vddio_q,
- input vssio_q,
- input analog_a,
- input analog_b,
- input [`MPRJ_IO_PADS-1:0] io,
- input [`MPRJ_IO_PADS-1:0] io_out,
- input [`MPRJ_IO_PADS-1:0] oeb_n,
+ inout vdd,
+ inout vdd1v8,
+ inout vss,
+ input vddio_q,
+ input vssio_q,
+ input analog_a,
+ input analog_b,
+ input [`MPRJ_IO_PADS-1:0] io,
+ input [`MPRJ_IO_PADS-1:0] io_out,
+ input [`MPRJ_IO_PADS-1:0] oeb_n,
input [`MPRJ_IO_PADS-1:0] hldh_n,
- input [`MPRJ_IO_PADS-1:0] enh,
+ input [`MPRJ_IO_PADS-1:0] enh,
input [`MPRJ_IO_PADS-1:0] inp_dis,
input [`MPRJ_IO_PADS-1:0] ib_mode_sel,
+ input [`MPRJ_IO_PADS-1:0] vtrip_sel,
+ input [`MPRJ_IO_PADS-1:0] slow_sel,
+ input [`MPRJ_IO_PADS-1:0] holdover,
input [`MPRJ_IO_PADS-1:0] analog_en,
input [`MPRJ_IO_PADS-1:0] analog_sel,
input [`MPRJ_IO_PADS-1:0] analog_pol,
input [`MPRJ_IO_PADS*3-1:0] dm,
- output [`MPRJ_IO_PADS-1:0] io_in
+ output [`MPRJ_IO_PADS-1:0] io_in
);
`MPRJ_IO_PAD_V(io, io_in, io_out, `MPRJ_IO_PADS,
oeb_n, hldh_n, enh, inp_dis, ib_mode_sel,
+ vtrip_sel, slow_sel, holdolver,
analog_en, analog_sel, analog_pol, dm);
-endmodule
\ No newline at end of file
+endmodule
diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v
index 16a288e..ad2ac30 100644
--- a/verilog/rtl/pads.v
+++ b/verilog/rtl/pads.v
@@ -207,7 +207,7 @@
.tie_hi_esd(), \
.tie_lo_esd(loop_``X) )
-`define MPRJ_IO_PAD_V(X,Y,Y_OUT,V,OUT_EN_N,HLD_N, ENH, INP_DIS, MODE_SEL, AN_EN, AN_SEL, AN_POL, MODE) \
+`define MPRJ_IO_PAD_V(X,Y,Y_OUT,V,OUT_EN_N,HLD_N, ENH, INP_DIS, MODE_SEL, VTRIP_SEL, SLOW_SEL, HOLD_SEL, AN_EN, AN_SEL, AN_POL, MODE) \
wire [V-1:0] loop_``X; \
s8iom0_gpiov2_pad X``_pad [V-1:0] ( \
`ABUTMENT_PINS \
@@ -224,9 +224,9 @@
.enable_vddio(vdd1v8), \
.inp_dis(INP_DIS), \
.ib_mode_sel(MODE_SEL), \
- .vtrip_sel(vss), \
- .slow(vss), \
- .hld_ovr(vss), \
+ .vtrip_sel(VTRIP_SEL), \
+ .slow(SLOW_SEL), \
+ .hld_ovr(HOLD_SEL), \
.analog_en(AN_EN), \
.analog_sel(AN_SEL), \
.analog_pol(AN_POL), \
@@ -238,73 +238,3 @@
.in_h(), \
.tie_hi_esd(), \
.tie_lo_esd(loop_``X) )
-
-`define I2C_RX(X,Y) \
- wire loop_``X; \
- s8iom0s8_top_gpio_ovtv2 X``_pad ( \
- `ABUTMENT_PINS \
- `ifndef TOP_ROUTING \
- .pad(X), \
- `endif \
- .out(vss), \
- .oe_n(vdd1v8), \
- .hld_h_n(vdd3v3), \
- .enable_h(porb_h), \
- .enable_inp_h(loop_``X), \
- .enable_vdda_h(porb_h), \
- .enable_vddio(vdd1v8), \
- .enable_vswitch_h(vss), \
- .inp_dis(por), \
- .vtrip_sel(vss), \
- .hys_trim(vdd1v8), \
- .slow(vss), \
- .slew_ctl({vss, vss}), \ // 2 bits
- .hld_ovr(vss), \
- .analog_en(vss), \
- .analog_sel(vss), \
- .analog_pol(vss), \
- .dm({vss, vss, vdd1v8}), \ // 3 bits
- .ib_mode_sel({vss, vss}), \ // 2 bits
- .vinref(vdd1v8), \
- .pad_a_noesd_h(), \
- .pad_a_esd_0_h(), \
- .pad_a_esd_1_h(), \
- .in(Y), \
- .in_h(), \
- .tie_hi_esd(), \
- .tie_lo_esd() )
-
-`define I2C_TX(X,Y) \
- wire loop_``X; \
- s8iom0s8_top_gpio_ovtv2 X``_pad ( \
- `ABUTMENT_PINS \
- `ifndef TOP_ROUTING \
- .pad(X), \
- `endif \
- .out(Y), \
- .oe_n(vss), \
- .hld_h_n(vdd3v3), \
- .enable_h(porb_h), \
- .enable_inp_h(loop_``X), \
- .enable_vdda_h(porb_h), \
- .enable_vddio(vdd1v8), \
- .enable_vswitch_h(vss), \
- .inp_dis(vdd1v8), \
- .vtrip_sel(vss), \
- .hys_trim(vdd1v8), \
- .slow(vss), \
- .slew_ctl({vss, vss}), \ // 2 bits
- .hld_ovr(vss), \
- .analog_en(vss), \
- .analog_sel(vss), \
- .analog_pol(vss), \
- .dm({vdd1v8, vdd1v8, vss}), \ // 3 bits
- .ib_mode_sel({vss, vss}), \ // 2 bits
- .vinref(vdd1v8), \
- .pad_a_noesd_h(), \
- .pad_a_esd_0_h(), \
- .pad_a_esd_1_h(), \
- .in(), \
- .in_h(), \
- .tie_hi_esd(), \
- .tie_lo_esd())
diff --git a/verilog/rtl/simple_spi_master.v b/verilog/rtl/simple_spi_master.v
new file mode 100755
index 0000000..de6ac2a
--- /dev/null
+++ b/verilog/rtl/simple_spi_master.v
@@ -0,0 +1,373 @@
+//----------------------------------------------------------------------------
+// Module: simple_spi_master
+//
+//----------------------------------------------------------------------------
+// Copyright (C) 2019 efabless, inc.
+//
+// This source file may be used and distributed without
+// restriction provided that this copyright statement is not
+// removed from the file and that any derivative work contains
+// the original copyright notice and the associated disclaimer.
+//
+// This source file is free software; you can redistribute it
+// and/or modify it under the terms of the GNU Lesser General
+// Public License as published by the Free Software Foundation;
+// either version 2.1 of the License, or (at your option) any
+// later version.
+//
+// This source is distributed in the hope that it will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+// PURPOSE. See the GNU Lesser General Public License for more
+// details.
+//
+//--------------------------------------------------------------------
+//
+// resetn: active low async reset
+// clk: master clock (before prescaler)
+// stream:
+// 0 = apply/release CSB separately for each byte
+// 1 = apply CSB until stream bit is cleared
+// mlb:
+// 0 = msb 1st
+// 1 = lsb 1st
+// invsck:
+// 0 = normal SCK
+// 1 = inverted SCK
+// invcsb:
+// 0 = normal CSB (active low)
+// 1 = inverted CSB (active high)
+// mode:
+// 0 = read and change data on opposite SCK edges
+// 1 = read and change data on the same SCK edge
+// enable:
+// 0 = disable the SPI master
+// 1 = enable the SPI master
+// irqena:
+// 0 = disable interrupt
+// 1 = enable interrupt
+// prescaler: count (in master clock cycles) of 1/2 SCK cycle.
+//
+// reg_dat_we:
+// 1 = data write enable
+// reg_dat_re:
+// 1 = data read enable
+// reg_cfg_*: Signaling for read/write of configuration register
+// reg_dat_*: Signaling for read/write of data register
+//
+// err_out: Indicates attempt to read/write before data ready
+// (failure to wait for reg_dat_wait to clear)
+//
+// Between "mode" and "invsck", all four standard SPI modes are supported
+//
+//--------------------------------------------------------------------
+
+module simple_spi_master_wb #(
+ parameter BASE_ADR = 32'h2100_0000,
+ parameter CONFIG = 8'h00,
+ parameter DATA = 8'h04
+) (
+ input wb_clk_i,
+ input wb_rst_i,
+ input [31:0] wb_adr_i,
+ input [31:0] wb_dat_i,
+ input [3:0] wb_sel_i,
+ input wb_we_i,
+ input wb_cyc_i,
+ input wb_stb_i,
+ output wb_ack_o,
+ output [31:0] wb_dat_o,
+
+ input sdi, // SPI input
+ output csb, // SPI chip select
+ output sck, // SPI clock
+ output sdo, // SPI output
+ output irq // interrupt output
+);
+
+ wire [31:0] simple_spi_master_reg_cfg_do;
+ wire [31:0] simple_spi_master_reg_dat_do;
+
+ wire resetn = ~wb_rst_i;
+ wire valid = wb_stb_i && wb_cyc_i;
+ wire simple_spi_master_reg_cfg_sel = valid && (wb_adr_i == (BASE_ADR | CONFIG));
+ wire simple_spi_master_reg_dat_sel = valid && (wb_adr_i == (BASE_ADR | DATA));
+
+ wire [1:0] reg_cfg_we = (simple_spi_master_reg_cfg_sel) ?
+ (wb_sel_i[1:0] & {2{wb_we_i}}): 2'b00;
+ wire reg_dat_we = (simple_spi_master_reg_dat_sel) ? (wb_sel_i[0] & wb_we_i): 1'b0;
+
+ wire [31:0] mem_wdata = wb_dat_i;
+ wire reg_dat_re = simple_spi_master_reg_dat_sel && !wb_sel_i && ~wb_we_i;
+
+ assign wb_dat_o = (simple_spi_master_reg_cfg_sel) ? simple_spi_master_reg_cfg_do :
+ simple_spi_master_reg_dat_do;
+ assign wb_ack_o = (simple_spi_master_reg_cfg_sel || simple_spi_master_reg_dat_sel)
+ && (!reg_dat_wait);
+
+ simple_spi_master spi_master (
+ .resetn(resetn),
+ .clk(wb_clk_i),
+ .reg_cfg_we(reg_cfg_we),
+ .reg_cfg_di(mem_wdata),
+ .reg_cfg_do(simple_spi_master_reg_cfg_do),
+ .reg_dat_we(reg_dat_we),
+ .reg_dat_re(reg_dat_re),
+ .reg_dat_di(mem_wdata),
+ .reg_dat_do(simple_spi_master_reg_dat_do),
+ .reg_dat_wait(reg_dat_wait),
+
+ .sdi(sdi), // SPI input
+ .csb(csb), // SPI chip select
+ .sck(sck), // SPI clock
+ .sdo(sdo), // SPI output
+ .irq_out(irq) // interrupt
+ );
+endmodule
+
+module simple_spi_master (
+ input resetn,
+ input clk, // master clock (assume 100MHz)
+
+ input [1:0] reg_cfg_we,
+ input [31:0] reg_cfg_di,
+ output [31:0] reg_cfg_do,
+
+ input reg_dat_we,
+ input reg_dat_re,
+ input [31:0] reg_dat_di,
+ output [31:0] reg_dat_do,
+ output reg_dat_wait,
+ output irq_out,
+ output err_out,
+
+ input sdi, // SPI input
+ output csb, // SPI chip select
+ output sck, // SPI clock
+ output sdo // SPI output
+);
+
+ parameter IDLE = 2'b00;
+ parameter SENDL = 2'b01;
+ parameter SENDH = 2'b10;
+ parameter FINISH = 2'b11;
+
+ reg done;
+ reg isdo, hsck, icsb;
+ reg [1:0] state;
+ reg isck;
+ reg err_out;
+
+ reg [7:0] treg, rreg, d_latched;
+ reg [2:0] nbit;
+
+ reg [7:0] prescaler;
+ reg [7:0] count;
+ reg invsck;
+ reg invcsb;
+ reg mlb;
+ reg irqena;
+ reg stream;
+ reg mode;
+ reg enable;
+
+ wire csb;
+ wire irq_out;
+ wire sck;
+ wire sdo;
+
+ // Define behavior for inverted SCK and inverted CSB
+ assign csb = (invcsb) ? ~icsb : icsb;
+ assign sck = (invsck) ? ~isck : isck;
+
+ // No bidirectional 3-pin mode defined, so SDO is enabled whenever CSB is low.
+ assign sdo = icsb ? 1'bz : isdo;
+
+ assign irq_out = irqena & done;
+
+ // Read configuration and data registers
+ assign reg_cfg_do = {17'd0, irqena, enable, stream, mode, invsck, invcsb, mlb, prescaler};
+ assign reg_dat_wait = ~done;
+ assign reg_dat_do = done ? rreg : ~0;
+
+ // Write configuration register
+ always @(posedge clk or negedge resetn) begin
+ if (resetn == 1'b0) begin
+ prescaler <= 8'd2;
+ invcsb <= 1'b0;
+ invsck <= 1'b0;
+ mlb <= 1'b0;
+ enable <= 1'b0;
+ irqena <= 1'b0;
+ stream <= 1'b0;
+ mode <= 1'b0;
+ end else begin
+ if (reg_cfg_we[0]) prescaler <= reg_cfg_di[7:0];
+ if (reg_cfg_we[1]) begin
+ mlb <= reg_cfg_di[8];
+ invcsb <= reg_cfg_di[9];
+ invsck <= reg_cfg_di[10];
+ mode <= reg_cfg_di[11];
+ stream <= reg_cfg_di[12];
+ enable <= reg_cfg_di[13];
+ irqena <= reg_cfg_di[14];
+ end //reg_cfg_we[1]
+ end //resetn
+ end //always
+
+ // Watch for read and write enables on clk, not hsck, so as not to
+ // miss them.
+
+ reg w_latched, r_latched;
+
+ always @(posedge clk or negedge resetn) begin
+ if (resetn == 1'b0) begin
+ err_out <= 1'b0;
+ w_latched <= 1'b0;
+ r_latched <= 1'b0;
+ d_latched <= 8'd0;
+ end else begin
+ // Clear latches on SEND, otherwise latch when seen
+ if (state == SENDL || state == SENDH) begin
+ if (reg_dat_we == 1'b0) begin
+ w_latched <= 1'b0;
+ end
+ end else begin
+ if (reg_dat_we == 1'b1) begin
+ if (done == 1'b0 && w_latched == 1'b1) begin
+ err_out <= 1'b1;
+ end else begin
+ w_latched <= 1'b1;
+ d_latched <= reg_dat_di[7:0];
+ err_out <= 1'b0;
+ end
+ end
+ end
+
+ if (reg_dat_re == 1'b1) begin
+ if (r_latched == 1'b1) begin
+ r_latched <= 1'b0;
+ end else begin
+ err_out <= 1'b1; // byte not available
+ end
+ end else if (state == FINISH) begin
+ r_latched <= 1'b1;
+ end if (state == SENDL || state == SENDH) begin
+ if (r_latched == 1'b1) begin
+ err_out <= 1'b1; // last byte was never read
+ end else begin
+ r_latched <= 1'b0;
+ end
+ end
+ end
+ end
+
+ // State transition.
+
+ always @(posedge hsck or negedge resetn) begin
+ if (resetn == 1'b0) begin
+ state <= IDLE;
+ nbit <= 3'd0;
+ icsb <= 1'b1;
+ done <= 1'b1;
+ end else begin
+ if (state == IDLE) begin
+ if (w_latched == 1'b1) begin
+ state <= SENDL;
+ nbit <= 3'd0;
+ icsb <= 1'b0;
+ done <= 1'b0;
+ end else begin
+ icsb <= ~stream;
+ end
+ end else if (state == SENDL) begin
+ state <= SENDH;
+ end else if (state == SENDH) begin
+ nbit <= nbit + 1;
+ if (nbit == 3'd7) begin
+ state <= FINISH;
+ end else begin
+ state <= SENDL;
+ end
+ end else if (state == FINISH) begin
+ icsb <= ~stream;
+ done <= 1'b1;
+ state <= IDLE;
+ end
+ end
+ end
+
+ // Set up internal clock. The enable bit gates the internal clock
+ // to shut down the master SPI when disabled.
+
+ always @(posedge clk or negedge resetn) begin
+ if (resetn == 1'b0) begin
+ count <= 8'd0;
+ hsck <= 1'b0;
+ end else begin
+ if (enable == 1'b0) begin
+ count <= 8'd0;
+ end else begin
+ count <= count + 1;
+ if (count == prescaler) begin
+ hsck <= ~hsck;
+ count <= 8'd0;
+ end // count
+ end // enable
+ end // resetn
+ end // always
+
+ // sck is half the rate of hsck
+
+ always @(posedge hsck or negedge resetn) begin
+ if (resetn == 1'b0) begin
+ isck <= 1'b0;
+ end else begin
+ if (state == IDLE || state == FINISH)
+ isck <= 1'b0;
+ else
+ isck <= ~isck;
+ end // resetn
+ end // always
+
+ // Main procedure: read, write, shift data
+
+ always @(posedge hsck or negedge resetn) begin
+ if (resetn == 1'b0) begin
+ rreg <= 8'hff;
+ treg <= 8'hff;
+ isdo <= 1'b0;
+ end else begin
+ if (isck == 1'b0 && (state == SENDL || state == SENDH)) begin
+ if (mlb == 1'b1) begin
+ // LSB first, sdi@msb -> right shift
+ rreg <= {sdi, rreg[7:1]};
+ end else begin
+ // MSB first, sdi@lsb -> left shift
+ rreg <= {rreg[6:0], sdi};
+ end
+ end // read on ~isck
+
+ if (w_latched == 1'b1) begin
+ if (mlb == 1'b1) begin
+ treg <= {1'b1, d_latched[7:1]};
+ isdo <= d_latched[0];
+ end else begin
+ treg <= {d_latched[6:0], 1'b1};
+ isdo <= d_latched[7];
+ end // mlb
+ end else if ((mode ^ isck) == 1'b1) begin
+ if (mlb == 1'b1) begin
+ // LSB first, shift right
+ treg <= {1'b1, treg[7:1]};
+ isdo <= treg[0];
+ end else begin
+ // MSB first shift LEFT
+ treg <= {treg[6:0], 1'b1};
+ isdo <= treg[7];
+ end // mlb
+ end // write on mode ^ isck
+ end // resetn
+ end // always
+
+endmodule
diff --git a/verilog/rtl/spi_slave.v b/verilog/rtl/spi_slave.v
deleted file mode 100644
index 16a1923..0000000
--- a/verilog/rtl/spi_slave.v
+++ /dev/null
@@ -1,179 +0,0 @@
-//------------------------------------------------
-// spi_slave.v
-//------------------------------------------------
-// General purpose SPI slave module
-//------------------------------------------------
-// Written by Tim Edwards
-// efabless, inc., april 23, 2017
-//------------------------------------------------
-// This file is distributed free and open source
-//------------------------------------------------
-
-// SCK --- Clock input
-// SDI --- Data input
-// SDO --- Data output
-// CSB --- Chip select (sense negative)
-// idata --- Data from chip to transmit out, in 8 bits
-// odata --- Input data to chip, in 8 bits
-// addr --- Decoded address to upstream circuits
-// rdstb --- Read strobe, tells upstream circuit to supply next byte to idata
-// wrstb --- Write strobe, tells upstream circuit to latch odata.
-
-// Data format (general purpose):
-// 8 bit format
-// 1st byte: Command word (see below)
-// 2nd byte: Address word (register 0 to 255)
-// 3rd byte: Data word (value 0 to 255)
-
-// Command format:
-// 00000000 No operation
-// 10000000 Write until CSB raised
-// 01000000 Read until CSB raised
-// 11000000 Simultaneous read/write until CSB raised
-// wrnnn000 Read/write as above, for nnn = 1 to 7 bytes, then terminate
-
-// Lower three bits are reserved for future use.
-// All serial bytes are read and written msb first.
-
-// Fixed control and status registers
-
-// Address 0 is reserved and contains flags for SPI mode. This is
-// currently undefined and is always value 0.
-// Address 1 is reserved and contains manufacturer ID low 8 bits.
-// Address 2 is reserved and contains manufacturer ID high 4 bits
-// and mask revision number (4 bits).
-// Address 3 is reserved and contains product ID (8 bits).
-// Addresses 4 to 255 are available for general purpose use.
-
-`define COMMAND 2'b00
-`define ADDRESS 2'b01
-`define DATA 2'b10
-`define IDLE 2'b11 // Not used
-
-module spi_slave(SCK, SDI, CSB, SDO, sdoenb, idata, odata, oaddr, rdstb, wrstb);
- input SCK;
- input SDI;
- input CSB;
- output SDO;
- output sdoenb;
- input [7:0] idata;
- output [7:0] odata;
- output [7:0] oaddr;
- output rdstb;
- output wrstb;
-
- reg [7:0] addr;
- reg wrstb;
- reg rdstb;
- reg sdoenb;
- reg [1:0] state;
- reg [2:0] count;
- reg writemode;
- reg readmode;
- reg [2:0] fixed;
- wire [7:0] odata;
- reg [6:0] predata;
- wire [7:0] oaddr;
- reg [7:0] ldata;
-
- assign odata = {predata, SDI};
- assign oaddr = (state == `ADDRESS) ? {addr[6:0], SDI} : addr;
- assign SDO = ldata[7];
-
- // Readback data is captured on the falling edge of SCK so that
- // it is guaranteed valid at the next rising edge.
- always @(negedge SCK or posedge CSB) begin
- if (CSB == 1'b1) begin
- wrstb <= 1'b0;
- ldata <= 8'b00000000;
- sdoenb <= 1'b1;
- end else begin
-
- // After CSB low, 1st SCK starts command
-
- if (state == `DATA) begin
- if (readmode == 1'b1) begin
- sdoenb <= 1'b0;
- if (count == 3'b000) begin
- ldata <= idata;
- end else begin
- ldata <= {ldata[6:0], 1'b0}; // Shift out
- end
- end else begin
- sdoenb <= 1'b1;
- end
-
- // Apply write strobe on SCK negative edge on the next-to-last
- // data bit so that it updates data on the rising edge of SCK
- // on the last data bit.
-
- if (count == 3'b111) begin
- if (writemode == 1'b1) begin
- wrstb <= 1'b1;
- end
- end else begin
- wrstb <= 1'b0;
- end
- end else begin
- wrstb <= 1'b0;
- sdoenb <= 1'b1;
- end // ! state `DATA
- end // ! CSB
- end // always @ ~SCK
-
- always @(posedge SCK or posedge CSB) begin
- if (CSB == 1'b1) begin
- // Default state on reset
- addr <= 8'h00;
- rdstb <= 1'b0;
- predata <= 7'b0000000;
- state <= `COMMAND;
- count <= 3'b000;
- readmode <= 1'b0;
- writemode <= 1'b0;
- fixed <= 3'b000;
- end else begin
- // After CSB low, 1st SCK starts command
- if (state == `COMMAND) begin
- rdstb <= 1'b0;
- count <= count + 1;
- if (count == 3'b000) begin
- writemode <= SDI;
- end else if (count == 3'b001) begin
- readmode <= SDI;
- end else if (count < 3'b101) begin
- fixed <= {fixed[1:0], SDI};
- end else if (count == 3'b111) begin
- state <= `ADDRESS;
- end
- end else if (state == `ADDRESS) begin
- count <= count + 1;
- addr <= {addr[6:0], SDI};
- if (count == 3'b111) begin
- if (readmode == 1'b1) begin
- rdstb <= 1'b1;
- end
- state <= `DATA;
- end else begin
- rdstb <= 1'b0;
- end
- end else if (state == `DATA) begin
- predata <= {predata[6:0], SDI};
- count <= count + 1;
- if (count == 3'b111) begin
- if (fixed == 3'b001) begin
- state <= `COMMAND;
- end else if (fixed != 3'b000) begin
- fixed <= fixed - 1;
- addr <= addr + 1; // Auto increment address (fixed)
- end else begin
- addr <= addr + 1; // Auto increment address (streaming)
- end
- end else begin
- rdstb <= 1'b0;
- end
- end // ! state `DATA
- end // ! CSB
- end // always @ SCK
-
-endmodule // spi_slave
diff --git a/verilog/rtl/spi_sysctrl.v b/verilog/rtl/spi_sysctrl.v
deleted file mode 100644
index 7a34a7f..0000000
--- a/verilog/rtl/spi_sysctrl.v
+++ /dev/null
@@ -1,182 +0,0 @@
-module spi_sysctrl_wb #(
- parameter BASE_ADR = 32'h2E00_0000,
- parameter SPI_CFG = 8'h00,
- parameter SPI_ENA = 8'h04,
- parameter SPI_PLL_CFG = 8'h08,
- parameter SPI_MFGR_ID = 8'h0c,
- parameter SPI_PROD_ID = 8'h10,
- parameter SPI_MASK_REV = 8'h14,
- parameter SPI_PLL_BYPASS = 8'h18
-) (
- input wb_clk_i,
- input wb_rst_i,
-
- input [31:0] wb_dat_i,
- input [31:0] wb_adr_i,
- input [3:0] wb_sel_i,
- input wb_cyc_i,
- input wb_stb_i,
- input wb_we_i,
-
- output [31:0] wb_dat_o,
- output wb_ack_o,
-
- // Read-Only HKSPI Registers
- input [7:0] spi_ro_config, // (verify) wire input to the core not connected to HKSPI, what should it be connected to ?
-
- input [4:0] spi_ro_pll_div,
- input [2:0] spi_ro_pll_sel,
- input spi_ro_xtal_ena,
- input spi_ro_reg_ena,
-
- input [25:0] spi_ro_pll_trim,
- input spi_ro_pll_dco_ena,
-
- input [11:0] spi_ro_mfgr_id,
- input [7:0] spi_ro_prod_id,
- input [3:0] spi_ro_mask_rev,
- input pll_bypass
-);
-
- wire resetn;
- wire valid;
- wire ready;
- wire [3:0] iomem_we;
-
- assign resetn = ~wb_rst_i;
- assign valid = wb_stb_i && wb_cyc_i;
-
- assign iomem_we = wb_sel_i & {4{wb_we_i}};
- assign wb_ack_o = ready;
-
- spi_sysctrl #(
- .BASE_ADR(BASE_ADR),
- .SPI_CFG(SPI_CFG),
- .SPI_ENA(SPI_ENA),
- .SPI_PLL_CFG(SPI_PLL_CFG),
- .SPI_MFGR_ID(SPI_MFGR_ID),
- .SPI_PROD_ID(SPI_PROD_ID),
- .SPI_MASK_REV(SPI_MASK_REV),
- .SPI_PLL_BYPASS(SPI_PLL_BYPASS)
- ) spi_sysctrl (
- .clk(wb_clk_i),
- .resetn(resetn),
-
- .iomem_addr(wb_adr_i),
- .iomem_valid(valid),
- .iomem_wstrb(iomem_we),
- .iomem_wdata(wb_dat_i),
- .iomem_rdata(wb_dat_o),
- .iomem_ready(ready),
-
- .spi_ro_config(spi_ro_config), // (verify) wire input to the core not connected to HKSPI, what should it be connected to ?
- .spi_ro_pll_div(spi_ro_pll_div),
- .spi_ro_pll_sel(spi_ro_pll_sel),
- .spi_ro_xtal_ena(spi_ro_xtal_ena),
- .spi_ro_reg_ena(spi_ro_reg_ena),
-
- .spi_ro_pll_trim(spi_ro_pll_trim),
- .spi_ro_pll_dco_ena(spi_ro_pll_dco_ena),
-
- .spi_ro_mfgr_id(spi_ro_mfgr_id),
- .spi_ro_prod_id(spi_ro_prod_id),
- .spi_ro_mask_rev(spi_ro_mask_rev),
- .pll_bypass(pll_bypass)
- );
-
-endmodule
-
-module spi_sysctrl #(
- parameter BASE_ADR = 32'h2300_0000,
- parameter SPI_CFG = 8'h00,
- parameter SPI_ENA = 8'h04,
- parameter SPI_PLL_CFG = 8'h08,
- parameter SPI_MFGR_ID = 8'h0c,
- parameter SPI_PROD_ID = 8'h10,
- parameter SPI_MASK_REV = 8'h14,
- parameter SPI_PLL_BYPASS = 8'h18
-) (
- input clk,
- input resetn,
-
- input [31:0] iomem_addr,
- input iomem_valid,
- input [3:0] iomem_wstrb,
- input [31:0] iomem_wdata,
- output reg [31:0] iomem_rdata,
- output reg iomem_ready,
-
- input [7:0] spi_ro_config, // (verify) wire input to the core not connected to HKSPI, what should it be connected to ?
-
- input [4:0] spi_ro_pll_div,
- input [2:0] spi_ro_pll_sel,
- input spi_ro_xtal_ena,
- input spi_ro_reg_ena,
-
- input [25:0] spi_ro_pll_trim,
- input spi_ro_pll_dco_ena,
-
- input [11:0] spi_ro_mfgr_id,
- input [7:0] spi_ro_prod_id,
- input [3:0] spi_ro_mask_rev,
- input pll_bypass
-);
- // Read-only Registers
-
- wire spi_cfg_sel;
- wire spi_ena_sel;
- wire pll_cfg_sel;
- wire spi_mfgr_sel;
- wire spi_prod_sel;
- wire spi_maskrev_sel;
- wire pll_bypass_sel;
-
-
- assign spi_cfg_sel = (iomem_addr[7:0] == SPI_CFG);
- assign spi_ena_sel = (iomem_addr[7:0] == SPI_ENA);
- assign pll_cfg_sel = (iomem_addr[7:0] == SPI_PLL_CFG);
- assign spi_mfgr_sel = (iomem_addr[7:0] == SPI_MFGR_ID);
- assign spi_prod_sel = (iomem_addr[7:0] == SPI_PROD_ID);
-
- assign spi_maskrev_sel = (iomem_addr[7:0] == SPI_MASK_REV);
- assign pll_bypass_sel = (iomem_addr[7:0] == SPI_PLL_BYPASS);
-
- always @(posedge clk) begin
- iomem_ready <= 0;
- if (iomem_valid && !iomem_ready && iomem_addr[31:8] == BASE_ADR[31:8]) begin
- iomem_ready <= 1;
- if (spi_cfg_sel) begin
- iomem_rdata <= {24'd0, spi_ro_config};
-
- end else if (spi_ena_sel) begin
- iomem_rdata <= {
- 22'd0,
- spi_ro_pll_div,
- spi_ro_pll_sel,
- spi_ro_xtal_ena,
- spi_ro_reg_ena
- };
-
- end else if (pll_cfg_sel) begin
- iomem_rdata <= {
- 5'd0,
- spi_ro_pll_trim,
- spi_ro_pll_dco_ena
- };
-
- end else if (spi_mfgr_sel) begin
- iomem_rdata <= {20'd0, spi_ro_mfgr_id};
-
- end else if (spi_prod_sel) begin
- iomem_rdata <= {24'd0, spi_ro_prod_id};
-
- end else if (spi_maskrev_sel) begin
- iomem_rdata <= {28'd0, spi_ro_mask_rev};
-
- end else if (pll_bypass_sel) begin
- iomem_rdata <= {31'd0, pll_bypass};
- end
- end
- end
-
-endmodule
\ No newline at end of file
diff --git a/verilog/rtl/spimemio.v b/verilog/rtl/spimemio.v
index 053aa61..456c2d0 100644
--- a/verilog/rtl/spimemio.v
+++ b/verilog/rtl/spimemio.v
@@ -22,7 +22,7 @@
input wb_rst_i,
input [31:0] wb_adr_i,
- input [31:0] wb_dat_i,
+ input [31:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input wb_cyc_i,
@@ -36,6 +36,12 @@
output [31:0] wb_flash_dat_o,
output [31:0] wb_cfg_dat_o,
+ input pass_thru,
+ input pass_thru_csb,
+ input pass_thru_sck,
+ input pass_thru_sdi,
+ output pass_thru_sdo,
+
output flash_csb,
output flash_clk,
@@ -280,28 +286,35 @@
xfer_io3_90 <= xfer_io3_do;
end
- assign flash_csb = config_en ? xfer_csb : config_csb;
- assign flash_clk = config_en ? xfer_clk : config_clk;
+ wire pass_thru;
+ wire pass_thru_csb;
+ wire pass_thru_sck;
+ wire pass_thru_sdi;
+ wire pass_thru_sdo;
- assign flash_csb_oeb = ~resetn;
- assign flash_clk_oeb = ~resetn;
+ assign flash_csb = (pass_thru) ? pass_thru_csb : (config_en ? xfer_csb : config_csb);
+ assign flash_clk = (pass_thru) ? pass_thru_sck : (config_en ? xfer_clk : config_clk);
- assign flash_io0_oeb = ~resetn ? 1'b1 : (config_en ? ~xfer_io0_oe : ~config_oe[0]);
- assign flash_io1_oeb = ~resetn ? 1'b1 : (config_en ? ~xfer_io1_oe : ~config_oe[1]);
- assign flash_io2_oeb = ~resetn ? 1'b1 : (config_en ? ~xfer_io2_oe : ~config_oe[2]);
- assign flash_io3_oeb = ~resetn ? 1'b1 : (config_en ? ~xfer_io3_oe : ~config_oe[3]);
+ assign flash_csb_oeb = (pass_thru) ? 1'b0 : (~resetn ? 1'b1 : 1'b0);
+ assign flash_clk_oeb = (pass_thru) ? 1'b0 : (~resetn ? 1'b1 : 1'b0);
+
+ assign flash_io0_oeb = pass_thru ? 1'b0 : ~resetn ? 1'b1 : (config_en ? ~xfer_io0_oe : ~config_oe[0]);
+ assign flash_io1_oeb = (pass_thru | ~resetn) ? 1'b1 : (config_en ? ~xfer_io1_oe : ~config_oe[1]);
+ assign flash_io2_oeb = (pass_thru | ~resetn) ? 1'b1 : (config_en ? ~xfer_io2_oe : ~config_oe[2]);
+ assign flash_io3_oeb = (pass_thru | ~resetn) ? 1'b1 : (config_en ? ~xfer_io3_oe : ~config_oe[3]);
assign flash_csb_ieb = 1'b1; /* Always disabled */
assign flash_clk_ieb = 1'b1; /* Always disabled */
- assign flash_io0_ieb = ~resetn ? 1'b1 : (config_en ? xfer_io0_oe : config_oe[0]);
- assign flash_io1_ieb = ~resetn ? 1'b1 : (config_en ? xfer_io1_oe : config_oe[1]);
- assign flash_io2_ieb = ~resetn ? 1'b1 : (config_en ? xfer_io2_oe : config_oe[2]);
- assign flash_io3_ieb = ~resetn ? 1'b1 : (config_en ? xfer_io3_oe : config_oe[3]);
+ assign flash_io0_ieb = (pass_thru | ~resetn) ? 1'b1 : (config_en ? xfer_io0_oe : config_oe[0]);
+ assign flash_io1_ieb = (pass_thru | ~resetn) ? 1'b1 : (config_en ? xfer_io1_oe : config_oe[1]);
+ assign flash_io2_ieb = (pass_thru | ~resetn) ? 1'b1 : (config_en ? xfer_io2_oe : config_oe[2]);
+ assign flash_io3_ieb = (pass_thru | ~resetn) ? 1'b1 : (config_en ? xfer_io3_oe : config_oe[3]);
- assign flash_io0_do = config_en ? (config_ddr ? xfer_io0_90 : xfer_io0_do) : config_do[0];
+ assign flash_io0_do = pass_thru ? pass_thru_sdi : (config_en ? (config_ddr ? xfer_io0_90 : xfer_io0_do) : config_do[0]);
assign flash_io1_do = config_en ? (config_ddr ? xfer_io1_90 : xfer_io1_do) : config_do[1];
assign flash_io2_do = config_en ? (config_ddr ? xfer_io2_90 : xfer_io2_do) : config_do[2];
assign flash_io3_do = config_en ? (config_ddr ? xfer_io3_90 : xfer_io3_do) : config_do[3];
+ assign pass_thru_sdo = pass_thru ? flash_io1_di : 1'b0;
wire xfer_dspi = din_ddr && !din_qspi;
wire xfer_ddr = din_ddr && din_qspi;
diff --git a/verilog/rtl/striVe_spi.v b/verilog/rtl/striVe_spi.v
deleted file mode 100644
index 54643c3..0000000
--- a/verilog/rtl/striVe_spi.v
+++ /dev/null
@@ -1,194 +0,0 @@
-//-------------------------------------
-// SPI controller for striVe (PicoSoC)
-//-------------------------------------
-// Written by Tim Edwards
-// efabless, inc. December 23, 2019
-//-------------------------------------
-
-`include "spi_slave.v"
-
-//-----------------------------------------------------------
-// This is a standalone slave SPI for the striVe chip that is
-// intended to be independent of the picosoc and independent
-// of all IP blocks except the power-on-reset. This SPI has
-// register outputs controlling the functions that critically
-// affect operation of the picosoc and so cannot be accessed
-// from the picosoc itself. This includes the PLL enables
-// and trim, and the crystal oscillator enable. It also has
-// a general reset for the picosoc, an IRQ input, a bypass for
-// the entire crystal oscillator and PLL chain, the
-// manufacturer and product IDs and product revision number.
-// To be independent of the 1.8V regulator, the slave SPI is
-// synthesized with the 3V digital library and runs off of
-// the 3V supply.
-//
-//-----------------------------------------------------------
-
-//------------------------------------------------------------
-// Picochip defined registers:
-// Register 0: SPI status and control (unused & reserved)
-// Register 1h: Mask revision (= 0) (readonly)
-// Register 1l and 2: Manufacturer ID (0x456) (readonly)
-// Register 3: Product ID (= 2) (readonly)
-//
-// Register 4: SkyWater IP enable and trim (xtal, regulator, PLL) (8 bits)
-// Register 5: PLL bypass (1 bit)
-// Register 6: IRQ (1 bit)
-// Register 7: reset (1 bit)
-// Register 8: trap (1 bit) (readonly)
-//------------------------------------------------------------
-
-module striVe_spi(
-`ifdef LVS
- vdd, vss,
-`endif
- RSTB, SCK, SDI, CSB, SDO, sdo_enb,
- xtal_ena, reg_ena, pll_dco_ena, pll_div, pll_sel,
- pll_trim, pll_bypass, irq, reset, RST, trap,
- mfgr_id, prod_id, mask_rev_in, mask_rev);
-
-`ifdef LVS
- inout vdd; // 3.3V supply
- inout vss; // common ground
-`endif
-
- input RSTB; // 3.3V domain
- input SCK; // 3.3V domain
- input SDI; // 3.3V domain
- input CSB; // 3.3V domain
- output SDO; // 3.3V domain
- output sdo_enb;
- output xtal_ena;
- output reg_ena;
- output pll_dco_ena;
- output [25:0] pll_trim;
- output [2:0] pll_sel;
- output [4:0] pll_div;
- output pll_bypass;
- output irq;
- output reset;
- output RST;
- input trap;
- input [3:0] mask_rev_in; // metal programmed; 3.3V domain
- output [11:0] mfgr_id;
- output [7:0] prod_id;
- output [3:0] mask_rev;
-
- reg xtal_ena;
- reg reg_ena;
- reg [25:0] pll_trim;
- reg [4:0] pll_div;
- reg [2:0] pll_sel;
- reg pll_dco_ena;
- reg pll_bypass;
- reg irq;
- reg reset;
-
- wire [7:0] odata;
- wire [7:0] idata;
- wire [7:0] iaddr;
-
- wire trap;
- wire rdstb;
- wire wrstb;
-
- assign RST = ~RSTB;
-
- // Instantiate the SPI slave module
-
- spi_slave U1 (
- .SCK(SCK),
- .SDI(SDI),
- .CSB(CSB),
- .SDO(SDO),
- .sdoenb(sdo_enb),
- .idata(odata),
- .odata(idata),
- .oaddr(iaddr),
- .rdstb(rdstb),
- .wrstb(wrstb)
- );
-
- wire [11:0] mfgr_id;
- wire [7:0] prod_id;
- wire [3:0] mask_rev;
-
- assign mfgr_id = 12'h456; // Hard-coded
- assign prod_id = 8'h05; // Hard-coded
- assign mask_rev = mask_rev_in; // Copy in to out.
-
- // Send register contents to odata on SPI read command
- // All values are 1-4 bits and no shadow registers are required.
-
- assign odata =
- (iaddr == 8'h00) ? 8'h00 : // SPI status (fixed)
- (iaddr == 8'h01) ? {mask_rev, mfgr_id[11:8]} : // Mask rev (metal programmed)
- (iaddr == 8'h02) ? mfgr_id[7:0] : // Manufacturer ID (fixed)
- (iaddr == 8'h03) ? prod_id : // Product ID (fixed)
- (iaddr == 8'h04) ? {5'b00000, xtal_ena, reg_ena, pll_dco_ena} :
- (iaddr == 8'h05) ? {7'b0000000, pll_bypass} :
- (iaddr == 8'h06) ? {7'b0000000, irq} :
- (iaddr == 8'h07) ? {7'b0000000, reset} :
- (iaddr == 8'h08) ? {7'b0000000, trap} :
- (iaddr == 8'h09) ? pll_trim[7:0] :
- (iaddr == 8'h0a) ? pll_trim[15:8] :
- (iaddr == 8'h0b) ? pll_trim[23:16] :
- (iaddr == 8'h0c) ? {6'b000000, pll_trim[25:24]} :
- (iaddr == 8'h0d) ? {5'b00000, pll_sel} :
- (iaddr == 8'h0e) ? {3'b000, pll_div} :
- 8'h00; // Default
-
- // Register mapping and I/O to slave module
-
- always @(posedge SCK or negedge RSTB) begin
- if (RSTB == 1'b0) begin
- // Set trim for PLL at (almost) slowest rate (~90MHz). However,
- // pll_trim[12] must be set to zero for proper startup.
- pll_trim <= 26'b11111111111110111111111111;
- pll_sel <= 3'b000;
- pll_div <= 5'b00100; // Default divide-by-8
- xtal_ena <= 1'b1;
- reg_ena <= 1'b1;
- pll_dco_ena <= 1'b1; // Default free-running PLL
- pll_bypass <= 1'b1; // NOTE: Default bypass mode (don't use PLL)
- irq <= 1'b0;
- reset <= 1'b0;
- end else if (wrstb == 1'b1) begin
- case (iaddr)
- 8'h04: begin
- pll_dco_ena <= idata[2];
- reg_ena <= idata[1];
- xtal_ena <= idata[0];
- end
- 8'h05: begin
- pll_bypass <= idata[0];
- end
- 8'h06: begin
- irq <= idata[0];
- end
- 8'h07: begin
- reset <= idata[0];
- end
- // Register 8 is read-only
- 8'h09: begin
- pll_trim[7:0] <= idata;
- end
- 8'h0a: begin
- pll_trim[15:8] <= idata;
- end
- 8'h0b: begin
- pll_trim[23:16] <= idata;
- end
- 8'h0c: begin
- pll_trim[25:24] <= idata[1:0];
- end
- 8'h0d: begin
- pll_sel <= idata[2:0];
- end
- 8'h0e: begin
- pll_div <= idata[4:0];
- end
- endcase // (iaddr)
- end
- end
-endmodule // striVe_spi_orig
diff --git a/verilog/rtl/sysctrl.v b/verilog/rtl/sysctrl.v
index 9d66e66..62ed4fc 100644
--- a/verilog/rtl/sysctrl.v
+++ b/verilog/rtl/sysctrl.v
@@ -2,8 +2,7 @@
parameter BASE_ADR = 32'h2F00_0000,
parameter PLL_OUT = 8'h0c,
parameter TRAP_OUT = 8'h10,
- parameter IRQ7_SRC = 8'h14,
- parameter IRQ8_SRC = 8'h18
+ parameter IRQ7_SRC = 8'h14
) (
input wb_clk_i,
input wb_rst_i,
@@ -20,8 +19,7 @@
output pll_output_dest,
output trap_output_dest,
- output irq_7_inputsrc,
- output irq_8_inputsrc
+ output irq_7_inputsrc
);
@@ -40,8 +38,7 @@
.BASE_ADR(BASE_ADR),
.PLL_OUT(PLL_OUT),
.TRAP_OUT(TRAP_OUT),
- .IRQ7_SRC(IRQ7_SRC),
- .IRQ8_SRC(IRQ8_SRC)
+ .IRQ7_SRC(IRQ7_SRC)
) sysctrl (
.clk(wb_clk_i),
.resetn(resetn),
@@ -56,8 +53,7 @@
.pll_output_dest(pll_output_dest),
.trap_output_dest(trap_output_dest),
- .irq_7_inputsrc(irq_7_inputsrc),
- .irq_8_inputsrc(irq_8_inputsrc)
+ .irq_7_inputsrc(irq_7_inputsrc)
);
endmodule
@@ -66,8 +62,7 @@
parameter BASE_ADR = 32'h2300_0000,
parameter PLL_OUT = 8'h0c,
parameter TRAP_OUT = 8'h10,
- parameter IRQ7_SRC = 8'h14,
- parameter IRQ8_SRC = 8'h18
+ parameter IRQ7_SRC = 8'h14
) (
input clk,
input resetn,
@@ -81,27 +76,23 @@
output pll_output_dest,
output trap_output_dest,
- output irq_7_inputsrc,
- output irq_8_inputsrc
+ output irq_7_inputsrc
);
reg pll_output_dest;
reg trap_output_dest;
reg irq_7_inputsrc;
- reg irq_8_inputsrc;
assign pll_out_sel = (iomem_addr[7:0] == PLL_OUT);
assign trap_out_sel = (iomem_addr[7:0] == TRAP_OUT);
assign irq7_sel = (iomem_addr[7:0] == IRQ7_SRC);
- assign irq8_sel = (iomem_addr[7:0] == IRQ8_SRC);
always @(posedge clk) begin
if (!resetn) begin
pll_output_dest <= 0;
trap_output_dest <= 0;
irq_7_inputsrc <= 0;
- irq_8_inputsrc <= 0;
end else begin
iomem_ready <= 0;
if (iomem_valid && !iomem_ready && iomem_addr[31:8] == BASE_ADR[31:8]) begin
@@ -122,11 +113,6 @@
if (iomem_wstrb[0])
irq_7_inputsrc <= iomem_wdata[0];
- end else if (irq8_sel) begin
- iomem_rdata <= {31'd0, irq_8_inputsrc};
- if (iomem_wstrb[0])
- irq_8_inputsrc <= iomem_wdata[0];
-
end
end
end
diff --git a/verilog/rtl/user_id_programming.v b/verilog/rtl/user_id_programming.v
new file mode 100644
index 0000000..4e80555
--- /dev/null
+++ b/verilog/rtl/user_id_programming.v
@@ -0,0 +1,36 @@
+// This module represents an unprogrammed mask revision
+// block that is configured with via programming on the
+// chip top level. This value is passed to the block as
+// a parameter
+
+module user_id_programming #(
+ parameter [ 0:0] USER_PROJECT_ID = 32'h0
+) (
+ output [31:0] mask_rev
+);
+ wire [31:0] mask_rev;
+ wire [31:0] user_proj_id_high;
+ wire [31:0] user_proj_id_low;
+
+ // For the mask revision input, use an array of digital constant logic cells
+
+ sky130_fd_sc_hd__conb_1 mask_rev_value [31:0] (
+ `ifdef LVS
+ .vpwr(vdd1v8),
+ .vpb(vdd1v8),
+ .vnb(vss),
+ .vgnd(vss),
+ `endif
+ .HI(user_proj_id_high),
+ .LO(user_proj_id_low)
+ );
+
+ genvar i;
+ generate
+ for (i = 0; i < 32; i = i+1) begin
+ assign mask_rev[i] = (USER_PROJECT_ID & (32'h01 << i)) ?
+ user_proj_id_high[i] : user_proj_id_low[i];
+ end
+ endgenerate
+
+endmodule
diff --git a/verilog/rtl/wb_intercon.v b/verilog/rtl/wb_intercon.v
index 3a2c58f..1397cd4 100644
--- a/verilog/rtl/wb_intercon.v
+++ b/verilog/rtl/wb_intercon.v
@@ -24,12 +24,12 @@
{8'hFF, {24{1'b0}} }
};
parameter [NS*AW-1:0] SLAVE_ADR = {
- {8'h28, {24{1'b0}} }, // Flash Configuration Register
- {8'h23, {24{1'b0}} }, // System Control
- {8'h21, {24{1'b0}} }, // GPIOs
- {8'h20, {24{1'b0}} }, // UART
- {8'h10, {24{1'b0}} }, // Flash
- {8'h00, {24{1'b0}} } // RAM
+ { 32'h2800_0000 }, // Flash Configuration Register
+ { 32'h2200_0000 }, // System Control
+ { 32'h2100_0000 }, // GPIOs
+ { 32'h2000_0000 }, // UART
+ { 32'h1000_0000 }, // Flash
+ { 32'h0000_0000 } // RAM
};
wire [NS-1: 0] slave_sel;
@@ -54,4 +54,4 @@
wbm_dat_o[i%DW] = wbm_dat_o[i%DW] | (slave_sel[i/DW] & wbs_dat_i[i]);
end
-endmodule
\ No newline at end of file
+endmodule
