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shalanfd13eb52020-08-21 16:48:07 +02001/*
2 * PicoSoC - A simple example SoC using PicoRV32
3 *
4 * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * Revision 1, July 2019: Added signals to drive flash_clk and flash_csb
19 * output enable (inverted), tied to reset so that the flash is completely
20 * isolated from the processor when the processor is in reset.
21 *
22 * Also: Made ram_wenb a 4-bit bus so that the memory access can be made
23 * byte-wide for byte-wide instructions.
24 */
25
26`ifdef PICORV32_V
Tim Edwards04ba17f2020-10-02 22:27:50 -040027`error "mgmt_soc.v must be read before picorv32.v!"
shalanfd13eb52020-08-21 16:48:07 +020028`endif
29
Tim Edwards04ba17f2020-10-02 22:27:50 -040030`define PICORV32_REGS mgmt_soc_regs
shalanfd13eb52020-08-21 16:48:07 +020031
32`include "picorv32.v"
33`include "spimemio.v"
34`include "simpleuart.v"
Tim Edwards04ba17f2020-10-02 22:27:50 -040035`include "simple_spi_master.v"
36`include "counter_timer.v"
shalanfd13eb52020-08-21 16:48:07 +020037`include "wb_intercon.v"
38`include "mem_wb.v"
39`include "gpio_wb.v"
shalanfd13eb52020-08-21 16:48:07 +020040`include "sysctrl.v"
41`include "la_wb.v"
shalan0d14e6e2020-08-31 16:50:48 +020042`include "mprj_ctrl.v"
Tim Edwards04ba17f2020-10-02 22:27:50 -040043`include "convert_gpio_sigs.v"
shalanfd13eb52020-08-21 16:48:07 +020044
45module mgmt_soc (
46`ifdef LVS
47 inout vdd1v8, /* 1.8V domain */
48 inout vss,
49`endif
50 input pll_clk,
51 input ext_clk,
52 input ext_clk_sel,
53
54 input clk,
55 input resetn,
56
Tim Edwards04ba17f2020-10-02 22:27:50 -040057 // Trap state from CPU
58 output trap,
59
60 // GPIO (one pin)
61 output gpio_out_pad, // Connect to out on gpio pad
62 input gpio_in_pad, // Connect to in on gpio pad
63 output gpio_mode0_pad, // Connect to dm[0] on gpio pad
64 output gpio_mode1_pad, // Connect to dm[2] on gpio pad
65 output gpio_outenb_pad, // Connect to oe_n on gpio pad
66 output gpio_inenb_pad, // Connect to inp_dis on gpio pad
shalanfd13eb52020-08-21 16:48:07 +020067
68 // LA signals
69 input [127:0] la_input, // From Mega-Project to cpu
70 output [127:0] la_output, // From CPU to Mega-Project
shalan0d14e6e2020-08-31 16:50:48 +020071 output [127:0] la_oen, // LA output enable (active low)
72
Tim Edwards04ba17f2020-10-02 22:27:50 -040073 // Mega-Project I/O Configuration (serial load)
74 output mprj_io_loader_resetn,
75 output mprj_io_loader_clock,
76 output mprj_io_loader_data,
shalanfd13eb52020-08-21 16:48:07 +020077
Tim Edwards04ba17f2020-10-02 22:27:50 -040078 // Mega-Project pad data (when management SoC controls the pad)
Tim Edwards44bab472020-10-04 22:09:54 -040079 // inout [MPRJ_IO_PADS-1:0] mgmt_io_data,
80 input [MPRJ_IO_PADS-1:0] mgmt_in_data,
81 output [MPRJ_IO_PADS-1:0] mgmt_out_data,
82 output [MPRJ_IO_PADS-1:0] mgmt_outz_data,
83 output [MPRJ_IO_PADS-1:0] mgmt_oeb_data,
shalanfd13eb52020-08-21 16:48:07 +020084
Tim Edwards04ba17f2020-10-02 22:27:50 -040085 // SPI master
86 output spi_csb,
87 output spi_sck,
88 output spi_sdo,
Tim Edwards44bab472020-10-04 22:09:54 -040089 output spi_sdoenb,
Tim Edwards04ba17f2020-10-02 22:27:50 -040090 input spi_sdi,
shalanfd13eb52020-08-21 16:48:07 +020091
Tim Edwards04ba17f2020-10-02 22:27:50 -040092 // UART
shalanfd13eb52020-08-21 16:48:07 +020093 output ser_tx,
94 input ser_rx,
95
96 // IRQ
97 input irq_pin, // dedicated IRQ pin
98 input irq_spi, // IRQ from standalone SPI
99
shalanfd13eb52020-08-21 16:48:07 +0200100 // Flash memory control (SPI master)
101 output flash_csb,
102 output flash_clk,
103
104 output flash_csb_oeb,
105 output flash_clk_oeb,
106
107 output flash_io0_oeb,
108 output flash_io1_oeb,
109 output flash_io2_oeb,
110 output flash_io3_oeb,
111
112 output flash_csb_ieb,
113 output flash_clk_ieb,
114
115 output flash_io0_ieb,
116 output flash_io1_ieb,
117 output flash_io2_ieb,
118 output flash_io3_ieb,
119
120 output flash_io0_do,
121 output flash_io1_do,
122 output flash_io2_do,
123 output flash_io3_do,
124
125 input flash_io0_di,
126 input flash_io1_di,
127 input flash_io2_di,
128 input flash_io3_di,
129
Tim Edwards04ba17f2020-10-02 22:27:50 -0400130 // SPI pass-thru mode
131 input pass_thru_mgmt,
132 input pass_thru_mgmt_csb,
133 input pass_thru_mgmt_sck,
134 input pass_thru_mgmt_sdi,
135 output pass_thru_mgmt_sdo,
136
shalan0d14e6e2020-08-31 16:50:48 +0200137 // WB MI A (Mega project)
138 input mprj_ack_i,
Tim Edwardsef8312e2020-09-22 17:20:06 -0400139 input [31:0] mprj_dat_i,
shalan0d14e6e2020-08-31 16:50:48 +0200140 output mprj_cyc_o,
Tim Edwardsef8312e2020-09-22 17:20:06 -0400141 output mprj_stb_o,
142 output mprj_we_o,
143 output [3:0] mprj_sel_o,
144 output [31:0] mprj_adr_o,
145 output [31:0] mprj_dat_o,
shalan0d14e6e2020-08-31 16:50:48 +0200146
147 // WB MI B (xbar)
shalanfd13eb52020-08-21 16:48:07 +0200148 input [31:0] xbar_dat_i,
149 input xbar_ack_i,
150 output xbar_cyc_o,
151 output xbar_stb_o,
152 output xbar_we_o,
153 output [3:0] xbar_sel_o,
154 output [31:0] xbar_adr_o,
155 output [31:0] xbar_dat_o
156);
157 /* Memory reverted back to 256 words while memory has to be synthesized */
shalan0d14e6e2020-08-31 16:50:48 +0200158 parameter integer MEM_WORDS = 8192;
shalanfd13eb52020-08-21 16:48:07 +0200159 parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory
160 parameter [31:0] PROGADDR_RESET = 32'h 1000_0000;
161 parameter [31:0] PROGADDR_IRQ = 32'h 0000_0000;
162
163 // Slaves Base Addresses
Tim Edwards04ba17f2020-10-02 22:27:50 -0400164 parameter RAM_BASE_ADR = 32'h 0000_0000;
165 parameter FLASH_BASE_ADR = 32'h 1000_0000;
166 parameter UART_BASE_ADR = 32'h 2000_0000;
167 parameter GPIO_BASE_ADR = 32'h 2100_0000;
168 parameter COUNTER_TIMER0_BASE_ADR = 32'h 2110_0000;
169 parameter COUNTER_TIMER1_BASE_ADR = 32'h 2120_0000;
170 parameter SPI_MASTER_BASE_ADR = 32'h 2130_0000;
171 parameter LA_BASE_ADR = 32'h 2200_0000;
172 parameter MPRJ_CTRL_ADR = 32'h 2300_0000;
173 parameter MPRJ_BASE_ADR = 32'h 3000_0000; // WB MI A
174 parameter SYS_BASE_ADR = 32'h 2F00_0000;
175 parameter FLASH_CTRL_CFG = 32'h 2D00_0000;
176 parameter XBAR_BASE_ADR = 32'h 8000_0000;
shalanfd13eb52020-08-21 16:48:07 +0200177
178 // UART
179 parameter UART_CLK_DIV = 8'h00;
180 parameter UART_DATA = 8'h04;
Tim Edwards04ba17f2020-10-02 22:27:50 -0400181
182 // SPI Master
183 parameter SPI_MASTER_CONFIG = 8'h00;
184 parameter SPI_MASTER_DATA = 8'h04;
185
186 // Counter-timer 0
187 parameter COUNTER_TIMER0_CONFIG = 8'h00;
188 parameter COUNTER_TIMER0_VALUE = 8'h04;
189 parameter COUNTER_TIMER0_DATA = 8'h08;
190
191 // Counter-timer 1
192 parameter COUNTER_TIMER1_CONFIG = 8'h00;
193 parameter COUNTER_TIMER1_VALUE = 8'h04;
194 parameter COUNTER_TIMER1_DATA = 8'h08;
shalanfd13eb52020-08-21 16:48:07 +0200195
196 // SOC GPIO
197 parameter GPIO_DATA = 8'h00;
198 parameter GPIO_ENA = 8'h04;
199 parameter GPIO_PU = 8'h08;
200 parameter GPIO_PD = 8'h0c;
201
shalan0d14e6e2020-08-31 16:50:48 +0200202 // LA
shalanfd13eb52020-08-21 16:48:07 +0200203 parameter LA_DATA_0 = 8'h00;
204 parameter LA_DATA_1 = 8'h04;
205 parameter LA_DATA_2 = 8'h08;
206 parameter LA_DATA_3 = 8'h0c;
207 parameter LA_ENA_0 = 8'h10;
208 parameter LA_ENA_1 = 8'h14;
209 parameter LA_ENA_2 = 8'h18;
210 parameter LA_ENA_3 = 8'h1c;
211
shalan0d14e6e2020-08-31 16:50:48 +0200212 // Mega-Project Control
213 parameter MPRJ_IO_PADS = 32;
Tim Edwardsc18c4742020-10-03 11:26:39 -0400214 parameter MPRJ_PWR_PADS = 32;
shalan0d14e6e2020-08-31 16:50:48 +0200215
shalanfd13eb52020-08-21 16:48:07 +0200216 // System Control Registers
Tim Edwards44bab472020-10-04 22:09:54 -0400217 parameter PLL_OUT = 8'h00;
218 parameter TRAP_OUT = 8'h04;
219 parameter IRQ7_SRC = 8'h08;
shalanfd13eb52020-08-21 16:48:07 +0200220
221 // Wishbone Interconnect
222 localparam ADR_WIDTH = 32;
223 localparam DAT_WIDTH = 32;
Tim Edwards04ba17f2020-10-02 22:27:50 -0400224 localparam NUM_SLAVES = 13;
shalanfd13eb52020-08-21 16:48:07 +0200225
226 parameter [NUM_SLAVES*ADR_WIDTH-1: 0] ADR_MASK = {
227 {8'h80, {ADR_WIDTH-8{1'b0}}},
228 {8'hFF, {ADR_WIDTH-8{1'b0}}},
229 {8'hFF, {ADR_WIDTH-8{1'b0}}},
230 {8'hFF, {ADR_WIDTH-8{1'b0}}},
231 {8'hFF, {ADR_WIDTH-8{1'b0}}},
232 {8'hFF, {ADR_WIDTH-8{1'b0}}},
233 {8'hFF, {ADR_WIDTH-8{1'b0}}},
234 {8'hFF, {ADR_WIDTH-8{1'b0}}},
shalan0d14e6e2020-08-31 16:50:48 +0200235 {8'hFF, {ADR_WIDTH-8{1'b0}}},
236 {8'hFF, {ADR_WIDTH-8{1'b0}}},
Tim Edwards04ba17f2020-10-02 22:27:50 -0400237 {8'hFF, {ADR_WIDTH-8{1'b0}}},
238 {8'hFF, {ADR_WIDTH-8{1'b0}}},
shalanfd13eb52020-08-21 16:48:07 +0200239 {8'hFF, {ADR_WIDTH-8{1'b0}}}
240 };
shalan0d14e6e2020-08-31 16:50:48 +0200241
shalanfd13eb52020-08-21 16:48:07 +0200242 parameter [NUM_SLAVES*ADR_WIDTH-1: 0] SLAVE_ADR = {
243 {XBAR_BASE_ADR},
244 {SYS_BASE_ADR},
shalanfd13eb52020-08-21 16:48:07 +0200245 {FLASH_CTRL_CFG},
shalan0d14e6e2020-08-31 16:50:48 +0200246 {MPRJ_BASE_ADR},
247 {MPRJ_CTRL_ADR},
shalanfd13eb52020-08-21 16:48:07 +0200248 {LA_BASE_ADR},
Tim Edwards04ba17f2020-10-02 22:27:50 -0400249 {SPI_MASTER_BASE_ADR},
250 {COUNTER_TIMER1_BASE_ADR},
251 {COUNTER_TIMER0_BASE_ADR},
shalanfd13eb52020-08-21 16:48:07 +0200252 {GPIO_BASE_ADR},
253 {UART_BASE_ADR},
254 {FLASH_BASE_ADR},
255 {RAM_BASE_ADR}
256 };
257
258 // memory-mapped I/O control registers
Tim Edwards04ba17f2020-10-02 22:27:50 -0400259 wire gpio_pullup; // Intermediate GPIO pullup
260 wire gpio_pulldown; // Intermediate GPIO pulldown
261 wire gpio_outenb; // Intermediate GPIO out enable (bar)
262 wire gpio_out; // Intermediate GPIO output
shalanfd13eb52020-08-21 16:48:07 +0200263
Tim Edwards04ba17f2020-10-02 22:27:50 -0400264 wire gpio; // GPIO output data
265 wire gpio_pu; // GPIO pull-up enable
266 wire gpio_pd; // GPIO pull-down enable
267 wire gpio_oeb; // GPIO output enable (sense negative)
shalanfd13eb52020-08-21 16:48:07 +0200268
Tim Edwardsef8312e2020-09-22 17:20:06 -0400269 wire pll_output_dest; // PLL clock output destination
270 wire trap_output_dest; // Trap signal output destination
271 wire irq_7_inputsrc; // IRQ 7 source
shalanfd13eb52020-08-21 16:48:07 +0200272
273 // GPIO assignments
Tim Edwards04ba17f2020-10-02 22:27:50 -0400274 assign gpio_out = (trap_output_dest == 1'b1) ? trap : gpio;
shalanfd13eb52020-08-21 16:48:07 +0200275
Tim Edwards04ba17f2020-10-02 22:27:50 -0400276 assign gpio_outenb = (trap_output_dest == 1'b0) ? gpio_oeb : 1'b0;
shalanfd13eb52020-08-21 16:48:07 +0200277
Tim Edwards04ba17f2020-10-02 22:27:50 -0400278 assign gpio_pullup = (trap_output_dest == 1'b0) ? gpio_pu : 1'b0;
shalanfd13eb52020-08-21 16:48:07 +0200279
Tim Edwards04ba17f2020-10-02 22:27:50 -0400280 assign gpio_pulldown = (trap_output_dest == 1'b0) ? gpio_pd : 1'b0;
shalanfd13eb52020-08-21 16:48:07 +0200281
Tim Edwardsef8312e2020-09-22 17:20:06 -0400282 // Convert GPIO signals to sky130_fd_io pad signals
Tim Edwards04ba17f2020-10-02 22:27:50 -0400283 convert_gpio_sigs convert_gpio_bit (
shalanfd13eb52020-08-21 16:48:07 +0200284 .gpio_out(gpio_out),
285 .gpio_outenb(gpio_outenb),
286 .gpio_pu(gpio_pullup),
287 .gpio_pd(gpio_pulldown),
288 .gpio_out_pad(gpio_out_pad),
289 .gpio_outenb_pad(gpio_outenb_pad),
290 .gpio_inenb_pad(gpio_inenb_pad),
291 .gpio_mode1_pad(gpio_mode1_pad),
292 .gpio_mode0_pad(gpio_mode0_pad)
293 );
294
295 reg [31:0] irq;
296 wire irq_7;
shalanfd13eb52020-08-21 16:48:07 +0200297 wire irq_stall;
298 wire irq_uart;
Tim Edwards04ba17f2020-10-02 22:27:50 -0400299 wire irq_spi_master;
300 wire irq_counter_timer0;
301 wire irq_counter_timer1;
shalanfd13eb52020-08-21 16:48:07 +0200302
shalanfd13eb52020-08-21 16:48:07 +0200303 assign irq_stall = 0;
Tim Edwards04ba17f2020-10-02 22:27:50 -0400304 assign irq_7 = (irq_7_inputsrc == 1'b1) ? gpio_in_pad : 1'b0;
shalanfd13eb52020-08-21 16:48:07 +0200305
306 always @* begin
307 irq = 0;
308 irq[3] = irq_stall;
309 irq[4] = irq_uart;
310 irq[5] = irq_pin;
311 irq[6] = irq_spi;
312 irq[7] = irq_7;
Tim Edwards04ba17f2020-10-02 22:27:50 -0400313 irq[9] = irq_spi_master;
314 irq[10] = irq_counter_timer0;
315 irq[11] = irq_counter_timer1;
shalanfd13eb52020-08-21 16:48:07 +0200316 end
317
shalanfd13eb52020-08-21 16:48:07 +0200318 // Assumption : no syscon module and wb_clk is the clock coming from the chip pin ?
319 assign wb_clk_i = clk;
320 assign wb_rst_i = ~resetn; // Redundant
321
322 // Wishbone Master
323 wire [31:0] cpu_adr_o;
324 wire [31:0] cpu_dat_i;
325 wire [3:0] cpu_sel_o;
326 wire cpu_we_o;
327 wire cpu_cyc_o;
328 wire cpu_stb_o;
329 wire [31:0] cpu_dat_o;
330 wire cpu_ack_i;
331
332 assign xbar_cyc_o = cpu_cyc_o;
333 assign xbar_we_o = cpu_we_o;
334 assign xbar_sel_o = cpu_sel_o;
335 assign xbar_adr_o = cpu_adr_o;
336 assign xbar_dat_o = cpu_dat_o;
337
338 picorv32_wb #(
339 .STACKADDR(STACKADDR),
340 .PROGADDR_RESET(PROGADDR_RESET),
341 .PROGADDR_IRQ(PROGADDR_IRQ),
342 .BARREL_SHIFTER(1),
343 .COMPRESSED_ISA(1),
344 .ENABLE_MUL(1),
345 .ENABLE_DIV(1),
346 .ENABLE_IRQ(1),
347 .ENABLE_IRQ_QREGS(0)
348 ) cpu (
349 .wb_clk_i (wb_clk_i),
350 .wb_rst_i (wb_rst_i),
351 .trap (trap),
352 .irq (irq),
353 .mem_instr(mem_instr),
354 .wbm_adr_o(cpu_adr_o),
355 .wbm_dat_i(cpu_dat_i),
356 .wbm_stb_o(cpu_stb_o),
357 .wbm_ack_i(cpu_ack_i),
358 .wbm_cyc_o(cpu_cyc_o),
359 .wbm_dat_o(cpu_dat_o),
360 .wbm_we_o(cpu_we_o),
361 .wbm_sel_o(cpu_sel_o)
362 );
363
364 // Wishbone Slave SPIMEMIO
365 wire spimemio_flash_stb_i;
366 wire spimemio_flash_ack_o;
367 wire [31:0] spimemio_flash_dat_o;
368
369 wire spimemio_cfg_stb_i;
370 wire spimemio_cfg_ack_o;
371 wire [31:0] spimemio_cfg_dat_o;
372
373 spimemio_wb spimemio (
374 .wb_clk_i(wb_clk_i),
375 .wb_rst_i(wb_rst_i),
376
377 .wb_adr_i(cpu_adr_o),
378 .wb_dat_i(cpu_dat_o),
379 .wb_sel_i(cpu_sel_o),
380 .wb_we_i(cpu_we_o),
381 .wb_cyc_i(cpu_cyc_o),
382
383 // FLash Slave
384 .wb_flash_stb_i(spimemio_flash_stb_i),
385 .wb_flash_ack_o(spimemio_flash_ack_o),
386 .wb_flash_dat_o(spimemio_flash_dat_o),
387
388 // Config Register Slave
389 .wb_cfg_stb_i(spimemio_cfg_stb_i),
390 .wb_cfg_ack_o(spimemio_cfg_ack_o),
391 .wb_cfg_dat_o(spimemio_cfg_dat_o),
392
Tim Edwards04ba17f2020-10-02 22:27:50 -0400393 .pass_thru(pass_thru_mgmt),
394 .pass_thru_csb(pass_thru_mgmt_csb),
395 .pass_thru_sck(pass_thru_mgmt_sck),
396 .pass_thru_sdi(pass_thru_mgmt_sdi),
397 .pass_thru_sdo(pass_thru_mgmt_sdo),
398
shalanfd13eb52020-08-21 16:48:07 +0200399 .flash_csb (flash_csb),
400 .flash_clk (flash_clk),
401
402 .flash_csb_oeb (flash_csb_oeb),
403 .flash_clk_oeb (flash_clk_oeb),
404
405 .flash_io0_oeb (flash_io0_oeb),
406 .flash_io1_oeb (flash_io1_oeb),
407 .flash_io2_oeb (flash_io2_oeb),
408 .flash_io3_oeb (flash_io3_oeb),
409
410 .flash_csb_ieb (flash_csb_ieb),
411 .flash_clk_ieb (flash_clk_ieb),
412
413 .flash_io0_ieb (flash_io0_ieb),
414 .flash_io1_ieb (flash_io1_ieb),
415 .flash_io2_ieb (flash_io2_ieb),
416 .flash_io3_ieb (flash_io3_ieb),
417
418 .flash_io0_do (flash_io0_do),
419 .flash_io1_do (flash_io1_do),
420 .flash_io2_do (flash_io2_do),
421 .flash_io3_do (flash_io3_do),
422
423 .flash_io0_di (flash_io0_di),
424 .flash_io1_di (flash_io1_di),
425 .flash_io2_di (flash_io2_di),
426 .flash_io3_di (flash_io3_di)
427 );
428
429 // Wishbone Slave uart
430 wire uart_stb_i;
431 wire uart_ack_o;
432 wire [31:0] uart_dat_o;
433
434 simpleuart_wb #(
435 .BASE_ADR(UART_BASE_ADR),
436 .CLK_DIV(UART_CLK_DIV),
437 .DATA(UART_DATA)
438 ) simpleuart (
439 // Wishbone Interface
440 .wb_clk_i(wb_clk_i),
441 .wb_rst_i(wb_rst_i),
442
443 .wb_adr_i(cpu_adr_o),
444 .wb_dat_i(cpu_dat_o),
445 .wb_sel_i(cpu_sel_o),
446 .wb_we_i(cpu_we_o),
447 .wb_cyc_i(cpu_cyc_o),
448
449 .wb_stb_i(uart_stb_i),
450 .wb_ack_o(uart_ack_o),
451 .wb_dat_o(uart_dat_o),
452
453 .ser_tx(ser_tx),
454 .ser_rx(ser_rx)
455 );
456
Tim Edwards04ba17f2020-10-02 22:27:50 -0400457 // Wishbone SPI master
458 wire spi_master_stb_i;
459 wire spi_master_ack_o;
460 wire [31:0] spi_master_dat_o;
461
462 simple_spi_master_wb #(
463 .BASE_ADR(SPI_MASTER_BASE_ADR),
464 .CONFIG(SPI_MASTER_CONFIG),
465 .DATA(SPI_MASTER_DATA)
466 ) simple_spi_master_inst (
467 // Wishbone Interface
468 .wb_clk_i(wb_clk_i),
469 .wb_rst_i(wb_rst_i),
470
471 .wb_adr_i(cpu_adr_o),
472 .wb_dat_i(cpu_dat_o),
473 .wb_sel_i(cpu_sel_o),
474 .wb_we_i(cpu_we_o),
475 .wb_cyc_i(cpu_cyc_o),
476
477 .wb_stb_i(spi_master_stb_i),
478 .wb_ack_o(spi_master_ack_o),
479 .wb_dat_o(spi_master_dat_o),
480
481 .csb(spi_csb),
482 .sck(spi_sck),
483 .sdi(spi_sdi),
484 .sdo(spi_sdo),
Tim Edwards44bab472020-10-04 22:09:54 -0400485 .sdoenb(spi_sdoenb),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400486 .irq(irq_spi_master)
487 );
488
489 // Wishbone Counter-timer 0
490 wire counter_timer0_stb_i;
491 wire counter_timer0_ack_o;
492 wire [31:0] counter_timer0_dat_o;
493
494 counter_timer_wb #(
495 .BASE_ADR(COUNTER_TIMER0_BASE_ADR),
496 .CONFIG(COUNTER_TIMER0_CONFIG),
497 .VALUE(COUNTER_TIMER0_VALUE),
498 .DATA(COUNTER_TIMER0_DATA)
499 ) counter_timer_0 (
500 // Wishbone Interface
501 .wb_clk_i(wb_clk_i),
502 .wb_rst_i(wb_rst_i),
503
504 .wb_adr_i(cpu_adr_o),
505 .wb_dat_i(cpu_dat_o),
506 .wb_sel_i(cpu_sel_o),
507 .wb_we_i(cpu_we_o),
508 .wb_cyc_i(cpu_cyc_o),
509
510 .wb_stb_i(counter_timer0_stb_i),
511 .wb_ack_o(counter_timer0_ack_o),
512 .wb_dat_o(counter_timer0_dat_o),
513 .irq(irq_counter_timer0)
514 );
515
516 // Wishbone Counter-timer 1
517 wire counter_timer1_stb_i;
518 wire counter_timer1_ack_o;
519 wire [31:0] counter_timer1_dat_o;
520
521 counter_timer_wb #(
522 .BASE_ADR(COUNTER_TIMER1_BASE_ADR),
523 .CONFIG(COUNTER_TIMER1_CONFIG),
524 .VALUE(COUNTER_TIMER1_VALUE),
525 .DATA(COUNTER_TIMER1_DATA)
526 ) counter_timer_1 (
527 // Wishbone Interface
528 .wb_clk_i(wb_clk_i),
529 .wb_rst_i(wb_rst_i),
530
531 .wb_adr_i(cpu_adr_o),
532 .wb_dat_i(cpu_dat_o),
533 .wb_sel_i(cpu_sel_o),
534 .wb_we_i(cpu_we_o),
535 .wb_cyc_i(cpu_cyc_o),
536
537 .wb_stb_i(counter_timer1_stb_i),
538 .wb_ack_o(counter_timer1_ack_o),
539 .wb_dat_o(counter_timer1_dat_o),
540 .irq(irq_counter_timer1)
541 );
542
shalanfd13eb52020-08-21 16:48:07 +0200543 // Wishbone Slave GPIO Registers
544 wire gpio_stb_i;
545 wire gpio_ack_o;
546 wire [31:0] gpio_dat_o;
547
548 gpio_wb #(
549 .BASE_ADR(GPIO_BASE_ADR),
550 .GPIO_DATA(GPIO_DATA),
551 .GPIO_ENA(GPIO_ENA),
552 .GPIO_PD(GPIO_PD),
553 .GPIO_PU(GPIO_PU)
554 ) gpio_wb (
555 .wb_clk_i(wb_clk_i),
556 .wb_rst_i(wb_rst_i),
shalanfd13eb52020-08-21 16:48:07 +0200557 .wb_adr_i(cpu_adr_o),
558 .wb_dat_i(cpu_dat_o),
559 .wb_sel_i(cpu_sel_o),
560 .wb_we_i(cpu_we_o),
561 .wb_cyc_i(cpu_cyc_o),
shalanfd13eb52020-08-21 16:48:07 +0200562 .wb_stb_i(gpio_stb_i),
563 .wb_ack_o(gpio_ack_o),
564 .wb_dat_o(gpio_dat_o),
565 .gpio_in_pad(gpio_in_pad),
shalanfd13eb52020-08-21 16:48:07 +0200566 .gpio(gpio),
567 .gpio_oeb(gpio_oeb),
568 .gpio_pu(gpio_pu),
569 .gpio_pd(gpio_pd)
570 );
571
shalanfd13eb52020-08-21 16:48:07 +0200572 // Wishbone Slave System Control Register
573 wire sys_stb_i;
574 wire sys_ack_o;
575 wire [31:0] sys_dat_o;
576
577 sysctrl_wb #(
578 .BASE_ADR(SYS_BASE_ADR),
shalanfd13eb52020-08-21 16:48:07 +0200579 .PLL_OUT(PLL_OUT),
580 .TRAP_OUT(TRAP_OUT),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400581 .IRQ7_SRC(IRQ7_SRC)
shalanfd13eb52020-08-21 16:48:07 +0200582 ) sysctrl (
583 .wb_clk_i(wb_clk_i),
584 .wb_rst_i(wb_rst_i),
585
586 .wb_adr_i(cpu_adr_o),
587 .wb_dat_i(cpu_dat_o),
588 .wb_sel_i(cpu_sel_o),
589 .wb_we_i(cpu_we_o),
590 .wb_cyc_i(cpu_cyc_o),
591
592 .wb_stb_i(sys_stb_i),
593 .wb_ack_o(sys_ack_o),
594 .wb_dat_o(sys_dat_o),
595
shalanfd13eb52020-08-21 16:48:07 +0200596 .pll_output_dest(pll_output_dest),
597 .trap_output_dest(trap_output_dest),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400598 .irq_7_inputsrc(irq_7_inputsrc)
shalanfd13eb52020-08-21 16:48:07 +0200599 );
600
601 // Logic Analyzer
602 wire la_stb_i;
603 wire la_ack_o;
604 wire [31:0] la_dat_o;
605
606 la_wb #(
607 .BASE_ADR(LA_BASE_ADR),
608 .LA_DATA_0(LA_DATA_0),
609 .LA_DATA_1(LA_DATA_1),
610 .LA_DATA_3(LA_DATA_3),
611 .LA_ENA_0(LA_ENA_0),
612 .LA_ENA_1(LA_ENA_1),
613 .LA_ENA_2(LA_ENA_2),
614 .LA_ENA_3(LA_ENA_3)
615 ) la (
616 .wb_clk_i(wb_clk_i),
617 .wb_rst_i(wb_rst_i),
618
619 .wb_adr_i(cpu_adr_o),
620 .wb_dat_i(cpu_dat_o),
621 .wb_sel_i(cpu_sel_o),
622 .wb_we_i(cpu_we_o),
623 .wb_cyc_i(cpu_cyc_o),
624
625 .wb_stb_i(la_stb_i),
626 .wb_ack_o(la_ack_o),
627 .wb_dat_o(la_dat_o),
628
629 .la_data(la_output),
shalan0d14e6e2020-08-31 16:50:48 +0200630 .la_data_in(la_input),
631 .la_oen(la_oen)
shalanfd13eb52020-08-21 16:48:07 +0200632 );
633
shalan0d14e6e2020-08-31 16:50:48 +0200634 // WB Slave Mega-Project Control
635 wire mprj_ctrl_stb_i;
636 wire mprj_ctrl_ack_o;
637 wire [31:0] mprj_ctrl_dat_o;
638
639 mprj_ctrl_wb #(
640 .BASE_ADR(MPRJ_CTRL_ADR),
641 .IO_PADS(MPRJ_IO_PADS),
Tim Edwardsc18c4742020-10-03 11:26:39 -0400642 .PWR_PADS(MPRJ_PWR_PADS)
shalan0d14e6e2020-08-31 16:50:48 +0200643 ) mprj_ctrl (
644 .wb_clk_i(wb_clk_i),
645 .wb_rst_i(wb_rst_i),
646
647 .wb_adr_i(cpu_adr_o),
648 .wb_dat_i(cpu_dat_o),
649 .wb_sel_i(cpu_sel_o),
650 .wb_we_i(cpu_we_o),
651 .wb_cyc_i(cpu_cyc_o),
652 .wb_stb_i(mprj_ctrl_stb_i),
653 .wb_ack_o(mprj_ctrl_ack_o),
654 .wb_dat_o(mprj_ctrl_dat_o),
655
Tim Edwards04ba17f2020-10-02 22:27:50 -0400656 .serial_clock(mprj_io_loader_clock),
657 .serial_resetn(mprj_io_loader_resetn),
658 .serial_data_out(mprj_io_loader_data),
Tim Edwards44bab472020-10-04 22:09:54 -0400659 // .mgmt_gpio_io(mgmt_io_data)
660 .mgmt_gpio_in(mgmt_in_data),
661 .mgmt_gpio_out(mgmt_out_data),
662 .mgmt_gpio_outz(mgmt_outz_data),
663 .mgmt_gpio_oeb(mgmt_oeb_data)
shalan0d14e6e2020-08-31 16:50:48 +0200664 );
665
shalanfd13eb52020-08-21 16:48:07 +0200666 // Wishbone Slave RAM
667 wire mem_stb_i;
668 wire mem_ack_o;
669 wire [31:0] mem_dat_o;
670
671 mem_wb #(
672 .MEM_WORDS(MEM_WORDS)
673 ) soc_mem (
674 .wb_clk_i(wb_clk_i),
675 .wb_rst_i(wb_rst_i),
676
677 .wb_adr_i(cpu_adr_o),
678 .wb_dat_i(cpu_dat_o),
679 .wb_sel_i(cpu_sel_o),
680 .wb_we_i(cpu_we_o),
681 .wb_cyc_i(cpu_cyc_o),
682
683 .wb_stb_i(mem_stb_i),
684 .wb_ack_o(mem_ack_o),
685 .wb_dat_o(mem_dat_o)
686 );
687
688 // Wishbone intercon logic
689 wb_intercon #(
690 .AW(ADR_WIDTH),
691 .DW(DAT_WIDTH),
692 .NS(NUM_SLAVES),
693 .ADR_MASK(ADR_MASK),
694 .SLAVE_ADR(SLAVE_ADR)
695 ) intercon (
696 // Master Interface
697 .wbm_adr_i(cpu_adr_o),
698 .wbm_stb_i(cpu_stb_o),
699 .wbm_dat_o(cpu_dat_i),
700 .wbm_ack_o(cpu_ack_i),
701
702 // Slaves Interface
Tim Edwards04ba17f2020-10-02 22:27:50 -0400703 .wbs_stb_o({ xbar_stb_o, sys_stb_i, spimemio_cfg_stb_i,
704 mprj_stb_o, mprj_ctrl_stb_i, la_stb_i,
705 spi_master_stb_i, counter_timer1_stb_i, counter_timer0_stb_i,
706 gpio_stb_i, uart_stb_i,
707 spimemio_flash_stb_i, mem_stb_i }),
708 .wbs_dat_i({ xbar_dat_i, sys_dat_o, spimemio_cfg_dat_o,
709 mprj_dat_i, mprj_ctrl_dat_o, la_dat_o,
710 spi_master_dat_o, counter_timer1_dat_o, counter_timer0_dat_o,
711 gpio_dat_o, uart_dat_o,
712 spimemio_flash_dat_o, mem_dat_o }),
713 .wbs_ack_i({ xbar_ack_i, sys_ack_o, spimemio_cfg_ack_o,
714 mprj_ack_i, mprj_ctrl_ack_o, la_ack_o,
715 spi_master_ack_o, counter_timer1_ack_o, counter_timer0_ack_o,
716 gpio_ack_o, uart_ack_o,
717 spimemio_flash_ack_o, mem_ack_o })
shalanfd13eb52020-08-21 16:48:07 +0200718 );
719
shalanfd13eb52020-08-21 16:48:07 +0200720endmodule
721
shalanfd13eb52020-08-21 16:48:07 +0200722// Implementation note:
723// Replace the following two modules with wrappers for your SRAM cells.
Tim Edwardsef8312e2020-09-22 17:20:06 -0400724
Tim Edwards04ba17f2020-10-02 22:27:50 -0400725module mgmt_soc_regs (
shalanfd13eb52020-08-21 16:48:07 +0200726 input clk, wen,
727 input [5:0] waddr,
728 input [5:0] raddr1,
729 input [5:0] raddr2,
730 input [31:0] wdata,
731 output [31:0] rdata1,
732 output [31:0] rdata2
733);
734 reg [31:0] regs [0:31];
735
736 always @(posedge clk)
737 if (wen) regs[waddr[4:0]] <= wdata;
738
739 assign rdata1 = regs[raddr1[4:0]];
740 assign rdata2 = regs[raddr2[4:0]];
741endmodule