| # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = |
| # Configuration file for running experiments |
| # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = |
| # timeout_each_job : FPGA Task script splits fpga flow into multiple jobs |
| # Each job execute fpga_flow script on combination of architecture & benchmark |
| # timeout_each_job is timeout for each job |
| # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = |
| |
| [GENERAL] |
| run_engine=openfpga_shell |
| power_analysis = false |
| spice_output=false |
| verilog_output=true |
| timeout_each_job = 20*60 |
| fpga_flow=vpr_blif |
| arch_variable_file=${PATH:TASK_DIR}/design_variables.yml |
| |
| |
| [OpenFPGA_SHELL] |
| openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga |
| openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml |
| openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml |
| external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml |
| openfpga_vpr_device_layout=12x12 |
| openfpga_vpr_route_chan_width=60 |
| |
| [ARCHITECTURES] |
| arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml |
| |
| [BENCHMARKS] |
| bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif |
| |
| [SYNTHESIS_PARAM] |
| bench0_top = top |
| bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act |
| bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v |
| |
| [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] |
| vpr_fpga_verilog_formal_verification_top_netlist= |
