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foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-001
/
slot-039
/
071773bb9a82e305753454321f9fa11d3c24bb23
commit
071773bb9a82e305753454321f9fa11d3c24bb23
[
log
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author
Ganesh Gore <goreganesh007@gmail.com>
Sun Dec 27 09:54:03 2020 -0700
committer
Ganesh Gore <goreganesh007@gmail.com>
Sun Dec 27 09:54:03 2020 -0700
tree
fd3a465bc7de96da54e6f86dedc24b10bfe601ac
parent
e7b736a9095ef3082356870509e22948fecb9aa2
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[LocalRun04] Bugfix on carrychain
OpenFPGA_task/arch/vpr_arch.xml
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checks/KlayoutMerge.log
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checks/caravel.magic.drc.mag
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checks/compare_caravel.txt
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checks/full_log.log
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checks/magic_drc.log
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checks/magic_extract.log
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checks/magic_merge_user_project_wrapper.log
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checks/manifest_check.mag.log
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checks/spdx_compliance_report.log
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gds/caravel.gds.gz
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gds/fpga_top_icv_in_design.gds.gz.sha1
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gds/user_project_wrapper.gds.gz
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source_commit_hash.txt
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verilog/OpenFPGA_Verilog/fabric_netlists.v
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verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v
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verilog/gl/caravel_sofa_chd_top.v
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verilog/gl/user_project_wrapper.v
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18 files changed
tree: fd3a465bc7de96da54e6f86dedc24b10bfe601ac
checks/
def/
doc/
gds/
lef/
macros/
mag/
maglef/
ngspice/
OpenFPGA_task/
openlane/
qflow/
scripts/
spi/
utils/
verilog/
info.yaml
LICENSE
Makefile
mpw-one-b.md
README.md
source_commit_hash.txt
README.md
Caravel-QLSOFA-HD
Highlights
Opensource 12x12 FPGA designed using OpenFPGA prototyping tool
Designed with Skywater130nm PDK with HD standard cell library + and
Custom Transmission Gate Cells
Base K4 architecture from VPR with
60 vertical and horizontal channels
Soft adder implementation
Designed using commercial PnR tool
Contribution
NOTE
This repository is created for The eFabless Open MPW shuttle program submission
The repository is auto-updated. For any commits issues and feature requests, please check
Skywater-OpenFPGA
Caravel design and CIIC Harness
For caravel related updated refer
efabless/caravel