commit 071773bb9a82e305753454321f9fa11d3c24bb23
author Ganesh Gore <goreganesh007@gmail.com> Sun Dec 27 09:54:03 2020 -0700
committer Ganesh Gore <goreganesh007@gmail.com> Sun Dec 27 09:54:03 2020 -0700
tree fd3a465bc7de96da54e6f86dedc24b10bfe601ac
parent e7b736a9095ef3082356870509e22948fecb9aa2

[LocalRun04] Bugfix on carrychain

OpenFPGA_task/arch/vpr_arch.xml

diff --git a/OpenFPGA_task/arch/vpr_arch.xml b/OpenFPGA_task/arch/vpr_arch.xml
index 07c6ba8..44db1ed 100644
--- a/OpenFPGA_task/arch/vpr_arch.xml
+++ b/OpenFPGA_task/arch/vpr_arch.xml
@@ -1,9 +1,9 @@
-<!-- 
+<!--
   Low-cost homogeneous FPGA Architecture.
 
   - Skywater 130 nm technology
-  - General purpose logic block: 
-    K = 4, N = 8, fracturable 4 LUTs (can operate as one 4-LUT or two 3-LUTs with all 3 inputs shared) 
+  - General purpose logic block:
+    K = 4, N = 8, fracturable 4 LUTs (can operate as one 4-LUT or two 3-LUTs with all 3 inputs shared)
     with optionally registered outputs
   - Routing architecture:
       - 10% L = 1, fc_in = 0.15, Fc_out = 0.10
@@ -14,13 +14,13 @@
   Authors: Xifan Tang
 -->
 <architecture>
-  <!-- 
-       ODIN II specific config begins 
-       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+  <!--
+       ODIN II specific config begins
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to
        ".model [type_of_block]") that this architecture supports.
 
-       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
-       already special structures in blif (.names, .input, .output, and .latch) 
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
+       already special structures in blif (.names, .input, .output, and .latch)
        that describe them.
   -->
   <models>
@@ -204,19 +204,19 @@
     </fixed_layout>
   </layout>
   <device>
-    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
 			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
 			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
-			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
-			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
 			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
-			     lined up with Stratix IV. 
+			     lined up with Stratix IV.
 			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
 			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
 			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
 	                     by 2.5x when looking up in Jeff's tables.
 			     The delay values are lined up with Stratix IV, which has an architecture similar to this
-			     proposed FPGA, and which is also 40 nm 
+			     proposed FPGA, and which is also 40 nm
 			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
 			     4x minimum drive strength buffer. -->
     <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
@@ -234,14 +234,14 @@
   <switchlist>
     <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
 	       book area formula. This means the mux transistors are about 5x minimum drive strength.
-	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
 	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
 	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
-	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified
 	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
-	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
 	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
-	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
 	       2.5x when looking up in Jeff's tables.
 	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
 	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
@@ -252,7 +252,7 @@
     <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
   </switchlist>
   <segmentlist>
-    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
 			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
 			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
     <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
@@ -286,8 +286,8 @@
            If you need to register the I/O, define clocks in the circuit models
            These clocks can be handled in back-end
        -->
-      <!-- A mode denotes the physical implementation of an I/O 
-           This mode will be not packable but is mainly used for fabric verilog generation   
+      <!-- A mode denotes the physical implementation of an I/O
+           This mode will be not packable but is mainly used for fabric verilog generation
         -->
       <mode name="physical" disabled_in_pack="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
@@ -306,7 +306,7 @@
 
       <!-- IOs can operate as either inputs or outputs.
 	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
-	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     the delays to and from registers in the I/O (and generally I/Os are registered
 	     today and that is when you timing analyze them.
 	     -->
       <mode name="inpad">
@@ -333,8 +333,8 @@
     </pb_type>
     <!-- Define I/O pads ends -->
     <!-- Define general purpose logic block (CLB) begin -->
-    <!-- -Due to the absence of local routing, 
-         the 4 inputs of fracturable LUT4 are no longer equivalent, 
+    <!-- -Due to the absence of local routing,
+         the 4 inputs of fracturable LUT4 are no longer equivalent,
          because the 4th input can not be switched when the dual-LUT3 modes are used.
          So pin equivalence should be applied to the first 3 inputs only
 	  -->
@@ -364,8 +364,8 @@
       <output name="sc_out" num_pins="1"/>
       <output name="cout" num_pins="1"/>
       <clock name="clk" num_pins="1"/>
-      <!-- Describe fracturable logic element.  
-             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+      <!-- Describe fracturable logic element.
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
              The outputs of the fracturable logic element can be optionally registered
         -->
       <pb_type name="fle" num_pb="8">
@@ -434,13 +434,15 @@
               <T_setup value="66e-12" port="ff.DI" clock="clk"/>
               <T_setup value="66e-12" port="ff.reset" clock="clk"/>
               <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>         
+            </pb_type>
             <interconnect>
               <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
-              <direct name="direct2" input="fabric.sc_in" output="ff[0].DI"/>
-              <direct name="direct3" input="ff[0].Q" output="ff[1].DI"/>
-              <direct name="direct4" input="ff[1].Q" output="fabric.sc_out"/>
-              <direct name="direct5" input="ff[1].Q" output="fabric.reg_out"/>
+              <direct name="direct2" input="fabric.cin" output="frac_logic.cin"/>
+              <direct name="direct3" input="fabric.sc_in" output="ff[0].DI"/>
+              <direct name="direct4" input="ff[0].Q" output="ff[1].DI"/>
+              <direct name="direct5" input="ff[1].Q" output="fabric.sc_out"/>
+              <direct name="direct6" input="ff[1].Q" output="fabric.reg_out"/>
+              <direct name="direct7" input="frac_logic.cout" output="fabric.cout"/>
               <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
               <complete name="complete2" input="fabric.reset" output="ff[1:0].reset"/>
               <mux name="mux1" input="frac_logic.out[0:0] fabric.reg_in" output="ff[0:0].D">
@@ -629,7 +631,7 @@
             <direct name="direct4" input="fle.clk" output="shift_reg.clk"/>
           </interconnect>
         </mode>
-        <!-- Define shift register end --> 
+        <!-- Define shift register end -->
       </pb_type>
       <interconnect>
         <!-- We use direct connections to reduce the area to the most
@@ -691,8 +693,8 @@
         </complete>
         <complete name="resets" input="clb.reset" output="fle[7:0].reset">
         </complete>
-        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
-               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
+               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
                then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
                naive specification).
           -->

checks/KlayoutMerge.log

diff --git a/checks/KlayoutMerge.log b/checks/KlayoutMerge.log
index 513a90d..7c2ebc2 100644
--- a/checks/KlayoutMerge.log
+++ b/checks/KlayoutMerge.log
@@ -1,2 +1 @@
 Placing module at (326.540000,1393.580000)
-removing cell user_proj_example

checks/caravel.magic.drc.mag

diff --git a/checks/caravel.magic.drc.mag b/checks/caravel.magic.drc.mag
index 14d8bc1..75e5924 100644
--- a/checks/caravel.magic.drc.mag
+++ b/checks/caravel.magic.drc.mag
@@ -1,7 +1,7 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1608507776
+timestamp 1609087257
 << checkpaint >>
 rect -3932 -3932 721532 1041532
 << metal1 >>
@@ -80930,7 +80930,7 @@
 transform 1 0 0 0 1 0
 box 0 0 717600 1037600
 use user_project_wrapper  mprj
-timestamp 1608507776
+timestamp 1609087257
 transform 1 0 65308 0 1 278716
 box -8576 -7506 592500 711442
 << properties >>

checks/compare_caravel.txt

diff --git a/checks/compare_caravel.txt b/checks/compare_caravel.txt
index 2ccd2d5..debb591 100644
--- a/checks/compare_caravel.txt
+++ b/checks/compare_caravel.txt
@@ -3,7 +3,7 @@
  .travisCI/travisBuild.sh                           |     28 -
  OpenFPGA_task/arch/fabric_key.xml                  |    678 +
  OpenFPGA_task/arch/openfpga_arch.xml               |    330 +
- OpenFPGA_task/arch/vpr_arch.xml                    |    737 +
+ OpenFPGA_task/arch/vpr_arch.xml                    |    739 +
  OpenFPGA_task/config/task.conf                     |     39 +
  OpenFPGA_task/config/task_generation.conf          |     39 +
  OpenFPGA_task/config/task_simulation.conf          |     33 +
@@ -26,42 +26,42 @@
  OpenFPGA_task/user_project_wrapper_empty.def       |   1219 +
  OpenFPGA_task/user_project_wrapper_template.def    |   3768 +
  README.md                                          |    158 +-
- checks/KlayoutMerge.log                            |      2 +
+ checks/KlayoutMerge.log                            |      1 +
  checks/caravel.magic.drc                           |    104 +
- checks/caravel.magic.drc.mag                       |  80938 ++++++++++
+ checks/caravel.magic.drc.mag                       |  80938 ++++++++
  checks/caravel.magic.namelist                      |      1 +
  checks/caravel.magic.rdb                           |     63 +
  checks/caravel.magic.typelist                      |      1 +
  checks/compare_caravel.txt                         |      0
- checks/full_log.log                                |     57 +
+ checks/full_log.log                                |     56 +
  checks/magic_drc.log                               |   5095 +
- checks/magic_extract.log                           |  20268 +++
+ checks/magic_extract.log                           |  10873 ++
  checks/magic_merge_user_project_wrapper.log        |   5250 +
  checks/manifest_check.mag.log                      |      2 +
  checks/manifest_check.maglef.log                   |     13 +
  checks/manifest_check.rtl.log                      |     37 +
  checks/mprj.magic.namelist                         |      1 +
  checks/mprj.magic.typelist                         |      1 +
- checks/spdx_compliance_report.log                  |    125 +
- gds/caravel.gds.gz                                 |    Bin 52991493 -> 59641419 bytes
+ checks/spdx_compliance_report.log                  |    123 +
+ gds/caravel.gds.gz                                 |    Bin 52991493 -> 57163768 bytes
  gds/user_proj_example.gds.gz                       |    Bin 742584 -> 0 bytes
- gds/user_project_wrapper.gds.gz                    |    Bin 6394035 -> 3561254 bytes
+ gds/user_project_wrapper.gds.gz                    |    Bin 6394035 -> 3559736 bytes
  gds/user_project_wrapper_empty.gds.gz              |    Bin 73084 -> 0 bytes
  info.yaml                                          |      6 +-
  mag/.magicrc                                       |     16 -
  qflow/digital_pll_controller/tech                  |      1 -
  qflow/ring_osc2x13/tech                            |      1 -
- source_commit_hash.txt                             |     14 +
+ source_commit_hash.txt                             |     17 +
  verilog/OpenFPGA_Verilog/InstancesMap.txt          |      1 +
  verilog/OpenFPGA_Verilog/define_simulation.v       |     18 +
  verilog/OpenFPGA_Verilog/fabric_netlists.v         |     72 +
- verilog/OpenFPGA_Verilog/fpga_core.v               |  49530 ++++++
+ verilog/OpenFPGA_Verilog/fpga_core.v               |  49530 +++++
  verilog/OpenFPGA_Verilog/fpga_defines.v            |     10 +
  verilog/OpenFPGA_Verilog/fpga_top.v                |  41442 +++++
  verilog/OpenFPGA_Verilog/lb/grid_clb.v             |    272 +
  .../lb/logical_tile_clb_mode_clb_.v                |    758 +
  .../lb/logical_tile_clb_mode_default__fle.v        |    173 +
- ...e_clb_mode_default__fle_mode_physical__fabric.v |    242 +
+ ...e_clb_mode_default__fle_mode_physical__fabric.v |    250 +
  ...t__fle_mode_physical__fabric_mode_default__ff.v |     61 +
  ...ode_physical__fabric_mode_default__frac_logic.v |    151 +
  ...ault__frac_logic_mode_default__carry_follower.v |     52 +
@@ -100,5 +100,6 @@
  .../sub_module/sky130_fd_sc_hd_wrapper.v           |     20 +
  verilog/OpenFPGA_Verilog/sub_module/wires.v        |     34 +
  verilog/OpenFPGA_Verilog/top_include_netlists.v    |     31 +
- verilog/gl/caravel_sofa_chd_top.v                  | 147104 ++++++++++++++++++
- 103 files changed, 377967 insertions(+), 268 deletions(-)
+ verilog/gl/caravel_sofa_chd_top.v                  | 173465 ++++++++++++++++++
+ verilog/gl/user_project_wrapper.v                  |    160 +-
+ 104 files changed, 395052 insertions(+), 318 deletions(-)

checks/full_log.log

diff --git a/checks/full_log.log b/checks/full_log.log
index 157ab24..8ac0c83 100644
--- a/checks/full_log.log
+++ b/checks/full_log.log
@@ -5,8 +5,8 @@
 {{LICENSE COMPLIANCE PASSED}} Apache-2.0 LICENSE file was found in project root
  No third party libraries found.
 Step 1 done without fatal errors.
-{{SPDX COMPLIANCE WARNING}} Found 123 non-compliant files with the SPDX Standard. Check full log for more information
-SPDX COMPLIANCE: NON-COMPLIANT FILES PREVIEW: ['/usr/local/workspace/Caravel-SOFA-CHD/README.md', '/usr/local/workspace/Caravel-SOFA-CHD/source_commit_hash.txt', '/usr/local/workspace/Caravel-SOFA-CHD/doc/caravel_datasheet.ps', '/usr/local/workspace/Caravel-SOFA-CHD/mag/clamp_list.txt', '/usr/local/workspace/Caravel-SOFA-CHD/mag/.magicrc', '/usr/local/workspace/Caravel-SOFA-CHD/maglef/.magicrc', '/usr/local/workspace/Caravel-SOFA-CHD/openlane/chip_dimensions.txt', '/usr/local/workspace/Caravel-SOFA-CHD/openlane/mgmt_protect/pdn.tcl', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/DFFRAM.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/chip_io.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/digital_pll.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/gpio_control_block.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/simple_por.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/storage.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/user_id_programming.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/mgmt_core.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/mgmt_protect.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/mgmt_protect_hv.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/mprj2_logic_high.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/mprj_logic_high.spice']
+{{SPDX COMPLIANCE WARNING}} Found 121 non-compliant files with the SPDX Standard. Check full log for more information
+SPDX COMPLIANCE: NON-COMPLIANT FILES PREVIEW: ['/usr/local/workspace/Caravel-SOFA-CHD/README.md', '/usr/local/workspace/Caravel-SOFA-CHD/source_commit_hash.txt', '/usr/local/workspace/Caravel-SOFA-CHD/doc/caravel_datasheet.ps', '/usr/local/workspace/Caravel-SOFA-CHD/mag/clamp_list.txt', '/usr/local/workspace/Caravel-SOFA-CHD/openlane/chip_dimensions.txt', '/usr/local/workspace/Caravel-SOFA-CHD/openlane/mgmt_protect/pdn.tcl', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/DFFRAM.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/chip_io.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/digital_pll.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/gpio_control_block.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/simple_por.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/storage.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/user_id_programming.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/mgmt_core.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/mgmt_protect.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/mgmt_protect_hv.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/mprj2_logic_high.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/mprj_logic_high.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.spice', '/usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/user_proj_example.spice']
  Executing Step 2 of 4: Checking YAML description.
  YAML file valid!
 Step 2 done without fatal errors.
@@ -23,8 +23,7 @@
 b'Removing manifest'
 b'Fetching manifest'
 b'Running sha1sum checks'
- Manifest Checks Failed. Please rebase your Repository to the latest Caravel master.
-.magicrc: FAILED
+ Nothing Happened
  Documentation Checks Passed.
  Makefile Checks Passed.
 instance caravel found
@@ -35,9 +34,9 @@
  Basic Hierarchy Checks Passed.
  Running Magic Extractions From GDS...
 user wrapper cell names differences: 
-['mprj']
+['fpga_top_uut']
 user wrapper cell type differences: 
-['user_proj_example']
+['fpga_top']
 toplevel cell names differences: 
 ['user_project_wrapper_0', 'mprj']
 toplevel cell type differences: 

checks/magic_drc.log

diff --git a/checks/magic_drc.log b/checks/magic_drc.log
index f6d353d..14e02e0 100644
--- a/checks/magic_drc.log
+++ b/checks/magic_drc.log
@@ -31,24 +31,24 @@
 Reading "$$M2M3_PR".
 Reading "$$M1M2_PR".
 Reading "$$M4M5_PR_16000_16000_2_1".
-Reading "sky130_fd_sc_hd__fill_2".
-Reading "sky130_fd_sc_hd__fill_8".
 Reading "sky130_fd_sc_hd__fill_4".
+Reading "sky130_fd_sc_hd__fill_8".
 Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__fill_2".
 Reading "sky130_fd_sc_hd__buf_1".
 Error while reading cell "sky130_fd_sc_hd__buf_1" (byte position 8706): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__clkbuf_1".
 Error while reading cell "sky130_fd_sc_hd__clkbuf_1" (byte position 12678): Unknown layer/datatype in boundary, layer=236 type=0
-Reading "sky130_fd_sc_hd__buf_6".
-Error while reading cell "sky130_fd_sc_hd__buf_6" (byte position 16488): Unknown layer/datatype in boundary, layer=236 type=0
-Reading "sky130_fd_sc_hd__bufbuf_16".
-Error while reading cell "sky130_fd_sc_hd__bufbuf_16" (byte position 23530): Unknown layer/datatype in boundary, layer=236 type=0
-Reading "sky130_fd_sc_hd__buf_4".
-Error while reading cell "sky130_fd_sc_hd__buf_4" (byte position 41792): Unknown layer/datatype in boundary, layer=236 type=0
-Reading "sky130_fd_sc_hd__buf_8".
-Error while reading cell "sky130_fd_sc_hd__buf_8" (byte position 47200): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__buf_2".
-Error while reading cell "sky130_fd_sc_hd__buf_2" (byte position 56092): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__buf_2" (byte position 16488): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__buf_6".
+Error while reading cell "sky130_fd_sc_hd__buf_6" (byte position 20984): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__bufbuf_16".
+Error while reading cell "sky130_fd_sc_hd__bufbuf_16" (byte position 28026): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__buf_4".
+Error while reading cell "sky130_fd_sc_hd__buf_4" (byte position 46288): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__buf_8".
+Error while reading cell "sky130_fd_sc_hd__buf_8" (byte position 51696): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__dfrtp_1".
 Error while reading cell "sky130_fd_sc_hd__dfrtp_1" (byte position 60590): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_uuopenfpga_cc_hd_invmux3_1".
@@ -64,12 +64,12 @@
 Error while reading cell "sky130_fd_sc_hd__sdfrtp_1" (byte position 105652): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__mux2_1".
 Error while reading cell "sky130_fd_sc_hd__mux2_1" (byte position 124542): Unknown layer/datatype in boundary, layer=236 type=0
-Reading "sky130_fd_sc_hd__or2_0".
-Error while reading cell "sky130_fd_sc_hd__or2_0" (byte position 131430): Unknown layer/datatype in boundary, layer=236 type=0
-Reading "sky130_fd_sc_hd__inv_8".
-Error while reading cell "sky130_fd_sc_hd__inv_8" (byte position 135384): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__inv_2".
-Error while reading cell "sky130_fd_sc_hd__inv_2" (byte position 142944): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__inv_2" (byte position 131430): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__or2_0".
+Error while reading cell "sky130_fd_sc_hd__or2_0" (byte position 135238): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__inv_8".
+Error while reading cell "sky130_fd_sc_hd__inv_8" (byte position 139192): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__dlygate4sd1_1".
 Error while reading cell "sky130_fd_sc_hd__dlygate4sd1_1" (byte position 146760): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__dlygate4sd3_1".
@@ -179,7 +179,7 @@
     9700 uses
     9800 uses
 Reading "sky130_fd_sc_hd__mux2_2".
-Error while reading cell "sky130_fd_sc_hd__mux2_2" (byte position 923982): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__mux2_2" (byte position 910382): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sb_0__0_".
     100 uses
     200 uses
@@ -227,7 +227,7 @@
     4400 uses
     4500 uses
 Reading "sky130_fd_sc_hd__dlygate4sd2_1".
-Error while reading cell "sky130_fd_sc_hd__dlygate4sd2_1" (byte position 1285714): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__dlygate4sd2_1" (byte position 1272114): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_uuopenfpga_cc_hd_invmux2_1".
 Reading "sb_0__1_".
     100 uses
@@ -325,7 +325,7 @@
     9300 uses
     9400 uses
 Reading "sky130_fd_sc_hd__inv_6".
-Error while reading cell "sky130_fd_sc_hd__inv_6" (byte position 2078114): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__inv_6" (byte position 2064514): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sb_0__2_".
     100 uses
     200 uses
@@ -644,7 +644,7 @@
     15700 uses
     15800 uses
 Reading "sky130_fd_sc_hd__bufbuf_8".
-Error while reading cell "sky130_fd_sc_hd__bufbuf_8" (byte position 4743568): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__bufbuf_8" (byte position 4729968): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sb_1__2_".
     100 uses
     200 uses
@@ -990,13 +990,13 @@
     6300 uses
     6400 uses
 Reading "sky130_fd_sc_hd__inv_4".
-Error while reading cell "sky130_fd_sc_hd__inv_4" (byte position 7506942): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__inv_4" (byte position 7493342): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__ebufn_4".
-Error while reading cell "sky130_fd_sc_hd__ebufn_4" (byte position 7511994): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__ebufn_4" (byte position 7498394): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__nand2b_1".
-Error while reading cell "sky130_fd_sc_hd__nand2b_1" (byte position 7521504): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__nand2b_1" (byte position 7507904): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__or2b_4".
-Error while reading cell "sky130_fd_sc_hd__or2b_4" (byte position 7526096): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__or2b_4" (byte position 7512496): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "cbx_1__0_".
     100 uses
     200 uses

checks/magic_extract.log

diff --git a/checks/magic_extract.log b/checks/magic_extract.log
index 116c085..d349222 100644
--- a/checks/magic_extract.log
+++ b/checks/magic_extract.log
@@ -323,8 +323,8 @@
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808360".
 Reading "sky130_fd_pr__pfet_01v8__example_55959141808361".
 Reading "sky130_fd_io__nfet_con_diff_wo_abt_270v2".
-Error while reading cell "sky130_fd_io__nfet_con_diff_wo_abt_270v2" (byte position 1223032): Unknown layer/datatype in boundary, layer=81 type=6
-Error while reading cell "sky130_fd_io__nfet_con_diff_wo_abt_270v2" (byte position 1224824): Unknown layer/datatype in boundary, layer=81 type=8
+Error while reading cell "sky130_fd_io__nfet_con_diff_wo_abt_270v2" (byte position 1223190): Unknown layer/datatype in boundary, layer=81 type=6
+Error while reading cell "sky130_fd_io__nfet_con_diff_wo_abt_270v2" (byte position 1224982): Unknown layer/datatype in boundary, layer=81 type=8
 Reading "sky130_fd_pr__pfet_01v8__example_55959141808656".
 Reading "sky130_fd_pr__pfet_01v8__example_55959141808654".
 Reading "sky130_fd_io__pfet_con_diff_wo_abt_270v2".
@@ -461,10 +461,10 @@
 Reading "sky130_fd_io__com_pudrvr_weakv2".
 Error while reading cell "sky130_fd_io__com_pudrvr_weakv2" (byte position 2581436): Unknown layer/datatype in boundary, layer=81 type=6
 Reading "sky130_fd_io__gpio_pddrvr_weakv2".
-Error while reading cell "sky130_fd_io__gpio_pddrvr_weakv2" (byte position 2643044): Unknown layer/datatype in boundary, layer=81 type=6
+Error while reading cell "sky130_fd_io__gpio_pddrvr_weakv2" (byte position 2643108): Unknown layer/datatype in boundary, layer=81 type=6
 Reading "sky130_fd_io__gpio_pudrvr_strongv2".
 Reading "sky130_fd_io__gpio_pddrvr_strong_slowv2".
-Error while reading cell "sky130_fd_io__gpio_pddrvr_strong_slowv2" (byte position 2989798): Unknown layer/datatype in boundary, layer=81 type=6
+Error while reading cell "sky130_fd_io__gpio_pddrvr_strong_slowv2" (byte position 2989862): Unknown layer/datatype in boundary, layer=81 type=6
 Reading "sky130_fd_io__tk_em1s_cdns_5595914180852".
 Reading "sky130_fd_pr__res_generic_po__example_5595914180853".
 Error while reading cell "sky130_fd_pr__res_generic_po__example_5595914180853" (byte position 2991204): Unknown layer/datatype in boundary, layer=66 type=14
@@ -554,7 +554,7 @@
 Reading "sky130_fd_io__hvsbt_inv_x4".
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808555".
 Reading "sky130_fd_io__signal_5_sym_hv_local_5term".
-Error while reading cell "sky130_fd_io__signal_5_sym_hv_local_5term" (byte position 5033274): Unknown layer/datatype in boundary, layer=81 type=19
+Error while reading cell "sky130_fd_io__signal_5_sym_hv_local_5term" (byte position 5033376): Unknown layer/datatype in boundary, layer=81 type=19
 Error while reading cell "sky130_fd_io__signal_5_sym_hv_local_5term" (byte position 5033664): Unknown layer/datatype in boundary, layer=66 type=9
 Reading "sky130_fd_pr__padplhp__example_559591418080".
 Error while reading cell "sky130_fd_pr__padplhp__example_559591418080" (byte position 5034608): Unknown layer/datatype in boundary, layer=81 type=20
@@ -627,7 +627,7 @@
 Reading "sky130_fd_pr__tpl1__example_55959141808685".
 Reading "sky130_fd_pr__tpl1__example_55959141808686".
 Reading "sky130_fd_io__amux_switch_1v2b".
-Error while reading cell "sky130_fd_io__amux_switch_1v2b" (byte position 5458186): Unknown layer/datatype in boundary, layer=81 type=6
+Error while reading cell "sky130_fd_io__amux_switch_1v2b" (byte position 5458918): Unknown layer/datatype in boundary, layer=81 type=6
 Reading "sky130_fd_io__gpiov2_amux_ctl_logic".
 Reading "sky130_fd_pr__pfet_01v8__example_55959141808591".
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808592".
@@ -635,7 +635,7 @@
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808594".
 Reading "sky130_fd_io__gpiov2_ibuf_se".
 Reading "sky130_fd_io__gpiov2_buf_localesd".
-Error while reading cell "sky130_fd_io__gpiov2_buf_localesd" (byte position 5598650): Unknown layer/datatype in boundary, layer=81 type=6
+Error while reading cell "sky130_fd_io__gpiov2_buf_localesd" (byte position 5598986): Unknown layer/datatype in boundary, layer=81 type=6
 Reading "sky130_fd_io__gpiov2_ictl_logic".
 CIF file read warning: Input off lambda grid by 2/5; snapped to grid.
 Reading "sky130_fd_io__com_ctl_hldv2".
@@ -643,8 +643,8 @@
 Reading "sky130_fd_io__gpiov2_octl_dat".
 Reading "sky130_fd_io__gpio_odrvrv2".
 Reading "sky130_fd_io__res75only_small".
-Error while reading cell "sky130_fd_io__res75only_small" (byte position 5927464): Unknown layer/datatype in boundary, layer=66 type=14
-Error while reading cell "sky130_fd_io__res75only_small" (byte position 5927528): Unknown layer/datatype in boundary, layer=81 type=19
+Error while reading cell "sky130_fd_io__res75only_small" (byte position 5927592): Unknown layer/datatype in boundary, layer=66 type=14
+Error while reading cell "sky130_fd_io__res75only_small" (byte position 5927656): Unknown layer/datatype in boundary, layer=81 type=19
 Reading "sky130_fd_io__com_bus_slice_m4".
 Reading "sky130_fd_io__top_gpio_pad".
 Reading "sky130_fd_io__pad_esd".
@@ -907,44 +907,44 @@
 Reading "pnand2_1".
 Reading "contact_32".
 Reading "contact_33".
-Reading "sky130_fd_sc_hd__bufbuf_8".
-Error while reading cell "sky130_fd_sc_hd__bufbuf_8" (byte position 11986942): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__or2b_4".
-Error while reading cell "sky130_fd_sc_hd__or2b_4" (byte position 12007372): Unknown layer/datatype in boundary, layer=236 type=0
-Reading "sky130_fd_sc_hd__inv_6".
-Error while reading cell "sky130_fd_sc_hd__inv_6" (byte position 12025322): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__or2b_4" (byte position 11958072): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__nand2b_1".
-Error while reading cell "sky130_fd_sc_hd__nand2b_1" (byte position 12039016): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__nand2b_1" (byte position 11964222): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__bufbuf_8".
+Error while reading cell "sky130_fd_sc_hd__bufbuf_8" (byte position 11970412): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__inv_6".
+Error while reading cell "sky130_fd_sc_hd__inv_6" (byte position 11979514): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_uuopenfpga_cc_hd_invmux2_1".
 Reading "sky130_fd_sc_hd__dlygate4sd2_1".
-Error while reading cell "sky130_fd_sc_hd__dlygate4sd2_1" (byte position 12083624): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__dlygate4sd2_1" (byte position 11995052): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__mux2_2".
-Error while reading cell "sky130_fd_sc_hd__mux2_2" (byte position 12105296): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__mux2_2" (byte position 12001234): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__dlygate4sd3_1".
-Error while reading cell "sky130_fd_sc_hd__dlygate4sd3_1" (byte position 12123164): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__dlygate4sd3_1" (byte position 12008000): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__dlygate4sd1_1".
-Error while reading cell "sky130_fd_sc_hd__dlygate4sd1_1" (byte position 12139478): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__dlygate4sd1_1" (byte position 12014176): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__or2_0".
-Error while reading cell "sky130_fd_sc_hd__or2_0" (byte position 12151260): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__or2_0" (byte position 12019034): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__mux2_1".
-Error while reading cell "sky130_fd_sc_hd__mux2_1" (byte position 12171846): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__mux2_1" (byte position 12024026): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__sdfrtp_1".
-Error while reading cell "sky130_fd_sc_hd__sdfrtp_1" (byte position 12228434): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__sdfrtp_1" (byte position 12036692): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__nand2_1".
-Error while reading cell "sky130_fd_sc_hd__nand2_1" (byte position 12240212): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__nand2_1" (byte position 12048554): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__nor2_1".
-Error while reading cell "sky130_fd_sc_hd__nor2_1" (byte position 12251132): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__nor2_1" (byte position 12052550): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_uuopenfpga_cc_hd_invmux3_1".
 Reading "sky130_fd_sc_hd__dfrtp_1".
-Error while reading cell "sky130_fd_sc_hd__dfrtp_1" (byte position 12341046): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__dfrtp_1" (byte position 12076012): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__bufbuf_16".
-Error while reading cell "sky130_fd_sc_hd__bufbuf_16" (byte position 12395756): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__bufbuf_16" (byte position 12089814): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__buf_6".
-Error while reading cell "sky130_fd_sc_hd__buf_6" (byte position 12416790): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__buf_6" (byte position 12105316): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__buf_1".
-Error while reading cell "sky130_fd_sc_hd__buf_1" (byte position 12428614): Unknown layer/datatype in boundary, layer=236 type=0
-Reading "sky130_fd_sc_hd__fill_4".
+Error while reading cell "sky130_fd_sc_hd__buf_1" (byte position 12111726): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__fill_8".
+Reading "sky130_fd_sc_hd__fill_4".
 Reading "$$M4M5_PR_16000_16000_2_1".
 Reading "$$M1M2_PR".
 Reading "$$M2M3_PR".
@@ -956,15 +956,15 @@
 Reading "sky130_fd_io__hvc_clampv2".
     100 uses
 Reading "sky130_fd_pr__res_bent_po__example_55959141808692".
-Error while reading cell "sky130_fd_pr__res_bent_po__example_55959141808692" (byte position 17412968): Unknown layer/datatype in boundary, layer=66 type=14
+Error while reading cell "sky130_fd_pr__res_bent_po__example_55959141808692" (byte position 17087516): Unknown layer/datatype in boundary, layer=66 type=14
 Reading "sky130_fd_pr__res_bent_po__example_55959141808689".
-Error while reading cell "sky130_fd_pr__res_bent_po__example_55959141808689" (byte position 17416202): Unknown layer/datatype in boundary, layer=66 type=14
+Error while reading cell "sky130_fd_pr__res_bent_po__example_55959141808689" (byte position 17090750): Unknown layer/datatype in boundary, layer=66 type=14
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808701".
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808703".
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808704".
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808695".
 Reading "sky130_fd_pr__res_bent_po__example_55959141808688".
-Error while reading cell "sky130_fd_pr__res_bent_po__example_55959141808688" (byte position 17472632): Unknown layer/datatype in boundary, layer=66 type=14
+Error while reading cell "sky130_fd_pr__res_bent_po__example_55959141808688" (byte position 17147180): Unknown layer/datatype in boundary, layer=66 type=14
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808699".
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808696".
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808698".
@@ -974,18 +974,18 @@
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808705".
 Reading "sky130_fd_pr__dfl1__example_55959141808682".
 Reading "sky130_fd_pr__res_bent_po__example_55959141808690".
-Error while reading cell "sky130_fd_pr__res_bent_po__example_55959141808690" (byte position 17525444): Unknown layer/datatype in boundary, layer=66 type=14
+Error while reading cell "sky130_fd_pr__res_bent_po__example_55959141808690" (byte position 17199992): Unknown layer/datatype in boundary, layer=66 type=14
 Reading "sky130_fd_pr__res_bent_po__example_55959141808691".
-Error while reading cell "sky130_fd_pr__res_bent_po__example_55959141808691" (byte position 17529190): Unknown layer/datatype in boundary, layer=66 type=14
+Error while reading cell "sky130_fd_pr__res_bent_po__example_55959141808691" (byte position 17203738): Unknown layer/datatype in boundary, layer=66 type=14
 Reading "sky130_fd_pr__pfet_01v8__example_55959141808687".
 Reading "sky130_fd_io__gnd2gnd_120x2_lv_isosub".
-Error while reading cell "sky130_fd_io__gnd2gnd_120x2_lv_isosub" (byte position 17536512): Unknown layer/datatype in boundary, layer=81 type=19
+Error while reading cell "sky130_fd_io__gnd2gnd_120x2_lv_isosub" (byte position 17211846): Unknown layer/datatype in boundary, layer=81 type=19
 Reading "sky130_fd_io__top_gpiov2".
 Reading "sky130_fd_io__overlay_gpiov2".
 Reading "sky130_fd_pr__res_bent_po__example_55959141808768".
-Error while reading cell "sky130_fd_pr__res_bent_po__example_55959141808768" (byte position 19485704): Unknown layer/datatype in boundary, layer=66 type=14
+Error while reading cell "sky130_fd_pr__res_bent_po__example_55959141808768" (byte position 19160252): Unknown layer/datatype in boundary, layer=66 type=14
 Reading "sky130_fd_pr__res_bent_nd__example_55959141808769".
-Error while reading cell "sky130_fd_pr__res_bent_nd__example_55959141808769" (byte position 19488482): Unknown layer/datatype in boundary, layer=65 type=14
+Error while reading cell "sky130_fd_pr__res_bent_nd__example_55959141808769" (byte position 19163030): Unknown layer/datatype in boundary, layer=65 type=14
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808770".
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808771".
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808772".
@@ -1004,13 +1004,13 @@
 Reading "sky130_fd_pr__pfet_01v8__example_55959141808786".
 Reading "sky130_fd_pr__pfet_01v8__example_55959141808787".
 Reading "sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2".
-Error while reading cell "sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2" (byte position 20312960): Unknown layer/datatype in boundary, layer=81 type=6
-Error while reading cell "sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2" (byte position 20314752): Unknown layer/datatype in boundary, layer=81 type=8
+Error while reading cell "sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2" (byte position 19987572): Unknown layer/datatype in boundary, layer=81 type=6
+Error while reading cell "sky130_fd_io__nfet_con_diff_wo_abt_270_xres4v2" (byte position 19989364): Unknown layer/datatype in boundary, layer=81 type=8
 Reading "sky130_fd_io__xres_p_em1c_cdns_55959141808753".
 Reading "sky130_fd_pr__res_generic_nd__example_55959141808754".
-Error while reading cell "sky130_fd_pr__res_generic_nd__example_55959141808754" (byte position 20317884): Unknown layer/datatype in boundary, layer=65 type=14
+Error while reading cell "sky130_fd_pr__res_generic_nd__example_55959141808754" (byte position 19992432): Unknown layer/datatype in boundary, layer=65 type=14
 Reading "sky130_fd_pr__res_generic_nd__example_55959141808755".
-Error while reading cell "sky130_fd_pr__res_generic_nd__example_55959141808755" (byte position 20318506): Unknown layer/datatype in boundary, layer=65 type=14
+Error while reading cell "sky130_fd_pr__res_generic_nd__example_55959141808755" (byte position 19993054): Unknown layer/datatype in boundary, layer=65 type=14
 Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808756".
 Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808757".
 Reading "sky130_fd_io__xres_tk_p_em1o_cdns_55959141808758".
@@ -1044,8 +1044,8 @@
 Reading "sky130_fd_pr__via_l1m1__example_55959141808751".
 Reading "sky130_fd_pr__via_l1m1__example_55959141808752".
 Reading "sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2".
-Error while reading cell "sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2" (byte position 21203842): Unknown layer/datatype in boundary, layer=81 type=6
-Error while reading cell "sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2" (byte position 21205634): Unknown layer/datatype in boundary, layer=81 type=8
+Error while reading cell "sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2" (byte position 20878390): Unknown layer/datatype in boundary, layer=81 type=6
+Error while reading cell "sky130_fd_io__pfet_con_diff_wo_abt_270_xres4v2" (byte position 20880182): Unknown layer/datatype in boundary, layer=81 type=8
 Reading "sky130_fd_pr__via_m1m2__example_55959141808551".
 Reading "sky130_fd_pr__via_m1m2__example_55959141808552".
 Reading "sky130_fd_pr__via_m1m2__example_55959141808724".
@@ -1057,7 +1057,7 @@
 Reading "sky130_fd_pr__via_m1m2__example_55959141808727".
 Reading "sky130_fd_pr__via_m1m2__example_55959141808728".
 Reading "sky130_fd_pr__res_bent_po__example_55959141808715".
-Error while reading cell "sky130_fd_pr__res_bent_po__example_55959141808715" (byte position 21219160): Unknown layer/datatype in boundary, layer=66 type=14
+Error while reading cell "sky130_fd_pr__res_bent_po__example_55959141808715" (byte position 20893708): Unknown layer/datatype in boundary, layer=66 type=14
 Reading "sky130_fd_pr__pfet_01v8__example_55959141808716".
 Reading "sky130_fd_pr__pfet_01v8__example_55959141808718".
 Reading "sky130_fd_pr__pfet_01v8__example_55959141808720".
@@ -1065,21 +1065,21 @@
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808722".
 Reading "sky130_fd_pr__nfet_01v8__example_55959141808723".
 Reading "sky130_fd_sc_hd__inv_8".
-Error while reading cell "sky130_fd_sc_hd__inv_8" (byte position 21255516): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__inv_8" (byte position 20904484): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__ebufn_4".
-Error while reading cell "sky130_fd_sc_hd__ebufn_4" (byte position 21293362): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__ebufn_4" (byte position 20920978): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__inv_1".
-Error while reading cell "sky130_fd_sc_hd__inv_1" (byte position 21307446): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__inv_1" (byte position 20937010): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__clkbuf_8".
-Error while reading cell "sky130_fd_sc_hd__clkbuf_8" (byte position 21338574): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__clkbuf_8" (byte position 20946350): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__inv_4".
-Error while reading cell "sky130_fd_sc_hd__inv_4" (byte position 21358642): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__inv_4" (byte position 20960118): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__clkinv_1".
-Error while reading cell "sky130_fd_sc_hd__clkinv_1" (byte position 21373850): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__clkinv_1" (byte position 20969546): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__buf_4".
-Error while reading cell "sky130_fd_sc_hd__buf_4" (byte position 21395350): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__buf_4" (byte position 20978258): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__buf_8".
-Error while reading cell "sky130_fd_sc_hd__buf_8" (byte position 21430786): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__buf_8" (byte position 20990506): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "bank".
     100 uses
     200 uses
@@ -1095,11 +1095,11 @@
     300 uses
     400 uses
 Reading "control_logic_r".
-Error while reading cell "control_logic_r" (byte position 22629414): Warning:  Cell control_logic_r boundary was redefined.
-Error while reading cell "control_logic_r" (byte position 22629414): Warning:  Cell control_logic_r boundary was redefined.
-Error while reading cell "control_logic_r" (byte position 22629414): Warning:  Cell control_logic_r boundary was redefined.
-Error while reading cell "control_logic_r" (byte position 22629414): Warning:  Cell control_logic_r boundary was redefined.
-Error while reading cell "control_logic_r" (byte position 22629414): Warning:  Cell control_logic_r boundary was redefined.
+Error while reading cell "control_logic_r" (byte position 22201486): Warning:  Cell control_logic_r boundary was redefined.
+Error while reading cell "control_logic_r" (byte position 22201486): Warning:  Cell control_logic_r boundary was redefined.
+Error while reading cell "control_logic_r" (byte position 22201486): Warning:  Cell control_logic_r boundary was redefined.
+Error while reading cell "control_logic_r" (byte position 22201486): Warning:  Cell control_logic_r boundary was redefined.
+Error while reading cell "control_logic_r" (byte position 22201486): Warning:  Cell control_logic_r boundary was redefined.
 Reading "cr_3".
 Reading "control_logic_rw".
     100 uses
@@ -1108,13 +1108,13 @@
 Reading "row_addr_dff".
 Reading "contact_34".
 Reading "sky130_fd_sc_hd__clkbuf_1".
-Error while reading cell "sky130_fd_sc_hd__clkbuf_1" (byte position 22675682): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__clkbuf_1" (byte position 22236042): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__inv_2".
-Error while reading cell "sky130_fd_sc_hd__inv_2" (byte position 22690782): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__inv_2" (byte position 22243122): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__buf_2".
-Error while reading cell "sky130_fd_sc_hd__buf_2" (byte position 22708634): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__buf_2" (byte position 22251306): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__conb_1".
-Error while reading cell "sky130_fd_sc_hd__conb_1" (byte position 22721448): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__conb_1" (byte position 22260036): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__fill_1".
 Reading "sky130_fd_sc_hd__fill_2".
 Reading "$$M1M2_PR_3200_3200_1_9".
@@ -1125,7 +1125,176 @@
 Reading "$$M4M5_PR_16000_16000_1_7".
 Reading "$$M4M5_PR_16000_16000_2_7".
 Reading "$$M2M3_PR_C".
-Reading "sb_2__2_".
+Reading "cby_2__1_".
+    100 uses
+    200 uses
+    300 uses
+    400 uses
+    500 uses
+    600 uses
+    700 uses
+    800 uses
+    900 uses
+    1000 uses
+    1100 uses
+    1200 uses
+    1300 uses
+    1400 uses
+    1500 uses
+    1600 uses
+    1700 uses
+    1800 uses
+    1900 uses
+    2000 uses
+    2100 uses
+    2200 uses
+    2300 uses
+    2400 uses
+    2500 uses
+    2600 uses
+    2700 uses
+    2800 uses
+    2900 uses
+    3000 uses
+    3100 uses
+    3200 uses
+    3300 uses
+    3400 uses
+    3500 uses
+    3600 uses
+    3700 uses
+    3800 uses
+    3900 uses
+    4000 uses
+    4100 uses
+    4200 uses
+    4300 uses
+    4400 uses
+    4500 uses
+    4600 uses
+    4700 uses
+    4800 uses
+    4900 uses
+    5000 uses
+    5100 uses
+    5200 uses
+    5300 uses
+    5400 uses
+    5500 uses
+    5600 uses
+    5700 uses
+    5800 uses
+    5900 uses
+    6000 uses
+    6100 uses
+    6200 uses
+    6300 uses
+    6400 uses
+    6500 uses
+    6600 uses
+    6700 uses
+    6800 uses
+    6900 uses
+    7000 uses
+    7100 uses
+    7200 uses
+    7300 uses
+    7400 uses
+Reading "cby_1__1_".
+    100 uses
+    200 uses
+    300 uses
+    400 uses
+    500 uses
+    600 uses
+    700 uses
+    800 uses
+    900 uses
+    1000 uses
+    1100 uses
+    1200 uses
+    1300 uses
+    1400 uses
+    1500 uses
+    1600 uses
+    1700 uses
+    1800 uses
+    1900 uses
+    2000 uses
+    2100 uses
+    2200 uses
+    2300 uses
+    2400 uses
+    2500 uses
+    2600 uses
+    2700 uses
+    2800 uses
+    2900 uses
+    3000 uses
+    3100 uses
+    3200 uses
+    3300 uses
+    3400 uses
+    3500 uses
+    3600 uses
+    3700 uses
+    3800 uses
+    3900 uses
+    4000 uses
+    4100 uses
+    4200 uses
+    4300 uses
+    4400 uses
+    4500 uses
+    4600 uses
+    4700 uses
+    4800 uses
+    4900 uses
+    5000 uses
+    5100 uses
+    5200 uses
+    5300 uses
+    5400 uses
+    5500 uses
+    5600 uses
+    5700 uses
+    5800 uses
+    5900 uses
+    6000 uses
+    6100 uses
+    6200 uses
+    6300 uses
+    6400 uses
+    6500 uses
+    6600 uses
+    6700 uses
+    6800 uses
+    6900 uses
+    7000 uses
+Reading "cby_0__1_".
+    100 uses
+    200 uses
+    300 uses
+    400 uses
+    500 uses
+    600 uses
+    700 uses
+    800 uses
+    900 uses
+    1000 uses
+    1100 uses
+    1200 uses
+    1300 uses
+    1400 uses
+    1500 uses
+    1600 uses
+    1700 uses
+    1800 uses
+    1900 uses
+    2000 uses
+    2100 uses
+    2200 uses
+Reading "cbx_1__2_".
     100 uses
     200 uses
     300 uses
@@ -1201,124 +1370,201 @@
     7300 uses
     7400 uses
     7500 uses
-    7600 uses
-    7700 uses
-    7800 uses
-    7900 uses
-    8000 uses
-    8100 uses
-    8200 uses
-    8300 uses
-    8400 uses
-    8500 uses
-    8600 uses
-    8700 uses
-    8800 uses
-    8900 uses
-    9000 uses
-    9100 uses
-    9200 uses
-    9300 uses
-    9400 uses
-    9500 uses
-    9600 uses
-    9700 uses
-    9800 uses
-    9900 uses
-    10000 uses
-    10100 uses
-    10200 uses
-    10300 uses
-    10400 uses
-    10500 uses
-    10600 uses
-    10700 uses
-    10800 uses
-    10900 uses
-    11000 uses
-    11100 uses
-    11200 uses
-    11300 uses
-    11400 uses
-    11500 uses
-    11600 uses
-    11700 uses
-    11800 uses
-    11900 uses
-    12000 uses
-    12100 uses
-    12200 uses
-    12300 uses
-    12400 uses
-    12500 uses
-    12600 uses
-    12700 uses
-    12800 uses
-    12900 uses
-    13000 uses
-    13100 uses
-    13200 uses
-    13300 uses
-    13400 uses
-    13500 uses
-    13600 uses
-    13700 uses
-    13800 uses
-    13900 uses
-    14000 uses
-    14100 uses
-    14200 uses
-    14300 uses
-    14400 uses
-    14500 uses
-    14600 uses
-    14700 uses
-    14800 uses
-    14900 uses
-    15000 uses
-    15100 uses
-    15200 uses
-    15300 uses
-    15400 uses
-    15500 uses
-    15600 uses
-    15700 uses
-    15800 uses
-    15900 uses
-    16000 uses
-    16100 uses
-    16200 uses
-    16300 uses
-    16400 uses
-    16500 uses
-    16600 uses
-    16700 uses
-    16800 uses
-    16900 uses
-    17000 uses
-    17100 uses
-    17200 uses
-    17300 uses
-    17400 uses
-    17500 uses
-    17600 uses
-    17700 uses
-    17800 uses
-    17900 uses
-    18000 uses
-    18100 uses
-    18200 uses
-    18300 uses
-    18400 uses
-    18500 uses
-    18600 uses
-    18700 uses
-    18800 uses
-    18900 uses
-    19000 uses
-    19100 uses
-    19200 uses
-    19300 uses
+Reading "cbx_1__1_".
+    100 uses
+    200 uses
+    300 uses
+    400 uses
+    500 uses
+    600 uses
+    700 uses
+    800 uses
+    900 uses
+    1000 uses
+    1100 uses
+    1200 uses
+    1300 uses
+    1400 uses
+    1500 uses
+    1600 uses
+    1700 uses
+    1800 uses
+    1900 uses
+    2000 uses
+    2100 uses
+    2200 uses
+    2300 uses
+    2400 uses
+    2500 uses
+    2600 uses
+    2700 uses
+    2800 uses
+    2900 uses
+    3000 uses
+    3100 uses
+    3200 uses
+    3300 uses
+    3400 uses
+    3500 uses
+    3600 uses
+    3700 uses
+    3800 uses
+    3900 uses
+    4000 uses
+    4100 uses
+    4200 uses
+    4300 uses
+    4400 uses
+    4500 uses
+    4600 uses
+    4700 uses
+    4800 uses
+    4900 uses
+    5000 uses
+    5100 uses
+    5200 uses
+    5300 uses
+    5400 uses
+    5500 uses
+    5600 uses
+    5700 uses
+    5800 uses
+    5900 uses
+    6000 uses
+    6100 uses
+    6200 uses
+    6300 uses
+    6400 uses
+    6500 uses
+    6600 uses
+    6700 uses
+    6800 uses
+    6900 uses
+    7000 uses
+    7100 uses
+    7200 uses
+Reading "cbx_1__0_".
+    100 uses
+    200 uses
+    300 uses
+    400 uses
+    500 uses
+    600 uses
+    700 uses
+    800 uses
+    900 uses
+    1000 uses
+    1100 uses
+    1200 uses
+    1300 uses
+    1400 uses
+    1500 uses
+    1600 uses
+    1700 uses
+    1800 uses
+    1900 uses
+    2000 uses
+    2100 uses
+    2200 uses
+    2300 uses
+    2400 uses
+    2500 uses
+    2600 uses
+    2700 uses
+    2800 uses
+    2900 uses
+    3000 uses
+    3100 uses
+    3200 uses
+    3300 uses
+    3400 uses
+    3500 uses
+    3600 uses
+    3700 uses
+    3800 uses
+    3900 uses
+    4000 uses
+    4100 uses
+    4200 uses
+    4300 uses
+    4400 uses
+    4500 uses
+    4600 uses
+    4700 uses
+    4800 uses
+    4900 uses
+    5000 uses
+    5100 uses
+    5200 uses
+    5300 uses
+    5400 uses
+    5500 uses
+    5600 uses
+Reading "sb_2__2_".
+    100 uses
+    200 uses
+    300 uses
+    400 uses
+    500 uses
+    600 uses
+    700 uses
+    800 uses
+    900 uses
+    1000 uses
+    1100 uses
+    1200 uses
+    1300 uses
+    1400 uses
+    1500 uses
+    1600 uses
+    1700 uses
+    1800 uses
+    1900 uses
+    2000 uses
+    2100 uses
+    2200 uses
+    2300 uses
+    2400 uses
+    2500 uses
+    2600 uses
+    2700 uses
+    2800 uses
+    2900 uses
+    3000 uses
+    3100 uses
+    3200 uses
+    3300 uses
+    3400 uses
+    3500 uses
+    3600 uses
+    3700 uses
+    3800 uses
+    3900 uses
+    4000 uses
+    4100 uses
+    4200 uses
+    4300 uses
+    4400 uses
+    4500 uses
+    4600 uses
+    4700 uses
+    4800 uses
+    4900 uses
+    5000 uses
+    5100 uses
+    5200 uses
+    5300 uses
+    5400 uses
+    5500 uses
+    5600 uses
+    5700 uses
+    5800 uses
+    5900 uses
+    6000 uses
+    6100 uses
+    6200 uses
+    6300 uses
+    6400 uses
 Reading "sb_2__1_".
     100 uses
     200 uses
@@ -1421,210 +1667,6 @@
     9900 uses
     10000 uses
     10100 uses
-    10200 uses
-    10300 uses
-    10400 uses
-    10500 uses
-    10600 uses
-    10700 uses
-    10800 uses
-    10900 uses
-    11000 uses
-    11100 uses
-    11200 uses
-    11300 uses
-    11400 uses
-    11500 uses
-    11600 uses
-    11700 uses
-    11800 uses
-    11900 uses
-    12000 uses
-    12100 uses
-    12200 uses
-    12300 uses
-    12400 uses
-    12500 uses
-    12600 uses
-    12700 uses
-    12800 uses
-    12900 uses
-    13000 uses
-    13100 uses
-    13200 uses
-    13300 uses
-    13400 uses
-    13500 uses
-    13600 uses
-    13700 uses
-    13800 uses
-    13900 uses
-    14000 uses
-    14100 uses
-    14200 uses
-    14300 uses
-    14400 uses
-    14500 uses
-    14600 uses
-    14700 uses
-    14800 uses
-    14900 uses
-    15000 uses
-    15100 uses
-    15200 uses
-    15300 uses
-    15400 uses
-    15500 uses
-    15600 uses
-    15700 uses
-    15800 uses
-    15900 uses
-    16000 uses
-    16100 uses
-    16200 uses
-    16300 uses
-    16400 uses
-    16500 uses
-    16600 uses
-    16700 uses
-    16800 uses
-    16900 uses
-    17000 uses
-    17100 uses
-    17200 uses
-    17300 uses
-    17400 uses
-    17500 uses
-    17600 uses
-    17700 uses
-    17800 uses
-    17900 uses
-    18000 uses
-    18100 uses
-    18200 uses
-    18300 uses
-    18400 uses
-    18500 uses
-    18600 uses
-    18700 uses
-    18800 uses
-    18900 uses
-    19000 uses
-    19100 uses
-    19200 uses
-    19300 uses
-    19400 uses
-    19500 uses
-    19600 uses
-    19700 uses
-    19800 uses
-    19900 uses
-    20000 uses
-    20100 uses
-    20200 uses
-    20300 uses
-    20400 uses
-    20500 uses
-    20600 uses
-    20700 uses
-    20800 uses
-    20900 uses
-    21000 uses
-    21100 uses
-    21200 uses
-    21300 uses
-    21400 uses
-    21500 uses
-    21600 uses
-    21700 uses
-    21800 uses
-    21900 uses
-    22000 uses
-    22100 uses
-    22200 uses
-    22300 uses
-    22400 uses
-    22500 uses
-    22600 uses
-    22700 uses
-    22800 uses
-    22900 uses
-    23000 uses
-    23100 uses
-    23200 uses
-    23300 uses
-    23400 uses
-    23500 uses
-    23600 uses
-    23700 uses
-    23800 uses
-    23900 uses
-    24000 uses
-    24100 uses
-    24200 uses
-    24300 uses
-    24400 uses
-    24500 uses
-    24600 uses
-    24700 uses
-    24800 uses
-    24900 uses
-    25000 uses
-    25100 uses
-    25200 uses
-    25300 uses
-    25400 uses
-    25500 uses
-    25600 uses
-    25700 uses
-    25800 uses
-    25900 uses
-    26000 uses
-    26100 uses
-    26200 uses
-    26300 uses
-    26400 uses
-    26500 uses
-    26600 uses
-    26700 uses
-    26800 uses
-    26900 uses
-    27000 uses
-    27100 uses
-    27200 uses
-    27300 uses
-    27400 uses
-    27500 uses
-    27600 uses
-    27700 uses
-    27800 uses
-    27900 uses
-    28000 uses
-    28100 uses
-    28200 uses
-    28300 uses
-    28400 uses
-    28500 uses
-    28600 uses
-    28700 uses
-    28800 uses
-    28900 uses
-    29000 uses
-    29100 uses
-    29200 uses
-    29300 uses
-    29400 uses
-    29500 uses
-    29600 uses
-    29700 uses
-    29800 uses
-    29900 uses
-    30000 uses
-    30100 uses
-    30200 uses
-    30300 uses
-    30400 uses
-    30500 uses
 Reading "sb_2__0_".
     100 uses
     200 uses
@@ -1691,136 +1733,6 @@
     6300 uses
     6400 uses
     6500 uses
-    6600 uses
-    6700 uses
-    6800 uses
-    6900 uses
-    7000 uses
-    7100 uses
-    7200 uses
-    7300 uses
-    7400 uses
-    7500 uses
-    7600 uses
-    7700 uses
-    7800 uses
-    7900 uses
-    8000 uses
-    8100 uses
-    8200 uses
-    8300 uses
-    8400 uses
-    8500 uses
-    8600 uses
-    8700 uses
-    8800 uses
-    8900 uses
-    9000 uses
-    9100 uses
-    9200 uses
-    9300 uses
-    9400 uses
-    9500 uses
-    9600 uses
-    9700 uses
-    9800 uses
-    9900 uses
-    10000 uses
-    10100 uses
-    10200 uses
-    10300 uses
-    10400 uses
-    10500 uses
-    10600 uses
-    10700 uses
-    10800 uses
-    10900 uses
-    11000 uses
-    11100 uses
-    11200 uses
-    11300 uses
-    11400 uses
-    11500 uses
-    11600 uses
-    11700 uses
-    11800 uses
-    11900 uses
-    12000 uses
-    12100 uses
-    12200 uses
-    12300 uses
-    12400 uses
-    12500 uses
-    12600 uses
-    12700 uses
-    12800 uses
-    12900 uses
-    13000 uses
-    13100 uses
-    13200 uses
-    13300 uses
-    13400 uses
-    13500 uses
-    13600 uses
-    13700 uses
-    13800 uses
-    13900 uses
-    14000 uses
-    14100 uses
-    14200 uses
-    14300 uses
-    14400 uses
-    14500 uses
-    14600 uses
-    14700 uses
-    14800 uses
-    14900 uses
-    15000 uses
-    15100 uses
-    15200 uses
-    15300 uses
-    15400 uses
-    15500 uses
-    15600 uses
-    15700 uses
-    15800 uses
-    15900 uses
-    16000 uses
-    16100 uses
-    16200 uses
-    16300 uses
-    16400 uses
-    16500 uses
-    16600 uses
-    16700 uses
-    16800 uses
-    16900 uses
-    17000 uses
-    17100 uses
-    17200 uses
-    17300 uses
-    17400 uses
-    17500 uses
-    17600 uses
-    17700 uses
-    17800 uses
-    17900 uses
-    18000 uses
-    18100 uses
-    18200 uses
-    18300 uses
-    18400 uses
-    18500 uses
-    18600 uses
-    18700 uses
-    18800 uses
-    18900 uses
-    19000 uses
-    19100 uses
-    19200 uses
-    19300 uses
-    19400 uses
-    19500 uses
 Reading "sb_1__2_".
     100 uses
     200 uses
@@ -1932,1958 +1844,6 @@
     10800 uses
     10900 uses
     11000 uses
-    11100 uses
-    11200 uses
-    11300 uses
-    11400 uses
-    11500 uses
-    11600 uses
-    11700 uses
-    11800 uses
-    11900 uses
-    12000 uses
-    12100 uses
-    12200 uses
-    12300 uses
-    12400 uses
-    12500 uses
-    12600 uses
-    12700 uses
-    12800 uses
-    12900 uses
-    13000 uses
-    13100 uses
-    13200 uses
-    13300 uses
-    13400 uses
-    13500 uses
-    13600 uses
-    13700 uses
-    13800 uses
-    13900 uses
-    14000 uses
-    14100 uses
-    14200 uses
-    14300 uses
-    14400 uses
-    14500 uses
-    14600 uses
-    14700 uses
-    14800 uses
-    14900 uses
-    15000 uses
-    15100 uses
-    15200 uses
-    15300 uses
-    15400 uses
-    15500 uses
-    15600 uses
-    15700 uses
-    15800 uses
-    15900 uses
-    16000 uses
-    16100 uses
-    16200 uses
-    16300 uses
-    16400 uses
-    16500 uses
-    16600 uses
-    16700 uses
-    16800 uses
-    16900 uses
-    17000 uses
-    17100 uses
-    17200 uses
-    17300 uses
-    17400 uses
-    17500 uses
-    17600 uses
-    17700 uses
-    17800 uses
-    17900 uses
-    18000 uses
-    18100 uses
-    18200 uses
-    18300 uses
-    18400 uses
-    18500 uses
-    18600 uses
-    18700 uses
-    18800 uses
-    18900 uses
-    19000 uses
-    19100 uses
-    19200 uses
-    19300 uses
-    19400 uses
-    19500 uses
-    19600 uses
-    19700 uses
-    19800 uses
-    19900 uses
-    20000 uses
-    20100 uses
-    20200 uses
-    20300 uses
-    20400 uses
-    20500 uses
-    20600 uses
-    20700 uses
-    20800 uses
-    20900 uses
-    21000 uses
-    21100 uses
-    21200 uses
-    21300 uses
-    21400 uses
-    21500 uses
-    21600 uses
-    21700 uses
-    21800 uses
-    21900 uses
-    22000 uses
-    22100 uses
-    22200 uses
-    22300 uses
-    22400 uses
-    22500 uses
-    22600 uses
-    22700 uses
-    22800 uses
-    22900 uses
-    23000 uses
-    23100 uses
-    23200 uses
-    23300 uses
-    23400 uses
-    23500 uses
-    23600 uses
-    23700 uses
-    23800 uses
-    23900 uses
-    24000 uses
-    24100 uses
-    24200 uses
-    24300 uses
-    24400 uses
-    24500 uses
-    24600 uses
-    24700 uses
-    24800 uses
-    24900 uses
-    25000 uses
-    25100 uses
-    25200 uses
-    25300 uses
-    25400 uses
-    25500 uses
-    25600 uses
-    25700 uses
-    25800 uses
-    25900 uses
-    26000 uses
-    26100 uses
-    26200 uses
-    26300 uses
-    26400 uses
-    26500 uses
-    26600 uses
-    26700 uses
-    26800 uses
-    26900 uses
-    27000 uses
-    27100 uses
-    27200 uses
-    27300 uses
-    27400 uses
-    27500 uses
-    27600 uses
-    27700 uses
-    27800 uses
-    27900 uses
-    28000 uses
-    28100 uses
-    28200 uses
-    28300 uses
-    28400 uses
-    28500 uses
-    28600 uses
-    28700 uses
-    28800 uses
-    28900 uses
-    29000 uses
-    29100 uses
-    29200 uses
-    29300 uses
-    29400 uses
-    29500 uses
-    29600 uses
-    29700 uses
-    29800 uses
-    29900 uses
-    30000 uses
-    30100 uses
-    30200 uses
-    30300 uses
-    30400 uses
-    30500 uses
-    30600 uses
-    30700 uses
-    30800 uses
-    30900 uses
-    31000 uses
-    31100 uses
-    31200 uses
-    31300 uses
-    31400 uses
-    31500 uses
-    31600 uses
-    31700 uses
-    31800 uses
-    31900 uses
-    32000 uses
-    32100 uses
-    32200 uses
-    32300 uses
-    32400 uses
-    32500 uses
-    32600 uses
-    32700 uses
-    32800 uses
-    32900 uses
-    33000 uses
-    33100 uses
-Reading "sb_1__0_".
-    100 uses
-    200 uses
-    300 uses
-    400 uses
-    500 uses
-    600 uses
-    700 uses
-    800 uses
-    900 uses
-    1000 uses
-    1100 uses
-    1200 uses
-    1300 uses
-    1400 uses
-    1500 uses
-    1600 uses
-    1700 uses
-    1800 uses
-    1900 uses
-    2000 uses
-    2100 uses
-    2200 uses
-    2300 uses
-    2400 uses
-    2500 uses
-    2600 uses
-    2700 uses
-    2800 uses
-    2900 uses
-    3000 uses
-    3100 uses
-    3200 uses
-    3300 uses
-    3400 uses
-    3500 uses
-    3600 uses
-    3700 uses
-    3800 uses
-    3900 uses
-    4000 uses
-    4100 uses
-    4200 uses
-    4300 uses
-    4400 uses
-    4500 uses
-    4600 uses
-    4700 uses
-    4800 uses
-    4900 uses
-    5000 uses
-    5100 uses
-    5200 uses
-    5300 uses
-    5400 uses
-    5500 uses
-    5600 uses
-    5700 uses
-    5800 uses
-    5900 uses
-    6000 uses
-    6100 uses
-    6200 uses
-    6300 uses
-    6400 uses
-    6500 uses
-    6600 uses
-    6700 uses
-    6800 uses
-    6900 uses
-    7000 uses
-    7100 uses
-    7200 uses
-    7300 uses
-    7400 uses
-    7500 uses
-    7600 uses
-    7700 uses
-    7800 uses
-    7900 uses
-    8000 uses
-    8100 uses
-    8200 uses
-    8300 uses
-    8400 uses
-    8500 uses
-    8600 uses
-    8700 uses
-    8800 uses
-    8900 uses
-    9000 uses
-    9100 uses
-    9200 uses
-    9300 uses
-    9400 uses
-    9500 uses
-    9600 uses
-    9700 uses
-    9800 uses
-    9900 uses
-    10000 uses
-    10100 uses
-    10200 uses
-    10300 uses
-    10400 uses
-    10500 uses
-    10600 uses
-    10700 uses
-    10800 uses
-    10900 uses
-    11000 uses
-    11100 uses
-    11200 uses
-    11300 uses
-    11400 uses
-    11500 uses
-    11600 uses
-    11700 uses
-    11800 uses
-    11900 uses
-    12000 uses
-    12100 uses
-    12200 uses
-    12300 uses
-    12400 uses
-    12500 uses
-    12600 uses
-    12700 uses
-    12800 uses
-    12900 uses
-    13000 uses
-    13100 uses
-    13200 uses
-    13300 uses
-    13400 uses
-    13500 uses
-    13600 uses
-    13700 uses
-    13800 uses
-    13900 uses
-    14000 uses
-    14100 uses
-    14200 uses
-    14300 uses
-    14400 uses
-    14500 uses
-    14600 uses
-    14700 uses
-    14800 uses
-    14900 uses
-    15000 uses
-    15100 uses
-    15200 uses
-    15300 uses
-    15400 uses
-    15500 uses
-    15600 uses
-    15700 uses
-    15800 uses
-    15900 uses
-    16000 uses
-    16100 uses
-    16200 uses
-    16300 uses
-    16400 uses
-    16500 uses
-    16600 uses
-    16700 uses
-    16800 uses
-    16900 uses
-    17000 uses
-    17100 uses
-    17200 uses
-    17300 uses
-    17400 uses
-    17500 uses
-    17600 uses
-    17700 uses
-    17800 uses
-    17900 uses
-    18000 uses
-    18100 uses
-    18200 uses
-    18300 uses
-    18400 uses
-    18500 uses
-    18600 uses
-    18700 uses
-    18800 uses
-    18900 uses
-    19000 uses
-    19100 uses
-    19200 uses
-    19300 uses
-    19400 uses
-    19500 uses
-    19600 uses
-    19700 uses
-    19800 uses
-    19900 uses
-    20000 uses
-    20100 uses
-    20200 uses
-    20300 uses
-    20400 uses
-    20500 uses
-    20600 uses
-    20700 uses
-    20800 uses
-    20900 uses
-    21000 uses
-    21100 uses
-    21200 uses
-    21300 uses
-    21400 uses
-    21500 uses
-    21600 uses
-    21700 uses
-    21800 uses
-    21900 uses
-    22000 uses
-    22100 uses
-    22200 uses
-    22300 uses
-    22400 uses
-    22500 uses
-    22600 uses
-    22700 uses
-    22800 uses
-    22900 uses
-    23000 uses
-    23100 uses
-    23200 uses
-    23300 uses
-    23400 uses
-    23500 uses
-    23600 uses
-    23700 uses
-    23800 uses
-    23900 uses
-    24000 uses
-    24100 uses
-    24200 uses
-    24300 uses
-    24400 uses
-    24500 uses
-    24600 uses
-    24700 uses
-    24800 uses
-    24900 uses
-    25000 uses
-    25100 uses
-    25200 uses
-    25300 uses
-    25400 uses
-    25500 uses
-    25600 uses
-    25700 uses
-    25800 uses
-    25900 uses
-    26000 uses
-    26100 uses
-    26200 uses
-    26300 uses
-    26400 uses
-    26500 uses
-    26600 uses
-    26700 uses
-    26800 uses
-    26900 uses
-    27000 uses
-    27100 uses
-    27200 uses
-    27300 uses
-    27400 uses
-    27500 uses
-    27600 uses
-    27700 uses
-    27800 uses
-    27900 uses
-    28000 uses
-    28100 uses
-    28200 uses
-    28300 uses
-    28400 uses
-    28500 uses
-    28600 uses
-    28700 uses
-    28800 uses
-    28900 uses
-    29000 uses
-    29100 uses
-    29200 uses
-    29300 uses
-    29400 uses
-    29500 uses
-    29600 uses
-    29700 uses
-    29800 uses
-    29900 uses
-    30000 uses
-    30100 uses
-    30200 uses
-    30300 uses
-    30400 uses
-    30500 uses
-    30600 uses
-    30700 uses
-    30800 uses
-    30900 uses
-    31000 uses
-    31100 uses
-    31200 uses
-    31300 uses
-    31400 uses
-    31500 uses
-    31600 uses
-    31700 uses
-    31800 uses
-    31900 uses
-    32000 uses
-    32100 uses
-    32200 uses
-    32300 uses
-    32400 uses
-    32500 uses
-    32600 uses
-    32700 uses
-    32800 uses
-    32900 uses
-    33000 uses
-Reading "sb_0__2_".
-    100 uses
-    200 uses
-    300 uses
-    400 uses
-    500 uses
-    600 uses
-    700 uses
-    800 uses
-    900 uses
-    1000 uses
-    1100 uses
-    1200 uses
-    1300 uses
-    1400 uses
-    1500 uses
-    1600 uses
-    1700 uses
-    1800 uses
-    1900 uses
-    2000 uses
-    2100 uses
-    2200 uses
-    2300 uses
-    2400 uses
-    2500 uses
-    2600 uses
-    2700 uses
-    2800 uses
-    2900 uses
-    3000 uses
-    3100 uses
-    3200 uses
-    3300 uses
-    3400 uses
-    3500 uses
-    3600 uses
-    3700 uses
-    3800 uses
-    3900 uses
-    4000 uses
-    4100 uses
-    4200 uses
-    4300 uses
-    4400 uses
-    4500 uses
-    4600 uses
-    4700 uses
-    4800 uses
-    4900 uses
-    5000 uses
-    5100 uses
-    5200 uses
-    5300 uses
-    5400 uses
-    5500 uses
-    5600 uses
-    5700 uses
-    5800 uses
-    5900 uses
-    6000 uses
-    6100 uses
-    6200 uses
-    6300 uses
-    6400 uses
-    6500 uses
-    6600 uses
-    6700 uses
-    6800 uses
-    6900 uses
-    7000 uses
-    7100 uses
-    7200 uses
-    7300 uses
-    7400 uses
-    7500 uses
-    7600 uses
-    7700 uses
-    7800 uses
-    7900 uses
-    8000 uses
-    8100 uses
-    8200 uses
-    8300 uses
-    8400 uses
-    8500 uses
-    8600 uses
-    8700 uses
-    8800 uses
-    8900 uses
-    9000 uses
-    9100 uses
-    9200 uses
-    9300 uses
-    9400 uses
-    9500 uses
-    9600 uses
-    9700 uses
-    9800 uses
-    9900 uses
-    10000 uses
-    10100 uses
-    10200 uses
-    10300 uses
-    10400 uses
-    10500 uses
-    10600 uses
-    10700 uses
-    10800 uses
-    10900 uses
-    11000 uses
-    11100 uses
-    11200 uses
-    11300 uses
-    11400 uses
-    11500 uses
-    11600 uses
-    11700 uses
-    11800 uses
-    11900 uses
-    12000 uses
-    12100 uses
-    12200 uses
-    12300 uses
-    12400 uses
-    12500 uses
-    12600 uses
-    12700 uses
-    12800 uses
-    12900 uses
-    13000 uses
-    13100 uses
-    13200 uses
-    13300 uses
-    13400 uses
-    13500 uses
-    13600 uses
-    13700 uses
-    13800 uses
-Reading "sb_0__0_".
-    100 uses
-    200 uses
-    300 uses
-    400 uses
-    500 uses
-    600 uses
-    700 uses
-    800 uses
-    900 uses
-    1000 uses
-    1100 uses
-    1200 uses
-    1300 uses
-    1400 uses
-    1500 uses
-    1600 uses
-    1700 uses
-    1800 uses
-    1900 uses
-    2000 uses
-    2100 uses
-    2200 uses
-    2300 uses
-    2400 uses
-    2500 uses
-    2600 uses
-    2700 uses
-    2800 uses
-    2900 uses
-    3000 uses
-    3100 uses
-    3200 uses
-    3300 uses
-    3400 uses
-    3500 uses
-    3600 uses
-    3700 uses
-    3800 uses
-    3900 uses
-    4000 uses
-    4100 uses
-    4200 uses
-    4300 uses
-    4400 uses
-    4500 uses
-    4600 uses
-    4700 uses
-    4800 uses
-    4900 uses
-    5000 uses
-    5100 uses
-    5200 uses
-    5300 uses
-    5400 uses
-    5500 uses
-    5600 uses
-    5700 uses
-    5800 uses
-    5900 uses
-    6000 uses
-    6100 uses
-    6200 uses
-    6300 uses
-    6400 uses
-    6500 uses
-    6600 uses
-    6700 uses
-    6800 uses
-    6900 uses
-    7000 uses
-    7100 uses
-    7200 uses
-    7300 uses
-    7400 uses
-    7500 uses
-    7600 uses
-    7700 uses
-    7800 uses
-    7900 uses
-    8000 uses
-    8100 uses
-    8200 uses
-    8300 uses
-    8400 uses
-    8500 uses
-    8600 uses
-    8700 uses
-    8800 uses
-    8900 uses
-    9000 uses
-    9100 uses
-    9200 uses
-    9300 uses
-    9400 uses
-    9500 uses
-    9600 uses
-    9700 uses
-    9800 uses
-    9900 uses
-    10000 uses
-    10100 uses
-    10200 uses
-    10300 uses
-    10400 uses
-    10500 uses
-    10600 uses
-    10700 uses
-    10800 uses
-    10900 uses
-    11000 uses
-    11100 uses
-    11200 uses
-    11300 uses
-    11400 uses
-    11500 uses
-    11600 uses
-    11700 uses
-    11800 uses
-    11900 uses
-    12000 uses
-    12100 uses
-    12200 uses
-    12300 uses
-    12400 uses
-    12500 uses
-    12600 uses
-    12700 uses
-    12800 uses
-    12900 uses
-    13000 uses
-    13100 uses
-    13200 uses
-    13300 uses
-    13400 uses
-    13500 uses
-    13600 uses
-    13700 uses
-Reading "cby_2__1_".
-    100 uses
-    200 uses
-    300 uses
-    400 uses
-    500 uses
-    600 uses
-    700 uses
-    800 uses
-    900 uses
-    1000 uses
-    1100 uses
-    1200 uses
-    1300 uses
-    1400 uses
-    1500 uses
-    1600 uses
-    1700 uses
-    1800 uses
-    1900 uses
-    2000 uses
-    2100 uses
-    2200 uses
-    2300 uses
-    2400 uses
-    2500 uses
-    2600 uses
-    2700 uses
-    2800 uses
-    2900 uses
-    3000 uses
-    3100 uses
-    3200 uses
-    3300 uses
-    3400 uses
-    3500 uses
-    3600 uses
-    3700 uses
-    3800 uses
-    3900 uses
-    4000 uses
-    4100 uses
-    4200 uses
-    4300 uses
-    4400 uses
-    4500 uses
-    4600 uses
-    4700 uses
-    4800 uses
-    4900 uses
-    5000 uses
-    5100 uses
-    5200 uses
-    5300 uses
-    5400 uses
-    5500 uses
-    5600 uses
-    5700 uses
-    5800 uses
-    5900 uses
-    6000 uses
-    6100 uses
-    6200 uses
-    6300 uses
-    6400 uses
-    6500 uses
-    6600 uses
-    6700 uses
-    6800 uses
-    6900 uses
-    7000 uses
-    7100 uses
-    7200 uses
-    7300 uses
-    7400 uses
-    7500 uses
-    7600 uses
-    7700 uses
-    7800 uses
-    7900 uses
-    8000 uses
-    8100 uses
-    8200 uses
-    8300 uses
-    8400 uses
-    8500 uses
-    8600 uses
-    8700 uses
-    8800 uses
-    8900 uses
-    9000 uses
-    9100 uses
-    9200 uses
-    9300 uses
-    9400 uses
-    9500 uses
-    9600 uses
-    9700 uses
-    9800 uses
-    9900 uses
-    10000 uses
-    10100 uses
-    10200 uses
-    10300 uses
-    10400 uses
-    10500 uses
-    10600 uses
-    10700 uses
-    10800 uses
-    10900 uses
-    11000 uses
-    11100 uses
-    11200 uses
-    11300 uses
-    11400 uses
-    11500 uses
-    11600 uses
-    11700 uses
-    11800 uses
-    11900 uses
-    12000 uses
-    12100 uses
-    12200 uses
-    12300 uses
-    12400 uses
-    12500 uses
-    12600 uses
-    12700 uses
-    12800 uses
-    12900 uses
-    13000 uses
-    13100 uses
-    13200 uses
-    13300 uses
-    13400 uses
-    13500 uses
-    13600 uses
-    13700 uses
-    13800 uses
-    13900 uses
-    14000 uses
-    14100 uses
-    14200 uses
-    14300 uses
-    14400 uses
-    14500 uses
-    14600 uses
-    14700 uses
-    14800 uses
-    14900 uses
-    15000 uses
-    15100 uses
-    15200 uses
-    15300 uses
-    15400 uses
-    15500 uses
-    15600 uses
-    15700 uses
-    15800 uses
-    15900 uses
-    16000 uses
-    16100 uses
-    16200 uses
-    16300 uses
-    16400 uses
-    16500 uses
-    16600 uses
-    16700 uses
-    16800 uses
-    16900 uses
-    17000 uses
-    17100 uses
-    17200 uses
-    17300 uses
-    17400 uses
-    17500 uses
-    17600 uses
-    17700 uses
-    17800 uses
-    17900 uses
-    18000 uses
-    18100 uses
-    18200 uses
-    18300 uses
-    18400 uses
-    18500 uses
-    18600 uses
-    18700 uses
-    18800 uses
-    18900 uses
-    19000 uses
-    19100 uses
-    19200 uses
-    19300 uses
-    19400 uses
-    19500 uses
-    19600 uses
-    19700 uses
-    19800 uses
-    19900 uses
-    20000 uses
-    20100 uses
-    20200 uses
-    20300 uses
-    20400 uses
-    20500 uses
-    20600 uses
-    20700 uses
-    20800 uses
-    20900 uses
-    21000 uses
-    21100 uses
-    21200 uses
-    21300 uses
-    21400 uses
-    21500 uses
-    21600 uses
-    21700 uses
-    21800 uses
-    21900 uses
-    22000 uses
-    22100 uses
-    22200 uses
-    22300 uses
-    22400 uses
-Reading "cby_1__1_".
-    100 uses
-    200 uses
-    300 uses
-    400 uses
-    500 uses
-    600 uses
-    700 uses
-    800 uses
-    900 uses
-    1000 uses
-    1100 uses
-    1200 uses
-    1300 uses
-    1400 uses
-    1500 uses
-    1600 uses
-    1700 uses
-    1800 uses
-    1900 uses
-    2000 uses
-    2100 uses
-    2200 uses
-    2300 uses
-    2400 uses
-    2500 uses
-    2600 uses
-    2700 uses
-    2800 uses
-    2900 uses
-    3000 uses
-    3100 uses
-    3200 uses
-    3300 uses
-    3400 uses
-    3500 uses
-    3600 uses
-    3700 uses
-    3800 uses
-    3900 uses
-    4000 uses
-    4100 uses
-    4200 uses
-    4300 uses
-    4400 uses
-    4500 uses
-    4600 uses
-    4700 uses
-    4800 uses
-    4900 uses
-    5000 uses
-    5100 uses
-    5200 uses
-    5300 uses
-    5400 uses
-    5500 uses
-    5600 uses
-    5700 uses
-    5800 uses
-    5900 uses
-    6000 uses
-    6100 uses
-    6200 uses
-    6300 uses
-    6400 uses
-    6500 uses
-    6600 uses
-    6700 uses
-    6800 uses
-    6900 uses
-    7000 uses
-    7100 uses
-    7200 uses
-    7300 uses
-    7400 uses
-    7500 uses
-    7600 uses
-    7700 uses
-    7800 uses
-    7900 uses
-    8000 uses
-    8100 uses
-    8200 uses
-    8300 uses
-    8400 uses
-    8500 uses
-    8600 uses
-    8700 uses
-    8800 uses
-    8900 uses
-    9000 uses
-    9100 uses
-    9200 uses
-    9300 uses
-    9400 uses
-    9500 uses
-    9600 uses
-    9700 uses
-    9800 uses
-    9900 uses
-    10000 uses
-    10100 uses
-    10200 uses
-    10300 uses
-    10400 uses
-    10500 uses
-    10600 uses
-    10700 uses
-    10800 uses
-    10900 uses
-    11000 uses
-    11100 uses
-    11200 uses
-    11300 uses
-    11400 uses
-    11500 uses
-    11600 uses
-    11700 uses
-    11800 uses
-    11900 uses
-    12000 uses
-    12100 uses
-    12200 uses
-    12300 uses
-    12400 uses
-    12500 uses
-    12600 uses
-    12700 uses
-    12800 uses
-    12900 uses
-    13000 uses
-    13100 uses
-    13200 uses
-    13300 uses
-    13400 uses
-    13500 uses
-    13600 uses
-    13700 uses
-    13800 uses
-    13900 uses
-    14000 uses
-    14100 uses
-    14200 uses
-    14300 uses
-    14400 uses
-    14500 uses
-    14600 uses
-    14700 uses
-    14800 uses
-    14900 uses
-    15000 uses
-    15100 uses
-    15200 uses
-    15300 uses
-    15400 uses
-    15500 uses
-    15600 uses
-    15700 uses
-    15800 uses
-    15900 uses
-    16000 uses
-    16100 uses
-    16200 uses
-    16300 uses
-    16400 uses
-    16500 uses
-    16600 uses
-    16700 uses
-    16800 uses
-    16900 uses
-    17000 uses
-    17100 uses
-    17200 uses
-    17300 uses
-    17400 uses
-    17500 uses
-    17600 uses
-    17700 uses
-    17800 uses
-    17900 uses
-    18000 uses
-    18100 uses
-    18200 uses
-    18300 uses
-    18400 uses
-    18500 uses
-    18600 uses
-    18700 uses
-    18800 uses
-    18900 uses
-    19000 uses
-    19100 uses
-    19200 uses
-    19300 uses
-    19400 uses
-    19500 uses
-    19600 uses
-    19700 uses
-    19800 uses
-    19900 uses
-    20000 uses
-    20100 uses
-    20200 uses
-    20300 uses
-    20400 uses
-    20500 uses
-    20600 uses
-    20700 uses
-    20800 uses
-    20900 uses
-    21000 uses
-    21100 uses
-Reading "cbx_1__0_".
-    100 uses
-    200 uses
-    300 uses
-    400 uses
-    500 uses
-    600 uses
-    700 uses
-    800 uses
-    900 uses
-    1000 uses
-    1100 uses
-    1200 uses
-    1300 uses
-    1400 uses
-    1500 uses
-    1600 uses
-    1700 uses
-    1800 uses
-    1900 uses
-    2000 uses
-    2100 uses
-    2200 uses
-    2300 uses
-    2400 uses
-    2500 uses
-    2600 uses
-    2700 uses
-    2800 uses
-    2900 uses
-    3000 uses
-    3100 uses
-    3200 uses
-    3300 uses
-    3400 uses
-    3500 uses
-    3600 uses
-    3700 uses
-    3800 uses
-    3900 uses
-    4000 uses
-    4100 uses
-    4200 uses
-    4300 uses
-    4400 uses
-    4500 uses
-    4600 uses
-    4700 uses
-    4800 uses
-    4900 uses
-    5000 uses
-    5100 uses
-    5200 uses
-    5300 uses
-    5400 uses
-    5500 uses
-    5600 uses
-    5700 uses
-    5800 uses
-    5900 uses
-    6000 uses
-    6100 uses
-    6200 uses
-    6300 uses
-    6400 uses
-    6500 uses
-    6600 uses
-    6700 uses
-    6800 uses
-    6900 uses
-    7000 uses
-    7100 uses
-    7200 uses
-    7300 uses
-    7400 uses
-    7500 uses
-    7600 uses
-    7700 uses
-    7800 uses
-    7900 uses
-    8000 uses
-    8100 uses
-    8200 uses
-    8300 uses
-    8400 uses
-    8500 uses
-    8600 uses
-    8700 uses
-    8800 uses
-    8900 uses
-    9000 uses
-    9100 uses
-    9200 uses
-    9300 uses
-    9400 uses
-    9500 uses
-    9600 uses
-    9700 uses
-    9800 uses
-    9900 uses
-    10000 uses
-    10100 uses
-    10200 uses
-    10300 uses
-    10400 uses
-    10500 uses
-    10600 uses
-    10700 uses
-    10800 uses
-    10900 uses
-    11000 uses
-    11100 uses
-    11200 uses
-    11300 uses
-    11400 uses
-    11500 uses
-    11600 uses
-    11700 uses
-    11800 uses
-    11900 uses
-    12000 uses
-    12100 uses
-    12200 uses
-    12300 uses
-    12400 uses
-    12500 uses
-    12600 uses
-    12700 uses
-    12800 uses
-    12900 uses
-    13000 uses
-    13100 uses
-    13200 uses
-    13300 uses
-    13400 uses
-    13500 uses
-    13600 uses
-    13700 uses
-    13800 uses
-    13900 uses
-    14000 uses
-    14100 uses
-    14200 uses
-    14300 uses
-    14400 uses
-    14500 uses
-    14600 uses
-    14700 uses
-    14800 uses
-    14900 uses
-    15000 uses
-    15100 uses
-    15200 uses
-    15300 uses
-    15400 uses
-    15500 uses
-    15600 uses
-    15700 uses
-    15800 uses
-    15900 uses
-    16000 uses
-    16100 uses
-    16200 uses
-    16300 uses
-    16400 uses
-    16500 uses
-    16600 uses
-    16700 uses
-    16800 uses
-    16900 uses
-    17000 uses
-Reading "cby_0__1_".
-    100 uses
-    200 uses
-    300 uses
-    400 uses
-    500 uses
-    600 uses
-    700 uses
-    800 uses
-    900 uses
-    1000 uses
-    1100 uses
-    1200 uses
-    1300 uses
-    1400 uses
-    1500 uses
-    1600 uses
-    1700 uses
-    1800 uses
-    1900 uses
-    2000 uses
-    2100 uses
-    2200 uses
-    2300 uses
-    2400 uses
-    2500 uses
-    2600 uses
-    2700 uses
-    2800 uses
-    2900 uses
-    3000 uses
-    3100 uses
-    3200 uses
-    3300 uses
-    3400 uses
-    3500 uses
-    3600 uses
-    3700 uses
-    3800 uses
-    3900 uses
-    4000 uses
-    4100 uses
-    4200 uses
-    4300 uses
-    4400 uses
-    4500 uses
-    4600 uses
-    4700 uses
-    4800 uses
-    4900 uses
-    5000 uses
-    5100 uses
-    5200 uses
-    5300 uses
-    5400 uses
-    5500 uses
-    5600 uses
-    5700 uses
-    5800 uses
-    5900 uses
-    6000 uses
-    6100 uses
-    6200 uses
-    6300 uses
-    6400 uses
-    6500 uses
-    6600 uses
-    6700 uses
-    6800 uses
-Reading "cbx_1__2_".
-    100 uses
-    200 uses
-    300 uses
-    400 uses
-    500 uses
-    600 uses
-    700 uses
-    800 uses
-    900 uses
-    1000 uses
-    1100 uses
-    1200 uses
-    1300 uses
-    1400 uses
-    1500 uses
-    1600 uses
-    1700 uses
-    1800 uses
-    1900 uses
-    2000 uses
-    2100 uses
-    2200 uses
-    2300 uses
-    2400 uses
-    2500 uses
-    2600 uses
-    2700 uses
-    2800 uses
-    2900 uses
-    3000 uses
-    3100 uses
-    3200 uses
-    3300 uses
-    3400 uses
-    3500 uses
-    3600 uses
-    3700 uses
-    3800 uses
-    3900 uses
-    4000 uses
-    4100 uses
-    4200 uses
-    4300 uses
-    4400 uses
-    4500 uses
-    4600 uses
-    4700 uses
-    4800 uses
-    4900 uses
-    5000 uses
-    5100 uses
-    5200 uses
-    5300 uses
-    5400 uses
-    5500 uses
-    5600 uses
-    5700 uses
-    5800 uses
-    5900 uses
-    6000 uses
-    6100 uses
-    6200 uses
-    6300 uses
-    6400 uses
-    6500 uses
-    6600 uses
-    6700 uses
-    6800 uses
-    6900 uses
-    7000 uses
-    7100 uses
-    7200 uses
-    7300 uses
-    7400 uses
-    7500 uses
-    7600 uses
-    7700 uses
-    7800 uses
-    7900 uses
-    8000 uses
-    8100 uses
-    8200 uses
-    8300 uses
-    8400 uses
-    8500 uses
-    8600 uses
-    8700 uses
-    8800 uses
-    8900 uses
-    9000 uses
-    9100 uses
-    9200 uses
-    9300 uses
-    9400 uses
-    9500 uses
-    9600 uses
-    9700 uses
-    9800 uses
-    9900 uses
-    10000 uses
-    10100 uses
-    10200 uses
-    10300 uses
-    10400 uses
-    10500 uses
-    10600 uses
-    10700 uses
-    10800 uses
-    10900 uses
-    11000 uses
-    11100 uses
-    11200 uses
-    11300 uses
-    11400 uses
-    11500 uses
-    11600 uses
-    11700 uses
-    11800 uses
-    11900 uses
-    12000 uses
-    12100 uses
-    12200 uses
-    12300 uses
-    12400 uses
-    12500 uses
-    12600 uses
-    12700 uses
-    12800 uses
-    12900 uses
-    13000 uses
-    13100 uses
-    13200 uses
-    13300 uses
-    13400 uses
-    13500 uses
-    13600 uses
-    13700 uses
-    13800 uses
-    13900 uses
-    14000 uses
-    14100 uses
-    14200 uses
-    14300 uses
-    14400 uses
-    14500 uses
-    14600 uses
-    14700 uses
-    14800 uses
-    14900 uses
-    15000 uses
-    15100 uses
-    15200 uses
-    15300 uses
-    15400 uses
-    15500 uses
-    15600 uses
-    15700 uses
-    15800 uses
-    15900 uses
-    16000 uses
-    16100 uses
-    16200 uses
-    16300 uses
-    16400 uses
-    16500 uses
-    16600 uses
-    16700 uses
-    16800 uses
-    16900 uses
-    17000 uses
-    17100 uses
-    17200 uses
-    17300 uses
-    17400 uses
-    17500 uses
-    17600 uses
-    17700 uses
-    17800 uses
-    17900 uses
-    18000 uses
-    18100 uses
-    18200 uses
-    18300 uses
-    18400 uses
-    18500 uses
-    18600 uses
-    18700 uses
-    18800 uses
-    18900 uses
-    19000 uses
-    19100 uses
-    19200 uses
-    19300 uses
-    19400 uses
-    19500 uses
-    19600 uses
-    19700 uses
-    19800 uses
-    19900 uses
-    20000 uses
-    20100 uses
-    20200 uses
-    20300 uses
-    20400 uses
-    20500 uses
-    20600 uses
-    20700 uses
-    20800 uses
-    20900 uses
-    21000 uses
-    21100 uses
-    21200 uses
-    21300 uses
-    21400 uses
-    21500 uses
-    21600 uses
-    21700 uses
-    21800 uses
-    21900 uses
-    22000 uses
-    22100 uses
-    22200 uses
-    22300 uses
-    22400 uses
-    22500 uses
-    22600 uses
-    22700 uses
-Reading "cbx_1__1_".
-    100 uses
-    200 uses
-    300 uses
-    400 uses
-    500 uses
-    600 uses
-    700 uses
-    800 uses
-    900 uses
-    1000 uses
-    1100 uses
-    1200 uses
-    1300 uses
-    1400 uses
-    1500 uses
-    1600 uses
-    1700 uses
-    1800 uses
-    1900 uses
-    2000 uses
-    2100 uses
-    2200 uses
-    2300 uses
-    2400 uses
-    2500 uses
-    2600 uses
-    2700 uses
-    2800 uses
-    2900 uses
-    3000 uses
-    3100 uses
-    3200 uses
-    3300 uses
-    3400 uses
-    3500 uses
-    3600 uses
-    3700 uses
-    3800 uses
-    3900 uses
-    4000 uses
-    4100 uses
-    4200 uses
-    4300 uses
-    4400 uses
-    4500 uses
-    4600 uses
-    4700 uses
-    4800 uses
-    4900 uses
-    5000 uses
-    5100 uses
-    5200 uses
-    5300 uses
-    5400 uses
-    5500 uses
-    5600 uses
-    5700 uses
-    5800 uses
-    5900 uses
-    6000 uses
-    6100 uses
-    6200 uses
-    6300 uses
-    6400 uses
-    6500 uses
-    6600 uses
-    6700 uses
-    6800 uses
-    6900 uses
-    7000 uses
-    7100 uses
-    7200 uses
-    7300 uses
-    7400 uses
-    7500 uses
-    7600 uses
-    7700 uses
-    7800 uses
-    7900 uses
-    8000 uses
-    8100 uses
-    8200 uses
-    8300 uses
-    8400 uses
-    8500 uses
-    8600 uses
-    8700 uses
-    8800 uses
-    8900 uses
-    9000 uses
-    9100 uses
-    9200 uses
-    9300 uses
-    9400 uses
-    9500 uses
-    9600 uses
-    9700 uses
-    9800 uses
-    9900 uses
-    10000 uses
-    10100 uses
-    10200 uses
-    10300 uses
-    10400 uses
-    10500 uses
-    10600 uses
-    10700 uses
-    10800 uses
-    10900 uses
-    11000 uses
-    11100 uses
-    11200 uses
-    11300 uses
-    11400 uses
-    11500 uses
-    11600 uses
-    11700 uses
-    11800 uses
-    11900 uses
-    12000 uses
-    12100 uses
-    12200 uses
-    12300 uses
-    12400 uses
-    12500 uses
-    12600 uses
-    12700 uses
-    12800 uses
-    12900 uses
-    13000 uses
-    13100 uses
-    13200 uses
-    13300 uses
-    13400 uses
-    13500 uses
-    13600 uses
-    13700 uses
-    13800 uses
-    13900 uses
-    14000 uses
-    14100 uses
-    14200 uses
-    14300 uses
-    14400 uses
-    14500 uses
-    14600 uses
-    14700 uses
-    14800 uses
-    14900 uses
-    15000 uses
-    15100 uses
-    15200 uses
-    15300 uses
-    15400 uses
-    15500 uses
-    15600 uses
-    15700 uses
-    15800 uses
-    15900 uses
-    16000 uses
-    16100 uses
-    16200 uses
-    16300 uses
-    16400 uses
-    16500 uses
-    16600 uses
-    16700 uses
-    16800 uses
-    16900 uses
-    17000 uses
-    17100 uses
-    17200 uses
-    17300 uses
-    17400 uses
-    17500 uses
-    17600 uses
-    17700 uses
-    17800 uses
-    17900 uses
-    18000 uses
-    18100 uses
-    18200 uses
-    18300 uses
-    18400 uses
-    18500 uses
-    18600 uses
-    18700 uses
-    18800 uses
-    18900 uses
-    19000 uses
-    19100 uses
-    19200 uses
-    19300 uses
-    19400 uses
-    19500 uses
-    19600 uses
-    19700 uses
-    19800 uses
-    19900 uses
-    20000 uses
-    20100 uses
-    20200 uses
-    20300 uses
-    20400 uses
-    20500 uses
-    20600 uses
-    20700 uses
-    20800 uses
-    20900 uses
-    21000 uses
-    21100 uses
-    21200 uses
-    21300 uses
-    21400 uses
-    21500 uses
-    21600 uses
-    21700 uses
 Reading "sb_1__1_".
     100 uses
     200 uses
@@ -4043,323 +2003,7 @@
     15600 uses
     15700 uses
     15800 uses
-    15900 uses
-    16000 uses
-    16100 uses
-    16200 uses
-    16300 uses
-    16400 uses
-    16500 uses
-    16600 uses
-    16700 uses
-    16800 uses
-    16900 uses
-    17000 uses
-    17100 uses
-    17200 uses
-    17300 uses
-    17400 uses
-    17500 uses
-    17600 uses
-    17700 uses
-    17800 uses
-    17900 uses
-    18000 uses
-    18100 uses
-    18200 uses
-    18300 uses
-    18400 uses
-    18500 uses
-    18600 uses
-    18700 uses
-    18800 uses
-    18900 uses
-    19000 uses
-    19100 uses
-    19200 uses
-    19300 uses
-    19400 uses
-    19500 uses
-    19600 uses
-    19700 uses
-    19800 uses
-    19900 uses
-    20000 uses
-    20100 uses
-    20200 uses
-    20300 uses
-    20400 uses
-    20500 uses
-    20600 uses
-    20700 uses
-    20800 uses
-    20900 uses
-    21000 uses
-    21100 uses
-    21200 uses
-    21300 uses
-    21400 uses
-    21500 uses
-    21600 uses
-    21700 uses
-    21800 uses
-    21900 uses
-    22000 uses
-    22100 uses
-    22200 uses
-    22300 uses
-    22400 uses
-    22500 uses
-    22600 uses
-    22700 uses
-    22800 uses
-    22900 uses
-    23000 uses
-    23100 uses
-    23200 uses
-    23300 uses
-    23400 uses
-    23500 uses
-    23600 uses
-    23700 uses
-    23800 uses
-    23900 uses
-    24000 uses
-    24100 uses
-    24200 uses
-    24300 uses
-    24400 uses
-    24500 uses
-    24600 uses
-    24700 uses
-    24800 uses
-    24900 uses
-    25000 uses
-    25100 uses
-    25200 uses
-    25300 uses
-    25400 uses
-    25500 uses
-    25600 uses
-    25700 uses
-    25800 uses
-    25900 uses
-    26000 uses
-    26100 uses
-    26200 uses
-    26300 uses
-    26400 uses
-    26500 uses
-    26600 uses
-    26700 uses
-    26800 uses
-    26900 uses
-    27000 uses
-    27100 uses
-    27200 uses
-    27300 uses
-    27400 uses
-    27500 uses
-    27600 uses
-    27700 uses
-    27800 uses
-    27900 uses
-    28000 uses
-    28100 uses
-    28200 uses
-    28300 uses
-    28400 uses
-    28500 uses
-    28600 uses
-    28700 uses
-    28800 uses
-    28900 uses
-    29000 uses
-    29100 uses
-    29200 uses
-    29300 uses
-    29400 uses
-    29500 uses
-    29600 uses
-    29700 uses
-    29800 uses
-    29900 uses
-    30000 uses
-    30100 uses
-    30200 uses
-    30300 uses
-    30400 uses
-    30500 uses
-    30600 uses
-    30700 uses
-    30800 uses
-    30900 uses
-    31000 uses
-    31100 uses
-    31200 uses
-    31300 uses
-    31400 uses
-    31500 uses
-    31600 uses
-    31700 uses
-    31800 uses
-    31900 uses
-    32000 uses
-    32100 uses
-    32200 uses
-    32300 uses
-    32400 uses
-    32500 uses
-    32600 uses
-    32700 uses
-    32800 uses
-    32900 uses
-    33000 uses
-    33100 uses
-    33200 uses
-    33300 uses
-    33400 uses
-    33500 uses
-    33600 uses
-    33700 uses
-    33800 uses
-    33900 uses
-    34000 uses
-    34100 uses
-    34200 uses
-    34300 uses
-    34400 uses
-    34500 uses
-    34600 uses
-    34700 uses
-    34800 uses
-    34900 uses
-    35000 uses
-    35100 uses
-    35200 uses
-    35300 uses
-    35400 uses
-    35500 uses
-    35600 uses
-    35700 uses
-    35800 uses
-    35900 uses
-    36000 uses
-    36100 uses
-    36200 uses
-    36300 uses
-    36400 uses
-    36500 uses
-    36600 uses
-    36700 uses
-    36800 uses
-    36900 uses
-    37000 uses
-    37100 uses
-    37200 uses
-    37300 uses
-    37400 uses
-    37500 uses
-    37600 uses
-    37700 uses
-    37800 uses
-    37900 uses
-    38000 uses
-    38100 uses
-    38200 uses
-    38300 uses
-    38400 uses
-    38500 uses
-    38600 uses
-    38700 uses
-    38800 uses
-    38900 uses
-    39000 uses
-    39100 uses
-    39200 uses
-    39300 uses
-    39400 uses
-    39500 uses
-    39600 uses
-    39700 uses
-    39800 uses
-    39900 uses
-    40000 uses
-    40100 uses
-    40200 uses
-    40300 uses
-    40400 uses
-    40500 uses
-    40600 uses
-    40700 uses
-    40800 uses
-    40900 uses
-    41000 uses
-    41100 uses
-    41200 uses
-    41300 uses
-    41400 uses
-    41500 uses
-    41600 uses
-    41700 uses
-    41800 uses
-    41900 uses
-    42000 uses
-    42100 uses
-    42200 uses
-    42300 uses
-    42400 uses
-    42500 uses
-    42600 uses
-    42700 uses
-    42800 uses
-    42900 uses
-    43000 uses
-    43100 uses
-    43200 uses
-    43300 uses
-    43400 uses
-    43500 uses
-    43600 uses
-    43700 uses
-    43800 uses
-    43900 uses
-    44000 uses
-    44100 uses
-    44200 uses
-    44300 uses
-    44400 uses
-    44500 uses
-    44600 uses
-    44700 uses
-    44800 uses
-    44900 uses
-    45000 uses
-    45100 uses
-    45200 uses
-    45300 uses
-    45400 uses
-    45500 uses
-    45600 uses
-    45700 uses
-    45800 uses
-    45900 uses
-    46000 uses
-    46100 uses
-    46200 uses
-    46300 uses
-    46400 uses
-    46500 uses
-    46600 uses
-    46700 uses
-    46800 uses
-    46900 uses
-    47000 uses
-    47100 uses
-    47200 uses
-    47300 uses
-    47400 uses
-Reading "sb_0__1_".
+Reading "sb_1__0_".
     100 uses
     200 uses
     300 uses
@@ -4470,179 +2114,194 @@
     10800 uses
     10900 uses
     11000 uses
-    11100 uses
-    11200 uses
-    11300 uses
-    11400 uses
-    11500 uses
-    11600 uses
-    11700 uses
-    11800 uses
-    11900 uses
-    12000 uses
-    12100 uses
-    12200 uses
-    12300 uses
-    12400 uses
-    12500 uses
-    12600 uses
-    12700 uses
-    12800 uses
-    12900 uses
-    13000 uses
-    13100 uses
-    13200 uses
-    13300 uses
-    13400 uses
-    13500 uses
-    13600 uses
-    13700 uses
-    13800 uses
-    13900 uses
-    14000 uses
-    14100 uses
-    14200 uses
-    14300 uses
-    14400 uses
-    14500 uses
-    14600 uses
-    14700 uses
-    14800 uses
-    14900 uses
-    15000 uses
-    15100 uses
-    15200 uses
-    15300 uses
-    15400 uses
-    15500 uses
-    15600 uses
-    15700 uses
-    15800 uses
-    15900 uses
-    16000 uses
-    16100 uses
-    16200 uses
-    16300 uses
-    16400 uses
-    16500 uses
-    16600 uses
-    16700 uses
-    16800 uses
-    16900 uses
-    17000 uses
-    17100 uses
-    17200 uses
-    17300 uses
-    17400 uses
-    17500 uses
-    17600 uses
-    17700 uses
-    17800 uses
-    17900 uses
-    18000 uses
-    18100 uses
-    18200 uses
-    18300 uses
-    18400 uses
-    18500 uses
-    18600 uses
-    18700 uses
-    18800 uses
-    18900 uses
-    19000 uses
-    19100 uses
-    19200 uses
-    19300 uses
-    19400 uses
-    19500 uses
-    19600 uses
-    19700 uses
-    19800 uses
-    19900 uses
-    20000 uses
-    20100 uses
-    20200 uses
-    20300 uses
-    20400 uses
-    20500 uses
-    20600 uses
-    20700 uses
-    20800 uses
-    20900 uses
-    21000 uses
-    21100 uses
-    21200 uses
-    21300 uses
-    21400 uses
-    21500 uses
-    21600 uses
-    21700 uses
-    21800 uses
-    21900 uses
-    22000 uses
-    22100 uses
-    22200 uses
-    22300 uses
-    22400 uses
-    22500 uses
-    22600 uses
-    22700 uses
-    22800 uses
-    22900 uses
-    23000 uses
-    23100 uses
-    23200 uses
-    23300 uses
-    23400 uses
-    23500 uses
-    23600 uses
-    23700 uses
-    23800 uses
-    23900 uses
-    24000 uses
-    24100 uses
-    24200 uses
-    24300 uses
-    24400 uses
-    24500 uses
-    24600 uses
-    24700 uses
-    24800 uses
-    24900 uses
-    25000 uses
-    25100 uses
-    25200 uses
-    25300 uses
-    25400 uses
-    25500 uses
-    25600 uses
-    25700 uses
-    25800 uses
-    25900 uses
-    26000 uses
-    26100 uses
-    26200 uses
-    26300 uses
-    26400 uses
-    26500 uses
-    26600 uses
-    26700 uses
-    26800 uses
-    26900 uses
-    27000 uses
-    27100 uses
-    27200 uses
-    27300 uses
-    27400 uses
-    27500 uses
-    27600 uses
-    27700 uses
-    27800 uses
-    27900 uses
-    28000 uses
-    28100 uses
-    28200 uses
-    28300 uses
+Reading "sb_0__2_".
+    100 uses
+    200 uses
+    300 uses
+    400 uses
+    500 uses
+    600 uses
+    700 uses
+    800 uses
+    900 uses
+    1000 uses
+    1100 uses
+    1200 uses
+    1300 uses
+    1400 uses
+    1500 uses
+    1600 uses
+    1700 uses
+    1800 uses
+    1900 uses
+    2000 uses
+    2100 uses
+    2200 uses
+    2300 uses
+    2400 uses
+    2500 uses
+    2600 uses
+    2700 uses
+    2800 uses
+    2900 uses
+    3000 uses
+    3100 uses
+    3200 uses
+    3300 uses
+    3400 uses
+    3500 uses
+    3600 uses
+    3700 uses
+    3800 uses
+    3900 uses
+    4000 uses
+    4100 uses
+    4200 uses
+    4300 uses
+    4400 uses
+    4500 uses
+    4600 uses
+Reading "sb_0__1_".
+    100 uses
+    200 uses
+    300 uses
+    400 uses
+    500 uses
+    600 uses
+    700 uses
+    800 uses
+    900 uses
+    1000 uses
+    1100 uses
+    1200 uses
+    1300 uses
+    1400 uses
+    1500 uses
+    1600 uses
+    1700 uses
+    1800 uses
+    1900 uses
+    2000 uses
+    2100 uses
+    2200 uses
+    2300 uses
+    2400 uses
+    2500 uses
+    2600 uses
+    2700 uses
+    2800 uses
+    2900 uses
+    3000 uses
+    3100 uses
+    3200 uses
+    3300 uses
+    3400 uses
+    3500 uses
+    3600 uses
+    3700 uses
+    3800 uses
+    3900 uses
+    4000 uses
+    4100 uses
+    4200 uses
+    4300 uses
+    4400 uses
+    4500 uses
+    4600 uses
+    4700 uses
+    4800 uses
+    4900 uses
+    5000 uses
+    5100 uses
+    5200 uses
+    5300 uses
+    5400 uses
+    5500 uses
+    5600 uses
+    5700 uses
+    5800 uses
+    5900 uses
+    6000 uses
+    6100 uses
+    6200 uses
+    6300 uses
+    6400 uses
+    6500 uses
+    6600 uses
+    6700 uses
+    6800 uses
+    6900 uses
+    7000 uses
+    7100 uses
+    7200 uses
+    7300 uses
+    7400 uses
+    7500 uses
+    7600 uses
+    7700 uses
+    7800 uses
+    7900 uses
+    8000 uses
+    8100 uses
+    8200 uses
+    8300 uses
+    8400 uses
+    8500 uses
+    8600 uses
+    8700 uses
+    8800 uses
+    8900 uses
+    9000 uses
+    9100 uses
+    9200 uses
+    9300 uses
+    9400 uses
+Reading "sb_0__0_".
+    100 uses
+    200 uses
+    300 uses
+    400 uses
+    500 uses
+    600 uses
+    700 uses
+    800 uses
+    900 uses
+    1000 uses
+    1100 uses
+    1200 uses
+    1300 uses
+    1400 uses
+    1500 uses
+    1600 uses
+    1700 uses
+    1800 uses
+    1900 uses
+    2000 uses
+    2100 uses
+    2200 uses
+    2300 uses
+    2400 uses
+    2500 uses
+    2600 uses
+    2700 uses
+    2800 uses
+    2900 uses
+    3000 uses
+    3100 uses
+    3200 uses
+    3300 uses
+    3400 uses
+    3500 uses
+    3600 uses
+    3700 uses
+    3800 uses
+    3900 uses
+    4000 uses
+    4100 uses
+    4200 uses
+    4300 uses
+    4400 uses
+    4500 uses
 Reading "grid_clb".
     100 uses
     200 uses
@@ -4742,204 +2401,6 @@
     9600 uses
     9700 uses
     9800 uses
-    9900 uses
-    10000 uses
-    10100 uses
-    10200 uses
-    10300 uses
-    10400 uses
-    10500 uses
-    10600 uses
-    10700 uses
-    10800 uses
-    10900 uses
-    11000 uses
-    11100 uses
-    11200 uses
-    11300 uses
-    11400 uses
-    11500 uses
-    11600 uses
-    11700 uses
-    11800 uses
-    11900 uses
-    12000 uses
-    12100 uses
-    12200 uses
-    12300 uses
-    12400 uses
-    12500 uses
-    12600 uses
-    12700 uses
-    12800 uses
-    12900 uses
-    13000 uses
-    13100 uses
-    13200 uses
-    13300 uses
-    13400 uses
-    13500 uses
-    13600 uses
-    13700 uses
-    13800 uses
-    13900 uses
-    14000 uses
-    14100 uses
-    14200 uses
-    14300 uses
-    14400 uses
-    14500 uses
-    14600 uses
-    14700 uses
-    14800 uses
-    14900 uses
-    15000 uses
-    15100 uses
-    15200 uses
-    15300 uses
-    15400 uses
-    15500 uses
-    15600 uses
-    15700 uses
-    15800 uses
-    15900 uses
-    16000 uses
-    16100 uses
-    16200 uses
-    16300 uses
-    16400 uses
-    16500 uses
-    16600 uses
-    16700 uses
-    16800 uses
-    16900 uses
-    17000 uses
-    17100 uses
-    17200 uses
-    17300 uses
-    17400 uses
-    17500 uses
-    17600 uses
-    17700 uses
-    17800 uses
-    17900 uses
-    18000 uses
-    18100 uses
-    18200 uses
-    18300 uses
-    18400 uses
-    18500 uses
-    18600 uses
-    18700 uses
-    18800 uses
-    18900 uses
-    19000 uses
-    19100 uses
-    19200 uses
-    19300 uses
-    19400 uses
-    19500 uses
-    19600 uses
-    19700 uses
-    19800 uses
-    19900 uses
-    20000 uses
-    20100 uses
-    20200 uses
-    20300 uses
-    20400 uses
-    20500 uses
-    20600 uses
-    20700 uses
-    20800 uses
-    20900 uses
-    21000 uses
-    21100 uses
-    21200 uses
-    21300 uses
-    21400 uses
-    21500 uses
-    21600 uses
-    21700 uses
-    21800 uses
-    21900 uses
-    22000 uses
-    22100 uses
-    22200 uses
-    22300 uses
-    22400 uses
-    22500 uses
-    22600 uses
-    22700 uses
-    22800 uses
-    22900 uses
-    23000 uses
-    23100 uses
-    23200 uses
-    23300 uses
-    23400 uses
-    23500 uses
-    23600 uses
-    23700 uses
-    23800 uses
-    23900 uses
-    24000 uses
-    24100 uses
-    24200 uses
-    24300 uses
-    24400 uses
-    24500 uses
-    24600 uses
-    24700 uses
-    24800 uses
-    24900 uses
-    25000 uses
-    25100 uses
-    25200 uses
-    25300 uses
-    25400 uses
-    25500 uses
-    25600 uses
-    25700 uses
-    25800 uses
-    25900 uses
-    26000 uses
-    26100 uses
-    26200 uses
-    26300 uses
-    26400 uses
-    26500 uses
-    26600 uses
-    26700 uses
-    26800 uses
-    26900 uses
-    27000 uses
-    27100 uses
-    27200 uses
-    27300 uses
-    27400 uses
-    27500 uses
-    27600 uses
-    27700 uses
-    27800 uses
-    27900 uses
-    28000 uses
-    28100 uses
-    28200 uses
-    28300 uses
-    28400 uses
-    28500 uses
-    28600 uses
-    28700 uses
-    28800 uses
-    28900 uses
-    29000 uses
-    29100 uses
-    29200 uses
-    29300 uses
-    29400 uses
-    29500 uses
-    29600 uses
 Reading "sky130_fd_io__overlay_vddio_hvc".
 Reading "sky130_fd_io__overlay_vccd_lvc".
 Reading "sky130_fd_io__top_power_lvc_wpad".
@@ -4971,7 +2432,7 @@
 Reading "sky130_fd_pr__via_m2m3__example_55959141808714".
 Reading "sky130_fd_pr__pfet_01v8__example_55959141808766".
 Reading "sky130_fd_io__gpio_buf_localesdv2".
-Error while reading cell "sky130_fd_io__gpio_buf_localesdv2" (byte position 64673052): Unknown layer/datatype in boundary, layer=81 type=6
+Error while reading cell "sky130_fd_io__gpio_buf_localesdv2" (byte position 43159236): Unknown layer/datatype in boundary, layer=81 type=6
 Reading "sky130_fd_io__com_res_weak_v2".
 Reading "sky130_fd_io__xres_inv_hysv2".
 Reading "sky130_fd_io__tk_tie_r_out_esd".
@@ -4982,73 +2443,73 @@
     100 uses
 Reading "sky130_fd_io__corner_bus_overlay".
 Reading "sky130_fd_sc_hvl__conb_1".
-Error while reading cell "sky130_fd_sc_hvl__conb_1" (byte position 69081326): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hvl__conb_1" (byte position 47563238): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__and3b_4".
-Error while reading cell "sky130_fd_sc_hd__and3b_4" (byte position 69088170): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__and3b_4" (byte position 47570218): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__mux4_1".
-Error while reading cell "sky130_fd_sc_hd__mux4_1" (byte position 69103714): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__mux4_1" (byte position 47580788): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__nor3b_4".
-Error while reading cell "sky130_fd_sc_hd__nor3b_4" (byte position 69113882): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__nor3b_4" (byte position 47593118): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__clkbuf_4".
-Error while reading cell "sky130_fd_sc_hd__clkbuf_4" (byte position 69119108): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__clkbuf_4" (byte position 47601992): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__nor4b_2".
-Error while reading cell "sky130_fd_sc_hd__nor4b_2" (byte position 69128446): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__nor4b_2" (byte position 47608320): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__and4b_2".
-Error while reading cell "sky130_fd_sc_hd__and4b_2" (byte position 69136726): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__and4b_2" (byte position 47617386): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__and4bb_2".
-Error while reading cell "sky130_fd_sc_hd__and4bb_2" (byte position 69144732): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__and4bb_2" (byte position 47626084): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__and4_2".
-Error while reading cell "sky130_fd_sc_hd__and4_2" (byte position 69152018): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__and4_2" (byte position 47633190): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__dlclkp_1".
-Error while reading cell "sky130_fd_sc_hd__dlclkp_1" (byte position 69162054): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__dlclkp_1" (byte position 47642560): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__and2_1".
-Error while reading cell "sky130_fd_sc_hd__and2_1" (byte position 69166964): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__and2_1" (byte position 47649984): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__dfxtp_1".
-Error while reading cell "sky130_fd_sc_hd__dfxtp_1" (byte position 69179094): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__dfxtp_1" (byte position 47658048): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__or2_2".
-Error while reading cell "sky130_fd_sc_hd__or2_2" (byte position 69183518): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__or2_2" (byte position 47667102): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__einvp_1".
-Error while reading cell "sky130_fd_sc_hd__einvp_1" (byte position 69188098): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__einvp_1" (byte position 47671498): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__clkinv_2".
-Error while reading cell "sky130_fd_sc_hd__clkinv_2" (byte position 69192410): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__clkinv_2" (byte position 47675872): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__clkinv_8".
-Error while reading cell "sky130_fd_sc_hd__clkinv_8" (byte position 69201670): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__clkinv_8" (byte position 47681048): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__einvn_8".
-Error while reading cell "sky130_fd_sc_hd__einvn_8" (byte position 69214002): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__einvn_8" (byte position 47691458): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__clkbuf_2".
-Error while reading cell "sky130_fd_sc_hd__clkbuf_2" (byte position 69218606): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__clkbuf_2" (byte position 47702048): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__einvp_2".
-Error while reading cell "sky130_fd_sc_hd__einvp_2" (byte position 69224862): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__einvp_2" (byte position 47707050): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__einvn_4".
-Error while reading cell "sky130_fd_sc_hd__einvn_4" (byte position 69232708): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__einvn_4" (byte position 47713738): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__and4_4".
-Error while reading cell "sky130_fd_sc_hd__and4_4" (byte position 69240166): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__and4_4" (byte position 47721454): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__a22oi_4".
-Error while reading cell "sky130_fd_sc_hd__a22oi_4" (byte position 69252226): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__a22oi_4" (byte position 47729698): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__a21o_4".
-Error while reading cell "sky130_fd_sc_hd__a21o_4" (byte position 69268572): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__a21o_4" (byte position 47741292): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__a21bo_4".
-Error while reading cell "sky130_fd_sc_hd__a21bo_4" (byte position 69285150): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__a21bo_4" (byte position 47749734): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__o21ai_4".
-Error while reading cell "sky130_fd_sc_hd__o21ai_4" (byte position 69301340): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__o21ai_4" (byte position 47757666): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__o32a_4".
-Error while reading cell "sky130_fd_sc_hd__o32a_4" (byte position 69313720): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__o32a_4" (byte position 47766858): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__or4_4".
-Error while reading cell "sky130_fd_sc_hd__or4_4" (byte position 69328228): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__or4_4" (byte position 47777940): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__o22a_4".
-Error while reading cell "sky130_fd_sc_hd__o22a_4" (byte position 69347562): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__o22a_4" (byte position 47786070): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__ebufn_2".
-Error while reading cell "sky130_fd_sc_hd__ebufn_2" (byte position 69354890): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__ebufn_2" (byte position 47794902): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__nor2_4".
-Error while reading cell "sky130_fd_sc_hd__nor2_4" (byte position 69369000): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__nor2_4" (byte position 47801876): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__or3_4".
-Error while reading cell "sky130_fd_sc_hd__or3_4" (byte position 69383196): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__or3_4" (byte position 47809132): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__a2bb2o_4".
-Error while reading cell "sky130_fd_sc_hd__a2bb2o_4" (byte position 69406088): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__a2bb2o_4" (byte position 47817814): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__o21a_4".
-Error while reading cell "sky130_fd_sc_hd__o21a_4" (byte position 69414144): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__o21a_4" (byte position 47828148): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__a211o_4".
-Error while reading cell "sky130_fd_sc_hd__a211o_4" (byte position 69432282): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__a211o_4" (byte position 47836702): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "pk_sram_1rw1r_32_256_8_sky130".
     100 uses
     200 uses
@@ -6609,44 +4070,40 @@
     155700 uses
     155800 uses
 Reading "sky130_fd_sc_hd__and3_4".
-Error while reading cell "sky130_fd_sc_hd__and3_4" (byte position 75766824): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__and3_4" (byte position 54165608): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__clkbuf_16".
-Error while reading cell "sky130_fd_sc_hd__clkbuf_16" (byte position 75792228): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__clkbuf_16" (byte position 54173910): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__and2_4".
-Error while reading cell "sky130_fd_sc_hd__and2_4" (byte position 75803682): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__and2_4" (byte position 54184986): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__a32o_4".
-Error while reading cell "sky130_fd_sc_hd__a32o_4" (byte position 75828036): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__a32o_4" (byte position 54192548): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__nand2_4".
-Error while reading cell "sky130_fd_sc_hd__nand2_4" (byte position 75843282): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__nand2_4" (byte position 54203058): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__or2_4".
-Error while reading cell "sky130_fd_sc_hd__or2_4" (byte position 75854766): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__or2_4" (byte position 54210608): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__dfrtp_4".
-Error while reading cell "sky130_fd_sc_hd__dfrtp_4" (byte position 75872762): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__dfrtp_4" (byte position 54221616): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__decap_8".
-Error while reading cell "sky130_fd_sc_hd__decap_8" (byte position 75879720): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__decap_8" (byte position 54233416): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
 Reading "sky130_fd_sc_hd__decap_4".
-Error while reading cell "sky130_fd_sc_hd__decap_4" (byte position 75891818): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__decap_4" (byte position 54240290): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__decap_12".
-Error while reading cell "sky130_fd_sc_hd__decap_12" (byte position 75900058): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__decap_12" (byte position 54243030): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__decap_3".
-Error while reading cell "sky130_fd_sc_hd__decap_3" (byte position 75905352): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__decap_3" (byte position 54247240): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__decap_6".
-Error while reading cell "sky130_fd_sc_hd__decap_6" (byte position 75911606): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__decap_6" (byte position 54249882): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hvl__lsbufhv2lv_1".
-Error while reading cell "sky130_fd_sc_hvl__lsbufhv2lv_1" (byte position 75930310): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hvl__lsbufhv2lv_1" (byte position 54258326): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hvl__fill_2".
-Error while reading cell "sky130_fd_sc_hvl__fill_2" (byte position 75933178): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hvl__fill_2" (byte position 54272138): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hvl__fill_1".
-Error while reading cell "sky130_fd_sc_hvl__fill_1" (byte position 75935614): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hvl__fill_1" (byte position 54274958): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hvl__decap_8".
-Error while reading cell "sky130_fd_sc_hvl__decap_8" (byte position 75942502): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hvl__decap_8" (byte position 54278198): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hvl__decap_4".
-Error while reading cell "sky130_fd_sc_hvl__decap_4" (byte position 75947310): Unknown layer/datatype in boundary, layer=236 type=0
-Reading "sky130_fd_sc_hd__dfxtp_4".
-Error while reading cell "sky130_fd_sc_hd__dfxtp_4" (byte position 75975580): Unknown layer/datatype in boundary, layer=236 type=0
-Reading "sky130_fd_sc_hd__diode_2".
-Error while reading cell "sky130_fd_sc_hd__diode_2" (byte position 75982418): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hvl__decap_4" (byte position 54284862): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "fpga_top".
     100 uses
     200 uses
@@ -10075,6862 +7532,6 @@
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-    1028300 uses
 Reading "sky130_ef_io__vddio_hvc_pad".
 Reading "sky130_ef_io__disconnect_vccd_slice_5um".
 Reading "sky130_ef_io__disconnect_vdda_slice_5um".
@@ -17363,9 +7964,9 @@
     40100 uses
     40200 uses
 Reading "sky130_fd_sc_hd__a41o_4".
-Error while reading cell "sky130_fd_sc_hd__a41o_4" (byte position 192169638): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__a41o_4" (byte position 127127052): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__o41a_4".
-Error while reading cell "sky130_fd_sc_hd__o41a_4" (byte position 192182810): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__o41a_4" (byte position 127139522): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "digital_pll".
     100 uses
     200 uses
@@ -17380,14 +7981,18 @@
     1100 uses
     1200 uses
 Reading "sky130_fd_sc_hd__a2111o_4".
-Error while reading cell "sky130_fd_sc_hd__a2111o_4" (byte position 194580694): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__a2111o_4" (byte position 129538238): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__a21oi_4".
-Error while reading cell "sky130_fd_sc_hd__a21oi_4" (byte position 194589296): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__a21oi_4" (byte position 129549700): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Error while reading cell "sky130_fd_sc_hd__dfxtp_4" (byte position 129560590): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sram_1rw1r_32_256_8_sky130".
 Reading "sky130_fd_sc_hd__dfstp_4".
-Error while reading cell "sky130_fd_sc_hd__dfstp_4" (byte position 194630678): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__dfstp_4" (byte position 129599540): Unknown layer/datatype in boundary, layer=236 type=0
+Reading "sky130_fd_sc_hd__diode_2".
+Error while reading cell "sky130_fd_sc_hd__diode_2" (byte position 129611794): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hd__einvp_8".
-Error while reading cell "sky130_fd_sc_hd__einvp_8" (byte position 194643368): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hd__einvp_8" (byte position 129618204): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_pr__pfet_g5v0d10v5_ZEUEFZ".
 Reading "sky130_fd_pr__nfet_g5v0d10v5_ZK8HQC".
 Reading "sky130_fd_pr__nfet_g5v0d10v5_TGFUGS".
@@ -17397,14 +8002,14 @@
 Reading "sky130_fd_pr__pfet_g5v0d10v5_3YBPVB".
 Reading "sky130_fd_pr__pfet_g5v0d10v5_YUHPXE".
 Reading "sky130_fd_sc_hvl__buf_8".
-Error while reading cell "sky130_fd_sc_hvl__buf_8" (byte position 194751174): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hvl__buf_8" (byte position 129718556): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hvl__schmittbuf_1".
-Error while reading cell "sky130_fd_sc_hvl__schmittbuf_1" (byte position 194762346): Unknown layer/datatype in boundary, layer=236 type=0
-Error while reading cell "sky130_fd_sc_hvl__schmittbuf_1" (byte position 194762410): Unknown layer/datatype in boundary, layer=65 type=14
+Error while reading cell "sky130_fd_sc_hvl__schmittbuf_1" (byte position 129738526): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hvl__schmittbuf_1" (byte position 129746250): Unknown layer/datatype in boundary, layer=65 type=14
 Reading "sky130_fd_sc_hvl__inv_8".
-Error while reading cell "sky130_fd_sc_hvl__inv_8" (byte position 194779708): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hvl__inv_8" (byte position 129749582): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_sc_hvl__fill_4".
-Error while reading cell "sky130_fd_sc_hvl__fill_4" (byte position 194783296): Unknown layer/datatype in boundary, layer=236 type=0
+Error while reading cell "sky130_fd_sc_hvl__fill_4" (byte position 129765120): Unknown layer/datatype in boundary, layer=236 type=0
 Reading "sky130_fd_pr__res_xhigh_po_0p69_S5N9F3".
 Reading "sky130_fd_pr__cap_mim_m3_2_W5U4AW".
 Reading "sky130_fd_pr__cap_mim_m3_1_WRT4AW".

checks/magic_merge_user_project_wrapper.log

diff --git a/checks/magic_merge_user_project_wrapper.log b/checks/magic_merge_user_project_wrapper.log
index a81f71f..19bbd9b 100644
--- a/checks/magic_merge_user_project_wrapper.log
+++ b/checks/magic_merge_user_project_wrapper.log
@@ -12,7 +12,7 @@
 Loading "../SOFA-Chips/SCRIPT/merge_fpga_top.tcl" from command line.
 Warning: Calma reading is not undoable!  I hope that's OK.
 Library written using GDS-II Release 5.0
-Library name: fpga_top_icv_in_design.gdsgz.merge566544152
+Library name: fpga_top_icv_in_design.gdsgz.merge1354503035
 Reading "sky130_fd_sc_hd__a2111o_1".
 Reading "sky130_fd_sc_hd__a2111o_2".
 Reading "sky130_fd_sc_hd__a2111o_4".
@@ -5189,17 +5189,17 @@
    Writing cell $$M2M3_PR
    Writing cell $$M1M2_PR
    Writing cell $$M4M5_PR_16000_16000_2_1
-   Writing cell sky130_fd_sc_hd__fill_2
-   Writing cell sky130_fd_sc_hd__fill_8
    Writing cell sky130_fd_sc_hd__fill_4
+   Writing cell sky130_fd_sc_hd__fill_8
    Writing cell sky130_fd_sc_hd__fill_1
+   Writing cell sky130_fd_sc_hd__fill_2
    Writing cell sky130_fd_sc_hd__buf_1
    Writing cell sky130_fd_sc_hd__clkbuf_1
+   Writing cell sky130_fd_sc_hd__buf_2
    Writing cell sky130_fd_sc_hd__buf_6
    Writing cell sky130_fd_sc_hd__bufbuf_16
    Writing cell sky130_fd_sc_hd__buf_4
    Writing cell sky130_fd_sc_hd__buf_8
-   Writing cell sky130_fd_sc_hd__buf_2
    Writing cell sky130_fd_sc_hd__dfrtp_1
    Writing cell sky130_uuopenfpga_cc_hd_invmux3_1
    Writing cell sky130_fd_sc_hd__nor2_1
@@ -5208,9 +5208,9 @@
    Writing cell sky130_fd_sc_hd__inv_1
    Writing cell sky130_fd_sc_hd__sdfrtp_1
    Writing cell sky130_fd_sc_hd__mux2_1
+   Writing cell sky130_fd_sc_hd__inv_2
    Writing cell sky130_fd_sc_hd__or2_0
    Writing cell sky130_fd_sc_hd__inv_8
-   Writing cell sky130_fd_sc_hd__inv_2
    Writing cell sky130_fd_sc_hd__dlygate4sd1_1
    Writing cell sky130_fd_sc_hd__dlygate4sd3_1
    Writing cell sky130_fd_sc_hd__clkbuf_8

checks/manifest_check.mag.log

diff --git a/checks/manifest_check.mag.log b/checks/manifest_check.mag.log
index 293ab27..40c81e2 100644
--- a/checks/manifest_check.mag.log
+++ b/checks/manifest_check.mag.log
@@ -1,2 +1,2 @@
 caravel.mag: OK
-.magicrc: FAILED
+.magicrc: OK

checks/spdx_compliance_report.log

diff --git a/checks/spdx_compliance_report.log b/checks/spdx_compliance_report.log
index 023741b..cbc42ba 100644
--- a/checks/spdx_compliance_report.log
+++ b/checks/spdx_compliance_report.log
@@ -4,8 +4,6 @@
 /usr/local/workspace/Caravel-SOFA-CHD/source_commit_hash.txt
 /usr/local/workspace/Caravel-SOFA-CHD/doc/caravel_datasheet.ps
 /usr/local/workspace/Caravel-SOFA-CHD/mag/clamp_list.txt
-/usr/local/workspace/Caravel-SOFA-CHD/mag/.magicrc
-/usr/local/workspace/Caravel-SOFA-CHD/maglef/.magicrc
 /usr/local/workspace/Caravel-SOFA-CHD/openlane/chip_dimensions.txt
 /usr/local/workspace/Caravel-SOFA-CHD/openlane/mgmt_protect/pdn.tcl
 /usr/local/workspace/Caravel-SOFA-CHD/spi/lvs/DFFRAM.spice

gds/caravel.gds.gz

diff --git a/gds/caravel.gds.gz b/gds/caravel.gds.gz
index e7d23e1..44f8a3c 100644
--- a/gds/caravel.gds.gz
+++ b/gds/caravel.gds.gz
Binary files differ

gds/fpga_top_icv_in_design.gds.gz.sha1

diff --git a/gds/fpga_top_icv_in_design.gds.gz.sha1 b/gds/fpga_top_icv_in_design.gds.gz.sha1
new file mode 100644
index 0000000..61f76cd
--- /dev/null
+++ b/gds/fpga_top_icv_in_design.gds.gz.sha1
@@ -0,0 +1 @@
+0e8c834d847b254163f74bf3cc1a780f5d87c5be ./gds/fpga_top_icv_in_design.gds.gz

gds/user_project_wrapper.gds.gz

diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index 4a873b8..d33ce77 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ

source_commit_hash.txt

diff --git a/source_commit_hash.txt b/source_commit_hash.txt
index 68728c6..23289f0 100644
--- a/source_commit_hash.txt
+++ b/source_commit_hash.txt
@@ -1,4 +1,7 @@
 = = = = = = = = = = = = = = = =
+Date       Sun Dec 27 16:26:44 UTC 2020
+GITHUB_SHA -
+= = = = = = = = = = = = = = = =
 Date       Sun Dec 20 23:06:10 UTC 2020
 GITHUB_SHA -
 = = = = = = = = = = = = = = = =

verilog/OpenFPGA_Verilog/fabric_netlists.v

diff --git a/verilog/OpenFPGA_Verilog/fabric_netlists.v b/verilog/OpenFPGA_Verilog/fabric_netlists.v
index 6529b19..d818117 100644
--- a/verilog/OpenFPGA_Verilog/fabric_netlists.v
+++ b/verilog/OpenFPGA_Verilog/fabric_netlists.v
@@ -12,18 +12,18 @@
 `include "./SRC/fpga_defines.v"
 
 //
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_1.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfrtp/sky130_fd_sc_hd__dfrtp_1.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v"
-`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/sky130_fd_sc_hd_wrapper.v"
+`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v"
+`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v"
+`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v"
+`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v"
+`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"
+`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v"
+`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
+`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
+`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_1.v"
+`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfrtp/sky130_fd_sc_hd__dfrtp_1.v"
+`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v"
+`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/sky130_fd_sc_hd_wrapper.v"
 //
 `include "./SRC/sub_module/inv_buf_passgate.v"
 `include "./SRC/sub_module/arch_encoder.v"

verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v

diff --git a/verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v b/verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v
index ec041fb..4b5409c 100644
--- a/verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v
+++ b/verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v
@@ -76,7 +76,8 @@
 
 wire [0:0] direct_interc_10_out;
 wire [0:0] direct_interc_11_out;
-wire [0:0] direct_interc_2_out;
+wire [0:0] direct_interc_12_out;
+wire [0:0] direct_interc_13_out;
 wire [0:0] direct_interc_3_out;
 wire [0:0] direct_interc_4_out;
 wire [0:0] direct_interc_5_out;
@@ -87,9 +88,8 @@
 wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q;
 wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q;
 wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail;
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout;
 wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out;
-wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin;
-wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cout;
 wire [0:0] mux_1level_size2_0_out;
 wire [0:1] mux_1level_size2_0_sram;
 wire [0:0] mux_1level_size2_1_out;
@@ -112,28 +112,28 @@
 	logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
 		.pReset(pReset[0]),
 		.prog_clk(prog_clk[0]),
-		.frac_logic_in({direct_interc_2_out[0], direct_interc_3_out[0], direct_interc_4_out[0], direct_interc_5_out[0]}),
-		.frac_logic_cin(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin[0]),
+		.frac_logic_in({direct_interc_3_out[0], direct_interc_4_out[0], direct_interc_5_out[0], direct_interc_6_out[0]}),
+		.frac_logic_cin(direct_interc_7_out[0]),
 		.ccff_head(ccff_head[0]),
 		.frac_logic_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0:1]),
-		.frac_logic_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cout[0]),
+		.frac_logic_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout[0]),
 		.ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail[0]));
 
 	logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
 		.Test_en(Test_en[0]),
 		.ff_D(mux_1level_size2_0_out[0]),
-		.ff_DI(direct_interc_6_out[0]),
-		.ff_reset(direct_interc_7_out[0]),
+		.ff_DI(direct_interc_8_out[0]),
+		.ff_reset(direct_interc_9_out[0]),
 		.ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]),
-		.ff_clk(direct_interc_8_out[0]));
+		.ff_clk(direct_interc_10_out[0]));
 
 	logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
 		.Test_en(Test_en[0]),
 		.ff_D(mux_1level_size2_1_out[0]),
-		.ff_DI(direct_interc_9_out[0]),
-		.ff_reset(direct_interc_10_out[0]),
+		.ff_DI(direct_interc_11_out[0]),
+		.ff_reset(direct_interc_12_out[0]),
 		.ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]),
-		.ff_clk(direct_interc_11_out[0]));
+		.ff_clk(direct_interc_13_out[0]));
 
 	mux_1level_tapbuf_size2 mux_fabric_out_0 (
 		.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]}),
@@ -170,45 +170,53 @@
 		.out(fabric_sc_out[0]));
 
 	direct_interc direct_interc_2_ (
-		.in(fabric_in[0]),
-		.out(direct_interc_2_out[0]));
+		.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout[0]),
+		.out(fabric_cout[0]));
 
 	direct_interc direct_interc_3_ (
-		.in(fabric_in[1]),
+		.in(fabric_in[0]),
 		.out(direct_interc_3_out[0]));
 
 	direct_interc direct_interc_4_ (
-		.in(fabric_in[2]),
+		.in(fabric_in[1]),
 		.out(direct_interc_4_out[0]));
 
 	direct_interc direct_interc_5_ (
-		.in(fabric_in[3]),
+		.in(fabric_in[2]),
 		.out(direct_interc_5_out[0]));
 
 	direct_interc direct_interc_6_ (
-		.in(fabric_sc_in[0]),
+		.in(fabric_in[3]),
 		.out(direct_interc_6_out[0]));
 
 	direct_interc direct_interc_7_ (
-		.in(fabric_reset[0]),
+		.in(fabric_cin[0]),
 		.out(direct_interc_7_out[0]));
 
 	direct_interc direct_interc_8_ (
-		.in(fabric_clk[0]),
+		.in(fabric_sc_in[0]),
 		.out(direct_interc_8_out[0]));
 
 	direct_interc direct_interc_9_ (
-		.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]),
+		.in(fabric_reset[0]),
 		.out(direct_interc_9_out[0]));
 
 	direct_interc direct_interc_10_ (
-		.in(fabric_reset[0]),
+		.in(fabric_clk[0]),
 		.out(direct_interc_10_out[0]));
 
 	direct_interc direct_interc_11_ (
-		.in(fabric_clk[0]),
+		.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]),
 		.out(direct_interc_11_out[0]));
 
+	direct_interc direct_interc_12_ (
+		.in(fabric_reset[0]),
+		.out(direct_interc_12_out[0]));
+
+	direct_interc direct_interc_13_ (
+		.in(fabric_clk[0]),
+		.out(direct_interc_13_out[0]));
+
 	mux_1level_size2 mux_ff_0_D_0 (
 		.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0], fabric_reg_in[0]}),
 		.sram(mux_1level_size2_0_sram[0:1]),

verilog/gl/caravel_sofa_chd_top.v

diff --git a/verilog/gl/caravel_sofa_chd_top.v b/verilog/gl/caravel_sofa_chd_top.v
index cb5b743..8d31ce2 100644
--- a/verilog/gl/caravel_sofa_chd_top.v
+++ b/verilog/gl/caravel_sofa_chd_top.v
@@ -5,30 +5,35 @@
 //
 //
 module cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , 
-    prog_clk , ccff_head , ccff_tail , mem_out ) ;
+    prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:0] mem_out ;
+input  VDD ;
+input  VSS ;
 
 wire copt_net_117 ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_117 ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_117 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( copt_net_118 ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1368 ( .A ( copt_net_117 ) , 
-    .X ( copt_net_115 ) ) ;
+    .X ( copt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1370 ( .A ( copt_net_115 ) , 
-    .X ( mem_out[0] ) ) ;
+    .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1371 ( .A ( mem_out[0] ) , 
-    .X ( copt_net_118 ) ) ;
+    .X ( copt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
-    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ;
 input  SOC_IN ;
 output SOC_OUT ;
 output SOC_DIR ;
@@ -36,25 +41,34 @@
 input  FPGA_OUT ;
 input  FPGA_DIR ;
 input  IO_ISOL_N ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
-    .B ( IO_ISOL_N ) , .Y ( aps_rename_513_ ) ) ;
-sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_79 ) , .Y ( SOC_DIR_N ) ) ;
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_513_ ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_79 ) , .Y ( SOC_DIR_N ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
-    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
-    .TE_B ( BUF_net_79 ) , .Z ( SOC_OUT ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_81 ) , .Y ( BUF_net_79 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( SOC_DIR ) ) ;
+    .TE_B ( BUF_net_79 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_81 ) , .Y ( BUF_net_79 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( SOC_DIR ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( aps_rename_513_ ) , 
-    .Y ( BUF_net_81 ) ) ;
+    .Y ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , 
     prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
-    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ;
 input  [0:0] IO_ISOL_N ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
@@ -65,25 +79,31 @@
 input  [0:0] ccff_head ;
 output [0:0] iopad_inpad ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] EMBEDDED_IO_HD_0_en ;
+supply1 VDD ;
+supply0 VSS ;
 
 cby_2__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( 
     .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
     .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
     .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
     .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
-    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
-    ccff_tail ) ;
+    ccff_tail , VDD , VSS ) ;
 input  [0:0] IO_ISOL_N ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
@@ -94,6 +114,11 @@
 input  [0:0] ccff_head ;
 output [0:0] io_inpad ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 cby_2__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( 
     .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
@@ -101,296 +126,428 @@
     .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
     .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
     .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
-    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size10_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size10_mem_6 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size10_mem_5 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size10_mem_4 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size10_mem_3 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size10_mem_2 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size10_mem_1 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size10_mem_0 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input2_mem2 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input2_mem2 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_58 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_58 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_57 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_57 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_32 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_32 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size10 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size10 ( in , sram , sram_inv , out , VDD , VSS , 
+    p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -401,166 +558,225 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_512_ ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_512_ ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_32 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_57 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_58 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cby_2__1__mux_2level_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( aps_rename_512_ ) , 
-    .Y ( BUF_net_100 ) ) ;
+    .Y ( BUF_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input2_mem2_6 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input2_mem2_6 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_56 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_55 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_55 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_54 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_54 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_31 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_31 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_30 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_30 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size10_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -571,166 +787,225 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_511_ ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_511_ ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_30 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_31 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_54 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_55 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_56 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cby_2__1__mux_2level_basis_input2_mem2_6 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_511_ ) , 
-    .Y ( BUF_net_98 ) ) ;
+    .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input2_mem2_5 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input2_mem2_5 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_53 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_52 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_52 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_51 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_51 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_29 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_29 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_28 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_28 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size10_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -741,166 +1016,225 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_510_ ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_510_ ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_28 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_29 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_51 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_52 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_53 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cby_2__1__mux_2level_basis_input2_mem2_5 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( aps_rename_510_ ) , 
-    .Y ( BUF_net_96 ) ) ;
+    .Y ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input2_mem2_4 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input2_mem2_4 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_50 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_49 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_49 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_48 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_48 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_27 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_27 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_26 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_26 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size10_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -911,163 +1245,221 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_27 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_48 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_49 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_50 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cby_2__1__mux_2level_basis_input2_mem2_4 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input2_mem2_3 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input2_mem2_3 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_47 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_46 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_46 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_45 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_45 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_25 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_25 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_24 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_24 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size10_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -1078,163 +1470,221 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_24 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_25 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_45 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_46 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_47 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cby_2__1__mux_2level_basis_input2_mem2_3 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input2_mem2_2 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input2_mem2_2 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_44 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_43 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_43 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_42 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_42 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_23 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_23 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_22 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_22 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size10_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -1245,166 +1695,225 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_509_ ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_509_ ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_22 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_23 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_42 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_43 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_44 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cby_2__1__mux_2level_basis_input2_mem2_2 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_509_ ) , 
-    .Y ( BUF_net_94 ) ) ;
+    .Y ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input2_mem2_1 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input2_mem2_1 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_41 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_40 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_40 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_39 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_39 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_21 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_21 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_20 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_20 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size10_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -1415,164 +1924,223 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_92 ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_92 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_20 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_21 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_39 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_40 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_41 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cby_2__1__mux_2level_basis_input2_mem2_1 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_92 ( .A ( net_net_92 ) , .X ( out[0] ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_92 ( .A ( net_net_92 ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input2_mem2_0 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input2_mem2_0 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_38 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_37 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_37 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_36 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_36 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_19 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_19 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_18 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_18 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size10_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -1583,366 +2151,515 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_18 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_19 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_36 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_37 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_38 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cby_2__1__mux_2level_basis_input2_mem2_0 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size12_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size12_mem_7 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size12_mem_6 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size12_mem_5 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size12_mem_4 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size12_mem_3 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size12_mem_2 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size12_mem_1 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_size12_mem_0 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_123 ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1361 ( .A ( ccff_head[0] ) , 
-    .X ( copt_net_108 ) ) ;
+    .X ( copt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1362 ( .A ( copt_net_108 ) , 
-    .X ( copt_net_109 ) ) ;
+    .X ( copt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1363 ( .A ( copt_net_111 ) , 
-    .X ( copt_net_110 ) ) ;
+    .X ( copt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1364 ( .A ( copt_net_109 ) , 
-    .X ( copt_net_111 ) ) ;
+    .X ( copt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1365 ( .A ( copt_net_110 ) , 
-    .X ( copt_net_112 ) ) ;
+    .X ( copt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1366 ( .A ( copt_net_112 ) , 
-    .X ( copt_net_113 ) ) ;
+    .X ( copt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1374 ( .A ( copt_net_113 ) , 
-    .X ( ropt_net_121 ) ) ;
+    .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1375 ( .A ( ropt_net_121 ) , 
-    .X ( ropt_net_122 ) ) ;
+    .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 ropt_h_inst_1376 ( .A ( ropt_net_122 ) , 
-    .X ( ropt_net_123 ) ) ;
+    .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_35 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_34 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_34 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_33 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_33 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_32 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_32 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_17 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_17 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_16 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_16 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size12 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size12 ( in , sram , sram_inv , out , VDD , VSS , 
+    p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -1953,171 +2670,231 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_508_ ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_508_ ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_17 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_32 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_33 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_34 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_35 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( aps_rename_508_ ) , 
-    .Y ( BUF_net_91 ) ) ;
+    .Y ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_31 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_30 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_30 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_29 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_29 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_28 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_28 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_15 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_15 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_14 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_14 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size12_7 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size12_7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -2128,168 +2905,227 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_15 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_28 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_29 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_30 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_31 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_27 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_26 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_26 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_25 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_25 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_24 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_24 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_13 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_13 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_12 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_12 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size12_6 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size12_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -2300,171 +3136,231 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_13 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_24 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_25 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_26 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_507_ ) , 
-    .Y ( BUF_net_89 ) ) ;
+    .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_23 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_22 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_22 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_21 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_21 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_20 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_20 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_11 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_11 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_10 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_10 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size12_5 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size12_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -2475,169 +3371,229 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_87 ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_87 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_11 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_20 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_21 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_22 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( net_net_87 ) , .X ( out[0] ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( net_net_87 ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_19 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_18 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_18 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_17 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_17 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_16 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_16 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_9 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_9 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_8 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_8 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size12_4 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size12_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -2648,168 +3604,227 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_8 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_9 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_16 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_17 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_18 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_15 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_14 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_14 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_13 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_13 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_12 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_12 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_7 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_7 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_6 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_6 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size12_3 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size12_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -2820,171 +3835,231 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_7 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_12 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_13 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_14 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_15 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( aps_rename_506_ ) , 
-    .Y ( BUF_net_86 ) ) ;
+    .Y ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_11 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_10 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_10 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_9 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_9 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_8 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_8 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_5 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_5 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_4 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size12_2 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size12_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -2995,169 +4070,229 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_84 ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_84 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_5 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_8 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_9 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_10 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( net_net_84 ) , .X ( out[0] ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( net_net_84 ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_7 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_6 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_6 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_5 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_5 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_4 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_4 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_3 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_2 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_2 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size12_1 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size12_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -3168,168 +4303,227 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_3 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_4 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_5 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_6 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_7 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module cby_2__1__mux_2level_basis_input4_mem4_3 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_2 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_2 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_1 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_1 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_basis_input4_mem4_0 ( in , mem , mem_inv , out ) ;
+module cby_2__1__mux_2level_basis_input4_mem4_0 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_1 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_1 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__local_encoder2to4_0 ( addr , data , data_inv ) ;
+module cby_2__1__local_encoder2to4_0 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_2__1__mux_2level_size12_0 ( in , sram , sram_inv , out , p0 ) ;
+module cby_2__1__mux_2level_size12_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -3340,37 +4534,45 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_2__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__local_encoder2to4_1 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_0 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_1 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_2 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_basis_input4_mem4_3 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( aps_rename_505_ ) , 
-    .Y ( BUF_net_83 ) ) ;
+    .Y ( BUF_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
@@ -3385,7 +4587,7 @@
     gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
     left_width_0_height_0__pin_0_ , left_width_0_height_0__pin_1_upper , 
     left_width_0_height_0__pin_1_lower , pReset_S_in , prog_clk_0_W_in , 
-    prog_clk_0_S_out , prog_clk_0_N_out ) ;
+    prog_clk_0_S_out , prog_clk_0_N_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:29] chany_bottom_in ;
 input  [0:29] chany_top_in ;
@@ -3421,6 +4623,8 @@
 input  prog_clk_0_W_in ;
 output prog_clk_0_S_out ;
 output prog_clk_0_N_out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] prog_clk ;
 wire prog_clk_0 ;
@@ -3457,6 +4661,8 @@
 wire [0:0] mux_2level_size12_mem_6_ccff_tail ;
 wire [0:0] mux_2level_size12_mem_7_ccff_tail ;
 wire [0:0] mux_2level_size12_mem_8_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 assign prog_clk_0 = prog_clk[0] ;
 
@@ -3468,7 +4674,8 @@
     .sram ( mux_2level_size12_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
         SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_103 ) ) ;
+    .out ( right_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_103 ) ) ;
 cby_2__1__mux_2level_size12_1 mux_right_ipin_0 (
     .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , 
         chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , 
@@ -3478,7 +4685,7 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
         SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
     .out ( { aps_rename_514_ } ) ,
-    .p0 ( optlc_net_103 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_103 ) ) ;
 cby_2__1__mux_2level_size12_2 mux_right_ipin_2 (
     .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , 
         chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
@@ -3487,7 +4694,8 @@
     .sram ( mux_2level_size12_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
         SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
-    .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_102 ) ) ;
+    .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_102 ) ) ;
 cby_2__1__mux_2level_size12_3 mux_right_ipin_4 (
     .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , 
         chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , 
@@ -3496,7 +4704,8 @@
     .sram ( mux_2level_size12_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
         SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
-    .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_101 ) ) ;
+    .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_101 ) ) ;
 cby_2__1__mux_2level_size12_4 mux_right_ipin_6 (
     .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , 
         chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , 
@@ -3506,7 +4715,7 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
         SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
     .out ( { aps_rename_516_ } ) ,
-    .p0 ( optlc_net_105 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_105 ) ) ;
 cby_2__1__mux_2level_size12_5 mux_right_ipin_8 (
     .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , 
         chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
@@ -3515,7 +4724,8 @@
     .sram ( mux_2level_size12_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
         SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
-    .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_104 ) ) ;
+    .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_104 ) ) ;
 cby_2__1__mux_2level_size12_6 mux_right_ipin_10 (
     .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , 
         chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , 
@@ -3524,7 +4734,8 @@
     .sram ( mux_2level_size12_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
         SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
-    .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_101 ) ) ;
+    .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_101 ) ) ;
 cby_2__1__mux_2level_size12_7 mux_right_ipin_12 (
     .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , 
         chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , 
@@ -3534,7 +4745,7 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
         SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
     .out ( { aps_rename_517_ } ) ,
-    .p0 ( optlc_net_103 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_103 ) ) ;
 cby_2__1__mux_2level_size12 mux_right_ipin_14 (
     .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , 
         chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
@@ -3543,51 +4754,52 @@
     .sram ( mux_2level_size12_8_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
         SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
-    .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_104 ) ) ;
+    .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_104 ) ) ;
 cby_2__1__mux_2level_size12_mem_0 mem_left_ipin_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
     .ccff_tail ( mux_2level_size12_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_0_sram ) ) ;
+    .mem_out ( mux_2level_size12_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_size12_mem_1 mem_right_ipin_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_1_sram ) ) ;
+    .mem_out ( mux_2level_size12_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_size12_mem_2 mem_right_ipin_2 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size10_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_2_sram ) ) ;
+    .mem_out ( mux_2level_size12_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_size12_mem_3 mem_right_ipin_4 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size10_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_3_sram ) ) ;
+    .mem_out ( mux_2level_size12_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_size12_mem_4 mem_right_ipin_6 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size10_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_4_sram ) ) ;
+    .mem_out ( mux_2level_size12_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_size12_mem_5 mem_right_ipin_8 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size10_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_5_sram ) ) ;
+    .mem_out ( mux_2level_size12_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_size12_mem_6 mem_right_ipin_10 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size10_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_6_sram ) ) ;
+    .mem_out ( mux_2level_size12_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_size12_mem_7 mem_right_ipin_12 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size10_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_7_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_7_sram ) ) ;
+    .mem_out ( mux_2level_size12_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_size12_mem mem_right_ipin_14 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size10_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_8_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_8_sram ) ) ;
+    .mem_out ( mux_2level_size12_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_size10_0 mux_right_ipin_1 (
     .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , 
         chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , 
@@ -3597,7 +4809,7 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
         SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
     .out ( { aps_rename_515_ } ) ,
-    .p0 ( optlc_net_102 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_102 ) ) ;
 cby_2__1__mux_2level_size10_1 mux_right_ipin_3 (
     .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , 
         chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , 
@@ -3606,7 +4818,8 @@
     .sram ( mux_2level_size10_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
         SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
-    .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_104 ) ) ;
+    .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_104 ) ) ;
 cby_2__1__mux_2level_size10_2 mux_right_ipin_5 (
     .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , 
         chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , 
@@ -3615,7 +4828,8 @@
     .sram ( mux_2level_size10_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
         SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
-    .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_102 ) ) ;
+    .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_102 ) ) ;
 cby_2__1__mux_2level_size10_3 mux_right_ipin_7 (
     .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , 
         chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , 
@@ -3625,7 +4839,7 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
         SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
     .out ( { ZBUF_6_f_0 } ) ,
-    .p0 ( optlc_net_105 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_105 ) ) ;
 cby_2__1__mux_2level_size10_4 mux_right_ipin_9 (
     .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , 
         chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , 
@@ -3635,7 +4849,7 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
         SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
     .out ( { ZBUF_6_f_1 } ) ,
-    .p0 ( optlc_net_104 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_104 ) ) ;
 cby_2__1__mux_2level_size10_5 mux_right_ipin_11 (
     .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , 
         chany_bottom_out[3] , chany_top_out[12] , chany_bottom_out[12] , 
@@ -3644,7 +4858,8 @@
     .sram ( mux_2level_size10_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
         SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
-    .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_102 ) ) ;
+    .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_102 ) ) ;
 cby_2__1__mux_2level_size10_6 mux_right_ipin_13 (
     .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , 
         chany_bottom_out[5] , chany_top_out[14] , chany_bottom_out[14] , 
@@ -3653,7 +4868,8 @@
     .sram ( mux_2level_size10_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
         SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
-    .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_105 ) ) ;
+    .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_105 ) ) ;
 cby_2__1__mux_2level_size10 mux_right_ipin_15 (
     .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , 
         chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , 
@@ -3662,47 +4878,48 @@
     .sram ( mux_2level_size10_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , 
         SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
-    .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_104 ) ) ;
+    .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_104 ) ) ;
 cby_2__1__mux_2level_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_size10_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_size10_0_sram ) ) ;
+    .mem_out ( mux_2level_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_size10_mem_1 mem_right_ipin_3 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_size10_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_size10_1_sram ) ) ;
+    .mem_out ( mux_2level_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_size10_mem_2 mem_right_ipin_5 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_size10_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_size10_2_sram ) ) ;
+    .mem_out ( mux_2level_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_size10_mem_3 mem_right_ipin_7 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_size10_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_size10_3_sram ) ) ;
+    .mem_out ( mux_2level_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_size10_mem_4 mem_right_ipin_9 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_size10_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_size10_4_sram ) ) ;
+    .mem_out ( mux_2level_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_size10_mem_5 mem_right_ipin_11 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_size10_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_size10_5_sram ) ) ;
+    .mem_out ( mux_2level_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_size10_mem_6 mem_right_ipin_13 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_7_ccff_tail ) , 
     .ccff_tail ( mux_2level_size10_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_size10_6_sram ) ) ;
+    .mem_out ( mux_2level_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__mux_2level_size10_mem mem_right_ipin_15 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_8_ccff_tail ) ,
     .ccff_tail ( { ccff_tail_mid } ) ,
-    .mem_out ( mux_2level_size10_7_sram ) ) ;
+    .mem_out ( mux_2level_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( 
     .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
@@ -3711,453 +4928,585 @@
     .io_outpad ( left_width_0_height_0__pin_0_ ) ,
     .ccff_head ( { ccff_tail_mid } ) ,
     .io_inpad ( left_width_0_height_0__pin_1_lower ) , 
-    .ccff_tail ( ccff_tail ) ) ;
-sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) ) ;
+    .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , 
-    .X ( prog_clk[0] ) ) ;
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , 
-    .X ( ctsbuf_net_1106 ) ) ;
+    .X ( ctsbuf_net_1106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , 
-    .X ( ctsbuf_net_2107 ) ) ;
+    .X ( ctsbuf_net_2107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) , 
-    .X ( chany_top_out[0] ) ) ;
+    .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) , 
-    .X ( chany_top_out[1] ) ) ;
+    .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[2] ) , 
-    .X ( chany_top_out[2] ) ) ;
+    .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[3] ) , 
-    .X ( chany_top_out[3] ) ) ;
+    .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[4] ) , 
-    .X ( chany_top_out[4] ) ) ;
+    .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[5] ) , 
-    .X ( chany_top_out[5] ) ) ;
+    .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[6] ) , 
-    .X ( chany_top_out[6] ) ) ;
+    .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[7] ) , 
-    .X ( chany_top_out[7] ) ) ;
+    .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[8] ) , 
-    .X ( chany_top_out[8] ) ) ;
+    .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[9] ) , 
-    .X ( chany_top_out[9] ) ) ;
+    .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[10] ) , 
-    .X ( chany_top_out[10] ) ) ;
+    .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[11] ) , 
-    .X ( chany_top_out[11] ) ) ;
+    .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[12] ) , 
-    .X ( chany_top_out[12] ) ) ;
+    .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[13] ) , 
-    .X ( chany_top_out[13] ) ) ;
+    .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[14] ) , 
-    .X ( chany_top_out[14] ) ) ;
+    .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[15] ) , 
-    .X ( chany_top_out[15] ) ) ;
+    .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[16] ) , 
-    .X ( chany_top_out[16] ) ) ;
+    .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[17] ) , 
-    .X ( chany_top_out[17] ) ) ;
+    .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[18] ) , 
-    .X ( chany_top_out[18] ) ) ;
+    .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[19] ) , 
-    .X ( chany_top_out[19] ) ) ;
+    .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[20] ) , 
-    .X ( chany_top_out[20] ) ) ;
+    .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_bottom_in[21] ) , 
-    .X ( chany_top_out[21] ) ) ;
+    .X ( chany_top_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[22] ) , 
-    .X ( chany_top_out[22] ) ) ;
+    .X ( chany_top_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[23] ) , 
-    .X ( chany_top_out[23] ) ) ;
+    .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_bottom_in[24] ) , 
-    .X ( chany_top_out[24] ) ) ;
+    .X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_bottom_in[25] ) , 
-    .X ( chany_top_out[25] ) ) ;
+    .X ( chany_top_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_bottom_in[26] ) , 
-    .X ( chany_top_out[26] ) ) ;
+    .X ( chany_top_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_bottom_in[27] ) , 
-    .X ( chany_top_out[27] ) ) ;
+    .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_bottom_in[28] ) , 
-    .X ( chany_top_out[28] ) ) ;
+    .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_bottom_in[29] ) , 
-    .X ( chany_top_out[29] ) ) ;
+    .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[0] ) , 
-    .X ( chany_bottom_out[0] ) ) ;
+    .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[1] ) , 
-    .X ( chany_bottom_out[1] ) ) ;
+    .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[2] ) , 
-    .X ( chany_bottom_out[2] ) ) ;
+    .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[3] ) , 
-    .X ( chany_bottom_out[3] ) ) ;
+    .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[4] ) , 
-    .X ( chany_bottom_out[4] ) ) ;
+    .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[5] ) , 
-    .X ( chany_bottom_out[5] ) ) ;
+    .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[6] ) , 
-    .X ( chany_bottom_out[6] ) ) ;
+    .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[7] ) , 
-    .X ( chany_bottom_out[7] ) ) ;
+    .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[8] ) , 
-    .X ( chany_bottom_out[8] ) ) ;
+    .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[9] ) , 
-    .X ( chany_bottom_out[9] ) ) ;
+    .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[10] ) , 
-    .X ( chany_bottom_out[10] ) ) ;
+    .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[11] ) , 
-    .X ( chany_bottom_out[11] ) ) ;
+    .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[12] ) , 
-    .X ( chany_bottom_out[12] ) ) ;
+    .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[13] ) , 
-    .X ( chany_bottom_out[13] ) ) ;
+    .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[14] ) , 
-    .X ( chany_bottom_out[14] ) ) ;
+    .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[15] ) , 
-    .X ( chany_bottom_out[15] ) ) ;
+    .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[16] ) , 
-    .X ( chany_bottom_out[16] ) ) ;
+    .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[17] ) , 
-    .X ( chany_bottom_out[17] ) ) ;
+    .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[18] ) , 
-    .X ( chany_bottom_out[18] ) ) ;
+    .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[19] ) , 
-    .X ( chany_bottom_out[19] ) ) ;
+    .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[20] ) , 
-    .X ( chany_bottom_out[20] ) ) ;
+    .X ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[21] ) , 
-    .X ( chany_bottom_out[21] ) ) ;
+    .X ( chany_bottom_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[22] ) , 
-    .X ( chany_bottom_out[22] ) ) ;
+    .X ( chany_bottom_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[23] ) , 
-    .X ( chany_bottom_out[23] ) ) ;
+    .X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[24] ) , 
-    .X ( chany_bottom_out[24] ) ) ;
+    .X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[25] ) , 
-    .X ( chany_bottom_out[25] ) ) ;
+    .X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[26] ) , 
-    .X ( chany_bottom_out[26] ) ) ;
+    .X ( chany_bottom_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[27] ) , 
-    .X ( chany_bottom_out[27] ) ) ;
+    .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_top_in[28] ) , 
-    .X ( chany_bottom_out[28] ) ) ;
+    .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_top_in[29] ) , 
-    .X ( chany_bottom_out[29] ) ) ;
+    .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_79__78 ( 
     .A ( left_width_0_height_0__pin_1_lower[0] ) , 
-    .X ( left_width_0_height_0__pin_1_upper[0] ) ) ;
+    .X ( left_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , 
-    .HI ( optlc_net_101 ) ) ;
+    .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , 
-    .HI ( optlc_net_102 ) ) ;
+    .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , 
-    .HI ( optlc_net_103 ) ) ;
+    .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , 
-    .HI ( optlc_net_104 ) ) ;
+    .HI ( optlc_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_73 ) , 
-    .HI ( optlc_net_105 ) ) ;
+    .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_112 ( .A ( aps_rename_517_ ) , 
-    .X ( left_grid_pin_28_[0] ) ) ;
+    .X ( left_grid_pin_28_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_113 ( .A ( aps_rename_514_ ) , 
-    .X ( left_grid_pin_16_[0] ) ) ;
+    .X ( left_grid_pin_16_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_114 ( .A ( aps_rename_516_ ) , 
-    .X ( left_grid_pin_22_[0] ) ) ;
+    .X ( left_grid_pin_22_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_115 ( .A ( aps_rename_515_ ) , 
-    .X ( left_grid_pin_17_[0] ) ) ;
+    .X ( left_grid_pin_17_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1359 ( .A ( ZBUF_6_f_0 ) , 
-    .X ( left_grid_pin_23_[0] ) ) ;
+    .X ( left_grid_pin_23_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 cts_buf_3711261 ( .A ( ctsbuf_net_1106 ) , 
-    .X ( prog_clk_0_S_out ) ) ;
+    .X ( prog_clk_0_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__clkbuf_8 cts_buf_3761266 ( .A ( ctsbuf_net_2107 ) , 
-    .X ( prog_clk_0_N_out ) ) ;
+    .X ( prog_clk_0_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1360 ( .A ( ZBUF_6_f_1 ) , 
-    .X ( left_grid_pin_25_[0] ) ) ;
+    .X ( left_grid_pin_25_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_size10_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( mem_out[3] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_size10_mem_6 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_size10_mem_5 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_size10_mem_4 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_size10_mem_3 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_size10_mem_2 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_size10_mem_1 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_size10_mem_0 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input2_mem2 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input2_mem2 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_basis_input4_mem4 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_54 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_54 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_53 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_53 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_30 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_30 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_size10 ( in , sram , sram_inv , out , p0 ) ;
+module cby_1__1__mux_2level_size10 ( in , sram , sram_inv , out , VDD , VSS , 
+    p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -4168,163 +5517,221 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_1__1__local_encoder2to4_30 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__local_encoder2to4 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_53 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_54 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cby_1__1__mux_2level_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input2_mem2_6 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input2_mem2_6 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_basis_input4_mem4_52 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_51 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_51 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_50 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_50 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_29 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_29 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_28 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_28 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+module cby_1__1__mux_2level_size10_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -4335,163 +5742,221 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_1__1__local_encoder2to4_28 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__local_encoder2to4_29 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_50 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_51 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_52 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cby_1__1__mux_2level_basis_input2_mem2_6 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input2_mem2_5 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input2_mem2_5 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_basis_input4_mem4_49 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_48 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_48 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_47 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_47 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_27 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_27 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_26 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_26 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+module cby_1__1__mux_2level_size10_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -4502,164 +5967,223 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_83 ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_83 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_1__1__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__local_encoder2to4_27 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_47 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_48 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_49 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cby_1__1__mux_2level_basis_input2_mem2_5 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( net_net_83 ) , .X ( out[0] ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( net_net_83 ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input2_mem2_4 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input2_mem2_4 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_basis_input4_mem4_46 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_45 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_45 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_44 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_44 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_25 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_25 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_24 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_24 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+module cby_1__1__mux_2level_size10_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -4670,163 +6194,221 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_1__1__local_encoder2to4_24 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__local_encoder2to4_25 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_44 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_45 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_46 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cby_1__1__mux_2level_basis_input2_mem2_4 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input2_mem2_3 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input2_mem2_3 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_basis_input4_mem4_43 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_42 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_42 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_41 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_41 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_23 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_23 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_22 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_22 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+module cby_1__1__mux_2level_size10_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -4837,163 +6419,221 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_1__1__local_encoder2to4_22 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__local_encoder2to4_23 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_41 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_42 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_43 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cby_1__1__mux_2level_basis_input2_mem2_3 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input2_mem2_2 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input2_mem2_2 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_basis_input4_mem4_40 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_39 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_39 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_38 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_38 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_21 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_21 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_20 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_20 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+module cby_1__1__mux_2level_size10_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -5004,163 +6644,221 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_1__1__local_encoder2to4_20 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__local_encoder2to4_21 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_38 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_39 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_40 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cby_1__1__mux_2level_basis_input2_mem2_2 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input2_mem2_1 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input2_mem2_1 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_basis_input4_mem4_37 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_36 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_36 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_35 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_35 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_19 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_19 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_18 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_18 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+module cby_1__1__mux_2level_size10_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -5171,163 +6869,221 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_1__1__local_encoder2to4_18 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__local_encoder2to4_19 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_35 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_36 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_37 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cby_1__1__mux_2level_basis_input2_mem2_1 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input2_mem2_0 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input2_mem2_0 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_basis_input4_mem4_34 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_33 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_33 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_32 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_32 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_17 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_17 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_16 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_16 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+module cby_1__1__mux_2level_size10_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -5338,347 +7094,487 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_82 ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_82 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_1__1__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__local_encoder2to4_17 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_32 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_33 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_34 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cby_1__1__mux_2level_basis_input2_mem2_0 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( net_net_82 ) , .X ( out[0] ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( net_net_82 ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_size12_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_size12_mem_6 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_size12_mem_5 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_size12_mem_4 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_size12_mem_3 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_size12_mem_2 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_size12_mem_1 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_size12_mem_0 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_124 ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1359 ( .A ( ccff_head[0] ) , 
-    .X ( copt_net_105 ) ) ;
+    .X ( copt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1360 ( .A ( copt_net_105 ) , 
-    .X ( copt_net_106 ) ) ;
+    .X ( copt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1366 ( .A ( copt_net_106 ) , 
-    .X ( copt_net_107 ) ) ;
+    .X ( copt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1368 ( .A ( copt_net_107 ) , 
-    .X ( copt_net_109 ) ) ;
+    .X ( copt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1374 ( .A ( copt_net_109 ) , 
-    .X ( copt_net_110 ) ) ;
+    .X ( copt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1375 ( .A ( copt_net_110 ) , 
-    .X ( copt_net_111 ) ) ;
+    .X ( copt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1386 ( .A ( ropt_net_123 ) , 
-    .X ( ropt_net_122 ) ) ;
+    .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1387 ( .A ( copt_net_111 ) , 
-    .X ( ropt_net_123 ) ) ;
+    .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1388 ( .A ( ropt_net_122 ) , 
-    .X ( ropt_net_124 ) ) ;
+    .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_basis_input4_mem4_31 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_30 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_30 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_29 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_29 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_28 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_28 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_15 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_15 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_14 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_14 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_size12 ( in , sram , sram_inv , out , p0 ) ;
+module cby_1__1__mux_2level_size12 ( in , sram , sram_inv , out , VDD , VSS , 
+    p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -5689,168 +7585,227 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_1__1__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__local_encoder2to4_15 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_28 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_29 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_30 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_31 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_basis_input4_mem4_27 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_26 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_26 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_25 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_25 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_24 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_24 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_13 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_13 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_12 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_12 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_size12_6 ( in , sram , sram_inv , out , p0 ) ;
+module cby_1__1__mux_2level_size12_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -5861,168 +7816,227 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_1__1__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__local_encoder2to4_13 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_24 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_25 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_26 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_basis_input4_mem4_23 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_22 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_22 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_21 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_21 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_20 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_20 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_11 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_11 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_10 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_10 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_size12_5 ( in , sram , sram_inv , out , p0 ) ;
+module cby_1__1__mux_2level_size12_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -6033,169 +8047,229 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_81 ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_81 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_1__1__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__local_encoder2to4_11 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_20 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_21 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_22 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( net_net_81 ) , .X ( out[0] ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( net_net_81 ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_basis_input4_mem4_19 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_18 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_18 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_17 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_17 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_16 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_16 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_9 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_9 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_8 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_8 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_size12_4 ( in , sram , sram_inv , out , p0 ) ;
+module cby_1__1__mux_2level_size12_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -6206,169 +8280,229 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_80 ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_80 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_1__1__local_encoder2to4_8 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__local_encoder2to4_9 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_16 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_17 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_18 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( net_net_80 ) , .X ( out[0] ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( net_net_80 ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_basis_input4_mem4_15 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_14 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_14 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_13 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_13 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_12 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_12 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_7 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_7 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_6 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_6 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_size12_3 ( in , sram , sram_inv , out , p0 ) ;
+module cby_1__1__mux_2level_size12_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -6379,168 +8513,227 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_1__1__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__local_encoder2to4_7 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_12 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_13 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_14 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_15 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_basis_input4_mem4_11 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_10 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_10 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_9 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_9 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_8 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_8 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_5 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_5 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_4 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_size12_2 ( in , sram , sram_inv , out , p0 ) ;
+module cby_1__1__mux_2level_size12_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -6551,171 +8744,231 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_1__1__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__local_encoder2to4_5 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_8 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_9 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_10 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_79 ( .A ( aps_rename_506_ ) , 
-    .Y ( BUF_net_79 ) ) ;
+    .Y ( BUF_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_basis_input4_mem4_7 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_6 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_6 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_5 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_5 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_4 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_4 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_3 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_2 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_2 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_size12_1 ( in , sram , sram_inv , out , p0 ) ;
+module cby_1__1__mux_2level_size12_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -6726,171 +8979,231 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_1__1__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__local_encoder2to4_3 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_4 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_5 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_6 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_7 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_77 ( .A ( aps_rename_505_ ) , 
-    .Y ( BUF_net_77 ) ) ;
+    .Y ( BUF_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_1__1__mux_2level_basis_input4_mem4_3 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_2 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_2 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_1 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_1 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_basis_input4_mem4_0 ( in , mem , mem_inv , out ) ;
+module cby_1__1__mux_2level_basis_input4_mem4_0 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_1 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_1 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__local_encoder2to4_0 ( addr , data , data_inv ) ;
+module cby_1__1__local_encoder2to4_0 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_1__1__mux_2level_size12_0 ( in , sram , sram_inv , out , p0 ) ;
+module cby_1__1__mux_2level_size12_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -6901,34 +9214,41 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_1__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__local_encoder2to4_1 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_0 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_1 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_2 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_basis_input4_mem4_3 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
@@ -6946,7 +9266,7 @@
     prog_clk_2_S_out , prog_clk_2_N_out , prog_clk_3_S_in , prog_clk_3_N_in , 
     prog_clk_3_N_out , prog_clk_3_S_out , clk_2_N_in , clk_2_S_in , 
     clk_2_S_out , clk_2_N_out , clk_3_S_in , clk_3_N_in , clk_3_N_out , 
-    clk_3_S_out ) ;
+    clk_3_S_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:29] chany_bottom_in ;
 input  [0:29] chany_top_in ;
@@ -7003,6 +9323,8 @@
 input  clk_3_N_in ;
 output clk_3_N_out ;
 output clk_3_S_out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] prog_clk ;
 wire prog_clk_0 ;
@@ -7037,6 +9359,8 @@
 wire [0:0] mux_2level_size12_mem_5_ccff_tail ;
 wire [0:0] mux_2level_size12_mem_6_ccff_tail ;
 wire [0:0] mux_2level_size12_mem_7_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 assign Test_en_E_in = Test_en_S_in ;
 assign Test_en_E_in = Test_en_W_in ;
@@ -7056,7 +9380,8 @@
     .sram ( mux_2level_size12_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
         SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_101 ) ) ;
+    .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_101 ) ) ;
 cby_1__1__mux_2level_size12_1 mux_right_ipin_2 (
     .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , 
         chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , 
@@ -7065,7 +9390,8 @@
     .sram ( mux_2level_size12_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
         SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
-    .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_98 ) ) ;
+    .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_98 ) ) ;
 cby_1__1__mux_2level_size12_2 mux_right_ipin_4 (
     .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , 
         chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , 
@@ -7074,7 +9400,8 @@
     .sram ( mux_2level_size12_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
         SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
-    .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_96 ) ) ;
+    .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_96 ) ) ;
 cby_1__1__mux_2level_size12_3 mux_right_ipin_6 (
     .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , 
         chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , 
@@ -7083,7 +9410,8 @@
     .sram ( mux_2level_size12_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
         SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
-    .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_98 ) ) ;
+    .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_98 ) ) ;
 cby_1__1__mux_2level_size12_4 mux_right_ipin_8 (
     .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , 
         chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , 
@@ -7092,7 +9420,8 @@
     .sram ( mux_2level_size12_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
         SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
-    .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_99 ) ) ;
+    .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_99 ) ) ;
 cby_1__1__mux_2level_size12_5 mux_right_ipin_10 (
     .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , 
         chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , 
@@ -7101,7 +9430,8 @@
     .sram ( mux_2level_size12_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
         SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
-    .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_96 ) ) ;
+    .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_96 ) ) ;
 cby_1__1__mux_2level_size12_6 mux_right_ipin_12 (
     .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , 
         chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , 
@@ -7110,7 +9440,8 @@
     .sram ( mux_2level_size12_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
         SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
-    .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_101 ) ) ;
+    .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_101 ) ) ;
 cby_1__1__mux_2level_size12 mux_right_ipin_14 (
     .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , 
         chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , 
@@ -7119,46 +9450,47 @@
     .sram ( mux_2level_size12_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
         SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
-    .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_98 ) ) ;
+    .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_98 ) ) ;
 cby_1__1__mux_2level_size12_mem_0 mem_right_ipin_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
     .ccff_tail ( mux_2level_size12_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_0_sram ) ) ;
+    .mem_out ( mux_2level_size12_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_size12_mem_1 mem_right_ipin_2 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size10_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_1_sram ) ) ;
+    .mem_out ( mux_2level_size12_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_size12_mem_2 mem_right_ipin_4 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size10_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_2_sram ) ) ;
+    .mem_out ( mux_2level_size12_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_size12_mem_3 mem_right_ipin_6 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size10_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_3_sram ) ) ;
+    .mem_out ( mux_2level_size12_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_size12_mem_4 mem_right_ipin_8 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size10_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_4_sram ) ) ;
+    .mem_out ( mux_2level_size12_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_size12_mem_5 mem_right_ipin_10 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size10_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_5_sram ) ) ;
+    .mem_out ( mux_2level_size12_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_size12_mem_6 mem_right_ipin_12 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size10_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_6_sram ) ) ;
+    .mem_out ( mux_2level_size12_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_size12_mem mem_right_ipin_14 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size10_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_7_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_7_sram ) ) ;
+    .mem_out ( mux_2level_size12_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_size10_0 mux_right_ipin_1 (
     .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , 
         chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , 
@@ -7167,7 +9499,8 @@
     .sram ( mux_2level_size10_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
         SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
-    .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_96 ) ) ;
+    .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_96 ) ) ;
 cby_1__1__mux_2level_size10_1 mux_right_ipin_3 (
     .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , 
         chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
@@ -7176,7 +9509,8 @@
     .sram ( mux_2level_size10_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
         SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
-    .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_102 ) ) ;
+    .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_102 ) ) ;
 cby_1__1__mux_2level_size10_2 mux_right_ipin_5 (
     .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , 
         chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , 
@@ -7185,7 +9519,8 @@
     .sram ( mux_2level_size10_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
         SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
-    .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_100 ) ) ;
+    .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_100 ) ) ;
 cby_1__1__mux_2level_size10_3 mux_right_ipin_7 (
     .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , 
         chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , 
@@ -7194,7 +9529,8 @@
     .sram ( mux_2level_size10_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
         SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
-    .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_96 ) ) ;
+    .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_96 ) ) ;
 cby_1__1__mux_2level_size10_4 mux_right_ipin_9 (
     .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , 
         chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , 
@@ -7203,7 +9539,8 @@
     .sram ( mux_2level_size10_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
         SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
-    .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_102 ) ) ;
+    .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_102 ) ) ;
 cby_1__1__mux_2level_size10_5 mux_right_ipin_11 (
     .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , 
         chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , 
@@ -7212,7 +9549,8 @@
     .sram ( mux_2level_size10_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
         SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
-    .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_97 ) ) ;
+    .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_97 ) ) ;
 cby_1__1__mux_2level_size10_6 mux_right_ipin_13 (
     .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , 
         chany_bottom_out[4] , chany_top_out[13] , chany_bottom_out[13] , 
@@ -7221,7 +9559,8 @@
     .sram ( mux_2level_size10_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
         SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
-    .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_97 ) ) ;
+    .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_97 ) ) ;
 cby_1__1__mux_2level_size10 mux_right_ipin_15 (
     .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , 
         chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , 
@@ -7230,285 +9569,300 @@
     .sram ( mux_2level_size10_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
         SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
-    .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_100 ) ) ;
+    .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_100 ) ) ;
 cby_1__1__mux_2level_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_size10_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_size10_0_sram ) ) ;
+    .mem_out ( mux_2level_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_size10_mem_1 mem_right_ipin_3 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_size10_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_size10_1_sram ) ) ;
+    .mem_out ( mux_2level_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_size10_mem_2 mem_right_ipin_5 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_size10_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_size10_2_sram ) ) ;
+    .mem_out ( mux_2level_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_size10_mem_3 mem_right_ipin_7 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_size10_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_size10_3_sram ) ) ;
+    .mem_out ( mux_2level_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_size10_mem_4 mem_right_ipin_9 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_size10_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_size10_4_sram ) ) ;
+    .mem_out ( mux_2level_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_size10_mem_5 mem_right_ipin_11 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_size10_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_size10_5_sram ) ) ;
+    .mem_out ( mux_2level_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_size10_mem_6 mem_right_ipin_13 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_size10_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_size10_6_sram ) ) ;
+    .mem_out ( mux_2level_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1__mux_2level_size10_mem mem_right_ipin_15 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_7_ccff_tail ) ,
     .ccff_tail ( { copt_net_119 } ) ,
-    .mem_out ( mux_2level_size10_7_sram ) ) ;
+    .mem_out ( mux_2level_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) , 
-    .X ( aps_rename_507_ ) ) ;
+    .X ( aps_rename_507_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , 
-    .X ( aps_rename_508_ ) ) ;
+    .X ( aps_rename_508_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__bufbuf_16 Test_en_E_FTB01 ( .A ( Test_en_E_in ) , 
-    .X ( Test_en_E_out ) ) ;
-sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) ) ;
+    .X ( Test_en_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , 
-    .HI ( optlc_net_96 ) ) ;
+    .HI ( optlc_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 Reset_N_FTB01 ( .A ( Reset_E_in ) , 
-    .X ( aps_rename_509_ ) ) ;
+    .X ( aps_rename_509_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__bufbuf_16 Reset_W_FTB01 ( .A ( Reset_E_in ) , 
-    .X ( Reset_W_out ) ) ;
+    .X ( Reset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 Reset_E_FTB01 ( .A ( Reset_E_in ) , 
-    .X ( aps_rename_510_ ) ) ;
+    .X ( aps_rename_510_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , 
-    .X ( prog_clk[0] ) ) ;
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , 
-    .X ( ctsbuf_net_1103 ) ) ;
+    .X ( ctsbuf_net_1103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_2 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , 
-    .X ( ctsbuf_net_2104 ) ) ;
+    .X ( ctsbuf_net_2104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) , 
-    .X ( aps_rename_511_ ) ) ;
+    .X ( aps_rename_511_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) , 
-    .X ( aps_rename_512_ ) ) ;
+    .X ( aps_rename_512_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) , 
-    .X ( aps_rename_513_ ) ) ;
+    .X ( aps_rename_513_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__bufbuf_16 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) , 
-    .X ( prog_clk_3_S_out ) ) ;
+    .X ( prog_clk_3_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 clk_2_S_FTB01 ( .A ( clk_2_S_in ) , 
-    .X ( aps_rename_514_ ) ) ;
+    .X ( aps_rename_514_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , 
-    .X ( aps_rename_515_ ) ) ;
+    .X ( aps_rename_515_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , 
-    .X ( aps_rename_516_ ) ) ;
+    .X ( aps_rename_516_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__bufbuf_16 clk_3_S_FTB01 ( .A ( clk_3_N_in ) , 
-    .X ( clk_3_S_out ) ) ;
+    .X ( clk_3_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) , 
-    .X ( chany_top_out[0] ) ) ;
+    .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) , 
-    .X ( chany_top_out[1] ) ) ;
+    .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[2] ) , 
-    .X ( chany_top_out[2] ) ) ;
+    .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[3] ) , 
-    .X ( chany_top_out[3] ) ) ;
+    .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[4] ) , 
-    .X ( chany_top_out[4] ) ) ;
+    .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[5] ) , 
-    .X ( chany_top_out[5] ) ) ;
+    .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[6] ) , 
-    .X ( chany_top_out[6] ) ) ;
+    .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[7] ) , 
-    .X ( chany_top_out[7] ) ) ;
+    .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[8] ) , 
-    .X ( chany_top_out[8] ) ) ;
+    .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[9] ) , 
-    .X ( chany_top_out[9] ) ) ;
+    .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[10] ) , 
-    .X ( chany_top_out[10] ) ) ;
+    .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[11] ) , 
-    .X ( chany_top_out[11] ) ) ;
+    .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[12] ) , 
-    .X ( chany_top_out[12] ) ) ;
+    .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[13] ) , 
-    .X ( chany_top_out[13] ) ) ;
+    .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[14] ) , 
-    .X ( chany_top_out[14] ) ) ;
+    .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[15] ) , 
-    .X ( chany_top_out[15] ) ) ;
+    .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[16] ) , 
-    .X ( chany_top_out[16] ) ) ;
+    .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[17] ) , 
-    .X ( chany_top_out[17] ) ) ;
+    .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[18] ) , 
-    .X ( chany_top_out[18] ) ) ;
+    .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[19] ) , 
-    .X ( chany_top_out[19] ) ) ;
+    .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[20] ) , 
-    .X ( chany_top_out[20] ) ) ;
+    .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[21] ) , 
-    .X ( chany_top_out[21] ) ) ;
+    .X ( chany_top_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[22] ) , 
-    .X ( chany_top_out[22] ) ) ;
+    .X ( chany_top_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_bottom_in[23] ) , 
-    .X ( chany_top_out[23] ) ) ;
+    .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[24] ) , 
-    .X ( chany_top_out[24] ) ) ;
+    .X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[25] ) , 
-    .X ( chany_top_out[25] ) ) ;
+    .X ( chany_top_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_bottom_in[26] ) , 
-    .X ( chany_top_out[26] ) ) ;
+    .X ( chany_top_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_bottom_in[27] ) , 
-    .X ( chany_top_out[27] ) ) ;
+    .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_bottom_in[28] ) , 
-    .X ( chany_top_out[28] ) ) ;
+    .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_bottom_in[29] ) , 
-    .X ( chany_top_out[29] ) ) ;
+    .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[0] ) , 
-    .X ( chany_bottom_out[0] ) ) ;
+    .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[1] ) , 
-    .X ( chany_bottom_out[1] ) ) ;
+    .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[2] ) , 
-    .X ( chany_bottom_out[2] ) ) ;
+    .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[3] ) , 
-    .X ( chany_bottom_out[3] ) ) ;
+    .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[4] ) , 
-    .X ( chany_bottom_out[4] ) ) ;
+    .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[5] ) , 
-    .X ( chany_bottom_out[5] ) ) ;
+    .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[6] ) , 
-    .X ( chany_bottom_out[6] ) ) ;
+    .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[7] ) , 
-    .X ( chany_bottom_out[7] ) ) ;
+    .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[8] ) , 
-    .X ( chany_bottom_out[8] ) ) ;
+    .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[9] ) , 
-    .X ( chany_bottom_out[9] ) ) ;
+    .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[10] ) , 
-    .X ( chany_bottom_out[10] ) ) ;
+    .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[11] ) , 
-    .X ( chany_bottom_out[11] ) ) ;
+    .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[12] ) , 
-    .X ( chany_bottom_out[12] ) ) ;
+    .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[13] ) , 
-    .X ( chany_bottom_out[13] ) ) ;
+    .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[14] ) , 
-    .X ( chany_bottom_out[14] ) ) ;
+    .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[15] ) , 
-    .X ( chany_bottom_out[15] ) ) ;
+    .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[16] ) , 
-    .X ( chany_bottom_out[16] ) ) ;
+    .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[17] ) , 
-    .X ( chany_bottom_out[17] ) ) ;
+    .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[18] ) , 
-    .X ( chany_bottom_out[18] ) ) ;
+    .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[19] ) , 
-    .X ( chany_bottom_out[19] ) ) ;
+    .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[20] ) , 
-    .X ( chany_bottom_out[20] ) ) ;
+    .X ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[21] ) , 
-    .X ( chany_bottom_out[21] ) ) ;
+    .X ( chany_bottom_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[22] ) , 
-    .X ( chany_bottom_out[22] ) ) ;
+    .X ( chany_bottom_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[23] ) , 
-    .X ( chany_bottom_out[23] ) ) ;
+    .X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[24] ) , 
-    .X ( chany_bottom_out[24] ) ) ;
+    .X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[25] ) , 
-    .X ( chany_bottom_out[25] ) ) ;
+    .X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[26] ) , 
-    .X ( chany_bottom_out[26] ) ) ;
+    .X ( chany_bottom_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[27] ) , 
-    .X ( chany_bottom_out[27] ) ) ;
+    .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[28] ) , 
-    .X ( chany_bottom_out[28] ) ) ;
+    .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[29] ) , 
-    .X ( chany_bottom_out[29] ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( Test_en_N_out ) ) ;
+    .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( Test_en_N_out ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( aps_rename_507_ ) , 
-    .Y ( BUF_net_85 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( Test_en_W_out ) ) ;
+    .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( Test_en_W_out ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_508_ ) , 
-    .Y ( BUF_net_87 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( pReset_N_out ) ) ;
-sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( pReset_S_in ) , .Y ( BUF_net_89 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( Reset_N_out ) ) ;
+    .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( pReset_N_out ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( pReset_S_in ) , .Y ( BUF_net_89 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( Reset_N_out ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( aps_rename_509_ ) , 
-    .Y ( BUF_net_91 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( Reset_E_out ) ) ;
+    .Y ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( Reset_E_out ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_510_ ) , 
-    .Y ( BUF_net_93 ) ) ;
+    .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , 
-    .Y ( prog_clk_3_N_out ) ) ;
+    .Y ( prog_clk_3_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( aps_rename_513_ ) , 
-    .Y ( BUF_net_95 ) ) ;
+    .Y ( BUF_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , 
-    .HI ( optlc_net_97 ) ) ;
+    .HI ( optlc_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , 
-    .HI ( optlc_net_98 ) ) ;
+    .HI ( optlc_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , 
-    .HI ( optlc_net_99 ) ) ;
+    .HI ( optlc_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , 
-    .HI ( optlc_net_100 ) ) ;
+    .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , 
-    .HI ( optlc_net_101 ) ) ;
+    .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , 
-    .HI ( optlc_net_102 ) ) ;
+    .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_111 ( .A ( aps_rename_516_ ) , 
-    .X ( clk_3_N_out ) ) ;
+    .X ( clk_3_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_112 ( .A ( aps_rename_511_ ) , 
-    .X ( prog_clk_2_S_out ) ) ;
+    .X ( prog_clk_2_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_113 ( .A ( aps_rename_514_ ) , 
-    .X ( clk_2_S_out ) ) ;
+    .X ( clk_2_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_114 ( .A ( aps_rename_512_ ) , 
-    .X ( prog_clk_2_N_out ) ) ;
+    .X ( prog_clk_2_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_115 ( .A ( aps_rename_515_ ) , 
-    .X ( clk_2_N_out ) ) ;
+    .X ( clk_2_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 cts_buf_3711261 ( .A ( ctsbuf_net_1103 ) , 
-    .X ( prog_clk_0_S_out ) ) ;
+    .X ( prog_clk_0_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__clkbuf_8 cts_buf_3761266 ( .A ( ctsbuf_net_2104 ) , 
-    .X ( prog_clk_0_N_out ) ) ;
+    .X ( prog_clk_0_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1380 ( .A ( copt_net_119 ) , 
-    .X ( copt_net_116 ) ) ;
+    .X ( copt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__bufbuf_8 copt_h_inst_1383 ( .A ( copt_net_120 ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1384 ( .A ( copt_net_116 ) , 
-    .X ( copt_net_120 ) ) ;
+    .X ( copt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , 
-    prog_clk , ccff_head , ccff_tail , mem_out ) ;
+    prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:0] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
-sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( copt_net_80 ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( copt_net_80 ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1231 ( .A ( copt_net_79 ) , 
-    .X ( copt_net_75 ) ) ;
+    .X ( copt_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1232 ( .A ( copt_net_78 ) , 
-    .X ( copt_net_76 ) ) ;
+    .X ( copt_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1233 ( .A ( copt_net_76 ) , 
-    .X ( copt_net_77 ) ) ;
+    .X ( copt_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1234 ( .A ( copt_net_75 ) , 
-    .X ( copt_net_78 ) ) ;
+    .X ( copt_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1235 ( .A ( mem_out[0] ) , 
-    .X ( copt_net_79 ) ) ;
+    .X ( copt_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1236 ( .A ( copt_net_77 ) , 
-    .X ( copt_net_80 ) ) ;
+    .X ( copt_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_0__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
-    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ;
 input  SOC_IN ;
 output SOC_OUT ;
 output SOC_DIR ;
@@ -7516,25 +9870,34 @@
 input  FPGA_OUT ;
 input  FPGA_DIR ;
 input  IO_ISOL_N ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
-    .B ( IO_ISOL_N ) , .Y ( aps_rename_506_ ) ) ;
-sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_63 ) , .Y ( SOC_DIR_N ) ) ;
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_506_ ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_63 ) , .Y ( SOC_DIR_N ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
-    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
-    .TE_B ( BUF_net_63 ) , .Z ( SOC_OUT ) ) ;
-sky130_fd_sc_hd__inv_4 BINV_R_63 ( .A ( BUF_net_65 ) , .Y ( BUF_net_63 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( SOC_DIR ) ) ;
+    .TE_B ( BUF_net_63 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_63 ( .A ( BUF_net_65 ) , .Y ( BUF_net_63 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( SOC_DIR ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( aps_rename_506_ ) , 
-    .Y ( BUF_net_65 ) ) ;
+    .Y ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_0__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , 
     prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
-    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ;
 input  [0:0] IO_ISOL_N ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
@@ -7545,25 +9908,31 @@
 input  [0:0] ccff_head ;
 output [0:0] iopad_inpad ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] EMBEDDED_IO_HD_0_en ;
+supply1 VDD ;
+supply0 VSS ;
 
 cby_0__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( 
     .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
     .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
     .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
     .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
-    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module cby_0__1__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
-    ccff_tail ) ;
+    ccff_tail , VDD , VSS ) ;
 input  [0:0] IO_ISOL_N ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
@@ -7574,6 +9943,11 @@
 input  [0:0] ccff_head ;
 output [0:0] io_inpad ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( 
     .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
@@ -7581,173 +9955,236 @@
     .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
     .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
     .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
-    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module cby_0__1__mux_2level_size12_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_71 ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1225 ( .A ( copt_net_73 ) , 
-    .X ( copt_net_69 ) ) ;
+    .X ( copt_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1226 ( .A ( copt_net_72 ) , 
-    .X ( copt_net_70 ) ) ;
+    .X ( copt_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1227 ( .A ( copt_net_69 ) , 
-    .X ( copt_net_71 ) ) ;
+    .X ( copt_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1228 ( .A ( copt_net_74 ) , 
-    .X ( copt_net_72 ) ) ;
+    .X ( copt_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1229 ( .A ( copt_net_70 ) , 
-    .X ( copt_net_73 ) ) ;
+    .X ( copt_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1230 ( .A ( ccff_head[0] ) , 
-    .X ( copt_net_74 ) ) ;
+    .X ( copt_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cby_0__1__mux_2level_basis_input4_mem4 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_0__1__mux_2level_basis_input4_mem4_2 ( in , mem , mem_inv , out ) ;
+module cby_0__1__mux_2level_basis_input4_mem4_2 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_0__1__mux_2level_basis_input4_mem4_1 ( in , mem , mem_inv , out ) ;
+module cby_0__1__mux_2level_basis_input4_mem4_1 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_0__1__mux_2level_basis_input4_mem4_0 ( in , mem , mem_inv , out ) ;
+module cby_0__1__mux_2level_basis_input4_mem4_0 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_0__1__local_encoder2to4 ( addr , data , data_inv ) ;
+module cby_0__1__local_encoder2to4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_0__1__local_encoder2to4_0 ( addr , data , data_inv ) ;
+module cby_0__1__local_encoder2to4_0 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cby_0__1__mux_2level_size12 ( in , sram , sram_inv , out , p0 ) ;
+module cby_0__1__mux_2level_size12 ( in , sram , sram_inv , out , VDD , VSS , 
+    p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -7758,37 +10195,45 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cby_0__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_0__1__local_encoder2to4 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_0__1__mux_2level_basis_input4_mem4_0 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_0__1__mux_2level_basis_input4_mem4_1 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_0__1__mux_2level_basis_input4_mem4_2 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_0__1__mux_2level_basis_input4_mem4 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( aps_rename_505_ ) , 
-    .Y ( BUF_net_67 ) ) ;
+    .Y ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
@@ -7797,7 +10242,8 @@
     IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
     right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , 
-    right_width_0_height_0__pin_1_lower , pReset_N_in , prog_clk_0_E_in ) ;
+    right_width_0_height_0__pin_1_lower , pReset_N_in , prog_clk_0_E_in , 
+    VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:29] chany_bottom_in ;
 input  [0:29] chany_top_in ;
@@ -7815,6 +10261,8 @@
 output [0:0] right_width_0_height_0__pin_1_lower ;
 input  pReset_N_in ;
 input  prog_clk_0_E_in ;
+input  VDD ;
+input  VSS ;
 
 wire ropt_net_139 ;
 wire ropt_net_131 ;
@@ -7848,6 +10296,8 @@
 wire [0:0] prog_clk ;
 wire prog_clk_0 ;
 wire [0:3] mux_2level_size12_0_sram ;
+supply1 VDD ;
+supply0 VSS ;
 
 assign prog_clk_0 = prog_clk[0] ;
 
@@ -7859,11 +10309,12 @@
     .sram ( mux_2level_size12_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
         SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_68 ) ) ;
+    .out ( left_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_68 ) ) ;
 cby_0__1__mux_2level_size12_mem mem_right_ipin_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
     .ccff_tail ( { ccff_tail_mid } ) ,
-    .mem_out ( mux_2level_size12_0_sram ) ) ;
+    .mem_out ( mux_2level_size12_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( 
     .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
@@ -7872,222 +10323,230 @@
     .io_outpad ( right_width_0_height_0__pin_0_ ) ,
     .ccff_head ( { ccff_tail_mid } ) ,
     .io_inpad ( right_width_0_height_0__pin_1_lower ) , 
-    .ccff_tail ( ccff_tail ) ) ;
-sky130_fd_sc_hd__buf_4 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) ) ;
+    .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_4 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , 
-    .X ( prog_clk[0] ) ) ;
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) , 
-    .X ( chany_top_out[0] ) ) ;
+    .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) , 
-    .X ( ropt_net_139 ) ) ;
+    .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_5__4 ( .A ( chany_bottom_in[2] ) , 
-    .X ( ropt_net_131 ) ) ;
+    .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_6__5 ( .A ( chany_bottom_in[3] ) , 
-    .X ( chany_top_out[3] ) ) ;
+    .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_7__6 ( .A ( chany_bottom_in[4] ) , 
-    .X ( ropt_net_140 ) ) ;
+    .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) , 
-    .X ( ropt_net_142 ) ) ;
+    .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , 
-    .X ( chany_top_out[6] ) ) ;
+    .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_10__9 ( .A ( chany_bottom_in[7] ) , 
-    .X ( chany_top_out[7] ) ) ;
+    .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_11__10 ( .A ( chany_bottom_in[8] ) , 
-    .X ( chany_top_out[8] ) ) ;
+    .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_12__11 ( .A ( chany_bottom_in[9] ) , 
-    .X ( chany_top_out[9] ) ) ;
+    .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_13__12 ( .A ( chany_bottom_in[10] ) , 
-    .X ( ropt_net_127 ) ) ;
+    .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , 
-    .X ( ropt_net_152 ) ) ;
+    .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_15__14 ( .A ( chany_bottom_in[12] ) , 
-    .X ( chany_top_out[12] ) ) ;
+    .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( chany_bottom_in[13] ) , 
-    .X ( ropt_net_133 ) ) ;
+    .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) , 
-    .X ( chany_top_out[14] ) ) ;
+    .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) , 
-    .X ( ropt_net_141 ) ) ;
+    .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_19__18 ( .A ( chany_bottom_in[16] ) , 
-    .X ( ropt_net_143 ) ) ;
+    .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , 
-    .X ( ropt_net_135 ) ) ;
+    .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , 
-    .X ( chany_top_out[18] ) ) ;
+    .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , 
-    .X ( ropt_net_154 ) ) ;
+    .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_23__22 ( .A ( chany_bottom_in[20] ) , 
-    .X ( ropt_net_156 ) ) ;
+    .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[21] ) , 
-    .X ( chany_top_out[21] ) ) ;
+    .X ( chany_top_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[22] ) , 
-    .X ( chany_top_out[22] ) ) ;
+    .X ( chany_top_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_bottom_in[23] ) , 
-    .X ( ropt_net_153 ) ) ;
+    .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[24] ) , 
-    .X ( chany_top_out[24] ) ) ;
+    .X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[25] ) , 
-    .X ( chany_top_out[25] ) ) ;
+    .X ( chany_top_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[26] ) , 
-    .X ( chany_top_out[26] ) ) ;
+    .X ( chany_top_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[27] ) , 
-    .X ( chany_top_out[27] ) ) ;
+    .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_31__30 ( .A ( chany_bottom_in[28] ) , 
-    .X ( ropt_net_130 ) ) ;
+    .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_bottom_in[29] ) , 
-    .X ( ropt_net_132 ) ) ;
+    .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[0] ) , 
-    .X ( chany_bottom_out[0] ) ) ;
+    .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[1] ) , 
-    .X ( ropt_net_147 ) ) ;
+    .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[2] ) , 
-    .X ( chany_bottom_out[2] ) ) ;
+    .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[3] ) , 
-    .X ( chany_bottom_out[3] ) ) ;
+    .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[4] ) , 
-    .X ( chany_bottom_out[4] ) ) ;
+    .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_38__37 ( .A ( chany_top_in[5] ) , 
-    .X ( ropt_net_138 ) ) ;
+    .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[6] ) , 
-    .X ( chany_bottom_out[6] ) ) ;
+    .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[7] ) , 
-    .X ( ropt_net_151 ) ) ;
+    .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[8] ) , 
-    .X ( chany_bottom_out[8] ) ) ;
+    .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chany_top_in[9] ) , 
-    .X ( ropt_net_128 ) ) ;
+    .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chany_top_in[10] ) , 
-    .X ( ropt_net_149 ) ) ;
+    .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_44__43 ( .A ( chany_top_in[11] ) , 
-    .X ( ropt_net_150 ) ) ;
+    .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[12] ) , 
-    .X ( chany_bottom_out[12] ) ) ;
+    .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chany_top_in[13] ) , 
-    .X ( ropt_net_129 ) ) ;
+    .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chany_top_in[14] ) , 
-    .X ( ropt_net_146 ) ) ;
+    .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_48__47 ( .A ( chany_top_in[15] ) , 
-    .X ( ropt_net_136 ) ) ;
+    .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[16] ) , 
-    .X ( chany_bottom_out[16] ) ) ;
+    .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_50__49 ( .A ( chany_top_in[17] ) , 
-    .X ( ropt_net_148 ) ) ;
+    .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[18] ) , 
-    .X ( chany_bottom_out[18] ) ) ;
+    .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[19] ) , 
-    .X ( chany_bottom_out[19] ) ) ;
+    .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_53__52 ( .A ( chany_top_in[20] ) , 
-    .X ( ropt_net_134 ) ) ;
+    .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[21] ) , 
-    .X ( chany_bottom_out[21] ) ) ;
+    .X ( chany_bottom_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[22] ) , 
-    .X ( chany_bottom_out[22] ) ) ;
+    .X ( chany_bottom_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( chany_top_in[23] ) , 
-    .X ( ropt_net_137 ) ) ;
+    .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[24] ) , 
-    .X ( chany_bottom_out[24] ) ) ;
+    .X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_58__57 ( .A ( chany_top_in[25] ) , 
-    .X ( ropt_net_144 ) ) ;
+    .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chany_top_in[26] ) , 
-    .X ( ropt_net_145 ) ) ;
+    .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[27] ) , 
-    .X ( chany_bottom_out[27] ) ) ;
+    .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[28] ) , 
-    .X ( chany_bottom_out[28] ) ) ;
+    .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[29] ) , 
-    .X ( chany_bottom_out[29] ) ) ;
+    .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_63__62 ( 
     .A ( right_width_0_height_0__pin_1_lower[0] ) , 
-    .X ( right_width_0_height_0__pin_1_upper[0] ) ) ;
+    .X ( right_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_69 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , 
-    .HI ( optlc_net_68 ) ) ;
+    .HI ( optlc_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1283 ( .A ( ropt_net_127 ) , 
-    .X ( chany_top_out[10] ) ) ;
+    .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1284 ( .A ( ropt_net_128 ) , 
-    .X ( chany_bottom_out[9] ) ) ;
+    .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1285 ( .A ( ropt_net_129 ) , 
-    .X ( chany_bottom_out[13] ) ) ;
+    .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1286 ( .A ( ropt_net_130 ) , 
-    .X ( chany_top_out[28] ) ) ;
+    .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1287 ( .A ( ropt_net_131 ) , 
-    .X ( chany_top_out[2] ) ) ;
+    .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1288 ( .A ( ropt_net_132 ) , 
-    .X ( chany_top_out[29] ) ) ;
+    .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1289 ( .A ( ropt_net_133 ) , 
-    .X ( chany_top_out[13] ) ) ;
+    .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1290 ( .A ( ropt_net_134 ) , 
-    .X ( chany_bottom_out[20] ) ) ;
+    .X ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1291 ( .A ( ropt_net_135 ) , 
-    .X ( chany_top_out[17] ) ) ;
+    .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1292 ( .A ( ropt_net_136 ) , 
-    .X ( chany_bottom_out[15] ) ) ;
+    .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1293 ( .A ( ropt_net_137 ) , 
-    .X ( chany_bottom_out[23] ) ) ;
+    .X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1294 ( .A ( ropt_net_138 ) , 
-    .X ( chany_bottom_out[5] ) ) ;
+    .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_139 ) , 
-    .X ( chany_top_out[1] ) ) ;
+    .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1296 ( .A ( ropt_net_140 ) , 
-    .X ( chany_top_out[4] ) ) ;
+    .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1297 ( .A ( ropt_net_141 ) , 
-    .X ( chany_top_out[15] ) ) ;
+    .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1298 ( .A ( ropt_net_142 ) , 
-    .X ( chany_top_out[5] ) ) ;
+    .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1299 ( .A ( ropt_net_143 ) , 
-    .X ( chany_top_out[16] ) ) ;
+    .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1300 ( .A ( ropt_net_144 ) , 
-    .X ( chany_bottom_out[25] ) ) ;
+    .X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1301 ( .A ( ropt_net_145 ) , 
-    .X ( chany_bottom_out[26] ) ) ;
+    .X ( chany_bottom_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1302 ( .A ( ropt_net_146 ) , 
-    .X ( chany_bottom_out[14] ) ) ;
+    .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1303 ( .A ( ropt_net_147 ) , 
-    .X ( chany_bottom_out[1] ) ) ;
+    .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1304 ( .A ( ropt_net_148 ) , 
-    .X ( chany_bottom_out[17] ) ) ;
+    .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1305 ( .A ( ropt_net_149 ) , 
-    .X ( chany_bottom_out[10] ) ) ;
+    .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1306 ( .A ( ropt_net_150 ) , 
-    .X ( chany_bottom_out[11] ) ) ;
+    .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1307 ( .A ( ropt_net_151 ) , 
-    .X ( chany_bottom_out[7] ) ) ;
+    .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1308 ( .A ( ropt_net_152 ) , 
-    .X ( chany_top_out[11] ) ) ;
+    .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1309 ( .A ( ropt_net_153 ) , 
-    .X ( chany_top_out[23] ) ) ;
+    .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1310 ( .A ( ropt_net_154 ) , 
-    .X ( chany_top_out[19] ) ) ;
+    .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1312 ( .A ( ropt_net_156 ) , 
-    .X ( chany_top_out[20] ) ) ;
+    .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , 
-    prog_clk , ccff_head , ccff_tail , mem_out ) ;
+    prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:0] mem_out ;
+input  VDD ;
+input  VSS ;
 
 wire copt_net_113 ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_113 ) ) ;
-sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_113 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_113 ) , 
-    .X ( copt_net_110 ) ) ;
+    .X ( copt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1361 ( .A ( copt_net_112 ) , 
-    .X ( copt_net_111 ) ) ;
+    .X ( copt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1362 ( .A ( copt_net_110 ) , 
-    .X ( copt_net_112 ) ) ;
+    .X ( copt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1363 ( .A ( copt_net_111 ) , 
-    .X ( mem_out[0] ) ) ;
+    .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
-    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ;
 input  SOC_IN ;
 output SOC_OUT ;
 output SOC_DIR ;
@@ -8095,24 +10554,32 @@
 input  FPGA_OUT ;
 input  FPGA_DIR ;
 input  IO_ISOL_N ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
-    .B ( IO_ISOL_N ) , .Y ( aps_rename_509_ ) ) ;
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_509_ ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
-    .TE_B ( BUF_net_84 ) , .Z ( FPGA_IN ) ) ;
+    .TE_B ( BUF_net_84 ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
-    .TE_B ( BUF_net_82 ) , .Z ( SOC_OUT ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_84 ) , .Y ( BUF_net_82 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( SOC_DIR ) ) ;
+    .TE_B ( BUF_net_82 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_84 ) , .Y ( BUF_net_82 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( SOC_DIR ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( aps_rename_509_ ) , 
-    .Y ( BUF_net_84 ) ) ;
+    .Y ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , 
     prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
-    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ;
 input  [0:0] IO_ISOL_N ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
@@ -8123,25 +10590,31 @@
 input  [0:0] ccff_head ;
 output [0:0] iopad_inpad ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] EMBEDDED_IO_HD_0_en ;
+supply1 VDD ;
+supply0 VSS ;
 
 cbx_1__2__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( 
     .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
     .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
     .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
     .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
-    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
-    ccff_tail ) ;
+    ccff_tail , VDD , VSS ) ;
 input  [0:0] IO_ISOL_N ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
@@ -8152,6 +10625,11 @@
 input  [0:0] ccff_head ;
 output [0:0] io_inpad ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 cbx_1__2__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( 
     .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
@@ -8159,296 +10637,428 @@
     .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
     .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
     .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
-    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_size10_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_size10_mem_6 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_size10_mem_5 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_size10_mem_4 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_size10_mem_3 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_size10_mem_2 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_size10_mem_1 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_size10_mem_0 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input2_mem2 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input2_mem2 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_basis_input4_mem4 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_58 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_58 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_57 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_57 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_32 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_32 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_size10 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__2__mux_2level_size10 ( in , sram , sram_inv , out , VDD , VSS , 
+    p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -8459,166 +11069,225 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_508_ ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_508_ ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_32 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__local_encoder2to4 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_57 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_58 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cbx_1__2__mux_2level_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( aps_rename_508_ ) , 
-    .Y ( BUF_net_97 ) ) ;
+    .Y ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input2_mem2_6 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input2_mem2_6 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_basis_input4_mem4_56 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_55 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_55 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_54 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_54 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_31 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_31 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_30 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_30 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__2__mux_2level_size10_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -8629,164 +11298,223 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_93 ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_93 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_30 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_31 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_54 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_55 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_56 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cbx_1__2__mux_2level_basis_input2_mem2_6 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_93 ( .A ( net_net_93 ) , .X ( out[0] ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_93 ( .A ( net_net_93 ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input2_mem2_5 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input2_mem2_5 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_basis_input4_mem4_53 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_52 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_52 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_51 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_51 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_29 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_29 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_28 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_28 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__2__mux_2level_size10_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -8797,163 +11525,221 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_28 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_29 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_51 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_52 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_53 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cbx_1__2__mux_2level_basis_input2_mem2_5 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input2_mem2_4 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input2_mem2_4 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_basis_input4_mem4_50 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_49 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_49 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_48 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_48 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_27 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_27 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_26 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_26 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__2__mux_2level_size10_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -8964,166 +11750,225 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_507_ ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_507_ ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_27 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_48 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_49 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_50 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cbx_1__2__mux_2level_basis_input2_mem2_4 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_507_ ) , 
-    .Y ( BUF_net_92 ) ) ;
+    .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input2_mem2_3 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input2_mem2_3 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_basis_input4_mem4_47 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_46 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_46 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_45 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_45 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_25 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_25 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_24 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_24 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__2__mux_2level_size10_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -9134,163 +11979,221 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_24 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_25 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_45 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_46 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_47 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cbx_1__2__mux_2level_basis_input2_mem2_3 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input2_mem2_2 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input2_mem2_2 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_basis_input4_mem4_44 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_43 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_43 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_42 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_42 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_23 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_23 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_22 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_22 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__2__mux_2level_size10_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -9301,164 +12204,223 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_90 ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_90 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_22 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_23 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_42 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_43 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_44 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cbx_1__2__mux_2level_basis_input2_mem2_2 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_90 ( .A ( net_net_90 ) , .X ( out[0] ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_90 ( .A ( net_net_90 ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input2_mem2_1 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input2_mem2_1 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_basis_input4_mem4_41 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_40 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_40 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_39 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_39 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_21 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_21 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_20 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_20 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__2__mux_2level_size10_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -9469,163 +12431,221 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_20 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_21 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_39 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_40 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_41 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cbx_1__2__mux_2level_basis_input2_mem2_1 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input2_mem2_0 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input2_mem2_0 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_basis_input4_mem4_38 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_37 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_37 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_36 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_36 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_19 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_19 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_18 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_18 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__2__mux_2level_size10_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -9636,367 +12656,517 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_89 ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_89 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_18 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_19 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_36 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_37 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_38 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cbx_1__2__mux_2level_basis_input2_mem2_0 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( .A ( net_net_89 ) , .X ( out[0] ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( .A ( net_net_89 ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_size12_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_size12_mem_7 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_size12_mem_6 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_size12_mem_5 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_size12_mem_4 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_size12_mem_3 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_size12_mem_2 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_size12_mem_1 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_size12_mem_0 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_121 ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_107 ) , 
-    .X ( copt_net_105 ) ) ;
+    .X ( copt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_105 ) , 
-    .X ( copt_net_106 ) ) ;
+    .X ( copt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( ccff_head[0] ) , 
-    .X ( copt_net_107 ) ) ;
+    .X ( copt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1365 ( .A ( ropt_net_123 ) , 
-    .X ( copt_net_115 ) ) ;
+    .X ( copt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1366 ( .A ( copt_net_106 ) , 
-    .X ( copt_net_116 ) ) ;
+    .X ( copt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1367 ( .A ( copt_net_116 ) , 
-    .X ( copt_net_117 ) ) ;
+    .X ( copt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1369 ( .A ( ropt_net_122 ) , 
-    .X ( ropt_net_121 ) ) ;
+    .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_4 ropt_h_inst_1370 ( .A ( copt_net_115 ) , 
-    .X ( ropt_net_122 ) ) ;
+    .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1371 ( .A ( copt_net_117 ) , 
-    .X ( ropt_net_123 ) ) ;
+    .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_basis_input4_mem4_35 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_34 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_34 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_33 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_33 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_32 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_32 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_17 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_17 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_16 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_16 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_size12 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__2__mux_2level_size12 ( in , sram , sram_inv , out , VDD , VSS , 
+    p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -10007,168 +13177,227 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_17 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_32 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_33 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_34 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_35 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_basis_input4_mem4_31 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_30 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_30 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_29 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_29 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_28 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_28 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_15 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_15 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_14 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_14 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_size12_7 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__2__mux_2level_size12_7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -10179,169 +13408,229 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_88 ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_88 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_15 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_28 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_29 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_30 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_31 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( net_net_88 ) , .X ( out[0] ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( net_net_88 ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_basis_input4_mem4_27 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_26 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_26 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_25 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_25 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_24 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_24 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_13 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_13 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_12 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_12 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_size12_6 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__2__mux_2level_size12_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -10352,168 +13641,227 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_13 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_24 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_25 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_26 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_basis_input4_mem4_23 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_22 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_22 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_21 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_21 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_20 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_20 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_11 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_11 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_10 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_10 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_size12_5 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__2__mux_2level_size12_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -10524,171 +13872,231 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_11 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_20 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_21 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_22 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( aps_rename_506_ ) , 
-    .Y ( BUF_net_95 ) ) ;
+    .Y ( BUF_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_basis_input4_mem4_19 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_18 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_18 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_17 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_17 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_16 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_16 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_9 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_9 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_8 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_8 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_size12_4 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__2__mux_2level_size12_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -10699,168 +14107,227 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_8 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_9 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_16 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_17 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_18 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_basis_input4_mem4_15 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_14 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_14 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_13 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_13 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_12 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_12 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_7 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_7 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_6 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_6 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_size12_3 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__2__mux_2level_size12_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -10871,169 +14338,229 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_87 ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_87 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_7 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_12 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_13 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_14 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_15 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( net_net_87 ) , .X ( out[0] ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( net_net_87 ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_basis_input4_mem4_11 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_10 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_10 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_9 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_9 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_8 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_8 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_5 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_5 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_4 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_size12_2 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__2__mux_2level_size12_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -11044,168 +14571,227 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_5 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_8 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_9 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_10 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_basis_input4_mem4_7 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_6 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_6 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_5 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_5 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_4 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_4 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_3 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_2 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_2 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_size12_1 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__2__mux_2level_size12_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -11216,168 +14802,227 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_3 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_4 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_5 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_6 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_7 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module cbx_1__2__mux_2level_basis_input4_mem4_3 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_2 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_2 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_1 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_1 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_basis_input4_mem4_0 ( in , mem , mem_inv , out ) ;
+module cbx_1__2__mux_2level_basis_input4_mem4_0 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_1 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_1 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__local_encoder2to4_0 ( addr , data , data_inv ) ;
+module cbx_1__2__local_encoder2to4_0 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__2__mux_2level_size12_0 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__2__mux_2level_size12_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -11388,37 +15033,45 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__local_encoder2to4_1 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_0 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_1 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_2 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_basis_input4_mem4_3 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( aps_rename_505_ ) , 
-    .Y ( BUF_net_86 ) ) ;
+    .Y ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
@@ -11434,7 +15087,8 @@
     bottom_width_0_height_0__pin_0_ , bottom_width_0_height_0__pin_1_upper , 
     bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_OUT_BOT , 
     SC_IN_BOT , SC_OUT_TOP , pReset_E_in , pReset_W_in , pReset_W_out , 
-    pReset_S_out , pReset_E_out , prog_clk_0_S_in , prog_clk_0_W_out ) ;
+    pReset_S_out , pReset_E_out , prog_clk_0_S_in , prog_clk_0_W_out , VDD , 
+    VSS ) ;
 input  [0:0] pReset ;
 input  [0:29] chanx_left_in ;
 input  [0:29] chanx_right_in ;
@@ -11477,6 +15131,8 @@
 output pReset_E_out ;
 input  prog_clk_0_S_in ;
 output prog_clk_0_W_out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] prog_clk ;
 wire prog_clk_0 ;
@@ -11513,6 +15169,8 @@
 wire [0:0] mux_2level_size12_mem_6_ccff_tail ;
 wire [0:0] mux_2level_size12_mem_7_ccff_tail ;
 wire [0:0] mux_2level_size12_mem_8_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 assign pReset_W_in = pReset_E_in ;
 assign prog_clk_0 = prog_clk[0] ;
@@ -11525,7 +15183,8 @@
     .sram ( mux_2level_size12_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
         SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_103 ) ) ;
+    .out ( top_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_103 ) ) ;
 cbx_1__2__mux_2level_size12_1 mux_top_ipin_0 (
     .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , 
         chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , 
@@ -11534,7 +15193,8 @@
     .sram ( mux_2level_size12_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
         SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
-    .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_100 ) ) ;
+    .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_100 ) ) ;
 cbx_1__2__mux_2level_size12_2 mux_top_ipin_2 (
     .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , 
         chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
@@ -11543,7 +15203,8 @@
     .sram ( mux_2level_size12_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
         SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
-    .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_101 ) ) ;
+    .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_101 ) ) ;
 cbx_1__2__mux_2level_size12_3 mux_top_ipin_4 (
     .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , 
         chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , 
@@ -11552,7 +15213,8 @@
     .sram ( mux_2level_size12_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
         SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
-    .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_98 ) ) ;
+    .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_98 ) ) ;
 cbx_1__2__mux_2level_size12_4 mux_top_ipin_6 (
     .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , 
         chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , 
@@ -11562,7 +15224,7 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
         SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
     .out ( { aps_rename_510_ } ) ,
-    .p0 ( optlc_net_98 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_98 ) ) ;
 cbx_1__2__mux_2level_size12_5 mux_top_ipin_8 (
     .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , 
         chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
@@ -11571,7 +15233,8 @@
     .sram ( mux_2level_size12_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
         SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
-    .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_99 ) ) ;
+    .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_99 ) ) ;
 cbx_1__2__mux_2level_size12_6 mux_top_ipin_10 (
     .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , 
         chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , 
@@ -11581,7 +15244,7 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
         SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
     .out ( { ropt_net_119 } ) ,
-    .p0 ( optlc_net_99 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_99 ) ) ;
 cbx_1__2__mux_2level_size12_7 mux_top_ipin_12 (
     .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , 
         chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , 
@@ -11590,7 +15253,8 @@
     .sram ( mux_2level_size12_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
         SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
-    .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_103 ) ) ;
+    .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_103 ) ) ;
 cbx_1__2__mux_2level_size12 mux_top_ipin_14 (
     .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , 
         chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
@@ -11600,51 +15264,51 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
         SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
     .out ( { aps_rename_513_ } ) ,
-    .p0 ( optlc_net_101 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_101 ) ) ;
 cbx_1__2__mux_2level_size12_mem_0 mem_bottom_ipin_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
     .ccff_tail ( mux_2level_size12_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_0_sram ) ) ;
+    .mem_out ( mux_2level_size12_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_size12_mem_1 mem_top_ipin_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_1_sram ) ) ;
+    .mem_out ( mux_2level_size12_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_size12_mem_2 mem_top_ipin_2 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size10_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_2_sram ) ) ;
+    .mem_out ( mux_2level_size12_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_size12_mem_3 mem_top_ipin_4 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size10_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_3_sram ) ) ;
+    .mem_out ( mux_2level_size12_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_size12_mem_4 mem_top_ipin_6 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size10_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_4_sram ) ) ;
+    .mem_out ( mux_2level_size12_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_size12_mem_5 mem_top_ipin_8 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size10_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_5_sram ) ) ;
+    .mem_out ( mux_2level_size12_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_size12_mem_6 mem_top_ipin_10 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size10_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_6_sram ) ) ;
+    .mem_out ( mux_2level_size12_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_size12_mem_7 mem_top_ipin_12 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size10_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_7_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_7_sram ) ) ;
+    .mem_out ( mux_2level_size12_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_size12_mem mem_top_ipin_14 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size10_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_8_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_8_sram ) ) ;
+    .mem_out ( mux_2level_size12_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_size10_0 mux_top_ipin_1 (
     .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , 
         chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , 
@@ -11653,7 +15317,8 @@
     .sram ( mux_2level_size10_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
         SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
-    .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_100 ) ) ;
+    .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_100 ) ) ;
 cbx_1__2__mux_2level_size10_1 mux_top_ipin_3 (
     .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , 
         chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , 
@@ -11662,7 +15327,8 @@
     .sram ( mux_2level_size10_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
         SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
-    .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_100 ) ) ;
+    .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_100 ) ) ;
 cbx_1__2__mux_2level_size10_2 mux_top_ipin_5 (
     .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , 
         chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , 
@@ -11671,7 +15337,8 @@
     .sram ( mux_2level_size10_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
         SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
-    .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_102 ) ) ;
+    .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_102 ) ) ;
 cbx_1__2__mux_2level_size10_3 mux_top_ipin_7 (
     .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , 
         chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , 
@@ -11681,7 +15348,7 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
         SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
     .out ( { aps_rename_511_ } ) ,
-    .p0 ( optlc_net_99 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_99 ) ) ;
 cbx_1__2__mux_2level_size10_4 mux_top_ipin_9 (
     .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , 
         chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , 
@@ -11690,7 +15357,8 @@
     .sram ( mux_2level_size10_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
         SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
-    .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_98 ) ) ;
+    .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_98 ) ) ;
 cbx_1__2__mux_2level_size10_5 mux_top_ipin_11 (
     .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , 
         chanx_left_out[3] , chanx_right_out[12] , chanx_left_out[12] , 
@@ -11700,7 +15368,7 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
         SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
     .out ( { aps_rename_512_ } ) ,
-    .p0 ( optlc_net_99 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_99 ) ) ;
 cbx_1__2__mux_2level_size10_6 mux_top_ipin_13 (
     .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , 
         chanx_left_out[5] , chanx_right_out[14] , chanx_left_out[14] , 
@@ -11709,7 +15377,8 @@
     .sram ( mux_2level_size10_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
         SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
-    .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_102 ) ) ;
+    .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_102 ) ) ;
 cbx_1__2__mux_2level_size10 mux_top_ipin_15 (
     .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , 
         chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , 
@@ -11718,47 +15387,48 @@
     .sram ( mux_2level_size10_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , 
         SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
-    .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_100 ) ) ;
+    .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_100 ) ) ;
 cbx_1__2__mux_2level_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_size10_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_size10_0_sram ) ) ;
+    .mem_out ( mux_2level_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_size10_mem_1 mem_top_ipin_3 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_size10_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_size10_1_sram ) ) ;
+    .mem_out ( mux_2level_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_size10_mem_2 mem_top_ipin_5 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_size10_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_size10_2_sram ) ) ;
+    .mem_out ( mux_2level_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_size10_mem_3 mem_top_ipin_7 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_size10_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_size10_3_sram ) ) ;
+    .mem_out ( mux_2level_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_size10_mem_4 mem_top_ipin_9 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_size10_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_size10_4_sram ) ) ;
+    .mem_out ( mux_2level_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_size10_mem_5 mem_top_ipin_11 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_size10_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_size10_5_sram ) ) ;
+    .mem_out ( mux_2level_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_size10_mem_6 mem_top_ipin_13 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_7_ccff_tail ) , 
     .ccff_tail ( mux_2level_size10_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_size10_6_sram ) ) ;
+    .mem_out ( mux_2level_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__mux_2level_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_8_ccff_tail ) ,
     .ccff_tail ( { ccff_tail_mid } ) ,
-    .mem_out ( mux_2level_size10_7_sram ) ) ;
+    .mem_out ( mux_2level_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( 
     .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
@@ -11767,471 +15437,604 @@
     .io_outpad ( bottom_width_0_height_0__pin_0_ ) ,
     .ccff_head ( { ccff_tail_mid } ) ,
     .io_inpad ( bottom_width_0_height_0__pin_1_lower ) , 
-    .ccff_tail ( ccff_tail ) ) ;
-sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ;
+    .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_W_in ) , 
-    .X ( pReset_W_out ) ) ;
+    .X ( pReset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 pReset_S_FTB01 ( .A ( pReset_W_in ) , 
-    .X ( aps_rename_514_ ) ) ;
+    .X ( aps_rename_514_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_W_in ) , 
-    .X ( aps_rename_515_ ) ) ;
+    .X ( aps_rename_515_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , 
-    .X ( prog_clk[0] ) ) ;
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , 
-    .X ( ctsbuf_net_1104 ) ) ;
+    .X ( ctsbuf_net_1104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , 
-    .X ( chanx_right_out[0] ) ) ;
+    .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , 
-    .X ( chanx_right_out[1] ) ) ;
+    .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , 
-    .X ( chanx_right_out[2] ) ) ;
+    .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) , 
-    .X ( chanx_right_out[3] ) ) ;
+    .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) , 
-    .X ( chanx_right_out[4] ) ) ;
+    .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) , 
-    .X ( chanx_right_out[5] ) ) ;
+    .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) , 
-    .X ( chanx_right_out[6] ) ) ;
+    .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) , 
-    .X ( chanx_right_out[7] ) ) ;
+    .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) , 
-    .X ( chanx_right_out[8] ) ) ;
+    .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) , 
-    .X ( chanx_right_out[9] ) ) ;
+    .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) , 
-    .X ( chanx_right_out[10] ) ) ;
+    .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) , 
-    .X ( chanx_right_out[11] ) ) ;
+    .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) , 
-    .X ( chanx_right_out[12] ) ) ;
+    .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) , 
-    .X ( chanx_right_out[13] ) ) ;
+    .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) , 
-    .X ( chanx_right_out[14] ) ) ;
+    .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) , 
-    .X ( chanx_right_out[15] ) ) ;
+    .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) , 
-    .X ( chanx_right_out[16] ) ) ;
+    .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) , 
-    .X ( chanx_right_out[17] ) ) ;
+    .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , 
-    .X ( chanx_right_out[18] ) ) ;
+    .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , 
-    .X ( chanx_right_out[19] ) ) ;
+    .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[20] ) , 
-    .X ( chanx_right_out[20] ) ) ;
+    .X ( chanx_right_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[21] ) , 
-    .X ( chanx_right_out[21] ) ) ;
+    .X ( chanx_right_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[22] ) , 
-    .X ( chanx_right_out[22] ) ) ;
+    .X ( chanx_right_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[23] ) , 
-    .X ( chanx_right_out[23] ) ) ;
+    .X ( chanx_right_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[24] ) , 
-    .X ( chanx_right_out[24] ) ) ;
+    .X ( chanx_right_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[25] ) , 
-    .X ( chanx_right_out[25] ) ) ;
+    .X ( chanx_right_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[26] ) , 
-    .X ( chanx_right_out[26] ) ) ;
+    .X ( chanx_right_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[27] ) , 
-    .X ( chanx_right_out[27] ) ) ;
+    .X ( chanx_right_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[28] ) , 
-    .X ( chanx_right_out[28] ) ) ;
+    .X ( chanx_right_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[29] ) , 
-    .X ( chanx_right_out[29] ) ) ;
+    .X ( chanx_right_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) , 
-    .X ( chanx_left_out[0] ) ) ;
+    .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) , 
-    .X ( chanx_left_out[1] ) ) ;
+    .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) , 
-    .X ( chanx_left_out[2] ) ) ;
+    .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) , 
-    .X ( chanx_left_out[3] ) ) ;
+    .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[4] ) , 
-    .X ( chanx_left_out[4] ) ) ;
+    .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[5] ) , 
-    .X ( chanx_left_out[5] ) ) ;
+    .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[6] ) , 
-    .X ( chanx_left_out[6] ) ) ;
+    .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[7] ) , 
-    .X ( chanx_left_out[7] ) ) ;
+    .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[8] ) , 
-    .X ( chanx_left_out[8] ) ) ;
+    .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[9] ) , 
-    .X ( chanx_left_out[9] ) ) ;
+    .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[10] ) , 
-    .X ( chanx_left_out[10] ) ) ;
+    .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[11] ) , 
-    .X ( chanx_left_out[11] ) ) ;
+    .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[12] ) , 
-    .X ( chanx_left_out[12] ) ) ;
+    .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[13] ) , 
-    .X ( chanx_left_out[13] ) ) ;
+    .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[14] ) , 
-    .X ( chanx_left_out[14] ) ) ;
+    .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[15] ) , 
-    .X ( chanx_left_out[15] ) ) ;
+    .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[16] ) , 
-    .X ( chanx_left_out[16] ) ) ;
+    .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[17] ) , 
-    .X ( chanx_left_out[17] ) ) ;
+    .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[18] ) , 
-    .X ( chanx_left_out[18] ) ) ;
+    .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[19] ) , 
-    .X ( chanx_left_out[19] ) ) ;
+    .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[20] ) , 
-    .X ( chanx_left_out[20] ) ) ;
+    .X ( chanx_left_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[21] ) , 
-    .X ( chanx_left_out[21] ) ) ;
+    .X ( chanx_left_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[22] ) , 
-    .X ( chanx_left_out[22] ) ) ;
+    .X ( chanx_left_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[23] ) , 
-    .X ( chanx_left_out[23] ) ) ;
+    .X ( chanx_left_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[24] ) , 
-    .X ( chanx_left_out[24] ) ) ;
+    .X ( chanx_left_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[25] ) , 
-    .X ( chanx_left_out[25] ) ) ;
+    .X ( chanx_left_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[26] ) , 
-    .X ( chanx_left_out[26] ) ) ;
+    .X ( chanx_left_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[27] ) , 
-    .X ( chanx_left_out[27] ) ) ;
+    .X ( chanx_left_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[28] ) , 
-    .X ( chanx_left_out[28] ) ) ;
+    .X ( chanx_left_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[29] ) , 
-    .X ( chanx_left_out[29] ) ) ;
+    .X ( chanx_left_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_79__78 ( 
     .A ( bottom_width_0_height_0__pin_1_lower[0] ) , 
-    .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ;
-sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
-sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ;
+    .X ( bottom_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , 
-    .HI ( optlc_net_98 ) ) ;
+    .HI ( optlc_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , 
-    .HI ( optlc_net_99 ) ) ;
+    .HI ( optlc_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , 
-    .HI ( optlc_net_100 ) ) ;
+    .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , 
-    .HI ( optlc_net_101 ) ) ;
+    .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_73 ) , 
-    .HI ( optlc_net_102 ) ) ;
+    .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_74 ) , 
-    .HI ( optlc_net_103 ) ) ;
+    .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_111 ( .A ( aps_rename_513_ ) , 
-    .X ( bottom_grid_pin_14_[0] ) ) ;
+    .X ( bottom_grid_pin_14_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_35_inst_112 ( .A ( aps_rename_510_ ) , 
-    .X ( bottom_grid_pin_6_[0] ) ) ;
+    .X ( bottom_grid_pin_6_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_35_inst_113 ( .A ( aps_rename_511_ ) , 
-    .X ( bottom_grid_pin_7_[0] ) ) ;
+    .X ( bottom_grid_pin_7_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_35_inst_114 ( .A ( aps_rename_512_ ) , 
-    .X ( bottom_grid_pin_11_[0] ) ) ;
+    .X ( bottom_grid_pin_11_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_115 ( .A ( aps_rename_515_ ) , 
-    .X ( pReset_E_out ) ) ;
+    .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_116 ( .A ( aps_rename_514_ ) , 
-    .X ( pReset_S_out ) ) ;
+    .X ( pReset_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ropt_mt_inst_1368 ( .A ( ropt_net_119 ) , 
-    .X ( bottom_grid_pin_10_[0] ) ) ;
+    .X ( bottom_grid_pin_10_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__clkbuf_8 cts_buf_3711262 ( .A ( ctsbuf_net_1104 ) , 
-    .X ( prog_clk_0_W_out ) ) ;
+    .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_size10_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
 
 wire copt_net_109 ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_109 ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_109 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( copt_net_111 ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_109 ) , 
-    .X ( mem_out[3] ) ) ;
+    .X ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1361 ( .A ( mem_out[3] ) , 
-    .X ( copt_net_110 ) ) ;
+    .X ( copt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1362 ( .A ( copt_net_112 ) , 
-    .X ( copt_net_111 ) ) ;
+    .X ( copt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1363 ( .A ( copt_net_110 ) , 
-    .X ( copt_net_112 ) ) ;
+    .X ( copt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_size10_mem_6 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_size10_mem_5 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_size10_mem_4 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_size10_mem_3 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_size10_mem_2 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_size10_mem_1 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_size10_mem_0 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input2_mem2 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input2_mem2 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_basis_input4_mem4 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_54 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_54 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_53 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_53 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_30 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_30 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_size10 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__1__mux_2level_size10 ( in , sram , sram_inv , out , VDD , VSS , 
+    p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -12242,163 +16045,221 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_30 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__local_encoder2to4 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_53 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_54 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cbx_1__1__mux_2level_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input2_mem2_6 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input2_mem2_6 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_basis_input4_mem4_52 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_51 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_51 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_50 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_50 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_29 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_29 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_28 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_28 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__1__mux_2level_size10_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -12409,163 +16270,221 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_28 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_29 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_50 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_51 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_52 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cbx_1__1__mux_2level_basis_input2_mem2_6 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input2_mem2_5 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input2_mem2_5 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_basis_input4_mem4_49 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_48 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_48 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_47 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_47 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_27 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_27 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_26 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_26 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__1__mux_2level_size10_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -12576,163 +16495,221 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_27 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_47 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_48 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_49 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cbx_1__1__mux_2level_basis_input2_mem2_5 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input2_mem2_4 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input2_mem2_4 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_basis_input4_mem4_46 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_45 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_45 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_44 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_44 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_25 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_25 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_24 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_24 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__1__mux_2level_size10_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -12743,166 +16720,225 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_508_ ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( aps_rename_508_ ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_24 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_25 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_44 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_45 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_46 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cbx_1__1__mux_2level_basis_input2_mem2_4 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_508_ ) , 
-    .Y ( BUF_net_87 ) ) ;
+    .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input2_mem2_3 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input2_mem2_3 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_basis_input4_mem4_43 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_42 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_42 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_41 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_41 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_23 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_23 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_22 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_22 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__1__mux_2level_size10_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -12913,163 +16949,221 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_22 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_23 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_41 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_42 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_43 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cbx_1__1__mux_2level_basis_input2_mem2_3 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input2_mem2_2 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input2_mem2_2 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_basis_input4_mem4_40 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_39 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_39 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_38 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_38 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_21 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_21 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_20 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_20 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__1__mux_2level_size10_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -13080,163 +17174,221 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_20 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_21 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_38 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_39 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_40 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cbx_1__1__mux_2level_basis_input2_mem2_2 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input2_mem2_1 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input2_mem2_1 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_basis_input4_mem4_37 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_36 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_36 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_35 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_35 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_19 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_19 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_18 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_18 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__1__mux_2level_size10_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -13247,163 +17399,221 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_18 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_19 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_35 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_36 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_37 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cbx_1__1__mux_2level_basis_input2_mem2_1 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input2_mem2_0 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input2_mem2_0 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_basis_input4_mem4_34 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_33 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_33 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_32 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_32 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_17 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_17 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_16 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_16 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__1__mux_2level_size10_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -13414,345 +17624,485 @@
 wire [0:0] mux_2level_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_85 ) ) ;
+    .A ( mux_2level_basis_input4_mem4_2_out[0] ) , .X ( net_net_85 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_17 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_32 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_33 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_34 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input2_mem2_0_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 cbx_1__1__mux_2level_basis_input2_mem2_0 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( net_net_85 ) , .X ( out[0] ) ) ;
+    .out ( mux_2level_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( net_net_85 ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_size12_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_size12_mem_6 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_size12_mem_5 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_size12_mem_4 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_size12_mem_3 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_size12_mem_2 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_size12_mem_1 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_size12_mem_0 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_123 ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( ccff_head[0] ) , 
-    .X ( copt_net_101 ) ) ;
+    .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_101 ) , 
-    .X ( copt_net_102 ) ) ;
+    .X ( copt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_102 ) , 
-    .X ( copt_net_103 ) ) ;
+    .X ( copt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_103 ) , 
-    .X ( copt_net_104 ) ) ;
+    .X ( copt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_104 ) , 
-    .X ( copt_net_105 ) ) ;
+    .X ( copt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( copt_net_105 ) , 
-    .X ( copt_net_106 ) ) ;
+    .X ( copt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1373 ( .A ( copt_net_106 ) , 
-    .X ( ropt_net_122 ) ) ;
+    .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1374 ( .A ( ropt_net_122 ) , 
-    .X ( ropt_net_123 ) ) ;
+    .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_basis_input4_mem4_31 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_30 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_30 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_29 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_29 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_28 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_28 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_15 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_15 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_14 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_14 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_size12 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__1__mux_2level_size12 ( in , sram , sram_inv , out , VDD , VSS , 
+    p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -13763,168 +18113,227 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_15 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_28 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_29 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_30 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_31 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_basis_input4_mem4_27 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_26 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_26 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_25 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_25 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_24 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_24 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_13 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_13 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_12 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_12 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_size12_6 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__1__mux_2level_size12_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -13935,171 +18344,231 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_507_ ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_13 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_24 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_25 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_26 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( aps_rename_507_ ) , 
-    .Y ( BUF_net_84 ) ) ;
+    .Y ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_basis_input4_mem4_23 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_22 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_22 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_21 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_21 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_20 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_20 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_11 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_11 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_10 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_10 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_size12_5 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__1__mux_2level_size12_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -14110,168 +18579,227 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_11 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_20 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_21 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_22 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_basis_input4_mem4_19 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_18 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_18 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_17 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_17 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_16 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_16 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_9 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_9 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_8 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_8 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_size12_4 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__1__mux_2level_size12_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -14282,168 +18810,227 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_8 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_9 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_16 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_17 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_18 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_basis_input4_mem4_15 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_14 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_14 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_13 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_13 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_12 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_12 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_7 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_7 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_6 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_6 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_size12_3 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__1__mux_2level_size12_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -14454,171 +19041,231 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_506_ ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_7 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_12 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_13 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_14 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_15 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( aps_rename_506_ ) , 
-    .Y ( BUF_net_82 ) ) ;
+    .Y ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_basis_input4_mem4_11 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_10 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_10 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_9 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_9 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_8 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_8 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_5 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_5 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_4 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_size12_2 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__1__mux_2level_size12_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -14629,169 +19276,229 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_80 ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_80 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_5 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_8 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_9 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_10 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( net_net_80 ) , .X ( out[0] ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( net_net_80 ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_basis_input4_mem4_7 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_6 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_6 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_5 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_5 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_4 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_4 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_3 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_2 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_2 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_size12_1 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__1__mux_2level_size12_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -14802,171 +19509,231 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( aps_rename_505_ ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_3 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_4 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_5 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_6 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_7 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_505_ ) , 
-    .Y ( BUF_net_93 ) ) ;
+    .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__1__mux_2level_basis_input4_mem4_3 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_2 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_2 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_1 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_1 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_basis_input4_mem4_0 ( in , mem , mem_inv , out ) ;
+module cbx_1__1__mux_2level_basis_input4_mem4_0 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_1 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_1 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__local_encoder2to4_0 ( addr , data , data_inv ) ;
+module cbx_1__1__local_encoder2to4_0 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__1__mux_2level_size12_0 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__1__mux_2level_size12_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -14977,34 +19744,41 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__local_encoder2to4_1 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_0 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_1 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_2 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_basis_input4_mem4_3 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
@@ -15024,7 +19798,7 @@
     prog_clk_3_W_in , prog_clk_3_E_in , prog_clk_3_E_out , prog_clk_3_W_out , 
     clk_1_W_in , clk_1_E_in , clk_1_N_out , clk_1_S_out , clk_2_E_in , 
     clk_2_W_in , clk_2_W_out , clk_2_E_out , clk_3_W_in , clk_3_E_in , 
-    clk_3_E_out , clk_3_W_out ) ;
+    clk_3_E_out , clk_3_W_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:29] chanx_left_in ;
 input  [0:29] chanx_right_in ;
@@ -15087,6 +19861,8 @@
 input  clk_3_E_in ;
 output clk_3_E_out ;
 output clk_3_W_out ;
+input  VDD ;
+input  VSS ;
 
 wire ropt_net_117 ;
 wire ropt_net_121 ;
@@ -15127,6 +19903,8 @@
 wire [0:0] mux_2level_size12_mem_5_ccff_tail ;
 wire [0:0] mux_2level_size12_mem_6_ccff_tail ;
 wire [0:0] mux_2level_size12_mem_7_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 assign pReset_W_in = pReset_E_in ;
 assign prog_clk_0 = prog_clk[0] ;
@@ -15145,7 +19923,8 @@
     .sram ( mux_2level_size12_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
         SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_96 ) ) ;
+    .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_96 ) ) ;
 cbx_1__1__mux_2level_size12_1 mux_top_ipin_2 (
     .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , 
         chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , 
@@ -15154,7 +19933,8 @@
     .sram ( mux_2level_size12_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
         SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
-    .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_99 ) ) ;
+    .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_99 ) ) ;
 cbx_1__1__mux_2level_size12_2 mux_top_ipin_4 (
     .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , 
         chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , 
@@ -15163,7 +19943,8 @@
     .sram ( mux_2level_size12_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
         SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
-    .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_94 ) ) ;
+    .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_94 ) ) ;
 cbx_1__1__mux_2level_size12_3 mux_top_ipin_6 (
     .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , 
         chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , 
@@ -15172,7 +19953,8 @@
     .sram ( mux_2level_size12_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
         SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
-    .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_96 ) ) ;
+    .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_96 ) ) ;
 cbx_1__1__mux_2level_size12_4 mux_top_ipin_8 (
     .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , 
         chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , 
@@ -15182,7 +19964,7 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
         SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
     .out ( { ZBUF_4_f_0 } ) ,
-    .p0 ( optlc_net_97 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_97 ) ) ;
 cbx_1__1__mux_2level_size12_5 mux_top_ipin_10 (
     .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , 
         chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , 
@@ -15192,7 +19974,7 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
         SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
     .out ( { ropt_net_115 } ) ,
-    .p0 ( optlc_net_94 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_94 ) ) ;
 cbx_1__1__mux_2level_size12_6 mux_top_ipin_12 (
     .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , 
         chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , 
@@ -15201,7 +19983,8 @@
     .sram ( mux_2level_size12_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
         SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
-    .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_96 ) ) ;
+    .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_96 ) ) ;
 cbx_1__1__mux_2level_size12 mux_top_ipin_14 (
     .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , 
         chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , 
@@ -15210,46 +19993,47 @@
     .sram ( mux_2level_size12_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
         SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
-    .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_95 ) ) ;
+    .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_95 ) ) ;
 cbx_1__1__mux_2level_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
     .ccff_tail ( mux_2level_size12_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_0_sram ) ) ;
+    .mem_out ( mux_2level_size12_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_size12_mem_1 mem_top_ipin_2 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size10_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_1_sram ) ) ;
+    .mem_out ( mux_2level_size12_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_size12_mem_2 mem_top_ipin_4 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size10_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_2_sram ) ) ;
+    .mem_out ( mux_2level_size12_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_size12_mem_3 mem_top_ipin_6 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size10_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_3_sram ) ) ;
+    .mem_out ( mux_2level_size12_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_size12_mem_4 mem_top_ipin_8 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size10_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_4_sram ) ) ;
+    .mem_out ( mux_2level_size12_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_size12_mem_5 mem_top_ipin_10 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size10_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_5_sram ) ) ;
+    .mem_out ( mux_2level_size12_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_size12_mem_6 mem_top_ipin_12 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size10_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_6_sram ) ) ;
+    .mem_out ( mux_2level_size12_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_size12_mem mem_top_ipin_14 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size10_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_7_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_7_sram ) ) ;
+    .mem_out ( mux_2level_size12_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_size10_0 mux_top_ipin_1 (
     .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , 
         chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , 
@@ -15258,7 +20042,8 @@
     .sram ( mux_2level_size10_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
         SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
-    .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_94 ) ) ;
+    .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_94 ) ) ;
 cbx_1__1__mux_2level_size10_1 mux_top_ipin_3 (
     .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , 
         chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
@@ -15267,7 +20052,8 @@
     .sram ( mux_2level_size10_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
         SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
-    .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_99 ) ) ;
+    .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_99 ) ) ;
 cbx_1__1__mux_2level_size10_2 mux_top_ipin_5 (
     .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , 
         chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , 
@@ -15277,7 +20063,7 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
         SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
     .out ( { ZBUF_6_f_0 } ) ,
-    .p0 ( optlc_net_94 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_94 ) ) ;
 cbx_1__1__mux_2level_size10_3 mux_top_ipin_7 (
     .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , 
         chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , 
@@ -15287,7 +20073,7 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
         SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
     .out ( { ropt_net_114 } ) ,
-    .p0 ( optlc_net_97 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_97 ) ) ;
 cbx_1__1__mux_2level_size10_4 mux_top_ipin_9 (
     .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , 
         chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
@@ -15296,7 +20082,8 @@
     .sram ( mux_2level_size10_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
         SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
-    .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_98 ) ) ;
+    .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_98 ) ) ;
 cbx_1__1__mux_2level_size10_5 mux_top_ipin_11 (
     .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , 
         chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , 
@@ -15305,7 +20092,8 @@
     .sram ( mux_2level_size10_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
         SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
-    .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_95 ) ) ;
+    .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_95 ) ) ;
 cbx_1__1__mux_2level_size10_6 mux_top_ipin_13 (
     .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , 
         chanx_left_out[4] , chanx_right_out[13] , chanx_left_out[13] , 
@@ -15314,7 +20102,8 @@
     .sram ( mux_2level_size10_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
         SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
-    .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_94 ) ) ;
+    .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_94 ) ) ;
 cbx_1__1__mux_2level_size10 mux_top_ipin_15 (
     .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , 
         chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , 
@@ -15324,282 +20113,296 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
         SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
     .out ( { ZBUF_4_f_1 } ) ,
-    .p0 ( optlc_net_97 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_97 ) ) ;
 cbx_1__1__mux_2level_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_size10_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_size10_0_sram ) ) ;
+    .mem_out ( mux_2level_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_size10_mem_1 mem_top_ipin_3 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_size10_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_size10_1_sram ) ) ;
+    .mem_out ( mux_2level_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_size10_mem_2 mem_top_ipin_5 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_size10_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_size10_2_sram ) ) ;
+    .mem_out ( mux_2level_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_size10_mem_3 mem_top_ipin_7 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_size10_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_size10_3_sram ) ) ;
+    .mem_out ( mux_2level_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_size10_mem_4 mem_top_ipin_9 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_size10_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_size10_4_sram ) ) ;
+    .mem_out ( mux_2level_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_size10_mem_5 mem_top_ipin_11 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_size10_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_size10_5_sram ) ) ;
+    .mem_out ( mux_2level_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_size10_mem_6 mem_top_ipin_13 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_size10_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_size10_6_sram ) ) ;
+    .mem_out ( mux_2level_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1__mux_2level_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_7_ccff_tail ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_size10_7_sram ) ) ;
-sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_size10_7_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_W_in ) , 
-    .X ( pReset_W_out ) ) ;
+    .X ( pReset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 pReset_S_FTB01 ( .A ( pReset_W_in ) , 
-    .X ( aps_rename_509_ ) ) ;
+    .X ( aps_rename_509_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__bufbuf_16 pReset_E_FTB01 ( .A ( pReset_W_in ) , 
-    .X ( pReset_E_out ) ) ;
+    .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
-    .X ( prog_clk[0] ) ) ;
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_2 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , 
-    .X ( ctsbuf_net_1100 ) ) ;
+    .X ( ctsbuf_net_1100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__bufbuf_16 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , 
-    .X ( prog_clk_1_N_out ) ) ;
+    .X ( prog_clk_1_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__bufbuf_16 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , 
-    .X ( prog_clk_1_S_out ) ) ;
+    .X ( prog_clk_1_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__bufbuf_16 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , 
-    .X ( prog_clk_2_W_out ) ) ;
+    .X ( prog_clk_2_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , 
-    .X ( aps_rename_510_ ) ) ;
+    .X ( aps_rename_510_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , 
-    .X ( aps_rename_511_ ) ) ;
+    .X ( aps_rename_511_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__bufbuf_16 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) , 
-    .X ( prog_clk_3_W_out ) ) ;
+    .X ( prog_clk_3_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , 
-    .X ( clk_1_N_out ) ) ;
+    .X ( clk_1_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_4 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , 
-    .X ( clk_1_S_out ) ) ;
-sky130_fd_sc_hd__buf_1 clk_2_W_FTB01 ( .A ( clk_2_W_in ) , .X ( net_net_90 ) ) ;
+    .X ( clk_1_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 clk_2_W_FTB01 ( .A ( clk_2_W_in ) , .X ( net_net_90 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__bufbuf_16 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , 
-    .X ( clk_2_E_out ) ) ;
-sky130_fd_sc_hd__buf_1 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , .X ( net_net_91 ) ) ;
+    .X ( clk_2_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , .X ( net_net_91 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__bufbuf_16 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , 
-    .X ( clk_3_W_out ) ) ;
+    .X ( clk_3_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) , 
-    .X ( chanx_right_out[0] ) ) ;
+    .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chanx_left_in[1] ) , 
-    .X ( chanx_right_out[1] ) ) ;
+    .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[2] ) , 
-    .X ( chanx_right_out[2] ) ) ;
+    .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[3] ) , 
-    .X ( chanx_right_out[3] ) ) ;
+    .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[4] ) , 
-    .X ( chanx_right_out[4] ) ) ;
+    .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[5] ) , 
-    .X ( chanx_right_out[5] ) ) ;
+    .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[6] ) , 
-    .X ( chanx_right_out[6] ) ) ;
+    .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[7] ) , 
-    .X ( chanx_right_out[7] ) ) ;
+    .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[8] ) , 
-    .X ( chanx_right_out[8] ) ) ;
+    .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[9] ) , 
-    .X ( chanx_right_out[9] ) ) ;
+    .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[10] ) , 
-    .X ( chanx_right_out[10] ) ) ;
+    .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[11] ) , 
-    .X ( chanx_right_out[11] ) ) ;
+    .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[12] ) , 
-    .X ( chanx_right_out[12] ) ) ;
+    .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[13] ) , 
-    .X ( chanx_right_out[13] ) ) ;
+    .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[14] ) , 
-    .X ( chanx_right_out[14] ) ) ;
+    .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[15] ) , 
-    .X ( chanx_right_out[15] ) ) ;
+    .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[16] ) , 
-    .X ( chanx_right_out[16] ) ) ;
+    .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[17] ) , 
-    .X ( chanx_right_out[17] ) ) ;
+    .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[18] ) , 
-    .X ( chanx_right_out[18] ) ) ;
+    .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[19] ) , 
-    .X ( chanx_right_out[19] ) ) ;
+    .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[20] ) , 
-    .X ( chanx_right_out[20] ) ) ;
+    .X ( chanx_right_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[21] ) , 
-    .X ( chanx_right_out[21] ) ) ;
+    .X ( chanx_right_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[22] ) , 
-    .X ( chanx_right_out[22] ) ) ;
+    .X ( chanx_right_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_left_in[23] ) , 
-    .X ( ropt_net_117 ) ) ;
+    .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[24] ) , 
-    .X ( chanx_right_out[24] ) ) ;
+    .X ( chanx_right_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[25] ) , 
-    .X ( chanx_right_out[25] ) ) ;
+    .X ( chanx_right_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[26] ) , 
-    .X ( chanx_right_out[26] ) ) ;
+    .X ( chanx_right_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[27] ) , 
-    .X ( chanx_right_out[27] ) ) ;
+    .X ( chanx_right_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[28] ) , 
-    .X ( chanx_right_out[28] ) ) ;
+    .X ( chanx_right_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[29] ) , 
-    .X ( chanx_right_out[29] ) ) ;
+    .X ( chanx_right_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[0] ) , 
-    .X ( chanx_left_out[0] ) ) ;
+    .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[1] ) , 
-    .X ( chanx_left_out[1] ) ) ;
+    .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[2] ) , 
-    .X ( chanx_left_out[2] ) ) ;
+    .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[3] ) , 
-    .X ( chanx_left_out[3] ) ) ;
+    .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[4] ) , 
-    .X ( chanx_left_out[4] ) ) ;
+    .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[5] ) , 
-    .X ( chanx_left_out[5] ) ) ;
+    .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[6] ) , 
-    .X ( chanx_left_out[6] ) ) ;
+    .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[7] ) , 
-    .X ( chanx_left_out[7] ) ) ;
+    .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[8] ) , 
-    .X ( chanx_left_out[8] ) ) ;
+    .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[9] ) , 
-    .X ( chanx_left_out[9] ) ) ;
+    .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[10] ) , 
-    .X ( chanx_left_out[10] ) ) ;
+    .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[11] ) , 
-    .X ( chanx_left_out[11] ) ) ;
+    .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[12] ) , 
-    .X ( chanx_left_out[12] ) ) ;
+    .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[13] ) , 
-    .X ( chanx_left_out[13] ) ) ;
+    .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[14] ) , 
-    .X ( chanx_left_out[14] ) ) ;
+    .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[15] ) , 
-    .X ( chanx_left_out[15] ) ) ;
+    .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[16] ) , 
-    .X ( chanx_left_out[16] ) ) ;
+    .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[17] ) , 
-    .X ( chanx_left_out[17] ) ) ;
+    .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[18] ) , 
-    .X ( chanx_left_out[18] ) ) ;
+    .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[19] ) , 
-    .X ( chanx_left_out[19] ) ) ;
+    .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[20] ) , 
-    .X ( chanx_left_out[20] ) ) ;
+    .X ( chanx_left_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[21] ) , 
-    .X ( chanx_left_out[21] ) ) ;
+    .X ( chanx_left_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[22] ) , 
-    .X ( chanx_left_out[22] ) ) ;
+    .X ( chanx_left_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( chanx_right_in[23] ) , 
-    .X ( ropt_net_121 ) ) ;
+    .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[24] ) , 
-    .X ( chanx_left_out[24] ) ) ;
+    .X ( chanx_left_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[25] ) , 
-    .X ( chanx_left_out[25] ) ) ;
+    .X ( chanx_left_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[26] ) , 
-    .X ( chanx_left_out[26] ) ) ;
+    .X ( chanx_left_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[27] ) , 
-    .X ( chanx_left_out[27] ) ) ;
+    .X ( chanx_left_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[28] ) , 
-    .X ( chanx_left_out[28] ) ) ;
+    .X ( chanx_left_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[29] ) , 
-    .X ( chanx_left_out[29] ) ) ;
-sky130_fd_sc_hd__buf_6 FTB_77__76 ( .A ( SC_IN_TOP ) , .X ( ropt_net_116 ) ) ;
-sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( SC_IN_BOT ) , .X ( ropt_net_119 ) ) ;
+    .X ( chanx_left_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_77__76 ( .A ( SC_IN_TOP ) , .X ( ropt_net_116 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( SC_IN_BOT ) , .X ( ropt_net_119 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( REGIN_FEEDTHROUGH ) , 
-    .X ( ropt_net_118 ) ) ;
+    .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( CIN_FEEDTHROUGH ) , 
-    .X ( ropt_net_120 ) ) ;
+    .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , 
-    .Y ( prog_clk_3_E_out ) ) ;
+    .Y ( prog_clk_3_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_511_ ) , 
-    .Y ( BUF_net_89 ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_90 ( .A ( net_net_90 ) , .X ( clk_2_W_out ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( net_net_91 ) , .X ( clk_3_E_out ) ) ;
+    .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_90 ( .A ( net_net_90 ) , .X ( clk_2_W_out ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( net_net_91 ) , .X ( clk_3_E_out ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , 
-    .HI ( optlc_net_94 ) ) ;
+    .HI ( optlc_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , 
-    .HI ( optlc_net_95 ) ) ;
+    .HI ( optlc_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , 
-    .HI ( optlc_net_96 ) ) ;
+    .HI ( optlc_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , 
-    .HI ( optlc_net_97 ) ) ;
+    .HI ( optlc_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , 
-    .HI ( optlc_net_98 ) ) ;
+    .HI ( optlc_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , 
-    .HI ( optlc_net_99 ) ) ;
+    .HI ( optlc_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_106 ( .A ( aps_rename_510_ ) , 
-    .X ( prog_clk_2_E_out ) ) ;
+    .X ( prog_clk_2_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_107 ( .A ( aps_rename_509_ ) , 
-    .X ( pReset_S_out ) ) ;
+    .X ( pReset_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1346 ( .A ( ZBUF_6_f_0 ) , 
-    .X ( bottom_grid_pin_5_[0] ) ) ;
+    .X ( bottom_grid_pin_5_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 cts_buf_3711253 ( .A ( ctsbuf_net_1100 ) , 
-    .X ( prog_clk_0_W_out ) ) ;
+    .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_1347 ( .A ( ZBUF_4_f_0 ) , 
-    .X ( bottom_grid_pin_8_[0] ) ) ;
+    .X ( bottom_grid_pin_8_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_1348 ( .A ( ZBUF_4_f_1 ) , 
-    .X ( bottom_grid_pin_15_[0] ) ) ;
+    .X ( bottom_grid_pin_15_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_2 ropt_mt_inst_1365 ( .A ( ropt_net_114 ) , 
-    .X ( bottom_grid_pin_7_[0] ) ) ;
+    .X ( bottom_grid_pin_7_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_2 ropt_mt_inst_1366 ( .A ( ropt_net_115 ) , 
-    .X ( bottom_grid_pin_10_[0] ) ) ;
+    .X ( bottom_grid_pin_10_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1367 ( .A ( ropt_net_116 ) , 
-    .X ( SC_OUT_BOT ) ) ;
+    .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1368 ( .A ( ropt_net_117 ) , 
-    .X ( chanx_right_out[23] ) ) ;
+    .X ( chanx_right_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1369 ( .A ( ropt_net_118 ) , 
-    .X ( REGOUT_FEEDTHROUGH ) ) ;
+    .X ( REGOUT_FEEDTHROUGH ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1370 ( .A ( ropt_net_119 ) , 
-    .X ( SC_OUT_TOP ) ) ;
+    .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1371 ( .A ( ropt_net_120 ) , 
-    .X ( COUT_FEEDTHROUGH ) ) ;
+    .X ( COUT_FEEDTHROUGH ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1372 ( .A ( ropt_net_121 ) , 
-    .X ( chanx_left_out[23] ) ) ;
+    .X ( chanx_left_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , 
-    prog_clk , ccff_head , ccff_tail , mem_out ) ;
+    prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:0] mem_out ;
+input  VDD ;
+input  VSS ;
 
 wire copt_net_132 ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_132 ) ) ;
-sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_132 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_2 copt_h_inst_1369 ( .A ( copt_net_132 ) , 
-    .X ( copt_net_128 ) ) ;
+    .X ( copt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1370 ( .A ( copt_net_128 ) , 
-    .X ( copt_net_129 ) ) ;
+    .X ( copt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1371 ( .A ( copt_net_129 ) , 
-    .X ( copt_net_130 ) ) ;
+    .X ( copt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1372 ( .A ( copt_net_130 ) , 
-    .X ( copt_net_131 ) ) ;
+    .X ( copt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1373 ( .A ( copt_net_131 ) , 
-    .X ( mem_out[0] ) ) ;
+    .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
-    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ;
 input  SOC_IN ;
 output SOC_OUT ;
 output SOC_DIR ;
@@ -15607,26 +20410,34 @@
 input  FPGA_OUT ;
 input  FPGA_DIR ;
 input  IO_ISOL_N ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
-    .B ( IO_ISOL_N ) , .Y ( aps_rename_510_ ) ) ;
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_510_ ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_510_ ) , 
-    .Y ( SOC_DIR_N ) ) ;
+    .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
-    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
-    .TE_B ( BUF_net_109 ) , .Z ( SOC_OUT ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_110 ) , .Y ( SOC_DIR ) ) ;
-sky130_fd_sc_hd__inv_4 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( BUF_net_109 ) ) ;
+    .TE_B ( BUF_net_109 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_110 ) , .Y ( SOC_DIR ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( BUF_net_109 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( aps_rename_510_ ) , 
-    .Y ( BUF_net_110 ) ) ;
+    .Y ( BUF_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , 
     prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
-    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ;
 input  [0:0] IO_ISOL_N ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
@@ -15637,25 +20448,31 @@
 input  [0:0] ccff_head ;
 output [0:0] iopad_inpad ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] EMBEDDED_IO_HD_0_en ;
+supply1 VDD ;
+supply0 VSS ;
 
 cbx_1__0__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( 
     .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
     .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
     .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
     .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
-    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
-    ccff_tail ) ;
+    ccff_tail , VDD , VSS ) ;
 input  [0:0] IO_ISOL_N ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
@@ -15666,6 +20483,11 @@
 input  [0:0] ccff_head ;
 output [0:0] io_inpad ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 cbx_1__0__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( 
     .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
@@ -15673,26 +20495,34 @@
     .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
     .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
     .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
-    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_7 ( pReset , 
-    prog_clk , ccff_head , ccff_tail , mem_out ) ;
+    prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:0] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__EMBEDDED_IO_HD_7 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
-    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ;
 input  SOC_IN ;
 output SOC_OUT ;
 output SOC_DIR ;
@@ -15700,25 +20530,34 @@
 input  FPGA_OUT ;
 input  FPGA_DIR ;
 input  IO_ISOL_N ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
-    .B ( IO_ISOL_N ) , .Y ( aps_rename_509_ ) ) ;
-sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_105 ) , .Y ( SOC_DIR_N ) ) ;
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_509_ ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_105 ) , .Y ( SOC_DIR_N ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
-    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
-    .TE_B ( BUF_net_105 ) , .Z ( SOC_OUT ) ) ;
-sky130_fd_sc_hd__inv_4 BINV_R_105 ( .A ( BUF_net_107 ) , .Y ( BUF_net_105 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( SOC_DIR ) ) ;
+    .TE_B ( BUF_net_105 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_105 ( .A ( BUF_net_107 ) , .Y ( BUF_net_105 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( SOC_DIR ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( aps_rename_509_ ) , 
-    .Y ( BUF_net_107 ) ) ;
+    .Y ( BUF_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__logical_tile_io_mode_physical__iopad_7 ( IO_ISOL_N , pReset , 
     prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
-    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ;
 input  [0:0] IO_ISOL_N ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
@@ -15729,25 +20568,31 @@
 input  [0:0] ccff_head ;
 output [0:0] iopad_inpad ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] EMBEDDED_IO_HD_0_en ;
+supply1 VDD ;
+supply0 VSS ;
 
 cbx_1__0__EMBEDDED_IO_HD_7 EMBEDDED_IO_HD_0_ ( 
     .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
     .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
     .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
     .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
-    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_7 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__logical_tile_io_mode_io__7 ( IO_ISOL_N , pReset , prog_clk , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
-    ccff_tail ) ;
+    ccff_tail , VDD , VSS ) ;
 input  [0:0] IO_ISOL_N ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
@@ -15758,6 +20603,11 @@
 input  [0:0] ccff_head ;
 output [0:0] io_inpad ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 cbx_1__0__logical_tile_io_mode_physical__iopad_7 logical_tile_io_mode_physical__iopad_0 ( 
     .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
@@ -15765,26 +20615,34 @@
     .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
     .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
     .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
-    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_6 ( pReset , 
-    prog_clk , ccff_head , ccff_tail , mem_out ) ;
+    prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:0] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__EMBEDDED_IO_HD_6 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
-    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ;
 input  SOC_IN ;
 output SOC_OUT ;
 output SOC_DIR ;
@@ -15792,26 +20650,34 @@
 input  FPGA_OUT ;
 input  FPGA_DIR ;
 input  IO_ISOL_N ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
-    .B ( IO_ISOL_N ) , .Y ( aps_rename_508_ ) ) ;
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_508_ ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_508_ ) , 
-    .Y ( SOC_DIR_N ) ) ;
+    .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
-    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
-    .TE_B ( BUF_net_102 ) , .Z ( SOC_OUT ) ) ;
+    .TE_B ( BUF_net_102 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_104 ( .A ( aps_rename_508_ ) , 
-    .Y ( BUF_net_104 ) ) ;
-sky130_fd_sc_hd__inv_4 BINV_R_102 ( .A ( BUF_net_104 ) , .Y ( BUF_net_102 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( SOC_DIR ) ) ;
+    .Y ( BUF_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_102 ( .A ( BUF_net_104 ) , .Y ( BUF_net_102 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( SOC_DIR ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__logical_tile_io_mode_physical__iopad_6 ( IO_ISOL_N , pReset , 
     prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
-    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ;
 input  [0:0] IO_ISOL_N ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
@@ -15822,25 +20688,31 @@
 input  [0:0] ccff_head ;
 output [0:0] iopad_inpad ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] EMBEDDED_IO_HD_0_en ;
+supply1 VDD ;
+supply0 VSS ;
 
 cbx_1__0__EMBEDDED_IO_HD_6 EMBEDDED_IO_HD_0_ ( 
     .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
     .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
     .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
     .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
-    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_6 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__logical_tile_io_mode_io__6 ( IO_ISOL_N , pReset , prog_clk , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
-    ccff_tail ) ;
+    ccff_tail , VDD , VSS ) ;
 input  [0:0] IO_ISOL_N ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
@@ -15851,6 +20723,11 @@
 input  [0:0] ccff_head ;
 output [0:0] io_inpad ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 cbx_1__0__logical_tile_io_mode_physical__iopad_6 logical_tile_io_mode_physical__iopad_0 ( 
     .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
@@ -15858,26 +20735,34 @@
     .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
     .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
     .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
-    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_5 ( pReset , 
-    prog_clk , ccff_head , ccff_tail , mem_out ) ;
+    prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:0] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__EMBEDDED_IO_HD_5 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
-    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ;
 input  SOC_IN ;
 output SOC_OUT ;
 output SOC_DIR ;
@@ -15885,22 +20770,29 @@
 input  FPGA_OUT ;
 input  FPGA_DIR ;
 input  IO_ISOL_N ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
-    .B ( IO_ISOL_N ) , .Y ( net_net_100 ) ) ;
-sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ;
+    .B ( IO_ISOL_N ) , .Y ( net_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
-    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
-    .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_100 ( .A ( net_net_100 ) , .X ( SOC_DIR ) ) ;
+    .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_100 ( .A ( net_net_100 ) , .X ( SOC_DIR ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__logical_tile_io_mode_physical__iopad_5 ( IO_ISOL_N , pReset , 
     prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
-    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ;
 input  [0:0] IO_ISOL_N ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
@@ -15911,25 +20803,31 @@
 input  [0:0] ccff_head ;
 output [0:0] iopad_inpad ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] EMBEDDED_IO_HD_0_en ;
+supply1 VDD ;
+supply0 VSS ;
 
 cbx_1__0__EMBEDDED_IO_HD_5 EMBEDDED_IO_HD_0_ ( 
     .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
     .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
     .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
     .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
-    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_5 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__logical_tile_io_mode_io__5 ( IO_ISOL_N , pReset , prog_clk , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
-    ccff_tail ) ;
+    ccff_tail , VDD , VSS ) ;
 input  [0:0] IO_ISOL_N ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
@@ -15940,6 +20838,11 @@
 input  [0:0] ccff_head ;
 output [0:0] io_inpad ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 cbx_1__0__logical_tile_io_mode_physical__iopad_5 logical_tile_io_mode_physical__iopad_0 ( 
     .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
@@ -15947,26 +20850,34 @@
     .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
     .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
     .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
-    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_4 ( pReset , 
-    prog_clk , ccff_head , ccff_tail , mem_out ) ;
+    prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:0] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__EMBEDDED_IO_HD_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
-    FPGA_OUT , FPGA_DIR , IO_ISOL_N , ZBUF_154_0 ) ;
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS , ZBUF_154_0 ) ;
 input  SOC_IN ;
 output SOC_OUT ;
 output SOC_DIR ;
@@ -15974,22 +20885,29 @@
 input  FPGA_OUT ;
 input  FPGA_DIR ;
 input  IO_ISOL_N ;
+input  VDD ;
+input  VSS ;
 input  ZBUF_154_0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
-    .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) ) ;
-sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_154_0 ) , .Y ( SOC_DIR_N ) ) ;
+    .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_154_0 ) , .Y ( SOC_DIR_N ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
-    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
-    .TE_B ( ZBUF_154_0 ) , .Z ( SOC_OUT ) ) ;
+    .TE_B ( ZBUF_154_0 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__logical_tile_io_mode_physical__iopad_4 ( IO_ISOL_N , pReset , 
     prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
-    iopad_outpad , ccff_head , iopad_inpad , ccff_tail , ZBUF_154_0 ) ;
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS , 
+    ZBUF_154_0 ) ;
 input  [0:0] IO_ISOL_N ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
@@ -16000,9 +20918,13 @@
 input  [0:0] ccff_head ;
 output [0:0] iopad_inpad ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 input  ZBUF_154_0 ;
 
 wire [0:0] EMBEDDED_IO_HD_0_en ;
+supply1 VDD ;
+supply0 VSS ;
 
 cbx_1__0__EMBEDDED_IO_HD_4 EMBEDDED_IO_HD_0_ ( 
     .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
@@ -16010,17 +20932,18 @@
     .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
     .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
     .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , 
-    .ZBUF_154_0 ( ZBUF_154_0 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .ZBUF_154_0 ( ZBUF_154_0 ) ) ;
 cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_4 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__logical_tile_io_mode_io__4 ( IO_ISOL_N , pReset , prog_clk , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
-    ccff_tail , ZBUF_154_0 ) ;
+    ccff_tail , VDD , VSS , ZBUF_154_0 ) ;
 input  [0:0] IO_ISOL_N ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
@@ -16031,35 +20954,47 @@
 input  [0:0] ccff_head ;
 output [0:0] io_inpad ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 input  ZBUF_154_0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( 
     .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , 
     .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
     .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
     .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
-    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , 
-    .ZBUF_154_0 ( ZBUF_154_0 ) ) ;
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .ZBUF_154_0 ( ZBUF_154_0 ) ) ;
 endmodule
 
 
 module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_3 ( pReset , 
-    prog_clk , ccff_head , ccff_tail , mem_out ) ;
+    prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:0] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__EMBEDDED_IO_HD_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
-    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ;
 input  SOC_IN ;
 output SOC_OUT ;
 output SOC_DIR ;
@@ -16067,22 +21002,29 @@
 input  FPGA_OUT ;
 input  FPGA_DIR ;
 input  IO_ISOL_N ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
-    .B ( IO_ISOL_N ) , .Y ( net_net_99 ) ) ;
-sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ;
+    .B ( IO_ISOL_N ) , .Y ( net_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
-    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
-    .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( net_net_99 ) , .X ( SOC_DIR ) ) ;
+    .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( net_net_99 ) , .X ( SOC_DIR ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__logical_tile_io_mode_physical__iopad_3 ( IO_ISOL_N , pReset , 
     prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
-    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ;
 input  [0:0] IO_ISOL_N ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
@@ -16093,25 +21035,31 @@
 input  [0:0] ccff_head ;
 output [0:0] iopad_inpad ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] EMBEDDED_IO_HD_0_en ;
+supply1 VDD ;
+supply0 VSS ;
 
 cbx_1__0__EMBEDDED_IO_HD_3 EMBEDDED_IO_HD_0_ ( 
     .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
     .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
     .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
     .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
-    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_3 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__logical_tile_io_mode_io__3 ( IO_ISOL_N , pReset , prog_clk , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
-    ccff_tail ) ;
+    ccff_tail , VDD , VSS ) ;
 input  [0:0] IO_ISOL_N ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
@@ -16122,6 +21070,11 @@
 input  [0:0] ccff_head ;
 output [0:0] io_inpad ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( 
     .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
@@ -16129,26 +21082,34 @@
     .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
     .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
     .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
-    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_2 ( pReset , 
-    prog_clk , ccff_head , ccff_tail , mem_out ) ;
+    prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:0] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__EMBEDDED_IO_HD_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
-    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ;
 input  SOC_IN ;
 output SOC_OUT ;
 output SOC_DIR ;
@@ -16156,25 +21117,34 @@
 input  FPGA_OUT ;
 input  FPGA_DIR ;
 input  IO_ISOL_N ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , 
-    .X ( aps_rename_507_ ) ) ;
-sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_97 ) , .Y ( SOC_DIR_N ) ) ;
+    .X ( aps_rename_507_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_97 ) , .Y ( SOC_DIR_N ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
-    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
-    .TE_B ( aps_rename_507_ ) , .Z ( SOC_OUT ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_98 ) , .Y ( SOC_DIR ) ) ;
-sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( BUF_net_97 ) ) ;
+    .TE_B ( aps_rename_507_ ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_98 ) , .Y ( SOC_DIR ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( BUF_net_97 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_507_ ) , 
-    .Y ( BUF_net_98 ) ) ;
+    .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( IO_ISOL_N , pReset , 
     prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
-    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ;
 input  [0:0] IO_ISOL_N ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
@@ -16185,25 +21155,31 @@
 input  [0:0] ccff_head ;
 output [0:0] iopad_inpad ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] EMBEDDED_IO_HD_0_en ;
+supply1 VDD ;
+supply0 VSS ;
 
 cbx_1__0__EMBEDDED_IO_HD_2 EMBEDDED_IO_HD_0_ ( 
     .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
     .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
     .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
     .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
-    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_2 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__logical_tile_io_mode_io__2 ( IO_ISOL_N , pReset , prog_clk , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
-    ccff_tail ) ;
+    ccff_tail , VDD , VSS ) ;
 input  [0:0] IO_ISOL_N ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
@@ -16214,6 +21190,11 @@
 input  [0:0] ccff_head ;
 output [0:0] io_inpad ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( 
     .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
@@ -16221,26 +21202,34 @@
     .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
     .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
     .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
-    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_1 ( pReset , 
-    prog_clk , ccff_head , ccff_tail , mem_out ) ;
+    prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:0] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__EMBEDDED_IO_HD_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
-    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ;
 input  SOC_IN ;
 output SOC_OUT ;
 output SOC_DIR ;
@@ -16248,25 +21237,34 @@
 input  FPGA_OUT ;
 input  FPGA_DIR ;
 input  IO_ISOL_N ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
-    .B ( IO_ISOL_N ) , .Y ( aps_rename_506_ ) ) ;
-sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_94 ) , .Y ( SOC_DIR_N ) ) ;
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_506_ ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_94 ) , .Y ( SOC_DIR_N ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
-    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
+    .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
-    .TE_B ( BUF_net_94 ) , .Z ( SOC_OUT ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_95 ) , .Y ( SOC_DIR ) ) ;
-sky130_fd_sc_hd__inv_4 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( BUF_net_94 ) ) ;
+    .TE_B ( BUF_net_94 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_95 ) , .Y ( SOC_DIR ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( BUF_net_94 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( aps_rename_506_ ) , 
-    .Y ( BUF_net_95 ) ) ;
+    .Y ( BUF_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__logical_tile_io_mode_physical__iopad_1 ( IO_ISOL_N , pReset , 
     prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
-    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ;
 input  [0:0] IO_ISOL_N ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
@@ -16277,25 +21275,31 @@
 input  [0:0] ccff_head ;
 output [0:0] iopad_inpad ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] EMBEDDED_IO_HD_0_en ;
+supply1 VDD ;
+supply0 VSS ;
 
 cbx_1__0__EMBEDDED_IO_HD_1 EMBEDDED_IO_HD_0_ ( 
     .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
     .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
     .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
     .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
-    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_1 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__logical_tile_io_mode_io__1 ( IO_ISOL_N , pReset , prog_clk , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
-    ccff_tail ) ;
+    ccff_tail , VDD , VSS ) ;
 input  [0:0] IO_ISOL_N ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
@@ -16306,6 +21310,11 @@
 input  [0:0] ccff_head ;
 output [0:0] io_inpad ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( 
     .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
@@ -16313,26 +21322,34 @@
     .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
     .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
     .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
-    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_0 ( pReset , 
-    prog_clk , ccff_head , ccff_tail , mem_out ) ;
+    prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:0] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__EMBEDDED_IO_HD_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , 
-    FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
+    FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ;
 input  SOC_IN ;
 output SOC_OUT ;
 output SOC_DIR ;
@@ -16340,24 +21357,32 @@
 input  FPGA_OUT ;
 input  FPGA_DIR ;
 input  IO_ISOL_N ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , 
-    .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ;
+    .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , 
-    .TE_B ( BUF_net_92 ) , .Z ( FPGA_IN ) ) ;
+    .TE_B ( BUF_net_92 ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , 
-    .TE_B ( BUF_net_90 ) , .Z ( SOC_OUT ) ) ;
-sky130_fd_sc_hd__inv_4 BINV_R_90 ( .A ( BUF_net_92 ) , .Y ( BUF_net_90 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( SOC_DIR ) ) ;
+    .TE_B ( BUF_net_90 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_4 BINV_R_90 ( .A ( BUF_net_92 ) , .Y ( BUF_net_90 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( SOC_DIR ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_4 BINV_R_92 ( .A ( aps_rename_505_ ) , 
-    .Y ( BUF_net_92 ) ) ;
+    .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( IO_ISOL_N , pReset , 
     prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , 
-    iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
+    iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ;
 input  [0:0] IO_ISOL_N ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
@@ -16368,25 +21393,31 @@
 input  [0:0] ccff_head ;
 output [0:0] iopad_inpad ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] EMBEDDED_IO_HD_0_en ;
+supply1 VDD ;
+supply0 VSS ;
 
 cbx_1__0__EMBEDDED_IO_HD_0 EMBEDDED_IO_HD_0_ ( 
     .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
     .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , 
     .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , 
     .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , 
-    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
+    .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_0 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__logical_tile_io_mode_io__0 ( IO_ISOL_N , pReset , prog_clk , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , 
-    ccff_tail ) ;
+    ccff_tail , VDD , VSS ) ;
 input  [0:0] IO_ISOL_N ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
@@ -16397,6 +21428,11 @@
 input  [0:0] ccff_head ;
 output [0:0] io_inpad ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( 
     .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
@@ -16404,335 +21440,478 @@
     .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , 
     .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , 
     .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , 
-    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
+    .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__mux_2level_size12_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__mux_2level_size12_mem_7 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__mux_2level_size12_mem_6 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__mux_2level_size12_mem_5 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__mux_2level_size12_mem_4 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__mux_2level_size12_mem_3 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__mux_2level_size12_mem_2 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__mux_2level_size12_mem_1 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__mux_2level_size12_mem_0 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_135 ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1362 ( .A ( copt_net_123 ) , 
-    .X ( copt_net_121 ) ) ;
+    .X ( copt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1363 ( .A ( copt_net_121 ) , 
-    .X ( copt_net_122 ) ) ;
+    .X ( copt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1364 ( .A ( copt_net_126 ) , 
-    .X ( copt_net_123 ) ) ;
+    .X ( copt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1365 ( .A ( copt_net_125 ) , 
-    .X ( copt_net_124 ) ) ;
+    .X ( copt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1366 ( .A ( copt_net_122 ) , 
-    .X ( copt_net_125 ) ) ;
+    .X ( copt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1367 ( .A ( ccff_head[0] ) , 
-    .X ( copt_net_126 ) ) ;
+    .X ( copt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1375 ( .A ( copt_net_124 ) , 
-    .X ( ropt_net_135 ) ) ;
+    .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__mux_2level_basis_input4_mem4 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_basis_input4_mem4_34 ( in , mem , mem_inv , out ) ;
+module cbx_1__0__mux_2level_basis_input4_mem4_34 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_basis_input4_mem4_33 ( in , mem , mem_inv , out ) ;
+module cbx_1__0__mux_2level_basis_input4_mem4_33 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_basis_input4_mem4_32 ( in , mem , mem_inv , out ) ;
+module cbx_1__0__mux_2level_basis_input4_mem4_32 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__local_encoder2to4 ( addr , data , data_inv ) ;
+module cbx_1__0__local_encoder2to4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__local_encoder2to4_16 ( addr , data , data_inv ) ;
+module cbx_1__0__local_encoder2to4_16 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_size12 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__0__mux_2level_size12 ( in , sram , sram_inv , out , VDD , VSS , 
+    p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -16743,168 +21922,227 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__0__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__local_encoder2to4 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_32 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_33 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_34 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module cbx_1__0__mux_2level_basis_input4_mem4_31 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_basis_input4_mem4_30 ( in , mem , mem_inv , out ) ;
+module cbx_1__0__mux_2level_basis_input4_mem4_30 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_basis_input4_mem4_29 ( in , mem , mem_inv , out ) ;
+module cbx_1__0__mux_2level_basis_input4_mem4_29 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_basis_input4_mem4_28 ( in , mem , mem_inv , out ) ;
+module cbx_1__0__mux_2level_basis_input4_mem4_28 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__local_encoder2to4_15 ( addr , data , data_inv ) ;
+module cbx_1__0__local_encoder2to4_15 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__local_encoder2to4_14 ( addr , data , data_inv ) ;
+module cbx_1__0__local_encoder2to4_14 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_size12_7 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__0__mux_2level_size12_7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -16915,169 +22153,229 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_112 ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_112 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__0__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__local_encoder2to4_15 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_28 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_29 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_30 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_31 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_112 ( .A ( net_net_112 ) , .X ( out[0] ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_112 ( .A ( net_net_112 ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__mux_2level_basis_input4_mem4_27 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_basis_input4_mem4_26 ( in , mem , mem_inv , out ) ;
+module cbx_1__0__mux_2level_basis_input4_mem4_26 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_basis_input4_mem4_25 ( in , mem , mem_inv , out ) ;
+module cbx_1__0__mux_2level_basis_input4_mem4_25 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_basis_input4_mem4_24 ( in , mem , mem_inv , out ) ;
+module cbx_1__0__mux_2level_basis_input4_mem4_24 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__local_encoder2to4_13 ( addr , data , data_inv ) ;
+module cbx_1__0__local_encoder2to4_13 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__local_encoder2to4_12 ( addr , data , data_inv ) ;
+module cbx_1__0__local_encoder2to4_12 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_size12_6 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__0__mux_2level_size12_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -17088,168 +22386,227 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__0__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__local_encoder2to4_13 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_24 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_25 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_26 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_27 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module cbx_1__0__mux_2level_basis_input4_mem4_23 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_basis_input4_mem4_22 ( in , mem , mem_inv , out ) ;
+module cbx_1__0__mux_2level_basis_input4_mem4_22 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_basis_input4_mem4_21 ( in , mem , mem_inv , out ) ;
+module cbx_1__0__mux_2level_basis_input4_mem4_21 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_basis_input4_mem4_20 ( in , mem , mem_inv , out ) ;
+module cbx_1__0__mux_2level_basis_input4_mem4_20 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__local_encoder2to4_11 ( addr , data , data_inv ) ;
+module cbx_1__0__local_encoder2to4_11 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__local_encoder2to4_10 ( addr , data , data_inv ) ;
+module cbx_1__0__local_encoder2to4_10 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_size12_5 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__0__mux_2level_size12_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -17260,168 +22617,227 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__0__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__local_encoder2to4_11 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_20 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_21 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_22 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_23 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module cbx_1__0__mux_2level_basis_input4_mem4_19 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_basis_input4_mem4_18 ( in , mem , mem_inv , out ) ;
+module cbx_1__0__mux_2level_basis_input4_mem4_18 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_basis_input4_mem4_17 ( in , mem , mem_inv , out ) ;
+module cbx_1__0__mux_2level_basis_input4_mem4_17 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_basis_input4_mem4_16 ( in , mem , mem_inv , out ) ;
+module cbx_1__0__mux_2level_basis_input4_mem4_16 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__local_encoder2to4_9 ( addr , data , data_inv ) ;
+module cbx_1__0__local_encoder2to4_9 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__local_encoder2to4_8 ( addr , data , data_inv ) ;
+module cbx_1__0__local_encoder2to4_8 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_size12_4 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__0__mux_2level_size12_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -17432,168 +22848,227 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__0__local_encoder2to4_8 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__local_encoder2to4_9 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_16 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_17 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_18 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_19 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module cbx_1__0__mux_2level_basis_input4_mem4_15 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_basis_input4_mem4_14 ( in , mem , mem_inv , out ) ;
+module cbx_1__0__mux_2level_basis_input4_mem4_14 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_basis_input4_mem4_13 ( in , mem , mem_inv , out ) ;
+module cbx_1__0__mux_2level_basis_input4_mem4_13 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_basis_input4_mem4_12 ( in , mem , mem_inv , out ) ;
+module cbx_1__0__mux_2level_basis_input4_mem4_12 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__local_encoder2to4_7 ( addr , data , data_inv ) ;
+module cbx_1__0__local_encoder2to4_7 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__local_encoder2to4_6 ( addr , data , data_inv ) ;
+module cbx_1__0__local_encoder2to4_6 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_size12_3 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__0__mux_2level_size12_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -17604,168 +23079,227 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__0__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__local_encoder2to4_7 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_12 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_13 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_14 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_15 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module cbx_1__0__mux_2level_basis_input4_mem4_11 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_basis_input4_mem4_10 ( in , mem , mem_inv , out ) ;
+module cbx_1__0__mux_2level_basis_input4_mem4_10 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_basis_input4_mem4_9 ( in , mem , mem_inv , out ) ;
+module cbx_1__0__mux_2level_basis_input4_mem4_9 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_basis_input4_mem4_8 ( in , mem , mem_inv , out ) ;
+module cbx_1__0__mux_2level_basis_input4_mem4_8 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__local_encoder2to4_5 ( addr , data , data_inv ) ;
+module cbx_1__0__local_encoder2to4_5 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__local_encoder2to4_4 ( addr , data , data_inv ) ;
+module cbx_1__0__local_encoder2to4_4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_size12_2 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__0__mux_2level_size12_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -17776,168 +23310,227 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__0__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__local_encoder2to4_5 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_8 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_9 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_10 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_11 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module cbx_1__0__mux_2level_basis_input4_mem4_7 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_basis_input4_mem4_6 ( in , mem , mem_inv , out ) ;
+module cbx_1__0__mux_2level_basis_input4_mem4_6 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_basis_input4_mem4_5 ( in , mem , mem_inv , out ) ;
+module cbx_1__0__mux_2level_basis_input4_mem4_5 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_basis_input4_mem4_4 ( in , mem , mem_inv , out ) ;
+module cbx_1__0__mux_2level_basis_input4_mem4_4 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__local_encoder2to4_3 ( addr , data , data_inv ) ;
+module cbx_1__0__local_encoder2to4_3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__local_encoder2to4_2 ( addr , data , data_inv ) ;
+module cbx_1__0__local_encoder2to4_2 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_size12_1 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__0__mux_2level_size12_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -17948,169 +23541,229 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_111 ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( net_net_111 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__0__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__local_encoder2to4_3 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_4 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_5 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_6 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_7 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_111 ( .A ( net_net_111 ) , .X ( out[0] ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_111 ( .A ( net_net_111 ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module cbx_1__0__mux_2level_basis_input4_mem4_3 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_basis_input4_mem4_2 ( in , mem , mem_inv , out ) ;
+module cbx_1__0__mux_2level_basis_input4_mem4_2 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_basis_input4_mem4_1 ( in , mem , mem_inv , out ) ;
+module cbx_1__0__mux_2level_basis_input4_mem4_1 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_basis_input4_mem4_0 ( in , mem , mem_inv , out ) ;
+module cbx_1__0__mux_2level_basis_input4_mem4_0 ( in , mem , mem_inv , out , 
+    VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__local_encoder2to4_1 ( addr , data , data_inv ) ;
+module cbx_1__0__local_encoder2to4_1 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__local_encoder2to4_0 ( addr , data , data_inv ) ;
+module cbx_1__0__local_encoder2to4_0 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module cbx_1__0__mux_2level_size12_0 ( in , sram , sram_inv , out , p0 ) ;
+module cbx_1__0__mux_2level_size12_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -18121,34 +23774,41 @@
 wire [0:0] mux_2level_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_1_0_ ( 
-    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 cbx_1__0__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__local_encoder2to4_1 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_0 mux_l1_in_0_ ( .in ( in[0:3] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_1 mux_l1_in_1_ ( .in ( in[4:7] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_2 mux_l1_in_2_ ( .in ( in[8:11] ) , 
     .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_basis_input4_mem4_3 mux_l2_in_0_ (
     .in ( { mux_2level_basis_input4_mem4_0_out[0] , 
         mux_2level_basis_input4_mem4_1_out[0] , 
         mux_2level_basis_input4_mem4_2_out[0] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
@@ -18174,7 +23834,7 @@
     top_width_0_height_0__pin_17_upper , top_width_0_height_0__pin_17_lower , 
     SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , pReset_E_in , 
     pReset_W_in , pReset_W_out , pReset_E_out , prog_clk_0_N_in , 
-    prog_clk_0_W_out ) ;
+    prog_clk_0_W_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:29] chanx_left_in ;
 input  [0:29] chanx_right_in ;
@@ -18232,6 +23892,8 @@
 output pReset_E_out ;
 input  prog_clk_0_N_in ;
 output prog_clk_0_W_out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] prog_clk ;
 wire prog_clk_0 ;
@@ -18260,6 +23922,8 @@
 wire [0:0] logical_tile_io_mode_io__5_ccff_tail ;
 wire [0:0] logical_tile_io_mode_io__6_ccff_tail ;
 wire [0:0] logical_tile_io_mode_io__7_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 assign pReset_W_in = pReset_E_in ;
 assign prog_clk_0 = prog_clk[0] ;
@@ -18272,7 +23936,8 @@
     .sram ( mux_2level_size12_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
         SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_118 ) ) ;
+    .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_118 ) ) ;
 cbx_1__0__mux_2level_size12_1 mux_top_ipin_1 (
     .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , 
         chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , 
@@ -18281,7 +23946,8 @@
     .sram ( mux_2level_size12_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
         SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
-    .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_116 ) ) ;
+    .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_116 ) ) ;
 cbx_1__0__mux_2level_size12_2 mux_top_ipin_2 (
     .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , 
         chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , 
@@ -18290,7 +23956,8 @@
     .sram ( mux_2level_size12_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
         SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
-    .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_117 ) ) ;
+    .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_117 ) ) ;
 cbx_1__0__mux_2level_size12_3 mux_top_ipin_3 (
     .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , 
         chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , 
@@ -18299,7 +23966,8 @@
     .sram ( mux_2level_size12_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
         SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
-    .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_119 ) ) ;
+    .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_119 ) ) ;
 cbx_1__0__mux_2level_size12_4 mux_top_ipin_4 (
     .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , 
         chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , 
@@ -18308,7 +23976,8 @@
     .sram ( mux_2level_size12_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
         SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
-    .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_116 ) ) ;
+    .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_116 ) ) ;
 cbx_1__0__mux_2level_size12_5 mux_top_ipin_5 (
     .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , 
         chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , 
@@ -18317,7 +23986,8 @@
     .sram ( mux_2level_size12_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
         SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
-    .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_117 ) ) ;
+    .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_117 ) ) ;
 cbx_1__0__mux_2level_size12_6 mux_top_ipin_6 (
     .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , 
         chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , 
@@ -18326,7 +23996,8 @@
     .sram ( mux_2level_size12_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
         SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
-    .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_117 ) ) ;
+    .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_117 ) ) ;
 cbx_1__0__mux_2level_size12_7 mux_top_ipin_7 (
     .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , 
         chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , 
@@ -18335,7 +24006,8 @@
     .sram ( mux_2level_size12_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
         SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
-    .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_116 ) ) ;
+    .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_116 ) ) ;
 cbx_1__0__mux_2level_size12 mux_top_ipin_8 (
     .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , 
         chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , 
@@ -18344,51 +24016,52 @@
     .sram ( mux_2level_size12_8_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
         SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
-    .out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_117 ) ) ;
+    .out ( bottom_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_117 ) ) ;
 cbx_1__0__mux_2level_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
     .ccff_tail ( mux_2level_size12_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_0_sram ) ) ;
+    .mem_out ( mux_2level_size12_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_size12_mem_1 mem_top_ipin_1 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_1_sram ) ) ;
+    .mem_out ( mux_2level_size12_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_size12_mem_2 mem_top_ipin_2 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_2_sram ) ) ;
+    .mem_out ( mux_2level_size12_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_size12_mem_3 mem_top_ipin_3 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_3_sram ) ) ;
+    .mem_out ( mux_2level_size12_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_size12_mem_4 mem_top_ipin_4 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_4_sram ) ) ;
+    .mem_out ( mux_2level_size12_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_size12_mem_5 mem_top_ipin_5 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_5_sram ) ) ;
+    .mem_out ( mux_2level_size12_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_size12_mem_6 mem_top_ipin_6 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_6_sram ) ) ;
+    .mem_out ( mux_2level_size12_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_size12_mem_7 mem_top_ipin_7 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_size12_mem_7_ccff_tail ) , 
-    .mem_out ( mux_2level_size12_7_sram ) ) ;
+    .mem_out ( mux_2level_size12_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__mux_2level_size12_mem mem_top_ipin_8 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_size12_mem_7_ccff_tail ) ,
     .ccff_tail ( { ccff_tail_mid } ) ,
-    .mem_out ( mux_2level_size12_8_sram ) ) ;
+    .mem_out ( mux_2level_size12_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( 
     .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , 
@@ -18397,7 +24070,8 @@
     .io_outpad ( top_width_0_height_0__pin_0_ ) ,
     .ccff_head ( { ccff_tail_mid } ) ,
     .io_inpad ( top_width_0_height_0__pin_1_lower ) , 
-    .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) ) ;
+    .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( 
     .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] ) , 
@@ -18406,7 +24080,8 @@
     .io_outpad ( top_width_0_height_0__pin_2_ ) , 
     .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) , 
     .io_inpad ( top_width_0_height_0__pin_3_lower ) , 
-    .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) ) ;
+    .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( 
     .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) , 
@@ -18415,7 +24090,8 @@
     .io_outpad ( top_width_0_height_0__pin_4_ ) , 
     .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , 
     .io_inpad ( top_width_0_height_0__pin_5_lower ) , 
-    .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) ) ;
+    .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( 
     .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) , 
@@ -18424,7 +24100,8 @@
     .io_outpad ( top_width_0_height_0__pin_6_ ) , 
     .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) , 
     .io_inpad ( top_width_0_height_0__pin_7_lower ) , 
-    .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) ) ;
+    .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( 
     .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] ) , 
@@ -18433,8 +24110,8 @@
     .io_outpad ( top_width_0_height_0__pin_8_ ) , 
     .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) , 
     .io_inpad ( top_width_0_height_0__pin_9_lower ) , 
-    .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) , 
-    .ZBUF_154_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] ) ) ;
+    .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .ZBUF_154_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] ) ) ;
 cbx_1__0__logical_tile_io_mode_io__5 logical_tile_io_mode_io__5 ( 
     .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] ) , 
@@ -18443,7 +24120,8 @@
     .io_outpad ( top_width_0_height_0__pin_10_ ) , 
     .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) , 
     .io_inpad ( top_width_0_height_0__pin_11_lower ) , 
-    .ccff_tail ( logical_tile_io_mode_io__5_ccff_tail ) ) ;
+    .ccff_tail ( logical_tile_io_mode_io__5_ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__logical_tile_io_mode_io__6 logical_tile_io_mode_io__6 ( 
     .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] ) , 
@@ -18452,7 +24130,8 @@
     .io_outpad ( top_width_0_height_0__pin_12_ ) , 
     .ccff_head ( logical_tile_io_mode_io__5_ccff_tail ) , 
     .io_inpad ( top_width_0_height_0__pin_13_lower ) , 
-    .ccff_tail ( logical_tile_io_mode_io__6_ccff_tail ) ) ;
+    .ccff_tail ( logical_tile_io_mode_io__6_ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__logical_tile_io_mode_io__7 logical_tile_io_mode_io__7 ( 
     .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] ) , 
@@ -18461,7 +24140,8 @@
     .io_outpad ( top_width_0_height_0__pin_14_ ) , 
     .ccff_head ( logical_tile_io_mode_io__6_ccff_tail ) , 
     .io_inpad ( top_width_0_height_0__pin_15_lower ) , 
-    .ccff_tail ( logical_tile_io_mode_io__7_ccff_tail ) ) ;
+    .ccff_tail ( logical_tile_io_mode_io__7_ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__8 ( 
     .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] ) , 
@@ -18470,3331 +24150,4704 @@
     .io_outpad ( top_width_0_height_0__pin_16_ ) , 
     .ccff_head ( logical_tile_io_mode_io__7_ccff_tail ) , 
     .io_inpad ( top_width_0_height_0__pin_17_lower ) , 
-    .ccff_tail ( ccff_tail ) ) ;
-sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ;
+    .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_W_in ) , 
-    .X ( net_net_113 ) ) ;
+    .X ( net_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_W_in ) , 
-    .X ( aps_rename_512_ ) ) ;
+    .X ( aps_rename_512_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
-    .X ( prog_clk[0] ) ) ;
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , 
-    .X ( ctsbuf_net_1120 ) ) ;
+    .X ( ctsbuf_net_1120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , 
-    .X ( chanx_right_out[0] ) ) ;
+    .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , 
-    .X ( chanx_right_out[1] ) ) ;
+    .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , 
-    .X ( chanx_right_out[2] ) ) ;
+    .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) , 
-    .X ( chanx_right_out[3] ) ) ;
+    .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) , 
-    .X ( chanx_right_out[4] ) ) ;
+    .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) , 
-    .X ( chanx_right_out[5] ) ) ;
+    .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) , 
-    .X ( chanx_right_out[6] ) ) ;
+    .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) , 
-    .X ( chanx_right_out[7] ) ) ;
+    .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) , 
-    .X ( chanx_right_out[8] ) ) ;
+    .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) , 
-    .X ( chanx_right_out[9] ) ) ;
+    .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) , 
-    .X ( chanx_right_out[10] ) ) ;
+    .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) , 
-    .X ( chanx_right_out[11] ) ) ;
+    .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) , 
-    .X ( chanx_right_out[12] ) ) ;
+    .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) , 
-    .X ( chanx_right_out[13] ) ) ;
+    .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) , 
-    .X ( chanx_right_out[14] ) ) ;
+    .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) , 
-    .X ( chanx_right_out[15] ) ) ;
+    .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) , 
-    .X ( chanx_right_out[16] ) ) ;
+    .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) , 
-    .X ( chanx_right_out[17] ) ) ;
+    .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , 
-    .X ( chanx_right_out[18] ) ) ;
+    .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , 
-    .X ( chanx_right_out[19] ) ) ;
+    .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[20] ) , 
-    .X ( chanx_right_out[20] ) ) ;
+    .X ( chanx_right_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[21] ) , 
-    .X ( chanx_right_out[21] ) ) ;
+    .X ( chanx_right_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[22] ) , 
-    .X ( chanx_right_out[22] ) ) ;
+    .X ( chanx_right_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[23] ) , 
-    .X ( chanx_right_out[23] ) ) ;
+    .X ( chanx_right_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[24] ) , 
-    .X ( chanx_right_out[24] ) ) ;
+    .X ( chanx_right_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[25] ) , 
-    .X ( chanx_right_out[25] ) ) ;
+    .X ( chanx_right_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[26] ) , 
-    .X ( chanx_right_out[26] ) ) ;
+    .X ( chanx_right_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[27] ) , 
-    .X ( chanx_right_out[27] ) ) ;
+    .X ( chanx_right_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[28] ) , 
-    .X ( chanx_right_out[28] ) ) ;
+    .X ( chanx_right_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[29] ) , 
-    .X ( chanx_right_out[29] ) ) ;
+    .X ( chanx_right_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) , 
-    .X ( chanx_left_out[0] ) ) ;
+    .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) , 
-    .X ( chanx_left_out[1] ) ) ;
+    .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) , 
-    .X ( chanx_left_out[2] ) ) ;
+    .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) , 
-    .X ( chanx_left_out[3] ) ) ;
+    .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[4] ) , 
-    .X ( chanx_left_out[4] ) ) ;
+    .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[5] ) , 
-    .X ( chanx_left_out[5] ) ) ;
+    .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[6] ) , 
-    .X ( chanx_left_out[6] ) ) ;
+    .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[7] ) , 
-    .X ( chanx_left_out[7] ) ) ;
+    .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[8] ) , 
-    .X ( chanx_left_out[8] ) ) ;
+    .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[9] ) , 
-    .X ( chanx_left_out[9] ) ) ;
+    .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[10] ) , 
-    .X ( chanx_left_out[10] ) ) ;
+    .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[11] ) , 
-    .X ( chanx_left_out[11] ) ) ;
+    .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[12] ) , 
-    .X ( chanx_left_out[12] ) ) ;
+    .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[13] ) , 
-    .X ( chanx_left_out[13] ) ) ;
+    .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[14] ) , 
-    .X ( chanx_left_out[14] ) ) ;
+    .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[15] ) , 
-    .X ( chanx_left_out[15] ) ) ;
+    .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[16] ) , 
-    .X ( chanx_left_out[16] ) ) ;
+    .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[17] ) , 
-    .X ( chanx_left_out[17] ) ) ;
+    .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[18] ) , 
-    .X ( chanx_left_out[18] ) ) ;
+    .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[19] ) , 
-    .X ( chanx_left_out[19] ) ) ;
+    .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[20] ) , 
-    .X ( chanx_left_out[20] ) ) ;
+    .X ( chanx_left_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[21] ) , 
-    .X ( chanx_left_out[21] ) ) ;
+    .X ( chanx_left_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[22] ) , 
-    .X ( chanx_left_out[22] ) ) ;
+    .X ( chanx_left_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[23] ) , 
-    .X ( chanx_left_out[23] ) ) ;
+    .X ( chanx_left_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[24] ) , 
-    .X ( chanx_left_out[24] ) ) ;
+    .X ( chanx_left_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[25] ) , 
-    .X ( chanx_left_out[25] ) ) ;
+    .X ( chanx_left_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[26] ) , 
-    .X ( chanx_left_out[26] ) ) ;
+    .X ( chanx_left_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[27] ) , 
-    .X ( chanx_left_out[27] ) ) ;
+    .X ( chanx_left_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[28] ) , 
-    .X ( chanx_left_out[28] ) ) ;
+    .X ( chanx_left_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[29] ) , 
-    .X ( chanx_left_out[29] ) ) ;
+    .X ( chanx_left_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_79__78 ( 
     .A ( top_width_0_height_0__pin_1_lower[0] ) , 
-    .X ( top_width_0_height_0__pin_1_upper[0] ) ) ;
+    .X ( top_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_80__79 ( 
     .A ( top_width_0_height_0__pin_3_lower[0] ) , 
-    .X ( top_width_0_height_0__pin_3_upper[0] ) ) ;
+    .X ( top_width_0_height_0__pin_3_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_81__80 ( 
     .A ( top_width_0_height_0__pin_5_lower[0] ) , 
-    .X ( top_width_0_height_0__pin_5_upper[0] ) ) ;
+    .X ( top_width_0_height_0__pin_5_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_82__81 ( 
     .A ( top_width_0_height_0__pin_7_lower[0] ) , 
-    .X ( top_width_0_height_0__pin_7_upper[0] ) ) ;
+    .X ( top_width_0_height_0__pin_7_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_83__82 ( 
     .A ( top_width_0_height_0__pin_9_lower[0] ) , 
-    .X ( top_width_0_height_0__pin_9_upper[0] ) ) ;
+    .X ( top_width_0_height_0__pin_9_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_84__83 ( 
     .A ( top_width_0_height_0__pin_11_lower[0] ) , 
-    .X ( top_width_0_height_0__pin_11_upper[0] ) ) ;
+    .X ( top_width_0_height_0__pin_11_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_85__84 ( 
     .A ( top_width_0_height_0__pin_13_lower[0] ) , 
-    .X ( top_width_0_height_0__pin_13_upper[0] ) ) ;
+    .X ( top_width_0_height_0__pin_13_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_86__85 ( 
     .A ( top_width_0_height_0__pin_15_lower[0] ) , 
-    .X ( top_width_0_height_0__pin_15_upper[0] ) ) ;
+    .X ( top_width_0_height_0__pin_15_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_87__86 ( 
     .A ( top_width_0_height_0__pin_17_lower[0] ) , 
-    .X ( top_width_0_height_0__pin_17_upper[0] ) ) ;
-sky130_fd_sc_hd__buf_6 FTB_88__87 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
-sky130_fd_sc_hd__buf_6 FTB_89__88 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ;
+    .X ( top_width_0_height_0__pin_17_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_88__87 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_89__88 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_113 ( .A ( net_net_113 ) , 
-    .X ( pReset_W_out ) ) ;
-sky130_fd_sc_hd__inv_6 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( pReset_E_out ) ) ;
+    .X ( pReset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( pReset_E_out ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_115 ( .A ( aps_rename_512_ ) , 
-    .Y ( BUF_net_115 ) ) ;
+    .Y ( BUF_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , 
-    .HI ( optlc_net_116 ) ) ;
+    .HI ( optlc_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , 
-    .HI ( optlc_net_117 ) ) ;
+    .HI ( optlc_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , 
-    .HI ( optlc_net_118 ) ) ;
+    .HI ( optlc_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_40 ) , 
-    .HI ( optlc_net_119 ) ) ;
+    .HI ( optlc_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_154_inst_123 ( .A ( aps_rename_511_ ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 cts_buf_3711269 ( .A ( ctsbuf_net_1120 ) , 
-    .X ( prog_clk_0_W_out ) ) ;
+    .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_77__76 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_77__76 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size3_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_76__75 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_76__75 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size3_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_75__74 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_75__74 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size3_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_74__73 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_74__73 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_84 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_83 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_83 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_84 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_176 ( .A ( BUF_net_177 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_176 ( .A ( BUF_net_177 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_177 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_177 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_177 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_82 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_81 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_80 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_80 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_81 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_82 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_174 ( .A ( BUF_net_175 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_174 ( .A ( BUF_net_175 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_175 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_175 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_175 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_79 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_78 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_77 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_77 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_78 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_79 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_172 ( .A ( BUF_net_173 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_172 ( .A ( BUF_net_173 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_173 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_173 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_173 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_76 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_75 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_74 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_74 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_75 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_76 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_171 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_171 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_171 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_6 FTB_73__72 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_73__72 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_35 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_72__71 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_72__71 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_34 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_71__70 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_71__70 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_33 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_32 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_69__68 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_69__68 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_31 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_68__67 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_68__67 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_30 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_67__66 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_67__66 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_29 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_66__65 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_66__65 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_28 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_65__64 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_65__64 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_27 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_64__63 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_64__63 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_26 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_63__62 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_63__62 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_25 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_62__61 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_62__61 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_24 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_61__60 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_61__60 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_23 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_60__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_60__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_22 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_21 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_20 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_57__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_57__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_19 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_56__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_56__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_18 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_17 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_16 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_15 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_14 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_13 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_12 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_11 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_10 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_9 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_8 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_7 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_6 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_5 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size2_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_73 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_72 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_72 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_73 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_169 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_71 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_70 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_35 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_35 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_70 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_71 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_167 ( .A ( BUF_net_168 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_167 ( .A ( BUF_net_168 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_168 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_168 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_168 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_69 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_68 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_34 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_34 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_68 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_69 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_67 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_66 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_33 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_33 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_66 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_67 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_165 ( .A ( BUF_net_166 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_165 ( .A ( BUF_net_166 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_166 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_166 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_166 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_65 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_64 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_32 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_32 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_64 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_65 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_163 ( .A ( BUF_net_164 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_163 ( .A ( BUF_net_164 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_164 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_164 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_164 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_63 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_62 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_31 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_31 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_62 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_63 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_162 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_61 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_60 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_30 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_30 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_60 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_61 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_161 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_161 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_161 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_59 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_58 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_29 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_29 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_58 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_59 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_159 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_159 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_159 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_57 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_56 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_28 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_28 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_56 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_57 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_55 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_54 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_27 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_27 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_54 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_55 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_157 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_157 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_157 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_53 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_52 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_26 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_26 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_52 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_53 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_155 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_155 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_155 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_51 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_50 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_25 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_25 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_50 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_51 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_153 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_49 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_48 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_24 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_24 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_48 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_49 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_47 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_46 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_23 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_46 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_47 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_151 ( .A ( BUF_net_152 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_151 ( .A ( BUF_net_152 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_152 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_152 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_152 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_45 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_44 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_22 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_44 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_45 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_150 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_150 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_150 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_43 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_42 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_21 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_42 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_43 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_148 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_148 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_148 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_41 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_40 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_20 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_40 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_41 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_39 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_38 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_19 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_38 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_39 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_146 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_146 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_146 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_37 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_36 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_18 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_36 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_37 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_143 ( .A ( BUF_net_144 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_143 ( .A ( BUF_net_144 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_144 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_144 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_144 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_35 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_34 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_17 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_34 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_35 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_141 ( .A ( BUF_net_142 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_141 ( .A ( BUF_net_142 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_142 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_142 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_142 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_33 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_32 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_16 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_32 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_33 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_140 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_140 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_140 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_31 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_30 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_15 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_30 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_31 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_138 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_138 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_138 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_29 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_28 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_14 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_28 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_29 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_136 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_136 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_136 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_27 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_26 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_13 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_26 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_27 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_134 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_134 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_134 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_25 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_24 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_12 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_24 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_25 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_132 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_132 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_132 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_23 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_22 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_11 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_22 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_23 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_130 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_130 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_130 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_21 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_20 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_10 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_20 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_21 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_128 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_19 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_18 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_18 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_19 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_127 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_17 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_16 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_16 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_17 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_126 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_126 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_126 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_15 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_14 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_14 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_15 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_124 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_124 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_124 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_13 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_12 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_13 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_122 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_122 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_122 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_11 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_10 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_10 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_120 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_120 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_120 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_9 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_8 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_8 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_9 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_118 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_118 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_118 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_7 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_6 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_7 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_116 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_116 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_116 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_5 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_4 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_4 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_114 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_114 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_114 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_3 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_2 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_2 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_3 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_112 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_112 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_112 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_1 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input2_mem1_0 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_0 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input2_mem1_1 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_110 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_110 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_110 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size4_mem_10 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size4_mem_9 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size4_mem_8 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size4_mem_7 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size4_mem_6 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size4_mem_5 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size4_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size4_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size4_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size4_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_size4_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_224 ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1375 ( .A ( copt_net_184 ) , 
-    .X ( copt_net_183 ) ) ;
+    .X ( copt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1376 ( .A ( ccff_head[0] ) , 
-    .X ( copt_net_184 ) ) ;
+    .X ( copt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1377 ( .A ( copt_net_183 ) , 
-    .X ( copt_net_185 ) ) ;
+    .X ( copt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1378 ( .A ( copt_net_185 ) , 
-    .X ( copt_net_186 ) ) ;
+    .X ( copt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1379 ( .A ( copt_net_186 ) , 
-    .X ( copt_net_187 ) ) ;
+    .X ( copt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1380 ( .A ( copt_net_187 ) , 
-    .X ( copt_net_188 ) ) ;
+    .X ( copt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1410 ( .A ( copt_net_188 ) , 
-    .X ( ropt_net_220 ) ) ;
+    .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1411 ( .A ( ropt_net_220 ) , 
-    .X ( ropt_net_221 ) ) ;
+    .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1412 ( .A ( ropt_net_221 ) , 
-    .X ( ropt_net_222 ) ) ;
+    .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1413 ( .A ( ropt_net_222 ) , 
-    .X ( ropt_net_223 ) ) ;
+    .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1414 ( .A ( ropt_net_223 ) , 
-    .X ( ropt_net_224 ) ) ;
+    .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input3_mem3 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_22 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__local_encoder2to3 ( addr , data , data_inv ) ;
+module sb_2__2__local_encoder2to3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__local_encoder2to3_22 ( addr , data , data_inv ) ;
+module sb_2__2__local_encoder2to3_22 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -21803,103 +28856,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__local_encoder2to3_22 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__2__local_encoder2to3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input3_mem3_22 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_108 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_108 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_108 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_21 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_20 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__local_encoder2to3_21 ( addr , data , data_inv ) ;
+module sb_2__2__local_encoder2to3_21 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__local_encoder2to3_20 ( addr , data , data_inv ) ;
+module sb_2__2__local_encoder2to3_20 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size4_10 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size4_10 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -21908,103 +28998,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__local_encoder2to3_20 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__2__local_encoder2to3_21 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input3_mem3_20 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input3_mem3_21 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_106 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_106 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_106 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_19 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_18 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__local_encoder2to3_19 ( addr , data , data_inv ) ;
+module sb_2__2__local_encoder2to3_19 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__local_encoder2to3_18 ( addr , data , data_inv ) ;
+module sb_2__2__local_encoder2to3_18 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size4_9 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size4_9 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -22013,103 +29140,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__local_encoder2to3_18 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__2__local_encoder2to3_19 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input3_mem3_18 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input3_mem3_19 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_104 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_104 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_104 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_17 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_16 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__local_encoder2to3_17 ( addr , data , data_inv ) ;
+module sb_2__2__local_encoder2to3_17 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__local_encoder2to3_16 ( addr , data , data_inv ) ;
+module sb_2__2__local_encoder2to3_16 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size4_8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -22118,103 +29282,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__local_encoder2to3_16 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__2__local_encoder2to3_17 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input3_mem3_16 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input3_mem3_17 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_102 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_102 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_102 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_15 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_14 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__local_encoder2to3_15 ( addr , data , data_inv ) ;
+module sb_2__2__local_encoder2to3_15 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__local_encoder2to3_14 ( addr , data , data_inv ) ;
+module sb_2__2__local_encoder2to3_14 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size4_7 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size4_7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -22223,103 +29424,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__local_encoder2to3_14 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__2__local_encoder2to3_15 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input3_mem3_14 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input3_mem3_15 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_100 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_100 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_100 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_13 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_12 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__local_encoder2to3_13 ( addr , data , data_inv ) ;
+module sb_2__2__local_encoder2to3_13 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__local_encoder2to3_12 ( addr , data , data_inv ) ;
+module sb_2__2__local_encoder2to3_12 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size4_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -22328,103 +29566,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__local_encoder2to3_12 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__2__local_encoder2to3_13 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input3_mem3_12 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input3_mem3_13 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_98 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_98 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_98 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_11 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_10 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__local_encoder2to3_11 ( addr , data , data_inv ) ;
+module sb_2__2__local_encoder2to3_11 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__local_encoder2to3_10 ( addr , data , data_inv ) ;
+module sb_2__2__local_encoder2to3_10 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size4_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -22433,103 +29708,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__local_encoder2to3_10 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__2__local_encoder2to3_11 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input3_mem3_10 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input3_mem3_11 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_96 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_96 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_96 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_9 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_8 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__local_encoder2to3_9 ( addr , data , data_inv ) ;
+module sb_2__2__local_encoder2to3_9 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__local_encoder2to3_8 ( addr , data , data_inv ) ;
+module sb_2__2__local_encoder2to3_8 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -22538,103 +29850,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__local_encoder2to3_8 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__2__local_encoder2to3_9 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input3_mem3_8 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input3_mem3_9 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_94 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_94 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_94 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_7 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_6 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__local_encoder2to3_7 ( addr , data , data_inv ) ;
+module sb_2__2__local_encoder2to3_7 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__local_encoder2to3_6 ( addr , data , data_inv ) ;
+module sb_2__2__local_encoder2to3_6 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -22643,103 +29992,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__2__local_encoder2to3_7 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input3_mem3_6 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input3_mem3_7 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_92 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_92 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_92 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_5 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_4 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__local_encoder2to3_5 ( addr , data , data_inv ) ;
+module sb_2__2__local_encoder2to3_5 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__local_encoder2to3_4 ( addr , data , data_inv ) ;
+module sb_2__2__local_encoder2to3_4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -22748,103 +30134,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__2__local_encoder2to3_5 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input3_mem3_4 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input3_mem3_5 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_90 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_90 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_90 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_3 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_2 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__local_encoder2to3_3 ( addr , data , data_inv ) ;
+module sb_2__2__local_encoder2to3_3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__local_encoder2to3_2 ( addr , data , data_inv ) ;
+module sb_2__2__local_encoder2to3_2 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -22853,103 +30276,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__2__local_encoder2to3_3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input3_mem3_2 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input3_mem3_3 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_88 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_88 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_88 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_1 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__2__mux_2level_tapbuf_basis_input3_mem3_0 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__local_encoder2to3_1 ( addr , data , data_inv ) ;
+module sb_2__2__local_encoder2to3_1 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__local_encoder2to3_0 ( addr , data , data_inv ) ;
+module sb_2__2__local_encoder2to3_0 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__2__mux_2level_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__2__mux_2level_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -22958,26 +30418,32 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__2__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__2__local_encoder2to3_1 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input3_mem3_0 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_basis_input3_mem3_1 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_86 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_86 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_86 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
@@ -22991,7 +30457,8 @@
     left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , 
     left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , 
     left_bottom_grid_pin_43_ , ccff_head , chany_bottom_out , chanx_left_out , 
-    ccff_tail , SC_IN_BOT , SC_OUT_BOT , pReset_W_in , prog_clk_0_S_in ) ;
+    ccff_tail , SC_IN_BOT , SC_OUT_BOT , pReset_W_in , prog_clk_0_S_in , VDD , 
+    VSS ) ;
 input  [0:0] pReset ;
 input  [0:29] chany_bottom_in ;
 input  [0:0] bottom_right_grid_pin_1_ ;
@@ -23021,6 +30488,8 @@
 output SC_OUT_BOT ;
 input  pReset_W_in ;
 input  prog_clk_0_S_in ;
+input  VDD ;
+input  VSS ;
 
 wire ropt_net_206 ;
 wire [0:0] prog_clk ;
@@ -23130,6 +30599,8 @@
 wire [0:0] mux_2level_tapbuf_size4_mem_7_ccff_tail ;
 wire [0:0] mux_2level_tapbuf_size4_mem_8_ccff_tail ;
 wire [0:0] mux_2level_tapbuf_size4_mem_9_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 assign prog_clk_0 = prog_clk[0] ;
 
@@ -23139,1970 +30610,2660 @@
     .sram ( mux_2level_tapbuf_size4_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
         SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_180 ) ) ;
+    .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_180 ) ) ;
 sb_2__2__mux_2level_tapbuf_size4_1 mux_bottom_track_3 (
     .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , 
         bottom_left_grid_pin_50_[0] , chanx_left_in[2] } ) ,
     .sram ( mux_2level_tapbuf_size4_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
         SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
-    .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_181 ) ) ;
+    .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_181 ) ) ;
 sb_2__2__mux_2level_tapbuf_size4_2 mux_bottom_track_5 (
     .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , 
         bottom_left_grid_pin_51_[0] , chanx_left_in[3] } ) ,
     .sram ( mux_2level_tapbuf_size4_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
         SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
-    .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_181 ) ) ;
+    .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_181 ) ) ;
 sb_2__2__mux_2level_tapbuf_size4_3 mux_bottom_track_7 (
     .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , 
         bottom_left_grid_pin_49_[0] , chanx_left_in[4] } ) ,
     .sram ( mux_2level_tapbuf_size4_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
         SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
-    .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_180 ) ) ;
+    .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_180 ) ) ;
 sb_2__2__mux_2level_tapbuf_size4_4 mux_bottom_track_9 (
     .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , 
         bottom_left_grid_pin_50_[0] , chanx_left_in[5] } ) ,
     .sram ( mux_2level_tapbuf_size4_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
         SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
-    .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_181 ) ) ;
+    .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_181 ) ) ;
 sb_2__2__mux_2level_tapbuf_size4_5 mux_bottom_track_11 (
     .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , 
         bottom_left_grid_pin_51_[0] , chanx_left_in[6] } ) ,
     .sram ( mux_2level_tapbuf_size4_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
         SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
-    .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_181 ) ) ;
+    .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_181 ) ) ;
 sb_2__2__mux_2level_tapbuf_size4_6 mux_left_track_1 (
     .in ( { chany_bottom_in[29] , left_top_grid_pin_1_[0] , 
         left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) ,
     .sram ( mux_2level_tapbuf_size4_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
         SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
-    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_178 ) ) ;
+    .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_178 ) ) ;
 sb_2__2__mux_2level_tapbuf_size4_7 mux_left_track_3 (
     .in ( { chany_bottom_in[0] , left_bottom_grid_pin_36_[0] , 
         left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) ,
     .sram ( mux_2level_tapbuf_size4_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
         SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
-    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_180 ) ) ;
+    .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_180 ) ) ;
 sb_2__2__mux_2level_tapbuf_size4_8 mux_left_track_5 (
     .in ( { chany_bottom_in[1] , left_bottom_grid_pin_37_[0] , 
         left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) ,
     .sram ( mux_2level_tapbuf_size4_8_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
         SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
-    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_180 ) ) ;
+    .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_180 ) ) ;
 sb_2__2__mux_2level_tapbuf_size4_9 mux_left_track_7 (
     .in ( { chany_bottom_in[2] , left_top_grid_pin_1_[0] , 
         left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) ,
     .sram ( mux_2level_tapbuf_size4_9_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
         SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
-    .out ( chanx_left_out[3] ) , .p0 ( optlc_net_180 ) ) ;
+    .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_180 ) ) ;
 sb_2__2__mux_2level_tapbuf_size4_10 mux_left_track_9 (
     .in ( { chany_bottom_in[3] , left_bottom_grid_pin_36_[0] , 
         left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) ,
     .sram ( mux_2level_tapbuf_size4_10_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
         SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
-    .out ( chanx_left_out[4] ) , .p0 ( optlc_net_180 ) ) ;
+    .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_180 ) ) ;
 sb_2__2__mux_2level_tapbuf_size4 mux_left_track_11 (
     .in ( { chany_bottom_in[4] , left_bottom_grid_pin_37_[0] , 
         left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) ,
     .sram ( mux_2level_tapbuf_size4_11_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
         SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
-    .out ( chanx_left_out[5] ) , .p0 ( optlc_net_180 ) ) ;
+    .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_180 ) ) ;
 sb_2__2__mux_2level_tapbuf_size4_mem_0 mem_bottom_track_1 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size4_mem_1 mem_bottom_track_3 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size4_mem_2 mem_bottom_track_5 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size4_mem_3 mem_bottom_track_7 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size4_mem_4 mem_bottom_track_9 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size4_mem_5 mem_bottom_track_11 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_5_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_5_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size4_mem_6 mem_left_track_1 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_14_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_6_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_6_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size4_mem_7 mem_left_track_3 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_7_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_7_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_7_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size4_mem_8 mem_left_track_5 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_7_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_8_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_8_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_8_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size4_mem_9 mem_left_track_7 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_8_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_9_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_9_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_9_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size4_mem_10 mem_left_track_9 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_9_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_10_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_10_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_10_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size4_mem mem_left_track_11 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_10_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_11_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_11_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_11_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_0 mux_bottom_track_13 (
     .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[7] } ) ,
     .sram ( mux_2level_tapbuf_size2_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
-    .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_181 ) ) ;
+    .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_181 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_1 mux_bottom_track_15 (
     .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) ,
     .sram ( mux_2level_tapbuf_size2_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
-    .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_181 ) ) ;
+    .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_181 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_2 mux_bottom_track_17 (
     .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) ,
     .sram ( mux_2level_tapbuf_size2_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) ,
-    .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_179 ) ) ;
+    .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_179 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_3 mux_bottom_track_19 (
     .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) ,
     .sram ( mux_2level_tapbuf_size2_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
-    .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_179 ) ) ;
+    .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_179 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_4 mux_bottom_track_21 (
     .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) ,
     .sram ( mux_2level_tapbuf_size2_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) ,
-    .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_182 ) ) ;
+    .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_182 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_5 mux_bottom_track_23 (
     .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) ,
     .sram ( mux_2level_tapbuf_size2_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
-    .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_181 ) ) ;
+    .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_181 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_6 mux_bottom_track_25 (
     .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[13] } ) ,
     .sram ( mux_2level_tapbuf_size2_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
-    .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_181 ) ) ;
+    .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_181 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_7 mux_bottom_track_27 (
     .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[14] } ) ,
     .sram ( mux_2level_tapbuf_size2_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
-    .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_181 ) ) ;
+    .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_181 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_8 mux_bottom_track_39 (
     .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[20] } ) ,
     .sram ( mux_2level_tapbuf_size2_8_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) ,
-    .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_179 ) ) ;
+    .out ( chany_bottom_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_179 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_9 mux_bottom_track_41 (
     .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[21] } ) ,
     .sram ( mux_2level_tapbuf_size2_9_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
-    .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_179 ) ) ;
+    .out ( chany_bottom_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_179 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_10 mux_bottom_track_43 (
     .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[22] } ) ,
     .sram ( mux_2level_tapbuf_size2_10_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
-    .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_179 ) ) ;
+    .out ( chany_bottom_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_179 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_11 mux_bottom_track_47 (
     .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[24] } ) ,
     .sram ( mux_2level_tapbuf_size2_11_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
-    .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_182 ) ) ;
+    .out ( chany_bottom_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_182 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_12 mux_bottom_track_49 (
     .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[25] } ) ,
     .sram ( mux_2level_tapbuf_size2_12_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
-    .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_180 ) ) ;
+    .out ( chany_bottom_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_180 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_13 mux_bottom_track_51 (
     .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[26] } ) ,
     .sram ( mux_2level_tapbuf_size2_13_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
-    .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_182 ) ) ;
+    .out ( chany_bottom_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_182 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_14 mux_bottom_track_53 (
     .in ( { bottom_left_grid_pin_51_[0] , chanx_left_in[27] } ) ,
     .sram ( mux_2level_tapbuf_size2_14_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
-    .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_182 ) ) ;
+    .out ( chany_bottom_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_182 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_15 mux_left_track_13 (
     .in ( { chany_bottom_in[5] , left_top_grid_pin_1_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_15_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
-    .out ( chanx_left_out[6] ) , .p0 ( optlc_net_180 ) ) ;
+    .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_180 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_16 mux_left_track_15 (
     .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_16_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
-    .out ( chanx_left_out[7] ) , .p0 ( optlc_net_182 ) ) ;
+    .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_182 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_17 mux_left_track_17 (
     .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_17_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
-    .out ( chanx_left_out[8] ) , .p0 ( optlc_net_178 ) ) ;
+    .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_178 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_18 mux_left_track_19 (
     .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_18_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) ,
-    .out ( chanx_left_out[9] ) , .p0 ( optlc_net_178 ) ) ;
+    .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_178 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_19 mux_left_track_21 (
     .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_19_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
-    .out ( chanx_left_out[10] ) , .p0 ( optlc_net_178 ) ) ;
+    .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_178 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_20 mux_left_track_23 (
     .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_20_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) ,
-    .out ( chanx_left_out[11] ) , .p0 ( optlc_net_178 ) ) ;
+    .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_178 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_21 mux_left_track_25 (
     .in ( { chany_bottom_in[11] , left_bottom_grid_pin_41_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_21_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
-    .out ( chanx_left_out[12] ) , .p0 ( optlc_net_178 ) ) ;
+    .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_178 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_22 mux_left_track_27 (
     .in ( { chany_bottom_in[12] , left_bottom_grid_pin_42_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_22_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) ,
-    .out ( chanx_left_out[13] ) , .p0 ( optlc_net_178 ) ) ;
+    .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_178 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_23 mux_left_track_31 (
     .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_23_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
-    .out ( chanx_left_out[15] ) , .p0 ( optlc_net_182 ) ) ;
+    .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_182 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_24 mux_left_track_33 (
     .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_24_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) ,
-    .out ( chanx_left_out[16] ) , .p0 ( optlc_net_179 ) ) ;
+    .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_179 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_25 mux_left_track_35 (
     .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_25_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) ,
-    .out ( chanx_left_out[17] ) , .p0 ( optlc_net_179 ) ) ;
+    .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_179 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_26 mux_left_track_37 (
     .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_26_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) ,
-    .out ( chanx_left_out[18] ) , .p0 ( optlc_net_179 ) ) ;
+    .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_179 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_27 mux_left_track_39 (
     .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_27_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) ,
-    .out ( chanx_left_out[19] ) , .p0 ( optlc_net_178 ) ) ;
+    .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_178 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_28 mux_left_track_41 (
     .in ( { chany_bottom_in[19] , left_bottom_grid_pin_41_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_28_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) ,
-    .out ( chanx_left_out[20] ) , .p0 ( optlc_net_178 ) ) ;
+    .out ( chanx_left_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_178 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_29 mux_left_track_43 (
     .in ( { chany_bottom_in[20] , left_bottom_grid_pin_42_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_29_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) ,
-    .out ( chanx_left_out[21] ) , .p0 ( optlc_net_178 ) ) ;
+    .out ( chanx_left_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_178 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_30 mux_left_track_45 (
     .in ( { chany_bottom_in[21] , left_top_grid_pin_1_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_30_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) ,
-    .out ( chanx_left_out[22] ) , .p0 ( optlc_net_178 ) ) ;
+    .out ( chanx_left_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_178 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_31 mux_left_track_47 (
     .in ( { chany_bottom_in[22] , left_bottom_grid_pin_36_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_31_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) ,
-    .out ( chanx_left_out[23] ) , .p0 ( optlc_net_179 ) ) ;
+    .out ( chanx_left_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_179 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_32 mux_left_track_49 (
     .in ( { chany_bottom_in[23] , left_bottom_grid_pin_37_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_32_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) ,
-    .out ( chanx_left_out[24] ) , .p0 ( optlc_net_182 ) ) ;
+    .out ( chanx_left_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_182 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_33 mux_left_track_51 (
     .in ( { chany_bottom_in[24] , left_bottom_grid_pin_38_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_33_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) ,
-    .out ( chanx_left_out[25] ) , .p0 ( optlc_net_182 ) ) ;
+    .out ( chanx_left_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_182 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_34 mux_left_track_55 (
     .in ( { chany_bottom_in[26] , left_bottom_grid_pin_40_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_34_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) ,
-    .out ( chanx_left_out[27] ) , .p0 ( optlc_net_179 ) ) ;
+    .out ( chanx_left_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_179 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_35 mux_left_track_57 (
     .in ( { chany_bottom_in[27] , left_bottom_grid_pin_41_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_35_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) ,
-    .out ( chanx_left_out[28] ) , .p0 ( optlc_net_179 ) ) ;
+    .out ( chanx_left_out[28] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_179 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2 mux_left_track_59 (
     .in ( { chany_bottom_in[28] , left_bottom_grid_pin_42_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_36_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) ,
-    .out ( chanx_left_out[29] ) , .p0 ( optlc_net_179 ) ) ;
+    .out ( chanx_left_out[29] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_179 ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_0 mem_bottom_track_13 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_1 mem_bottom_track_15 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_2 mem_bottom_track_17 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_3 mem_bottom_track_19 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_4 mem_bottom_track_21 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_5 mem_bottom_track_23 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_5_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_5_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_6 mem_bottom_track_25 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_6_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_6_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_7 mem_bottom_track_27 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_7_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_7_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_8 mem_bottom_track_39 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_8_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_8_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_8_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_9 mem_bottom_track_41 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_8_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_9_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_9_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_9_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_10 mem_bottom_track_43 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_9_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_10_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_10_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_10_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_11 mem_bottom_track_47 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_11_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_11_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_11_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_12 mem_bottom_track_49 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_11_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_12_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_12_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_12_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_13 mem_bottom_track_51 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_12_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_13_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_13_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_13_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_14 mem_bottom_track_53 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_13_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_14_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_14_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_14_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_15 mem_left_track_13 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_11_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_15_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_15_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_15_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_16 mem_left_track_15 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_15_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_16_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_16_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_16_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_17 mem_left_track_17 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_16_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_17_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_17_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_17_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_18 mem_left_track_19 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_17_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_18_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_18_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_18_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_19 mem_left_track_21 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_18_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_19_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_19_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_19_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_20 mem_left_track_23 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_19_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_20_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_20_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_20_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_21 mem_left_track_25 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_20_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_21_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_21_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_21_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_22 mem_left_track_27 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_21_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_22_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_22_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_22_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_23 mem_left_track_31 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_23_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_23_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_23_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_24 mem_left_track_33 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_23_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_24_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_24_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_24_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_25 mem_left_track_35 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_24_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_25_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_25_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_25_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_26 mem_left_track_37 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_25_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_26_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_26_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_26_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_27 mem_left_track_39 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_26_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_27_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_27_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_27_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_28 mem_left_track_41 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_27_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_28_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_28_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_28_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_29 mem_left_track_43 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_28_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_29_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_29_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_29_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_30 mem_left_track_45 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_29_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_30_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_30_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_30_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_31 mem_left_track_47 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_30_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_31_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_31_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_31_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_32 mem_left_track_49 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_31_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_32_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_32_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_32_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_33 mem_left_track_51 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_32_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_33_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_33_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_33_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_34 mem_left_track_55 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_34_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_34_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_34_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem_35 mem_left_track_57 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_34_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_35_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_35_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_35_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size2_mem mem_left_track_59 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_35_ccff_tail ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_tapbuf_size2_36_sram ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_tapbuf_size2_36_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size3_0 mux_bottom_track_29 (
     .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_51_[0] , 
         chanx_left_in[15] } ) ,
     .sram ( mux_2level_tapbuf_size3_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) ,
-    .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_181 ) ) ;
+    .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_181 ) ) ;
 sb_2__2__mux_2level_tapbuf_size3_1 mux_bottom_track_45 (
     .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_47_[0] , 
         chanx_left_in[23] } ) ,
     .sram ( mux_2level_tapbuf_size3_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) ,
-    .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_182 ) ) ;
+    .out ( chany_bottom_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_182 ) ) ;
 sb_2__2__mux_2level_tapbuf_size3_2 mux_left_track_29 (
     .in ( { chany_bottom_in[13] , left_top_grid_pin_1_[0] , 
         left_bottom_grid_pin_43_[0] } ) ,
     .sram ( mux_2level_tapbuf_size3_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) ,
-    .out ( chanx_left_out[14] ) , .p0 ( optlc_net_178 ) ) ;
+    .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_178 ) ) ;
 sb_2__2__mux_2level_tapbuf_size3 mux_left_track_53 (
     .in ( { chany_bottom_in[25] , left_bottom_grid_pin_39_[0] , 
         left_bottom_grid_pin_43_[0] } ) ,
     .sram ( mux_2level_tapbuf_size3_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) ,
-    .out ( chanx_left_out[26] ) , .p0 ( optlc_net_178 ) ) ;
+    .out ( chanx_left_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_178 ) ) ;
 sb_2__2__mux_2level_tapbuf_size3_mem_0 mem_bottom_track_29 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size3_mem_1 mem_bottom_track_45 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_10_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size3_mem_2 mem_left_track_29 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_22_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__2__mux_2level_tapbuf_size3_mem mem_left_track_53 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_33_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_3_sram ) ) ;
-sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , 
-    .X ( prog_clk[0] ) ) ;
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[0] ) , 
-    .X ( chany_bottom_out[29] ) ) ;
+    .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[16] ) , 
-    .X ( chany_bottom_out[15] ) ) ;
+    .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[17] ) , 
-    .X ( chany_bottom_out[16] ) ) ;
+    .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_left_in[18] ) , 
-    .X ( chany_bottom_out[17] ) ) ;
+    .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_82__81 ( .A ( chanx_left_in[19] ) , 
-    .X ( ropt_net_206 ) ) ;
+    .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chanx_left_in[28] ) , 
-    .X ( chany_bottom_out[27] ) ) ;
+    .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chanx_left_in[29] ) , 
-    .X ( chany_bottom_out[28] ) ) ;
-sky130_fd_sc_hd__buf_6 FTB_85__84 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ;
+    .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_85__84 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_180 ( .LO ( SYNOPSYS_UNCONNECTED_131 ) , 
-    .HI ( optlc_net_178 ) ) ;
+    .HI ( optlc_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_182 ( .LO ( SYNOPSYS_UNCONNECTED_132 ) , 
-    .HI ( optlc_net_179 ) ) ;
+    .HI ( optlc_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_185 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) , 
-    .HI ( optlc_net_180 ) ) ;
+    .HI ( optlc_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_187 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) , 
-    .HI ( optlc_net_181 ) ) ;
+    .HI ( optlc_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_189 ( .LO ( SYNOPSYS_UNCONNECTED_135 ) , 
-    .HI ( optlc_net_182 ) ) ;
+    .HI ( optlc_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1398 ( .A ( ropt_net_206 ) , 
-    .X ( chany_bottom_out[18] ) ) ;
+    .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_109__108 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size2_mem_5 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_108__107 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size2_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_107__106 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size2_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_106__105 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size2_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_105__104 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size2_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_104__103 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size2_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_103__102 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_36 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_36 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_188 ( .A ( BUF_net_189 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_188 ( .A ( BUF_net_189 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_189 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_189 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_189 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_35 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_34 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_34 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_35 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_33 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_32 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_32 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_33 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_186 ( .A ( BUF_net_187 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_186 ( .A ( BUF_net_187 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_187 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_187 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_187 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_31 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_30 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_30 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_31 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_29 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_28 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_28 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_29 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_27 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_26 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_26 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_27 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_25 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_24 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_24 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_25 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_102__101 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size3_mem_6 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_101__100 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size3_mem_5 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_100__99 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_100__99 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size3_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_99__98 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_99__98 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size3_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_98__97 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_98__97 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size3_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_97__96 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_97__96 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size3_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_96__95 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_96__95 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size3_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_95__94 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_95__94 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_23 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_22 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_21 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_21 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_22 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_23 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_184 ( .A ( BUF_net_185 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_184 ( .A ( BUF_net_185 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_185 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_185 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_185 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_20 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_19 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_18 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size3_6 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size3_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_18 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_19 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_20 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_17 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_16 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_15 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size3_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_15 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_16 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_17 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_183 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_14 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_13 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_12 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size3_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_13 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_14 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_182 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_11 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_10 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_9 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_9 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_10 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_8 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_7 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_6 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_7 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_8 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_194 ( .A ( BUF_net_195 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_194 ( .A ( BUF_net_195 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_195 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_195 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_195 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_5 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_4 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_3 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_3 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_4 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_2 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_1 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem1_0 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_0 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_1 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem1_2 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_181 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_94__93 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_94__93 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size4_mem_6 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_93__92 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_93__92 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size4_mem_5 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_92__91 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_92__91 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size4_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_91__90 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_91__90 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size4_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_90__89 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_90__89 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size4_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_89__88 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_89__88 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size4_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_88__87 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_88__87 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size4_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_87__86 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_87__86 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_78 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_86__85 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_86__85 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_58 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_58 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_85__84 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_85__84 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -25111,102 +33272,138 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__1__local_encoder2to3_58 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_78 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_180 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_77 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_76 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_57 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_57 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_84__83 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_84__83 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_56 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_56 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_83__82 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_83__82 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size4_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -25215,102 +33412,138 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__1__local_encoder2to3_56 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_57 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_76 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_77 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_75 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_74 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_55 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_55 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_82__81 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_82__81 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_54 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_54 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_81__80 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_81__80 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size4_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -25319,102 +33552,138 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__1__local_encoder2to3_54 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_55 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_74 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_75 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_73 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_72 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_53 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_53 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_80__79 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_80__79 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_52 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_52 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_79__78 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_79__78 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -25423,102 +33692,138 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__1__local_encoder2to3_52 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_53 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_72 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_73 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_71 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_70 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_51 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_51 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_78__77 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_78__77 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_50 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_50 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_77__76 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_77__76 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -25527,102 +33832,138 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__1__local_encoder2to3_50 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_51 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_70 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_71 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_69 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_68 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_49 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_49 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_76__75 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_76__75 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_48 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_48 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_75__74 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_75__74 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -25631,102 +33972,138 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__1__local_encoder2to3_48 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_49 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_68 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_69 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_67 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_66 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_47 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_47 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_74__73 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_74__73 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_46 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_46 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_73__72 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_73__72 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -25735,103 +34112,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__1__local_encoder2to3_46 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_47 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_66 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_67 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_178 ( .A ( BUF_net_179 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_178 ( .A ( BUF_net_179 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_179 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_179 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_179 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_65 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_64 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_45 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_45 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_72__71 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_72__71 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_44 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_44 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_71__70 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_71__70 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -25840,221 +34254,313 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__1__local_encoder2to3_44 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_45 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_64 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_65 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_176 ( .A ( BUF_net_177 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_176 ( .A ( BUF_net_177 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_177 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_177 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_177 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size6_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_69__68 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_69__68 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size6_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_68__67 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_68__67 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size6_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_67__66 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_67__66 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size6_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_66__65 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_66__65 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_63 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_62 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_61 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_43 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_43 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_65__64 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_65__64 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_42 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_42 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_64__63 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_64__63 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -26064,125 +34570,167 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__1__local_encoder2to3_42 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_43 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_61 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_62 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_63 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_60 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_59 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_58 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_41 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_41 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_63__62 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_63__62 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_40 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_40 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_62__61 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_62__61 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size6_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -26192,125 +34740,167 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__1__local_encoder2to3_40 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_41 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_58 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_59 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_60 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_57 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_56 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_55 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_39 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_39 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_61__60 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_61__60 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_38 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_38 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_60__59 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_60__59 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -26320,125 +34910,167 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__1__local_encoder2to3_38 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_39 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_55 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_56 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_57 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_54 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_53 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_52 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_37 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_37 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_36 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_36 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -26448,125 +35080,167 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__1__local_encoder2to3_36 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_37 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_52 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_53 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_54 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_175 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_51 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_50 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_49 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_35 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_35 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_57__56 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_57__56 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_34 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_34 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_56__55 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_56__55 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -26576,183 +35250,248 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__1__local_encoder2to3_34 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_35 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_49 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_50 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_51 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_173 ( .A ( BUF_net_174 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_173 ( .A ( BUF_net_174 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_174 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_174 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_174 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem2 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input4_mem4 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input4_mem4_10 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input4_mem4_9 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to4 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to4_6 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to4_6 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size10 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -26763,23 +35502,28 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__1__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to4 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input4_mem4_9 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input4_mem4_10 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input4_mem4 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -26787,225 +35531,323 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size5_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size5_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size5_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size5_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size5_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size5_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem2_12 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_48 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_47 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_33 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_33 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_32 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_32 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -27015,124 +35857,166 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__1__local_encoder2to3_32 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_33 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_47 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_48 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem2_12 mux_l1_in_1_ ( 
     .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_172 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem2_11 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_46 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_45 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_31 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_31 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_30 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_30 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size5_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -27142,124 +36026,166 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__1__local_encoder2to3_30 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_31 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_45 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_46 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem2_11 mux_l1_in_1_ ( 
     .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem2_10 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_44 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_43 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_29 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_29 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_28 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_28 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size5_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -27269,125 +36195,168 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__1__local_encoder2to3_28 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_29 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_43 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_44 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem2_10 mux_l1_in_1_ ( 
     .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_170 ( .A ( BUF_net_171 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_171 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_171 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_171 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem2_9 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_42 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_41 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_27 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_27 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_26 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_26 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -27397,125 +36366,168 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__1__local_encoder2to3_26 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_27 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_41 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_42 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem2_9 mux_l1_in_1_ ( 
     .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_168 ( .A ( BUF_net_169 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_168 ( .A ( BUF_net_169 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_169 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_169 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_169 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem2_8 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_40 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_39 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_25 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_25 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_24 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_24 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -27525,124 +36537,166 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__1__local_encoder2to3_24 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_25 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_39 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_40 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem2_8 mux_l1_in_1_ ( 
     .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem2_7 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_38 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_37 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_23 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_23 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_22 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_22 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -27652,206 +36706,286 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__1__local_encoder2to3_22 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_23 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_37 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_38 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem2_7 mux_l1_in_1_ ( 
     .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_167 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_167 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_167 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size9_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size9_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size9_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input4_mem4_8 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input4_mem4_7 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input4_mem4_6 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to4_5 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to4_5 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to4_4 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to4_4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size9 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:8] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -27861,149 +36995,198 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
     .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , 
-    .X ( aps_rename_506_ ) ) ;
+    .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__1__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to4_5 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input4_mem4_6 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input4_mem4_7 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input4_mem4_8 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , in[8] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_165 ( .A ( aps_rename_506_ ) , 
-    .Y ( BUF_net_165 ) ) ;
+    .Y ( BUF_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input4_mem4_5 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input4_mem4_4 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input4_mem4_3 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to4_3 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to4_3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to4_2 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to4_2 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size9_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:8] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -28013,149 +37196,198 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
     .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , 
-    .X ( aps_rename_505_ ) ) ;
+    .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__1__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to4_3 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input4_mem4_3 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input4_mem4_4 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input4_mem4_5 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , in[8] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_163 ( .A ( aps_rename_505_ ) , 
-    .Y ( BUF_net_163 ) ) ;
+    .Y ( BUF_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input4_mem4_2 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input4_mem4_1 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input4_mem4_0 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to4_1 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to4_1 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to4_0 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to4_0 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:8] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -28165,282 +37397,399 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to4_1 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input4_mem4_0 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input4_mem4_1 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input4_mem4_2 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , in[8] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size7_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size7_mem_5 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size7_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size7_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size7_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size7_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size7_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem2_6 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_36 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_35 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_34 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_21 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_21 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_20 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_20 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:6] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -28451,147 +37800,195 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__1__local_encoder2to3_20 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_21 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_34 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_35 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_36 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem2_6 mux_l1_in_2_ (
     .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem2_5 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_33 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_32 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_31 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_19 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_19 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_18 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_18 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:6] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -28602,147 +37999,195 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__1__local_encoder2to3_18 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_19 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_31 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_32 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_33 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem2_5 mux_l1_in_2_ (
     .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem2_4 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_30 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_29 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_28 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_17 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_17 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_16 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_16 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:6] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -28753,148 +38198,197 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__1__local_encoder2to3_16 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_17 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_28 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_29 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_30 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem2_4 mux_l1_in_2_ (
     .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_161 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_161 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_161 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem2_3 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_27 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_26 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_25 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_15 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_15 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_14 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_14 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:6] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -28905,148 +38399,197 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__1__local_encoder2to3_14 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_15 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_25 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_26 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_27 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem2_3 mux_l1_in_2_ (
     .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_192 ( .A ( BUF_net_193 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_192 ( .A ( BUF_net_193 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_193 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_193 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_193 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem2_2 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_24 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_23 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_22 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_13 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_13 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_12 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_12 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:6] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -29057,148 +38600,197 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__1__local_encoder2to3_12 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_13 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_22 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_23 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_24 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem2_2 mux_l1_in_2_ (
     .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_159 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_159 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_159 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem2_1 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_21 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_20 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_19 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_11 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_11 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_10 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_10 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:6] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -29209,147 +38801,195 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__1__local_encoder2to3_10 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_11 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_19 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_20 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_21 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem2_1 mux_l1_in_2_ (
     .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input2_mem2_0 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_18 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_17 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_16 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_9 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_9 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_8 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_8 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:6] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -29360,253 +39000,342 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__1__local_encoder2to3_8 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_9 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_16 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_17 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_18 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input2_mem2_0 mux_l1_in_2_ (
     .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_157 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_157 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_157 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size8_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size8_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size8_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_size8_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_221 ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1403 ( .A ( ropt_net_224 ) , 
-    .X ( copt_net_204 ) ) ;
+    .X ( copt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1404 ( .A ( copt_net_204 ) , 
-    .X ( copt_net_205 ) ) ;
+    .X ( copt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1405 ( .A ( copt_net_205 ) , 
-    .X ( copt_net_206 ) ) ;
+    .X ( copt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1406 ( .A ( copt_net_206 ) , 
-    .X ( copt_net_207 ) ) ;
+    .X ( copt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1407 ( .A ( copt_net_207 ) , 
-    .X ( copt_net_208 ) ) ;
+    .X ( copt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1412 ( .A ( ropt_net_223 ) , 
-    .X ( copt_net_213 ) ) ;
+    .X ( copt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1416 ( .A ( copt_net_213 ) , 
-    .X ( ropt_net_219 ) ) ;
+    .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1417 ( .A ( ropt_net_219 ) , 
-    .X ( ropt_net_220 ) ) ;
+    .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1418 ( .A ( ropt_net_220 ) , 
-    .X ( ropt_net_221 ) ) ;
+    .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1419 ( .A ( copt_net_208 ) , 
-    .X ( ropt_net_222 ) ) ;
+    .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1420 ( .A ( ropt_net_222 ) , 
-    .X ( ropt_net_223 ) ) ;
+    .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1421 ( .A ( ccff_head[0] ) , 
-    .X ( ropt_net_224 ) ) ;
+    .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_15 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_14 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_13 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_12 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_7 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_7 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_6 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_6 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:7] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -29617,148 +39346,196 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__1__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_7 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_12 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_13 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_14 mux_l1_in_2_ (
     .in ( { in[6] , in[7] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_15 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_2_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_11 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_10 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_9 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_8 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_5 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_5 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_4 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:7] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -29769,149 +39546,198 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__1__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_5 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_8 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_9 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_10 mux_l1_in_2_ (
     .in ( { in[6] , in[7] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_11 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_2_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_155 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_155 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_155 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_7 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_6 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_5 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_4 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_3 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_2 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_2 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:7] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -29922,149 +39748,198 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__1__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_4 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_5 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_6 mux_l1_in_2_ (
     .in ( { in[6] , in[7] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_7 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_2_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_153 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_153 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_153 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_3 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_2 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_1 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__1__mux_2level_tapbuf_basis_input3_mem3_0 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_1 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_1 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__local_encoder2to3_0 ( addr , data , data_inv ) ;
+module sb_2__1__local_encoder2to3_0 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__1__mux_2level_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__1__mux_2level_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:7] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -30075,36 +39950,44 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__1__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__local_encoder2to3_1 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_0 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_1 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_2 mux_l1_in_2_ (
     .in ( { in[6] , in[7] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_2__1__mux_2level_tapbuf_basis_input3_mem3_3 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_2_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_150 ( .A ( BUF_net_151 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_150 ( .A ( BUF_net_151 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_151 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_151 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_151 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
@@ -30122,7 +40005,7 @@
     left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , 
     left_bottom_grid_pin_43_ , ccff_head , chany_top_out , chany_bottom_out , 
     chanx_left_out , ccff_tail , pReset_W_in , pReset_N_out , 
-    prog_clk_0_N_in ) ;
+    prog_clk_0_N_in , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:29] chany_top_in ;
 input  [0:0] top_left_grid_pin_44_ ;
@@ -30161,6 +40044,8 @@
 input  pReset_W_in ;
 output pReset_N_out ;
 input  prog_clk_0_N_in ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] prog_clk ;
 wire prog_clk_0 ;
@@ -30261,6 +40146,8 @@
 wire [0:0] mux_2level_tapbuf_size9_mem_0_ccff_tail ;
 wire [0:0] mux_2level_tapbuf_size9_mem_1_ccff_tail ;
 wire [0:0] mux_2level_tapbuf_size9_mem_2_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 assign prog_clk_0 = prog_clk[0] ;
 
@@ -30271,7 +40158,8 @@
     .sram ( mux_2level_tapbuf_size8_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
         SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( chany_top_out[0] ) , .p0 ( optlc_net_197 ) ) ;
+    .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_197 ) ) ;
 sb_2__1__mux_2level_tapbuf_size8_1 mux_bottom_track_1 (
     .in ( { chany_bottom_out[4] , chany_bottom_out[20] , 
         bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , 
@@ -30280,7 +40168,8 @@
     .sram ( mux_2level_tapbuf_size8_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
         SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
-    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_197 ) ) ;
+    .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_197 ) ) ;
 sb_2__1__mux_2level_tapbuf_size8_2 mux_bottom_track_3 (
     .in ( { chany_bottom_out[7] , chany_bottom_out[21] , 
         bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , 
@@ -30289,7 +40178,8 @@
     .sram ( mux_2level_tapbuf_size8_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
         SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
-    .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_197 ) ) ;
+    .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_197 ) ) ;
 sb_2__1__mux_2level_tapbuf_size8 mux_bottom_track_5 (
     .in ( { chany_bottom_out[8] , chany_bottom_out[23] , 
         bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , 
@@ -30298,26 +40188,31 @@
     .sram ( mux_2level_tapbuf_size8_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
         SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
-    .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_196 ) ) ;
+    .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_196 ) ) ;
 sb_2__1__mux_2level_tapbuf_size8_mem_0 mem_top_track_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
     .ccff_tail ( mux_2level_tapbuf_size8_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size8_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size8_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size8_mem_1 mem_bottom_track_1 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size5_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size8_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size8_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size8_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size8_mem_2 mem_bottom_track_3 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size8_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size8_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size8_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size8_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size8_mem mem_bottom_track_5 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size8_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size8_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size8_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size8_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size7_0 mux_top_track_2 (
     .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , 
         top_left_grid_pin_51_[0] , chany_top_out[7] , chany_top_out[21] , 
@@ -30325,7 +40220,8 @@
     .sram ( mux_2level_tapbuf_size7_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
         SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
-    .out ( chany_top_out[1] ) , .p0 ( optlc_net_197 ) ) ;
+    .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_197 ) ) ;
 sb_2__1__mux_2level_tapbuf_size7_1 mux_top_track_4 (
     .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , 
         top_right_grid_pin_1_[0] , chany_top_out[8] , chany_top_out[23] , 
@@ -30333,7 +40229,8 @@
     .sram ( mux_2level_tapbuf_size7_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
         SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
-    .out ( chany_top_out[2] ) , .p0 ( optlc_net_197 ) ) ;
+    .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_197 ) ) ;
 sb_2__1__mux_2level_tapbuf_size7_2 mux_top_track_12 (
     .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_50_[0] , 
         chany_top_out[12] , chany_top_out[27] , chanx_left_in[6] , 
@@ -30341,7 +40238,8 @@
     .sram ( mux_2level_tapbuf_size7_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
         SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
-    .out ( chany_top_out[6] ) , .p0 ( optlc_net_201 ) ) ;
+    .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_201 ) ) ;
 sb_2__1__mux_2level_tapbuf_size7_3 mux_top_track_20 (
     .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_51_[0] , 
         chany_top_out[13] , chany_top_out[28] , chanx_left_in[5] , 
@@ -30349,7 +40247,8 @@
     .sram ( mux_2level_tapbuf_size7_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
         SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
-    .out ( chany_top_out[10] ) , .p0 ( optlc_net_201 ) ) ;
+    .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_201 ) ) ;
 sb_2__1__mux_2level_tapbuf_size7_4 mux_top_track_28 (
     .in ( { top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , 
         chany_top_out[15] , chany_top_out[29] , chanx_left_in[4] , 
@@ -30357,7 +40256,8 @@
     .sram ( mux_2level_tapbuf_size7_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
         SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
-    .out ( chany_top_out[14] ) , .p0 ( optlc_net_197 ) ) ;
+    .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_197 ) ) ;
 sb_2__1__mux_2level_tapbuf_size7_5 mux_bottom_track_13 (
     .in ( { chany_bottom_out[12] , chany_bottom_out[27] , 
         bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , 
@@ -30365,7 +40265,8 @@
     .sram ( mux_2level_tapbuf_size7_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
         SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
-    .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_201 ) ) ;
+    .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_201 ) ) ;
 sb_2__1__mux_2level_tapbuf_size7 mux_bottom_track_21 (
     .in ( { chany_bottom_out[13] , chany_bottom_out[28] , 
         bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_50_[0] , 
@@ -30373,42 +40274,50 @@
     .sram ( mux_2level_tapbuf_size7_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
         SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
-    .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_200 ) ) ;
+    .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_200 ) ) ;
 sb_2__1__mux_2level_tapbuf_size7_mem_0 mem_top_track_2 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size8_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size7_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size7_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size7_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size7_mem_1 mem_top_track_4 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size7_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size7_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size7_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size7_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size7_mem_2 mem_top_track_12 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size9_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size7_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size7_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size7_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size7_mem_3 mem_top_track_20 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size7_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size7_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size7_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size7_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size7_mem_4 mem_top_track_28 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size7_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size7_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size7_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size7_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size7_mem_5 mem_bottom_track_13 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size9_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size7_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size7_5_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size7_5_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size7_mem mem_bottom_track_21 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size7_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size7_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size7_6_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size7_6_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size9_0 mux_top_track_6 (
     .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , 
         top_left_grid_pin_48_[0] , top_left_grid_pin_50_[0] , 
@@ -30418,7 +40327,7 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
         SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
     .out ( { aps_rename_507_ } ) ,
-    .p0 ( optlc_net_198 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_198 ) ) ;
 sb_2__1__mux_2level_tapbuf_size9_1 mux_top_track_10 (
     .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , 
         top_left_grid_pin_49_[0] , top_left_grid_pin_51_[0] , 
@@ -30427,7 +40336,8 @@
     .sram ( mux_2level_tapbuf_size9_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
         SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
-    .out ( chany_top_out[5] ) , .p0 ( optlc_net_201 ) ) ;
+    .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_201 ) ) ;
 sb_2__1__mux_2level_tapbuf_size9 mux_bottom_track_11 (
     .in ( { chany_bottom_out[11] , chany_bottom_out[25] , 
         bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , 
@@ -30436,94 +40346,110 @@
     .sram ( mux_2level_tapbuf_size9_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
         SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
-    .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_200 ) ) ;
+    .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_200 ) ) ;
 sb_2__1__mux_2level_tapbuf_size9_mem_0 mem_top_track_6 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size7_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size9_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size9_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size9_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size9_mem_1 mem_top_track_10 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size9_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size9_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size9_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size9_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size9_mem mem_bottom_track_11 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size10_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size9_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size9_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size9_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size5_0 mux_top_track_36 (
     .in ( { top_left_grid_pin_47_[0] , chany_top_out[16] , chanx_left_in[3] , 
         chanx_left_in[14] , chanx_left_in[25] } ) ,
     .sram ( mux_2level_tapbuf_size5_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
         SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
-    .out ( chany_top_out[18] ) , .p0 ( optlc_net_197 ) ) ;
+    .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_197 ) ) ;
 sb_2__1__mux_2level_tapbuf_size5_1 mux_top_track_44 (
     .in ( { top_left_grid_pin_48_[0] , chany_top_out[17] , chanx_left_in[2] , 
         chanx_left_in[13] , chanx_left_in[24] } ) ,
     .sram ( mux_2level_tapbuf_size5_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
         SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
-    .out ( chany_top_out[22] ) , .p0 ( optlc_net_197 ) ) ;
+    .out ( chany_top_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_197 ) ) ;
 sb_2__1__mux_2level_tapbuf_size5_2 mux_top_track_52 (
     .in ( { top_left_grid_pin_49_[0] , chany_top_out[19] , chanx_left_in[1] , 
         chanx_left_in[12] , chanx_left_in[23] } ) ,
     .sram ( mux_2level_tapbuf_size5_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , 
         SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
-    .out ( chany_top_out[26] ) , .p0 ( optlc_net_198 ) ) ;
+    .out ( chany_top_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_198 ) ) ;
 sb_2__1__mux_2level_tapbuf_size5_3 mux_bottom_track_53 (
     .in ( { chany_bottom_out[19] , bottom_left_grid_pin_48_[0] , 
         chanx_left_in[0] , chanx_left_in[11] , chanx_left_in[22] } ) ,
     .sram ( mux_2level_tapbuf_size5_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , 
         SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
-    .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_196 ) ) ;
+    .out ( chany_bottom_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_196 ) ) ;
 sb_2__1__mux_2level_tapbuf_size5_4 mux_left_track_5 (
     .in ( { chany_bottom_out[8] , chany_bottom_in[1] , chany_top_out[8] , 
         left_bottom_grid_pin_38_[0] , chanx_left_out[19] } ) ,
     .sram ( mux_2level_tapbuf_size5_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , 
         SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
-    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_199 ) ) ;
+    .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_199 ) ) ;
 sb_2__1__mux_2level_tapbuf_size5 mux_left_track_11 (
     .in ( { chany_bottom_out[12] , chany_bottom_in[5] , chany_top_out[12] , 
         left_bottom_grid_pin_38_[0] , chanx_left_out[19] } ) ,
     .sram ( mux_2level_tapbuf_size5_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , 
         SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
-    .out ( chanx_left_out[5] ) , .p0 ( optlc_net_196 ) ) ;
+    .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_196 ) ) ;
 sb_2__1__mux_2level_tapbuf_size5_mem_0 mem_top_track_36 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size7_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size5_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size5_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size5_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size5_mem_1 mem_top_track_44 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size5_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size5_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size5_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size5_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size5_mem_2 mem_top_track_52 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size5_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size5_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size5_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size5_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size5_mem_3 mem_bottom_track_53 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size5_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size5_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size5_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size5_mem_4 mem_left_track_5 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size5_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size5_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size5_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size5_mem mem_left_track_11 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size5_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size5_5_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size5_5_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size10 mux_bottom_track_7 (
     .in ( { chany_bottom_out[9] , chany_bottom_out[24] , 
         bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , 
@@ -30534,12 +40460,13 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , 
         SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
     .out ( { aps_rename_508_ } ) ,
-    .p0 ( optlc_net_202 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_202 ) ) ;
 sb_2__1__mux_2level_tapbuf_size10_mem mem_bottom_track_7 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size8_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size10_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size10_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size10_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size6_0 mux_bottom_track_29 (
     .in ( { chany_bottom_out[15] , chany_bottom_out[29] , 
         bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_51_[0] , 
@@ -30547,7 +40474,8 @@
     .sram ( mux_2level_tapbuf_size6_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , 
         SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
-    .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_202 ) ) ;
+    .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_202 ) ) ;
 sb_2__1__mux_2level_tapbuf_size6_1 mux_left_track_1 (
     .in ( { chany_top_in[0] , chany_bottom_out[4] , chany_top_out[4] , 
         left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , 
@@ -30555,7 +40483,8 @@
     .sram ( mux_2level_tapbuf_size6_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , 
         SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
-    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_202 ) ) ;
+    .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_202 ) ) ;
 sb_2__1__mux_2level_tapbuf_size6_2 mux_left_track_3 (
     .in ( { chany_bottom_out[7] , chany_bottom_in[0] , chany_top_out[7] , 
         left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , 
@@ -30563,7 +40492,8 @@
     .sram ( mux_2level_tapbuf_size6_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , 
         SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
-    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_196 ) ) ;
+    .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_196 ) ) ;
 sb_2__1__mux_2level_tapbuf_size6_3 mux_left_track_7 (
     .in ( { chany_bottom_out[9] , chany_bottom_in[2] , chany_top_out[9] , 
         left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , 
@@ -30571,7 +40501,8 @@
     .sram ( mux_2level_tapbuf_size6_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , 
         SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) ,
-    .out ( chanx_left_out[3] ) , .p0 ( optlc_net_203 ) ) ;
+    .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_203 ) ) ;
 sb_2__1__mux_2level_tapbuf_size6 mux_left_track_9 (
     .in ( { chany_bottom_out[11] , chany_bottom_in[4] , chany_top_out[11] , 
         left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , 
@@ -30579,3564 +40510,4981 @@
     .sram ( mux_2level_tapbuf_size6_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , 
         SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) ,
-    .out ( chanx_left_out[4] ) , .p0 ( optlc_net_196 ) ) ;
+    .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_196 ) ) ;
 sb_2__1__mux_2level_tapbuf_size6_mem_0 mem_bottom_track_29 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size7_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size6_mem_1 mem_left_track_1 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size5_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size6_mem_2 mem_left_track_3 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size6_mem_3 mem_left_track_7 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size5_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size6_mem mem_left_track_9 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size4_0 mux_bottom_track_37 (
     .in ( { chany_bottom_out[16] , bottom_left_grid_pin_46_[0] , 
         chanx_left_in[9] , chanx_left_in[20] } ) ,
     .sram ( mux_2level_tapbuf_size4_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , 
         SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) ,
-    .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_202 ) ) ;
+    .out ( chany_bottom_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_202 ) ) ;
 sb_2__1__mux_2level_tapbuf_size4_1 mux_bottom_track_45 (
     .in ( { chany_bottom_out[17] , bottom_left_grid_pin_47_[0] , 
         chanx_left_in[10] , chanx_left_in[21] } ) ,
     .sram ( mux_2level_tapbuf_size4_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 , 
         SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) ,
-    .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_197 ) ) ;
+    .out ( chany_bottom_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_197 ) ) ;
 sb_2__1__mux_2level_tapbuf_size4_2 mux_left_track_13 (
     .in ( { chany_bottom_out[13] , chany_bottom_in[9] , chany_top_out[13] , 
         left_bottom_grid_pin_36_[0] } ) ,
     .sram ( mux_2level_tapbuf_size4_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 , 
         SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) ,
-    .out ( chanx_left_out[6] ) , .p0 ( optlc_net_196 ) ) ;
+    .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_196 ) ) ;
 sb_2__1__mux_2level_tapbuf_size4_3 mux_left_track_15 (
     .in ( { chany_bottom_out[15] , chany_bottom_in[13] , chany_top_out[15] , 
         left_bottom_grid_pin_37_[0] } ) ,
     .sram ( mux_2level_tapbuf_size4_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 , 
         SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) ,
-    .out ( chanx_left_out[7] ) , .p0 ( optlc_net_203 ) ) ;
+    .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_203 ) ) ;
 sb_2__1__mux_2level_tapbuf_size4_4 mux_left_track_17 (
     .in ( { chany_bottom_out[16] , chany_top_out[16] , chany_bottom_in[17] , 
         left_bottom_grid_pin_38_[0] } ) ,
     .sram ( mux_2level_tapbuf_size4_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 , 
         SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) ,
-    .out ( chanx_left_out[8] ) , .p0 ( optlc_net_203 ) ) ;
+    .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_203 ) ) ;
 sb_2__1__mux_2level_tapbuf_size4_5 mux_left_track_19 (
     .in ( { chany_bottom_out[17] , chany_top_out[17] , chany_bottom_in[21] , 
         left_bottom_grid_pin_39_[0] } ) ,
     .sram ( mux_2level_tapbuf_size4_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 , 
         SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) ,
-    .out ( chanx_left_out[9] ) , .p0 ( optlc_net_203 ) ) ;
+    .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_203 ) ) ;
 sb_2__1__mux_2level_tapbuf_size4_6 mux_left_track_21 (
     .in ( { chany_bottom_out[19] , chany_top_out[19] , chany_bottom_in[25] , 
         left_bottom_grid_pin_40_[0] } ) ,
     .sram ( mux_2level_tapbuf_size4_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 , 
         SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) ,
-    .out ( chanx_left_out[10] ) , .p0 ( optlc_net_203 ) ) ;
+    .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_203 ) ) ;
 sb_2__1__mux_2level_tapbuf_size4 mux_left_track_23 (
     .in ( { chany_bottom_out[20] , chany_top_out[20] , chany_bottom_in[29] , 
         chanx_left_out[19] } ) ,
     .sram ( mux_2level_tapbuf_size4_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 , 
         SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) ,
-    .out ( chanx_left_out[11] ) , .p0 ( optlc_net_199 ) ) ;
+    .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_199 ) ) ;
 sb_2__1__mux_2level_tapbuf_size4_mem_0 mem_bottom_track_37 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size4_mem_1 mem_bottom_track_45 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size4_mem_2 mem_left_track_13 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size5_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size4_mem_3 mem_left_track_15 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size4_mem_4 mem_left_track_17 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size4_mem_5 mem_left_track_19 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_5_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_5_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size4_mem_6 mem_left_track_21 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_6_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_6_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size4_mem mem_left_track_23 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_7_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_7_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_7_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size3_0 mux_left_track_25 (
     .in ( { chany_bottom_out[21] , chany_top_out[21] , 
         left_bottom_grid_pin_42_[0] } ) ,
     .sram ( mux_2level_tapbuf_size3_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 } ) ,
-    .out ( chanx_left_out[12] ) , .p0 ( optlc_net_196 ) ) ;
+    .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_196 ) ) ;
 sb_2__1__mux_2level_tapbuf_size3_1 mux_left_track_27 (
     .in ( { chany_bottom_out[23] , chany_top_out[23] , 
         left_bottom_grid_pin_43_[0] } ) ,
     .sram ( mux_2level_tapbuf_size3_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) ,
-    .out ( chanx_left_out[13] ) , .p0 ( optlc_net_199 ) ) ;
+    .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_199 ) ) ;
 sb_2__1__mux_2level_tapbuf_size3_2 mux_left_track_29 (
     .in ( { chany_bottom_out[24] , chany_top_out[24] , 
         left_bottom_grid_pin_36_[0] } ) ,
     .sram ( mux_2level_tapbuf_size3_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 } ) ,
-    .out ( chanx_left_out[14] ) , .p0 ( optlc_net_199 ) ) ;
+    .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_199 ) ) ;
 sb_2__1__mux_2level_tapbuf_size3_3 mux_left_track_31 (
     .in ( { chany_bottom_out[25] , chany_top_out[25] , 
         left_bottom_grid_pin_37_[0] } ) ,
     .sram ( mux_2level_tapbuf_size3_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_143 , SYNOPSYS_UNCONNECTED_144 } ) ,
-    .out ( chanx_left_out[15] ) , .p0 ( optlc_net_199 ) ) ;
+    .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_199 ) ) ;
 sb_2__1__mux_2level_tapbuf_size3_4 mux_left_track_33 (
     .in ( { chany_bottom_out[27] , chany_top_out[27] , 
         left_bottom_grid_pin_38_[0] } ) ,
     .sram ( mux_2level_tapbuf_size3_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_145 , SYNOPSYS_UNCONNECTED_146 } ) ,
-    .out ( chanx_left_out[16] ) , .p0 ( optlc_net_199 ) ) ;
+    .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_199 ) ) ;
 sb_2__1__mux_2level_tapbuf_size3_5 mux_left_track_35 (
     .in ( { chany_bottom_out[28] , chany_top_out[28] , 
         left_bottom_grid_pin_39_[0] } ) ,
     .sram ( mux_2level_tapbuf_size3_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 } ) ,
-    .out ( chanx_left_out[17] ) , .p0 ( optlc_net_196 ) ) ;
+    .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_196 ) ) ;
 sb_2__1__mux_2level_tapbuf_size3_6 mux_left_track_37 (
     .in ( { chany_bottom_out[29] , chany_top_out[29] , 
         left_bottom_grid_pin_40_[0] } ) ,
     .sram ( mux_2level_tapbuf_size3_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_149 , SYNOPSYS_UNCONNECTED_150 } ) ,
-    .out ( chanx_left_out[18] ) , .p0 ( optlc_net_196 ) ) ;
+    .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_196 ) ) ;
 sb_2__1__mux_2level_tapbuf_size3 mux_left_track_51 (
     .in ( { chany_top_in[9] , left_bottom_grid_pin_39_[0] , 
         left_bottom_grid_pin_43_[0] } ) ,
     .sram ( mux_2level_tapbuf_size3_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_151 , SYNOPSYS_UNCONNECTED_152 } ) ,
-    .out ( chanx_left_out[25] ) , .p0 ( optlc_net_199 ) ) ;
+    .out ( chanx_left_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_199 ) ) ;
 sb_2__1__mux_2level_tapbuf_size3_mem_0 mem_left_track_25 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_7_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size3_mem_1 mem_left_track_27 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size3_mem_2 mem_left_track_29 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size3_mem_3 mem_left_track_31 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size3_mem_4 mem_left_track_33 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size3_mem_5 mem_left_track_35 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_5_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_5_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size3_mem_6 mem_left_track_37 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_6_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_6_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size3_mem mem_left_track_51 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_7_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_7_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_7_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size2_0 mux_left_track_41 (
     .in ( { chany_top_in[29] , left_bottom_grid_pin_42_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 } ) ,
-    .out ( chanx_left_out[20] ) , .p0 ( optlc_net_196 ) ) ;
+    .out ( chanx_left_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_196 ) ) ;
 sb_2__1__mux_2level_tapbuf_size2_1 mux_left_track_45 (
     .in ( { chany_top_in[21] , left_bottom_grid_pin_36_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_155 , SYNOPSYS_UNCONNECTED_156 } ) ,
-    .out ( chanx_left_out[22] ) , .p0 ( optlc_net_196 ) ) ;
+    .out ( chanx_left_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_196 ) ) ;
 sb_2__1__mux_2level_tapbuf_size2_2 mux_left_track_47 (
     .in ( { chany_top_in[17] , left_bottom_grid_pin_37_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_157 , SYNOPSYS_UNCONNECTED_158 } ) ,
-    .out ( chanx_left_out[23] ) , .p0 ( optlc_net_196 ) ) ;
+    .out ( chanx_left_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_196 ) ) ;
 sb_2__1__mux_2level_tapbuf_size2_3 mux_left_track_49 (
     .in ( { chany_top_in[13] , left_bottom_grid_pin_38_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 } ) ,
-    .out ( chanx_left_out[24] ) , .p0 ( optlc_net_200 ) ) ;
+    .out ( chanx_left_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_200 ) ) ;
 sb_2__1__mux_2level_tapbuf_size2_4 mux_left_track_53 (
     .in ( { chany_top_in[5] , left_bottom_grid_pin_40_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_161 , SYNOPSYS_UNCONNECTED_162 } ) ,
-    .out ( chanx_left_out[26] ) , .p0 ( optlc_net_199 ) ) ;
+    .out ( chanx_left_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_199 ) ) ;
 sb_2__1__mux_2level_tapbuf_size2_5 mux_left_track_55 (
     .in ( { chany_top_in[4] , chanx_left_out[19] } ) ,
     .sram ( mux_2level_tapbuf_size2_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_163 , SYNOPSYS_UNCONNECTED_164 } ) ,
-    .out ( chanx_left_out[27] ) , .p0 ( optlc_net_200 ) ) ;
+    .out ( chanx_left_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_200 ) ) ;
 sb_2__1__mux_2level_tapbuf_size2 mux_left_track_57 (
     .in ( { chany_top_in[2] , left_bottom_grid_pin_42_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_165 , SYNOPSYS_UNCONNECTED_166 } ) ,
-    .out ( chanx_left_out[28] ) , .p0 ( optlc_net_199 ) ) ;
+    .out ( chanx_left_out[28] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_199 ) ) ;
 sb_2__1__mux_2level_tapbuf_size2_mem_0 mem_left_track_41 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size2_mem_1 mem_left_track_45 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size2_mem_2 mem_left_track_47 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size2_mem_3 mem_left_track_49 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size2_mem_4 mem_left_track_53 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_7_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size2_mem_5 mem_left_track_55 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_5_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_5_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__1__mux_2level_tapbuf_size2_mem mem_left_track_57 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_tapbuf_size2_6_sram ) ) ;
-sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_tapbuf_size2_6_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_199 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , 
-    .HI ( optlc_net_196 ) ) ;
+    .HI ( optlc_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
-    .X ( prog_clk[0] ) ) ;
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_110__109 ( .A ( chany_top_in[1] ) , 
-    .X ( chanx_left_out[29] ) ) ;
+    .X ( chanx_left_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_111__110 ( .A ( chany_top_in[3] ) , 
-    .X ( chany_bottom_out[4] ) ) ;
+    .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_112__111 ( .A ( chany_top_in[6] ) , 
-    .X ( chany_bottom_out[7] ) ) ;
+    .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_113__112 ( .A ( chany_top_in[7] ) , 
-    .X ( chany_bottom_out[8] ) ) ;
+    .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_114__113 ( .A ( chany_top_in[8] ) , 
-    .X ( chany_bottom_out[9] ) ) ;
+    .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_115__114 ( .A ( chany_top_in[10] ) , 
-    .X ( chany_bottom_out[11] ) ) ;
+    .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_116__115 ( .A ( chany_top_in[11] ) , 
-    .X ( chany_bottom_out[12] ) ) ;
+    .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_117__116 ( .A ( chany_top_in[12] ) , 
-    .X ( chany_bottom_out[13] ) ) ;
+    .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_118__117 ( .A ( chany_top_in[14] ) , 
-    .X ( chany_bottom_out[15] ) ) ;
+    .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_119__118 ( .A ( chany_top_in[15] ) , 
-    .X ( chany_bottom_out[16] ) ) ;
+    .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_120__119 ( .A ( chany_top_in[16] ) , 
-    .X ( chany_bottom_out[17] ) ) ;
+    .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_121__120 ( .A ( chany_top_in[18] ) , 
-    .X ( chany_bottom_out[19] ) ) ;
+    .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_122__121 ( .A ( chany_top_in[19] ) , 
-    .X ( chany_bottom_out[20] ) ) ;
+    .X ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_123__122 ( .A ( chany_top_in[20] ) , 
-    .X ( chany_bottom_out[21] ) ) ;
+    .X ( chany_bottom_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_124__123 ( .A ( chany_top_in[22] ) , 
-    .X ( chany_bottom_out[23] ) ) ;
+    .X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_125__124 ( .A ( chany_top_in[23] ) , 
-    .X ( chany_bottom_out[24] ) ) ;
+    .X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_126__125 ( .A ( chany_top_in[24] ) , 
-    .X ( chany_bottom_out[25] ) ) ;
+    .X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_127__126 ( .A ( chany_top_in[25] ) , 
-    .X ( chanx_left_out[21] ) ) ;
+    .X ( chanx_left_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_128__127 ( .A ( chany_top_in[26] ) , 
-    .X ( chany_bottom_out[27] ) ) ;
+    .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_129__128 ( .A ( chany_top_in[27] ) , 
-    .X ( chany_bottom_out[28] ) ) ;
+    .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_130__129 ( .A ( chany_top_in[28] ) , 
-    .X ( chany_bottom_out[29] ) ) ;
+    .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_131__130 ( .A ( chany_bottom_in[3] ) , 
-    .X ( chany_top_out[4] ) ) ;
+    .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_132__131 ( .A ( chany_bottom_in[6] ) , 
-    .X ( chany_top_out[7] ) ) ;
+    .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_133__132 ( .A ( chany_bottom_in[7] ) , 
-    .X ( chany_top_out[8] ) ) ;
+    .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_134__133 ( .A ( chany_bottom_in[8] ) , 
-    .X ( chany_top_out[9] ) ) ;
+    .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_135__134 ( .A ( chany_bottom_in[10] ) , 
-    .X ( chany_top_out[11] ) ) ;
+    .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_136__135 ( .A ( chany_bottom_in[11] ) , 
-    .X ( chany_top_out[12] ) ) ;
+    .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_137__136 ( .A ( chany_bottom_in[12] ) , 
-    .X ( chany_top_out[13] ) ) ;
+    .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_138__137 ( .A ( chany_bottom_in[14] ) , 
-    .X ( chany_top_out[15] ) ) ;
+    .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_139__138 ( .A ( chany_bottom_in[15] ) , 
-    .X ( chany_top_out[16] ) ) ;
+    .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_140__139 ( .A ( chany_bottom_in[16] ) , 
-    .X ( chany_top_out[17] ) ) ;
+    .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_141__140 ( .A ( chany_bottom_in[18] ) , 
-    .X ( chany_top_out[19] ) ) ;
+    .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_142__141 ( .A ( chany_bottom_in[19] ) , 
-    .X ( chany_top_out[20] ) ) ;
+    .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_143__142 ( .A ( chany_bottom_in[20] ) , 
-    .X ( chany_top_out[21] ) ) ;
+    .X ( chany_top_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_144__143 ( .A ( chany_bottom_in[22] ) , 
-    .X ( chany_top_out[23] ) ) ;
+    .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_145__144 ( .A ( chany_bottom_in[23] ) , 
-    .X ( chany_top_out[24] ) ) ;
+    .X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_146__145 ( .A ( chany_bottom_in[24] ) , 
-    .X ( chany_top_out[25] ) ) ;
+    .X ( chany_top_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_147__146 ( .A ( chany_bottom_in[26] ) , 
-    .X ( chany_top_out[27] ) ) ;
+    .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_148__147 ( .A ( chany_bottom_in[27] ) , 
-    .X ( chany_top_out[28] ) ) ;
+    .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_149__148 ( .A ( chany_bottom_in[28] ) , 
-    .X ( chany_top_out[29] ) ) ;
+    .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_150__149 ( .A ( left_bottom_grid_pin_41_[0] ) , 
-    .X ( chanx_left_out[19] ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_190 ( .A ( BUF_net_191 ) , .Y ( pReset_N_out ) ) ;
-sky130_fd_sc_hd__inv_1 BINV_R_191 ( .A ( pReset_W_in ) , .Y ( BUF_net_191 ) ) ;
+    .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_190 ( .A ( BUF_net_191 ) , .Y ( pReset_N_out ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_191 ( .A ( pReset_W_in ) , .Y ( BUF_net_191 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_201 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , 
-    .HI ( optlc_net_197 ) ) ;
+    .HI ( optlc_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_203 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , 
-    .HI ( optlc_net_198 ) ) ;
+    .HI ( optlc_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_205 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , 
-    .HI ( optlc_net_199 ) ) ;
+    .HI ( optlc_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_208 ( .LO ( SYNOPSYS_UNCONNECTED_171 ) , 
-    .HI ( optlc_net_200 ) ) ;
+    .HI ( optlc_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_211 ( .LO ( SYNOPSYS_UNCONNECTED_172 ) , 
-    .HI ( optlc_net_201 ) ) ;
+    .HI ( optlc_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_213 ( .LO ( SYNOPSYS_UNCONNECTED_173 ) , 
-    .HI ( optlc_net_202 ) ) ;
+    .HI ( optlc_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_215 ( .LO ( SYNOPSYS_UNCONNECTED_174 ) , 
-    .HI ( optlc_net_203 ) ) ;
+    .HI ( optlc_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_216 ( .A ( aps_rename_508_ ) , 
-    .X ( chany_bottom_out[3] ) ) ;
+    .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_217 ( .A ( aps_rename_507_ ) , 
-    .X ( chany_top_out[3] ) ) ;
+    .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
 
 wire copt_net_185 ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_185 ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_185 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_77__76 ( .A ( copt_net_186 ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 copt_h_inst_1378 ( .A ( copt_net_185 ) , 
-    .X ( mem_out[1] ) ) ;
+    .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 copt_h_inst_1379 ( .A ( mem_out[1] ) , 
-    .X ( copt_net_186 ) ) ;
+    .X ( copt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_34 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_76__75 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_76__75 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_33 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_75__74 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_75__74 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_32 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_74__73 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_74__73 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_31 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_73__72 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_73__72 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_30 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_72__71 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_72__71 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_29 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_71__70 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_71__70 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_28 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_27 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_69__68 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_69__68 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_26 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_68__67 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_68__67 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_25 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_67__66 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_67__66 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_24 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_66__65 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_66__65 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_23 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_65__64 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_65__64 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_22 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_64__63 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_64__63 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_21 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_63__62 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_63__62 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_20 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_62__61 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_62__61 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_19 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_61__60 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_61__60 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_18 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_60__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_60__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_17 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_16 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_15 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_57__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_57__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_14 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_56__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_56__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_13 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_12 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_11 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_10 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_9 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_8 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_7 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_6 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_5 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size2_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_85 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_85 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_165 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_165 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_165 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_84 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_83 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_34 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_34 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_83 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_84 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_82 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_81 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_33 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_33 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_81 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_82 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_80 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_79 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_32 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_32 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_79 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_80 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_163 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_163 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_163 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_78 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_77 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_31 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_31 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_77 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_78 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_76 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_75 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_30 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_30 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_75 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_76 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_74 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_73 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_29 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_29 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_73 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_74 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_161 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_161 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_161 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_72 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_71 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_28 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_28 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_71 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_72 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_159 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_159 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_159 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_70 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_69 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_27 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_27 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_69 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_70 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_157 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_157 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_157 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_68 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_67 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_26 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_26 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_67 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_68 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_155 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_155 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_155 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_66 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_65 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_25 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_25 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_65 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_66 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_153 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_153 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_153 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_64 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_63 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_24 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_24 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_63 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_64 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_150 ( .A ( BUF_net_151 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_150 ( .A ( BUF_net_151 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_151 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_151 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_151 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_62 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_61 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_23 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_61 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_62 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_148 ( .A ( BUF_net_149 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_148 ( .A ( BUF_net_149 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_149 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_149 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_149 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_60 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_59 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_22 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_59 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_60 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_146 ( .A ( BUF_net_147 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_146 ( .A ( BUF_net_147 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_147 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_147 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_147 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_58 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_57 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_21 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_57 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_58 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_145 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_145 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_145 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_56 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_55 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_20 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_55 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_56 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_143 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_143 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_143 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_54 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_53 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_19 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_53 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_54 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_140 ( .A ( BUF_net_141 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_140 ( .A ( BUF_net_141 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_141 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_141 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_141 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_52 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_51 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_18 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_51 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_52 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_139 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_139 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_139 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_50 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_49 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_17 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_49 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_50 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_137 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_137 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_137 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_48 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_47 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_16 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_47 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_48 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_46 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_45 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_15 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_45 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_46 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_44 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_43 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_14 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_43 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_44 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_135 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_135 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_135 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_42 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_41 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_13 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_41 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_42 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_133 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_133 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_133 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_40 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_39 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_12 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_39 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_40 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_131 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_131 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_131 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_38 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_37 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_11 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_37 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_38 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_129 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_129 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_129 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_36 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_35 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_10 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_35 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_36 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_127 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_127 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_127 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_34 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_33 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_33 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_34 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_125 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_125 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_125 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_32 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_31 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_31 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_32 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_123 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_123 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_123 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_30 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_29 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_29 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_30 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_28 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_27 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_27 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_28 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_121 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_121 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_121 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_26 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_25 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_25 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_26 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_24 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_23 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_23 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_24 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_119 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_119 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_119 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_22 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_21 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_21 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_22 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_20 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_19 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_19 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_20 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_18 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_17 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_17 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_18 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_117 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_117 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_117 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_16 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_15 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_15 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_16 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_115 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_115 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_115 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size3_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size3_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size3_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size3_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_14 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_13 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_12 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_13 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_14 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_113 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_113 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_113 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_11 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_10 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_9 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_9 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_10 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_111 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_111 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_111 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_8 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_7 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_6 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_7 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_8 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_109 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_5 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_4 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_3 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_3 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_4 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_108 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_108 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_108 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_2 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_1 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input2_mem1_0 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_0 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_1 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input2_mem1_2 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_106 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_106 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_106 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size4_mem_10 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size4_mem_9 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size4_mem_8 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size4_mem_7 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size4_mem_6 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size4_mem_5 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size4_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size4_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size4_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size4_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_size4_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_206 ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1368 ( .A ( copt_net_177 ) , 
-    .X ( copt_net_175 ) ) ;
+    .X ( copt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1369 ( .A ( copt_net_175 ) , 
-    .X ( copt_net_176 ) ) ;
+    .X ( copt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1370 ( .A ( ccff_head[0] ) , 
-    .X ( copt_net_177 ) ) ;
+    .X ( copt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1371 ( .A ( copt_net_176 ) , 
-    .X ( copt_net_178 ) ) ;
+    .X ( copt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1372 ( .A ( copt_net_178 ) , 
-    .X ( copt_net_179 ) ) ;
+    .X ( copt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1373 ( .A ( copt_net_179 ) , 
-    .X ( copt_net_180 ) ) ;
+    .X ( copt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1395 ( .A ( copt_net_180 ) , 
-    .X ( ropt_net_202 ) ) ;
+    .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1396 ( .A ( ropt_net_202 ) , 
-    .X ( ropt_net_203 ) ) ;
+    .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1397 ( .A ( ropt_net_205 ) , 
-    .X ( ropt_net_204 ) ) ;
+    .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1398 ( .A ( ropt_net_203 ) , 
-    .X ( ropt_net_205 ) ) ;
+    .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1399 ( .A ( ropt_net_204 ) , 
-    .X ( ropt_net_206 ) ) ;
+    .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input3_mem3 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_22 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__local_encoder2to3 ( addr , data , data_inv ) ;
+module sb_2__0__local_encoder2to3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__local_encoder2to3_22 ( addr , data , data_inv ) ;
+module sb_2__0__local_encoder2to3_22 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -34145,102 +45493,138 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_2__0__local_encoder2to3_22 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__0__local_encoder2to3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input3_mem3_22 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_21 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_20 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__local_encoder2to3_21 ( addr , data , data_inv ) ;
+module sb_2__0__local_encoder2to3_21 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__local_encoder2to3_20 ( addr , data , data_inv ) ;
+module sb_2__0__local_encoder2to3_20 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size4_10 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size4_10 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -34249,103 +45633,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__local_encoder2to3_20 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__0__local_encoder2to3_21 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input3_mem3_20 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input3_mem3_21 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_104 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_104 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_104 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_19 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_18 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__local_encoder2to3_19 ( addr , data , data_inv ) ;
+module sb_2__0__local_encoder2to3_19 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__local_encoder2to3_18 ( addr , data , data_inv ) ;
+module sb_2__0__local_encoder2to3_18 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size4_9 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size4_9 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -34354,103 +45775,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__local_encoder2to3_18 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__0__local_encoder2to3_19 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input3_mem3_18 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input3_mem3_19 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_102 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_102 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_102 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_17 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_16 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__local_encoder2to3_17 ( addr , data , data_inv ) ;
+module sb_2__0__local_encoder2to3_17 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__local_encoder2to3_16 ( addr , data , data_inv ) ;
+module sb_2__0__local_encoder2to3_16 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size4_8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -34459,103 +45917,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__local_encoder2to3_16 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__0__local_encoder2to3_17 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input3_mem3_16 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input3_mem3_17 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_100 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_100 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_100 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_15 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_14 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__local_encoder2to3_15 ( addr , data , data_inv ) ;
+module sb_2__0__local_encoder2to3_15 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__local_encoder2to3_14 ( addr , data , data_inv ) ;
+module sb_2__0__local_encoder2to3_14 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size4_7 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size4_7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -34564,103 +46059,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__local_encoder2to3_14 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__0__local_encoder2to3_15 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input3_mem3_14 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input3_mem3_15 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_98 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_98 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_98 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_13 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_12 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__local_encoder2to3_13 ( addr , data , data_inv ) ;
+module sb_2__0__local_encoder2to3_13 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__local_encoder2to3_12 ( addr , data , data_inv ) ;
+module sb_2__0__local_encoder2to3_12 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size4_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -34669,102 +46201,138 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__local_encoder2to3_12 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__0__local_encoder2to3_13 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input3_mem3_12 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input3_mem3_13 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_96 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_11 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_10 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__local_encoder2to3_11 ( addr , data , data_inv ) ;
+module sb_2__0__local_encoder2to3_11 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__local_encoder2to3_10 ( addr , data , data_inv ) ;
+module sb_2__0__local_encoder2to3_10 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size4_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -34773,103 +46341,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__local_encoder2to3_10 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__0__local_encoder2to3_11 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input3_mem3_10 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input3_mem3_11 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_95 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_95 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_95 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_9 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_8 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__local_encoder2to3_9 ( addr , data , data_inv ) ;
+module sb_2__0__local_encoder2to3_9 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__local_encoder2to3_8 ( addr , data , data_inv ) ;
+module sb_2__0__local_encoder2to3_8 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -34878,103 +46483,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__local_encoder2to3_8 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__0__local_encoder2to3_9 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input3_mem3_8 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input3_mem3_9 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_93 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_93 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_93 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_7 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_6 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__local_encoder2to3_7 ( addr , data , data_inv ) ;
+module sb_2__0__local_encoder2to3_7 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__local_encoder2to3_6 ( addr , data , data_inv ) ;
+module sb_2__0__local_encoder2to3_6 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -34983,103 +46625,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__0__local_encoder2to3_7 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input3_mem3_6 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input3_mem3_7 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_91 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_91 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_91 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_5 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_4 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__local_encoder2to3_5 ( addr , data , data_inv ) ;
+module sb_2__0__local_encoder2to3_5 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__local_encoder2to3_4 ( addr , data , data_inv ) ;
+module sb_2__0__local_encoder2to3_4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -35088,103 +46767,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__0__local_encoder2to3_5 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input3_mem3_4 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input3_mem3_5 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_89 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_89 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_89 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_3 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_2 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__local_encoder2to3_3 ( addr , data , data_inv ) ;
+module sb_2__0__local_encoder2to3_3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__local_encoder2to3_2 ( addr , data , data_inv ) ;
+module sb_2__0__local_encoder2to3_2 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -35193,103 +46909,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__0__local_encoder2to3_3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input3_mem3_2 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input3_mem3_3 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_87 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_87 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_87 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_1 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_2__0__mux_2level_tapbuf_basis_input3_mem3_0 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__local_encoder2to3_1 ( addr , data , data_inv ) ;
+module sb_2__0__local_encoder2to3_1 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__local_encoder2to3_0 ( addr , data , data_inv ) ;
+module sb_2__0__local_encoder2to3_0 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_2__0__mux_2level_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_2__0__mux_2level_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -35298,26 +47051,32 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_2__0__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__0__local_encoder2to3_1 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input3_mem3_0 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_basis_input3_mem3_1 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_85 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_85 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_85 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
@@ -35330,7 +47089,7 @@
     left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , 
     left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ , 
     left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_left_out , 
-    ccff_tail , pReset_W_in , pReset_N_out , prog_clk_0_N_in ) ;
+    ccff_tail , pReset_W_in , pReset_N_out , prog_clk_0_N_in , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:29] chany_top_in ;
 input  [0:0] top_left_grid_pin_44_ ;
@@ -35359,6 +47118,8 @@
 input  pReset_W_in ;
 output pReset_N_out ;
 input  prog_clk_0_N_in ;
+input  VDD ;
+input  VSS ;
 
 wire ropt_net_193 ;
 wire [0:0] prog_clk ;
@@ -35468,6 +47229,8 @@
 wire [0:0] mux_2level_tapbuf_size4_mem_7_ccff_tail ;
 wire [0:0] mux_2level_tapbuf_size4_mem_8_ccff_tail ;
 wire [0:0] mux_2level_tapbuf_size4_mem_9_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 assign prog_clk_0 = prog_clk[0] ;
 
@@ -35477,1841 +47240,2474 @@
     .sram ( mux_2level_tapbuf_size4_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
         SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( chany_top_out[0] ) , .p0 ( optlc_net_169 ) ) ;
+    .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_169 ) ) ;
 sb_2__0__mux_2level_tapbuf_size4_1 mux_top_track_2 (
     .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , 
         top_left_grid_pin_51_[0] , chanx_left_in[29] } ) ,
     .sram ( mux_2level_tapbuf_size4_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
         SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
-    .out ( chany_top_out[1] ) , .p0 ( optlc_net_174 ) ) ;
+    .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_174 ) ) ;
 sb_2__0__mux_2level_tapbuf_size4_2 mux_top_track_4 (
     .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , 
         top_right_grid_pin_1_[0] , chanx_left_in[28] } ) ,
     .sram ( mux_2level_tapbuf_size4_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
         SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
-    .out ( chany_top_out[2] ) , .p0 ( optlc_net_169 ) ) ;
+    .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_169 ) ) ;
 sb_2__0__mux_2level_tapbuf_size4_3 mux_top_track_6 (
     .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , 
         top_left_grid_pin_50_[0] , chanx_left_in[27] } ) ,
     .sram ( mux_2level_tapbuf_size4_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
         SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
-    .out ( chany_top_out[3] ) , .p0 ( optlc_net_169 ) ) ;
+    .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_169 ) ) ;
 sb_2__0__mux_2level_tapbuf_size4_4 mux_top_track_8 (
     .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , 
         top_left_grid_pin_51_[0] , chanx_left_in[26] } ) ,
     .sram ( mux_2level_tapbuf_size4_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
         SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
-    .out ( chany_top_out[4] ) , .p0 ( optlc_net_174 ) ) ;
+    .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_174 ) ) ;
 sb_2__0__mux_2level_tapbuf_size4_5 mux_top_track_10 (
     .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , 
         top_right_grid_pin_1_[0] , chanx_left_in[25] } ) ,
     .sram ( mux_2level_tapbuf_size4_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
         SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
-    .out ( chany_top_out[5] ) , .p0 ( optlc_net_174 ) ) ;
+    .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_174 ) ) ;
 sb_2__0__mux_2level_tapbuf_size4_6 mux_left_track_1 (
     .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , 
         left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) ,
     .sram ( mux_2level_tapbuf_size4_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
         SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
-    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_168 ) ) ;
+    .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_168 ) ) ;
 sb_2__0__mux_2level_tapbuf_size4_7 mux_left_track_3 (
     .in ( { chany_top_in[29] , left_bottom_grid_pin_3_[0] , 
         left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) ,
     .sram ( mux_2level_tapbuf_size4_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
         SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
-    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_168 ) ) ;
+    .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_168 ) ) ;
 sb_2__0__mux_2level_tapbuf_size4_8 mux_left_track_5 (
     .in ( { chany_top_in[28] , left_bottom_grid_pin_5_[0] , 
         left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) ,
     .sram ( mux_2level_tapbuf_size4_8_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
         SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
-    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_169 ) ) ;
+    .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_169 ) ) ;
 sb_2__0__mux_2level_tapbuf_size4_9 mux_left_track_7 (
     .in ( { chany_top_in[27] , left_bottom_grid_pin_1_[0] , 
         left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) ,
     .sram ( mux_2level_tapbuf_size4_9_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
         SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
-    .out ( chanx_left_out[3] ) , .p0 ( optlc_net_168 ) ) ;
+    .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_168 ) ) ;
 sb_2__0__mux_2level_tapbuf_size4_10 mux_left_track_9 (
     .in ( { chany_top_in[26] , left_bottom_grid_pin_3_[0] , 
         left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) ,
     .sram ( mux_2level_tapbuf_size4_10_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
         SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
-    .out ( chanx_left_out[4] ) , .p0 ( optlc_net_170 ) ) ;
+    .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_170 ) ) ;
 sb_2__0__mux_2level_tapbuf_size4 mux_left_track_11 (
     .in ( { chany_top_in[25] , left_bottom_grid_pin_5_[0] , 
         left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) ,
     .sram ( mux_2level_tapbuf_size4_11_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
         SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
-    .out ( chanx_left_out[5] ) , .p0 ( optlc_net_169 ) ) ;
+    .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_169 ) ) ;
 sb_2__0__mux_2level_tapbuf_size4_mem_0 mem_top_track_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size4_mem_1 mem_top_track_2 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size4_mem_2 mem_top_track_4 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size4_mem_3 mem_top_track_6 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size4_mem_4 mem_top_track_8 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size4_mem_5 mem_top_track_10 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_5_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_5_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size4_mem_6 mem_left_track_1 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_14_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_6_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_6_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size4_mem_7 mem_left_track_3 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_7_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_7_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_7_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size4_mem_8 mem_left_track_5 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_7_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_8_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_8_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_8_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size4_mem_9 mem_left_track_7 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_8_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_9_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_9_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_9_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size4_mem_10 mem_left_track_9 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_9_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_10_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_10_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_10_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size4_mem mem_left_track_11 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_10_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_11_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_11_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_11_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size3_0 mux_top_track_12 (
     .in ( { top_left_grid_pin_44_[0] , top_right_grid_pin_1_[0] , 
         chanx_left_in[24] } ) ,
     .sram ( mux_2level_tapbuf_size3_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
-    .out ( chany_top_out[6] ) , .p0 ( optlc_net_172 ) ) ;
+    .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_172 ) ) ;
 sb_2__0__mux_2level_tapbuf_size3_1 mux_top_track_44 (
     .in ( { top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , 
         chanx_left_in[8] } ) ,
     .sram ( mux_2level_tapbuf_size3_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
-    .out ( chany_top_out[22] ) , .p0 ( optlc_net_174 ) ) ;
+    .out ( chany_top_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_174 ) ) ;
 sb_2__0__mux_2level_tapbuf_size3_2 mux_left_track_13 (
     .in ( { chany_top_in[24] , left_bottom_grid_pin_1_[0] , 
         left_bottom_grid_pin_17_[0] } ) ,
     .sram ( mux_2level_tapbuf_size3_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) ,
-    .out ( chanx_left_out[6] ) , .p0 ( optlc_net_172 ) ) ;
+    .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_172 ) ) ;
 sb_2__0__mux_2level_tapbuf_size3_3 mux_left_track_29 (
     .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] , 
         left_bottom_grid_pin_17_[0] } ) ,
     .sram ( mux_2level_tapbuf_size3_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
-    .out ( chanx_left_out[14] ) , .p0 ( optlc_net_169 ) ) ;
+    .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_169 ) ) ;
 sb_2__0__mux_2level_tapbuf_size3 mux_left_track_45 (
     .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] , 
         left_bottom_grid_pin_17_[0] } ) ,
     .sram ( mux_2level_tapbuf_size3_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) ,
-    .out ( chanx_left_out[22] ) , .p0 ( optlc_net_169 ) ) ;
+    .out ( chanx_left_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_169 ) ) ;
 sb_2__0__mux_2level_tapbuf_size3_mem_0 mem_top_track_12 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size3_mem_1 mem_top_track_44 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_11_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size3_mem_2 mem_left_track_13 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_11_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size3_mem_3 mem_left_track_29 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_21_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size3_mem mem_left_track_45 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_28_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_0 mux_top_track_14 (
     .in ( { top_left_grid_pin_45_[0] , chanx_left_in[23] } ) ,
     .sram ( mux_2level_tapbuf_size2_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
-    .out ( chany_top_out[7] ) , .p0 ( optlc_net_172 ) ) ;
+    .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_172 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_1 mux_top_track_16 (
     .in ( { top_left_grid_pin_46_[0] , chanx_left_in[22] } ) ,
     .sram ( mux_2level_tapbuf_size2_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
-    .out ( chany_top_out[8] ) , .p0 ( optlc_net_172 ) ) ;
+    .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_172 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_2 mux_top_track_18 (
     .in ( { top_left_grid_pin_47_[0] , chanx_left_in[21] } ) ,
     .sram ( mux_2level_tapbuf_size2_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
-    .out ( chany_top_out[9] ) , .p0 ( optlc_net_173 ) ) ;
+    .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_173 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_3 mux_top_track_20 (
     .in ( { top_left_grid_pin_48_[0] , chanx_left_in[20] } ) ,
     .sram ( mux_2level_tapbuf_size2_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) ,
-    .out ( chany_top_out[10] ) , .p0 ( optlc_net_173 ) ) ;
+    .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_173 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_4 mux_top_track_22 (
     .in ( { top_left_grid_pin_49_[0] , chanx_left_in[19] } ) ,
     .sram ( mux_2level_tapbuf_size2_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
-    .out ( chany_top_out[11] ) , .p0 ( optlc_net_173 ) ) ;
+    .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_173 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_5 mux_top_track_24 (
     .in ( { top_left_grid_pin_50_[0] , chanx_left_in[18] } ) ,
     .sram ( mux_2level_tapbuf_size2_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
-    .out ( chany_top_out[12] ) , .p0 ( optlc_net_173 ) ) ;
+    .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_173 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_6 mux_top_track_26 (
     .in ( { top_left_grid_pin_51_[0] , chanx_left_in[17] } ) ,
     .sram ( mux_2level_tapbuf_size2_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
-    .out ( chany_top_out[13] ) , .p0 ( optlc_net_173 ) ) ;
+    .out ( chany_top_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_173 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_7 mux_top_track_28 (
     .in ( { top_right_grid_pin_1_[0] , chanx_left_in[16] } ) ,
     .sram ( mux_2level_tapbuf_size2_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
-    .out ( chany_top_out[14] ) , .p0 ( optlc_net_173 ) ) ;
+    .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_173 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_8 mux_top_track_36 (
     .in ( { top_left_grid_pin_44_[0] , chanx_left_in[12] } ) ,
     .sram ( mux_2level_tapbuf_size2_8_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
-    .out ( chany_top_out[18] ) , .p0 ( optlc_net_172 ) ) ;
+    .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_172 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_9 mux_top_track_38 (
     .in ( { top_left_grid_pin_45_[0] , chanx_left_in[11] } ) ,
     .sram ( mux_2level_tapbuf_size2_9_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
-    .out ( chany_top_out[19] ) , .p0 ( optlc_net_172 ) ) ;
+    .out ( chany_top_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_172 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_10 mux_top_track_40 (
     .in ( { top_left_grid_pin_46_[0] , chanx_left_in[10] } ) ,
     .sram ( mux_2level_tapbuf_size2_10_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
-    .out ( chany_top_out[20] ) , .p0 ( optlc_net_172 ) ) ;
+    .out ( chany_top_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_172 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_11 mux_top_track_42 (
     .in ( { top_left_grid_pin_47_[0] , chanx_left_in[9] } ) ,
     .sram ( mux_2level_tapbuf_size2_11_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
-    .out ( chany_top_out[21] ) , .p0 ( optlc_net_172 ) ) ;
+    .out ( chany_top_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_172 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_12 mux_top_track_46 (
     .in ( { top_left_grid_pin_49_[0] , chanx_left_in[7] } ) ,
     .sram ( mux_2level_tapbuf_size2_12_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
-    .out ( chany_top_out[23] ) , .p0 ( optlc_net_172 ) ) ;
+    .out ( chany_top_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_172 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_13 mux_top_track_48 (
     .in ( { top_left_grid_pin_50_[0] , chanx_left_in[6] } ) ,
     .sram ( mux_2level_tapbuf_size2_13_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) ,
-    .out ( chany_top_out[24] ) , .p0 ( optlc_net_169 ) ) ;
+    .out ( chany_top_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_169 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_14 mux_top_track_50 (
     .in ( { top_left_grid_pin_51_[0] , chanx_left_in[5] } ) ,
     .sram ( mux_2level_tapbuf_size2_14_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
-    .out ( chany_top_out[25] ) , .p0 ( optlc_net_172 ) ) ;
+    .out ( chany_top_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_172 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_15 mux_left_track_15 (
     .in ( { chany_top_in[23] , left_bottom_grid_pin_3_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_15_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) ,
-    .out ( chanx_left_out[7] ) , .p0 ( optlc_net_173 ) ) ;
+    .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_173 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_16 mux_left_track_17 (
     .in ( { chany_top_in[22] , left_bottom_grid_pin_5_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_16_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
-    .out ( chanx_left_out[8] ) , .p0 ( optlc_net_173 ) ) ;
+    .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_173 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_17 mux_left_track_19 (
     .in ( { chany_top_in[21] , left_bottom_grid_pin_7_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_17_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) ,
-    .out ( chanx_left_out[9] ) , .p0 ( optlc_net_171 ) ) ;
+    .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_171 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_18 mux_left_track_21 (
     .in ( { chany_top_in[20] , left_bottom_grid_pin_9_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_18_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
-    .out ( chanx_left_out[10] ) , .p0 ( optlc_net_171 ) ) ;
+    .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_171 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_19 mux_left_track_23 (
     .in ( { chany_top_in[19] , left_bottom_grid_pin_11_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_19_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) ,
-    .out ( chanx_left_out[11] ) , .p0 ( optlc_net_171 ) ) ;
+    .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_171 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_20 mux_left_track_25 (
     .in ( { chany_top_in[18] , left_bottom_grid_pin_13_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_20_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) ,
-    .out ( chanx_left_out[12] ) , .p0 ( optlc_net_170 ) ) ;
+    .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_170 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_21 mux_left_track_27 (
     .in ( { chany_top_in[17] , left_bottom_grid_pin_15_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_21_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) ,
-    .out ( chanx_left_out[13] ) , .p0 ( optlc_net_170 ) ) ;
+    .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_170 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_22 mux_left_track_31 (
     .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_22_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) ,
-    .out ( chanx_left_out[15] ) , .p0 ( optlc_net_170 ) ) ;
+    .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_170 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_23 mux_left_track_33 (
     .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_23_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) ,
-    .out ( chanx_left_out[16] ) , .p0 ( optlc_net_173 ) ) ;
+    .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_173 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_24 mux_left_track_35 (
     .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_24_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) ,
-    .out ( chanx_left_out[17] ) , .p0 ( optlc_net_171 ) ) ;
+    .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_171 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_25 mux_left_track_37 (
     .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_25_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) ,
-    .out ( chanx_left_out[18] ) , .p0 ( optlc_net_171 ) ) ;
+    .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_171 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_26 mux_left_track_39 (
     .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_26_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) ,
-    .out ( chanx_left_out[19] ) , .p0 ( optlc_net_171 ) ) ;
+    .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_171 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_27 mux_left_track_41 (
     .in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_27_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) ,
-    .out ( chanx_left_out[20] ) , .p0 ( optlc_net_170 ) ) ;
+    .out ( chanx_left_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_170 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_28 mux_left_track_43 (
     .in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_28_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) ,
-    .out ( chanx_left_out[21] ) , .p0 ( optlc_net_170 ) ) ;
+    .out ( chanx_left_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_170 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_29 mux_left_track_47 (
     .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_29_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) ,
-    .out ( chanx_left_out[23] ) , .p0 ( optlc_net_173 ) ) ;
+    .out ( chanx_left_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_173 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_30 mux_left_track_49 (
     .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_30_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) ,
-    .out ( chanx_left_out[24] ) , .p0 ( optlc_net_173 ) ) ;
+    .out ( chanx_left_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_173 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_31 mux_left_track_51 (
     .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_31_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) ,
-    .out ( chanx_left_out[25] ) , .p0 ( optlc_net_173 ) ) ;
+    .out ( chanx_left_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_173 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_32 mux_left_track_53 (
     .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_32_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) ,
-    .out ( chanx_left_out[26] ) , .p0 ( optlc_net_171 ) ) ;
+    .out ( chanx_left_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_171 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_33 mux_left_track_55 (
     .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_33_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) ,
-    .out ( chanx_left_out[27] ) , .p0 ( optlc_net_173 ) ) ;
+    .out ( chanx_left_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_173 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_34 mux_left_track_57 (
     .in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_34_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) ,
-    .out ( chanx_left_out[28] ) , .p0 ( optlc_net_173 ) ) ;
+    .out ( chanx_left_out[28] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_173 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2 mux_left_track_59 (
     .in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_35_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) ,
-    .out ( chanx_left_out[29] ) , .p0 ( optlc_net_172 ) ) ;
+    .out ( chanx_left_out[29] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_172 ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_0 mem_top_track_14 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_1 mem_top_track_16 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_2 mem_top_track_18 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_3 mem_top_track_20 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_4 mem_top_track_22 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_5 mem_top_track_24 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_5_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_5_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_6 mem_top_track_26 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_6_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_6_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_7 mem_top_track_28 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_7_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_7_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_8 mem_top_track_36 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_8_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_8_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_8_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_9 mem_top_track_38 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_8_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_9_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_9_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_9_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_10 mem_top_track_40 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_9_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_10_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_10_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_10_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_11 mem_top_track_42 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_10_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_11_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_11_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_11_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_12 mem_top_track_46 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_12_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_12_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_12_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_13 mem_top_track_48 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_12_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_13_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_13_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_13_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_14 mem_top_track_50 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_13_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_14_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_14_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_14_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_15 mem_left_track_15 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_15_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_15_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_15_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_16 mem_left_track_17 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_15_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_16_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_16_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_16_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_17 mem_left_track_19 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_16_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_17_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_17_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_17_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_18 mem_left_track_21 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_17_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_18_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_18_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_18_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_19 mem_left_track_23 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_18_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_19_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_19_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_19_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_20 mem_left_track_25 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_19_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_20_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_20_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_20_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_21 mem_left_track_27 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_20_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_21_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_21_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_21_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_22 mem_left_track_31 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_22_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_22_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_22_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_23 mem_left_track_33 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_22_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_23_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_23_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_23_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_24 mem_left_track_35 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_23_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_24_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_24_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_24_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_25 mem_left_track_37 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_24_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_25_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_25_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_25_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_26 mem_left_track_39 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_25_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_26_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_26_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_26_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_27 mem_left_track_41 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_26_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_27_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_27_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_27_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_28 mem_left_track_43 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_27_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_28_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_28_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_28_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_29 mem_left_track_47 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_29_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_29_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_29_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_30 mem_left_track_49 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_29_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_30_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_30_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_30_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_31 mem_left_track_51 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_30_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_31_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_31_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_31_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_32 mem_left_track_53 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_31_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_32_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_32_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_32_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_33 mem_left_track_55 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_32_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_33_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_33_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_33_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem_34 mem_left_track_57 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_33_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_34_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_34_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_34_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_2__0__mux_2level_tapbuf_size2_mem mem_left_track_59 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_34_ccff_tail ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_tapbuf_size2_35_sram ) ) ;
-sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_tapbuf_size2_35_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_170 ( .LO ( SYNOPSYS_UNCONNECTED_131 ) , 
-    .HI ( optlc_net_168 ) ) ;
+    .HI ( optlc_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
-    .X ( prog_clk[0] ) ) ;
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( chanx_left_in[1] ) , 
-    .X ( chany_top_out[29] ) ) ;
+    .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( chanx_left_in[2] ) , 
-    .X ( chany_top_out[28] ) ) ;
+    .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[3] ) , 
-    .X ( chany_top_out[27] ) ) ;
+    .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_left_in[4] ) , 
-    .X ( chany_top_out[26] ) ) ;
+    .X ( chany_top_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_left_in[13] ) , 
-    .X ( chany_top_out[17] ) ) ;
+    .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_83__82 ( .A ( chanx_left_in[14] ) , 
-    .X ( chany_top_out[16] ) ) ;
+    .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_84__83 ( .A ( chanx_left_in[15] ) , 
-    .X ( ropt_net_193 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( pReset_N_out ) ) ;
-sky130_fd_sc_hd__inv_1 BINV_R_167 ( .A ( pReset_W_in ) , .Y ( BUF_net_167 ) ) ;
+    .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( pReset_N_out ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_167 ( .A ( pReset_W_in ) , .Y ( BUF_net_167 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_173 ( .LO ( SYNOPSYS_UNCONNECTED_132 ) , 
-    .HI ( optlc_net_169 ) ) ;
+    .HI ( optlc_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) , 
-    .HI ( optlc_net_170 ) ) ;
+    .HI ( optlc_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) , 
-    .HI ( optlc_net_171 ) ) ;
+    .HI ( optlc_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_180 ( .LO ( SYNOPSYS_UNCONNECTED_135 ) , 
-    .HI ( optlc_net_172 ) ) ;
+    .HI ( optlc_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_182 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , 
-    .HI ( optlc_net_173 ) ) ;
+    .HI ( optlc_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_184 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , 
-    .HI ( optlc_net_174 ) ) ;
+    .HI ( optlc_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1386 ( .A ( ropt_net_193 ) , 
-    .X ( chany_top_out[15] ) ) ;
+    .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_106__105 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size2_mem_9 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_105__104 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size2_mem_8 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_104__103 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size2_mem_7 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_103__102 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size2_mem_6 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_102__101 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size2_mem_5 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_101__100 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size2_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_100__99 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_100__99 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size2_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_99__98 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_99__98 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size2_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_98__97 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_98__97 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size2_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_97__96 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_97__96 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size2_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_96__95 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_96__95 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_32 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_32 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_31 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_30 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_30 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_31 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_204 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_29 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_28 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_28 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_29 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_27 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_26 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_26 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_27 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_25 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_24 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_24 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_25 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_203 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_23 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_22 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_22 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_23 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_201 ( .A ( BUF_net_202 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_201 ( .A ( BUF_net_202 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_202 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_202 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_202 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_21 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_20 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_20 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_21 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_199 ( .A ( BUF_net_200 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_199 ( .A ( BUF_net_200 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_200 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_200 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_200 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_19 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_18 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_18 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_19 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_17 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_16 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_16 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_17 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_197 ( .A ( BUF_net_198 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_197 ( .A ( BUF_net_198 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_198 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_198 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_198 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_15 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_14 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_14 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_15 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_196 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_13 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_12 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_13 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_95__94 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_95__94 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size3_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_94__93 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_94__93 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size3_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_93__92 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_93__92 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size3_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_92__91 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_92__91 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_11 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_10 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_9 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_9 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_10 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_194 ( .A ( BUF_net_195 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_194 ( .A ( BUF_net_195 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_195 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_195 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_195 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_8 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_7 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_6 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_7 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_8 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_192 ( .A ( BUF_net_193 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_192 ( .A ( BUF_net_193 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_193 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_193 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_193 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_5 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_4 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_3 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_3 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_4 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_190 ( .A ( BUF_net_191 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_190 ( .A ( BUF_net_191 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_191 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_191 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_191 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_2 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_1 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem1_0 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_0 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_1 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem1_2 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_189 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_91__90 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_91__90 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size6_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_90__89 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_90__89 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size6_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_89__88 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_89__88 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size6_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_88__87 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_88__87 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_75 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_74 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_87__86 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_87__86 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_56 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_56 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_86__85 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_86__85 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -37321,126 +49717,169 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__local_encoder2to3_56 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_74 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_75 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_187 ( .A ( BUF_net_188 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_187 ( .A ( BUF_net_188 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_188 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_188 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_188 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_73 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_72 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_71 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_55 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_55 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_85__84 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_85__84 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_54 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_54 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_84__83 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_84__83 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -37450,126 +49889,169 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__local_encoder2to3_54 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3_55 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_71 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_72 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_73 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_185 ( .A ( BUF_net_186 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_185 ( .A ( BUF_net_186 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_186 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_186 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_186 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_70 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_69 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_68 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_53 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_53 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_83__82 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_83__82 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_52 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_52 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_82__81 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_82__81 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -37579,126 +50061,169 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__local_encoder2to3_52 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3_53 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_68 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_69 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_70 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_183 ( .A ( BUF_net_184 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_183 ( .A ( BUF_net_184 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_184 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_184 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_184 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_67 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_66 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_65 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_51 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_51 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_81__80 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_81__80 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_50 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_50 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_80__79 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_80__79 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -37708,268 +50233,386 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__local_encoder2to3_50 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3_51 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_65 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_66 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_67 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_181 ( .A ( BUF_net_182 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_181 ( .A ( BUF_net_182 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_182 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_182 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_182 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_79__78 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_79__78 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size4_mem_6 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_78__77 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_78__77 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size4_mem_5 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_77__76 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_77__76 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size4_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_76__75 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_76__75 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size4_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_75__74 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_75__74 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size4_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_74__73 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_74__73 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size4_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_73__72 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_73__72 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size4_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_72__71 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_72__71 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_64 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_63 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_49 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_49 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_71__70 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_71__70 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_48 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_48 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -37978,102 +50621,138 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__2__local_encoder2to3_48 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3_49 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_63 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_64 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_62 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_61 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_47 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_47 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_69__68 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_69__68 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_46 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_46 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_68__67 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_68__67 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size4_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -38082,102 +50761,138 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__local_encoder2to3_46 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3_47 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_61 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_62 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_180 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_60 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_59 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_45 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_45 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_67__66 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_67__66 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_44 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_44 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_66__65 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_66__65 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size4_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -38186,103 +50901,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__local_encoder2to3_44 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3_45 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_59 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_60 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_178 ( .A ( BUF_net_179 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_178 ( .A ( BUF_net_179 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_179 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_179 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_179 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_58 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_57 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_43 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_43 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_65__64 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_65__64 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_42 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_42 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_64__63 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_64__63 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -38291,102 +51043,138 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__local_encoder2to3_42 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3_43 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_57 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_58 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_177 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_56 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_55 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_41 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_41 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_63__62 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_63__62 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_40 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_40 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_62__61 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_62__61 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -38395,102 +51183,138 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__2__local_encoder2to3_40 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3_41 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_55 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_56 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_54 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_53 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_39 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_39 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_61__60 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_61__60 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_38 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_38 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_60__59 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_60__59 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -38499,103 +51323,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__local_encoder2to3_38 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3_39 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_53 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_54 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_175 ( .A ( BUF_net_176 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_175 ( .A ( BUF_net_176 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_176 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_176 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_176 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_52 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_51 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_37 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_37 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_36 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_36 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -38604,103 +51465,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__local_encoder2to3_36 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3_37 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_51 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_52 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_173 ( .A ( BUF_net_174 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_173 ( .A ( BUF_net_174 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_174 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_174 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_174 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_50 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_49 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_35 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_35 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_57__56 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_57__56 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_34 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_34 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_56__55 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_56__55 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -38709,219 +51607,310 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__2__local_encoder2to3_34 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3_35 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_49 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_50 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size5_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size5_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size5_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size5_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size5_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem2 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_48 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_47 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_33 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_33 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_32 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_32 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -38931,125 +51920,168 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__local_encoder2to3_32 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3_33 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_47 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_48 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem2 mux_l1_in_1_ ( .in ( in[3:4] ) , 
     .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_171 ( .A ( BUF_net_172 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_171 ( .A ( BUF_net_172 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_172 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_172 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_172 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_14 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_46 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_45 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_31 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_31 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_30 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_30 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size5_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -39059,125 +52091,168 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__local_encoder2to3_30 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3_31 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_45 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_46 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem2_14 mux_l1_in_1_ ( 
     .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_169 ( .A ( BUF_net_170 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_169 ( .A ( BUF_net_170 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_170 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_170 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_170 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_13 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_44 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_43 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_29 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_29 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_28 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_28 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -39187,124 +52262,166 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__local_encoder2to3_28 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3_29 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_43 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_44 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem2_13 mux_l1_in_1_ ( 
     .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_168 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_12 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_42 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_41 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_27 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_27 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_26 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_26 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -39314,125 +52431,168 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__local_encoder2to3_26 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3_27 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_41 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_42 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem2_12 mux_l1_in_1_ ( 
     .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_167 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_167 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_167 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_11 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_40 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_39 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_25 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_25 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_24 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_24 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -39442,186 +52602,256 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__local_encoder2to3_24 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3_25 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_39 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_40 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem2_11 mux_l1_in_1_ ( 
     .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_165 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_165 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_165 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size9_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size9_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input4_mem4 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input4_mem4_10 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input4_mem4_9 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to4 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to4_6 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to4_6 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size9 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:8] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -39631,149 +52861,198 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
     .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , 
-    .X ( aps_rename_506_ ) ) ;
+    .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__2__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to4 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input4_mem4_9 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input4_mem4_10 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input4_mem4 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , in[8] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_163 ( .A ( aps_rename_506_ ) , 
-    .Y ( BUF_net_163 ) ) ;
+    .Y ( BUF_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input4_mem4_8 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input4_mem4_7 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input4_mem4_6 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to4_5 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to4_5 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to4_4 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to4_4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:8] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -39783,202 +53062,276 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__2__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to4_5 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input4_mem4_6 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input4_mem4_7 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input4_mem4_8 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , in[8] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size10_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_10 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input4_mem4_5 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input4_mem4_4 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input4_mem4_3 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to4_3 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to4_3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to4_2 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to4_2 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size10 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -39989,24 +53342,28 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
     .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , 
-    .X ( aps_rename_505_ ) ) ;
+    .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__2__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to4_3 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input4_mem4_3 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input4_mem4_4 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input4_mem4_5 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -40014,146 +53371,197 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem2_10 mux_l1_in_2_ ( 
     .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_161 ( .A ( aps_rename_505_ ) , 
-    .Y ( BUF_net_161 ) ) ;
+    .Y ( BUF_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_9 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input4_mem4_2 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input4_mem4_1 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input4_mem4_0 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to4_1 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to4_1 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to4_0 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to4_0 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size10_0 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -40164,23 +53572,28 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__2__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to4_1 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input4_mem4_0 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input4_mem4_1 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input4_mem4_2 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -40188,184 +53601,257 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem2_9 mux_l1_in_2_ ( 
     .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size8_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size8_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size8_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_38 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_37 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_36 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_35 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_23 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_23 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_22 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_22 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:7] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -40376,149 +53862,198 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__local_encoder2to3_22 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3_23 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_35 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_36 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_37 mux_l1_in_2_ (
     .in ( { in[6] , in[7] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_38 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_2_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_159 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_159 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_159 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_34 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_33 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_32 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_31 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_21 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_21 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_20 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_20 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:7] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -40529,148 +54064,196 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__2__local_encoder2to3_20 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3_21 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_31 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_32 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_33 mux_l1_in_2_ (
     .in ( { in[6] , in[7] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_34 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_2_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_30 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_29 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_28 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_27 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_19 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_19 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_18 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_18 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:7] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -40681,353 +54264,491 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__2__local_encoder2to3_18 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3_19 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_27 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_28 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_29 mux_l1_in_2_ (
     .in ( { in[6] , in[7] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_30 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_2_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size7_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size7_mem_7 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size7_mem_6 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size7_mem_5 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size7_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size7_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size7_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size7_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_size7_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_242 ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1436 ( .A ( copt_net_220 ) , 
-    .X ( copt_net_219 ) ) ;
+    .X ( copt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1437 ( .A ( copt_net_221 ) , 
-    .X ( copt_net_220 ) ) ;
+    .X ( copt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1438 ( .A ( copt_net_222 ) , 
-    .X ( copt_net_221 ) ) ;
+    .X ( copt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1439 ( .A ( copt_net_223 ) , 
-    .X ( copt_net_222 ) ) ;
+    .X ( copt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1440 ( .A ( copt_net_224 ) , 
-    .X ( copt_net_223 ) ) ;
+    .X ( copt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1441 ( .A ( ccff_head[0] ) , 
-    .X ( copt_net_224 ) ) ;
+    .X ( copt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1467 ( .A ( copt_net_219 ) , 
-    .X ( ropt_net_236 ) ) ;
+    .X ( ropt_net_236 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1468 ( .A ( ropt_net_236 ) , 
-    .X ( ropt_net_237 ) ) ;
+    .X ( ropt_net_237 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1469 ( .A ( ropt_net_240 ) , 
-    .X ( ropt_net_238 ) ) ;
+    .X ( ropt_net_238 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1470 ( .A ( ropt_net_237 ) , 
-    .X ( ropt_net_239 ) ) ;
+    .X ( ropt_net_239 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1471 ( .A ( ropt_net_239 ) , 
-    .X ( ropt_net_240 ) ) ;
+    .X ( ropt_net_240 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1472 ( .A ( ropt_net_238 ) , 
-    .X ( ropt_net_241 ) ) ;
+    .X ( ropt_net_241 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1473 ( .A ( ropt_net_241 ) , 
-    .X ( ropt_net_242 ) ) ;
+    .X ( ropt_net_242 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_8 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_26 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_25 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_24 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_17 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_17 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_16 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_16 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:6] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -41038,147 +54759,195 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__2__local_encoder2to3_16 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3_17 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_24 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_25 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_26 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem2_8 mux_l1_in_2_ (
     .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_7 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_23 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_22 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_21 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_15 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_15 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_14 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_14 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size7_7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:6] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -41189,147 +54958,195 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__2__local_encoder2to3_14 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3_15 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_21 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_22 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_23 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem2_7 mux_l1_in_2_ (
     .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_6 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_20 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_19 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_18 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_13 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_13 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_12 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_12 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size7_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:6] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -41340,148 +55157,197 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__local_encoder2to3_12 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3_13 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_18 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_19 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_20 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem2_6 mux_l1_in_2_ (
     .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_157 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_157 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_157 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_5 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_17 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_16 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_15 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_11 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_11 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_10 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_10 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:6] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -41492,147 +55358,195 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__local_encoder2to3_10 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3_11 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_15 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_16 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_17 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem2_5 mux_l1_in_2_ (
     .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_155 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_4 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_14 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_13 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_12 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_9 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_9 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_8 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_8 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:6] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -41643,148 +55557,197 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__local_encoder2to3_8 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3_9 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_12 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_13 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_14 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem2_4 mux_l1_in_2_ (
     .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_153 ( .A ( BUF_net_154 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_153 ( .A ( BUF_net_154 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_154 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_154 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_154 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_3 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_11 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_10 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_9 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_7 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_7 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_6 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_6 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:6] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -41795,148 +55758,197 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3_7 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_9 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_10 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_11 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem2_3 mux_l1_in_2_ (
     .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_151 ( .A ( BUF_net_152 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_151 ( .A ( BUF_net_152 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_152 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_152 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_152 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_2 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_8 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_7 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_6 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_5 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_5 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_4 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:6] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -41947,148 +55959,197 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3_5 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_6 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_7 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_8 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem2_2 mux_l1_in_2_ (
     .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_208 ( .A ( BUF_net_209 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_208 ( .A ( BUF_net_209 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_209 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_209 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_209 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_1 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_5 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_4 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_3 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_3 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_2 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_2 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:6] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -42099,147 +56160,195 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__2__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3_3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_3 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_4 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_5 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem2_1 mux_l1_in_2_ (
     .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input2_mem2_0 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_2 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_1 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__2__mux_2level_tapbuf_basis_input3_mem3_0 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_1 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_1 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__local_encoder2to3_0 ( addr , data , data_inv ) ;
+module sb_1__2__local_encoder2to3_0 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__2__mux_2level_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__2__mux_2level_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:6] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -42250,36 +56359,44 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__2__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__local_encoder2to3_1 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_0 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_1 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input3_mem3_2 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_basis_input2_mem2_0 mux_l1_in_2_ (
     .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_150 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_150 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_150 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
@@ -42299,7 +56416,7 @@
     left_bottom_grid_pin_43_ , ccff_head , chanx_right_out , 
     chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_BOT , SC_OUT_BOT , 
     pReset_S_in , pReset_E_in , pReset_W_in , pReset_W_out , pReset_E_out , 
-    prog_clk_0_S_in ) ;
+    prog_clk_0_S_in , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:29] chanx_right_in ;
 input  [0:0] right_top_grid_pin_1_ ;
@@ -42343,6 +56460,8 @@
 output pReset_W_out ;
 output pReset_E_out ;
 input  prog_clk_0_S_in ;
+input  VDD ;
+input  VSS ;
 
 wire ropt_net_234 ;
 wire ropt_net_233 ;
@@ -42446,6 +56565,8 @@
 wire [0:3] mux_2level_tapbuf_size9_1_sram ;
 wire [0:0] mux_2level_tapbuf_size9_mem_0_ccff_tail ;
 wire [0:0] mux_2level_tapbuf_size9_mem_1_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 assign pReset_E_in = pReset_S_in ;
 assign pReset_E_in = pReset_W_in ;
@@ -42458,7 +56579,8 @@
     .sram ( mux_2level_tapbuf_size7_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
         SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_213 ) ) ;
+    .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_213 ) ) ;
 sb_1__2__mux_2level_tapbuf_size7_1 mux_right_track_2 (
     .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , 
         right_bottom_grid_pin_42_[0] , chany_bottom_in[8] , 
@@ -42466,7 +56588,8 @@
     .sram ( mux_2level_tapbuf_size7_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
         SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
-    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_213 ) ) ;
+    .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_213 ) ) ;
 sb_1__2__mux_2level_tapbuf_size7_2 mux_right_track_12 (
     .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , 
         chany_bottom_in[4] , chany_bottom_in[15] , chany_bottom_in[26] , 
@@ -42474,7 +56597,8 @@
     .sram ( mux_2level_tapbuf_size7_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
         SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
-    .out ( chanx_right_out[6] ) , .p0 ( optlc_net_212 ) ) ;
+    .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_212 ) ) ;
 sb_1__2__mux_2level_tapbuf_size7_3 mux_right_track_20 (
     .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] , 
         chany_bottom_in[3] , chany_bottom_in[14] , chany_bottom_in[25] , 
@@ -42482,7 +56606,8 @@
     .sram ( mux_2level_tapbuf_size7_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
         SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
-    .out ( chanx_right_out[10] ) , .p0 ( optlc_net_212 ) ) ;
+    .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_212 ) ) ;
 sb_1__2__mux_2level_tapbuf_size7_4 mux_right_track_28 (
     .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_43_[0] , 
         chany_bottom_in[2] , chany_bottom_in[13] , chany_bottom_in[24] , 
@@ -42490,7 +56615,8 @@
     .sram ( mux_2level_tapbuf_size7_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
         SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
-    .out ( chanx_right_out[14] ) , .p0 ( optlc_net_215 ) ) ;
+    .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_215 ) ) ;
 sb_1__2__mux_2level_tapbuf_size7_5 mux_left_track_1 (
     .in ( { chanx_left_out[4] , chanx_left_out[20] , chany_bottom_in[10] , 
         chany_bottom_in[21] , left_top_grid_pin_1_[0] , 
@@ -42498,7 +56624,8 @@
     .sram ( mux_2level_tapbuf_size7_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
         SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
-    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_216 ) ) ;
+    .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_216 ) ) ;
 sb_1__2__mux_2level_tapbuf_size7_6 mux_left_track_13 (
     .in ( { chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[4] , 
         chany_bottom_in[15] , chany_bottom_in[26] , left_top_grid_pin_1_[0] , 
@@ -42506,7 +56633,8 @@
     .sram ( mux_2level_tapbuf_size7_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
         SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
-    .out ( chanx_left_out[6] ) , .p0 ( optlc_net_216 ) ) ;
+    .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_216 ) ) ;
 sb_1__2__mux_2level_tapbuf_size7_7 mux_left_track_21 (
     .in ( { chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[5] , 
         chany_bottom_in[16] , chany_bottom_in[27] , 
@@ -42514,7 +56642,8 @@
     .sram ( mux_2level_tapbuf_size7_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
         SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
-    .out ( chanx_left_out[10] ) , .p0 ( optlc_net_210 ) ) ;
+    .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_210 ) ) ;
 sb_1__2__mux_2level_tapbuf_size7 mux_left_track_29 (
     .in ( { chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[6] , 
         chany_bottom_in[17] , chany_bottom_in[28] , 
@@ -42522,51 +56651,61 @@
     .sram ( mux_2level_tapbuf_size7_8_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
         SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
-    .out ( chanx_left_out[14] ) , .p0 ( optlc_net_210 ) ) ;
+    .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_210 ) ) ;
 sb_1__2__mux_2level_tapbuf_size7_mem_0 mem_right_track_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
     .ccff_tail ( mux_2level_tapbuf_size7_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size7_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size7_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size7_mem_1 mem_right_track_2 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size7_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size7_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size7_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size7_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size7_mem_2 mem_right_track_12 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size9_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size7_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size7_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size7_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size7_mem_3 mem_right_track_20 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size7_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size7_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size7_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size7_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size7_mem_4 mem_right_track_28 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size7_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size7_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size7_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size7_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size7_mem_5 mem_left_track_1 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_10_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size7_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size7_5_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size7_5_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size7_mem_6 mem_left_track_13 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size9_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size7_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size7_6_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size7_6_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size7_mem_7 mem_left_track_21 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size7_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size7_mem_7_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size7_7_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size7_7_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size7_mem mem_left_track_29 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size7_mem_7_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size7_mem_8_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size7_8_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size7_8_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size8_0 mux_right_track_4 (
     .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , 
         right_bottom_grid_pin_43_[0] , chany_bottom_in[7] , 
@@ -42575,7 +56714,8 @@
     .sram ( mux_2level_tapbuf_size8_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
         SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
-    .out ( chanx_right_out[2] ) , .p0 ( optlc_net_213 ) ) ;
+    .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_213 ) ) ;
 sb_1__2__mux_2level_tapbuf_size8_1 mux_left_track_3 (
     .in ( { chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] , 
         chany_bottom_in[11] , chany_bottom_in[22] , 
@@ -42584,7 +56724,8 @@
     .sram ( mux_2level_tapbuf_size8_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
         SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
-    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_216 ) ) ;
+    .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_216 ) ) ;
 sb_1__2__mux_2level_tapbuf_size8 mux_left_track_5 (
     .in ( { chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] , 
         chany_bottom_in[12] , chany_bottom_in[23] , 
@@ -42593,22 +56734,26 @@
     .sram ( mux_2level_tapbuf_size8_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
         SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
-    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_216 ) ) ;
+    .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_216 ) ) ;
 sb_1__2__mux_2level_tapbuf_size8_mem_0 mem_right_track_4 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size7_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size8_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size8_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size8_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size8_mem_1 mem_left_track_3 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size7_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size8_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size8_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size8_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size8_mem mem_left_track_5 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size8_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size8_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size8_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size8_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size10_0 mux_right_track_6 (
     .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , 
         right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , 
@@ -42619,7 +56764,7 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
         SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
     .out ( { aps_rename_507_ } ) ,
-    .p0 ( optlc_net_212 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_212 ) ) ;
 sb_1__2__mux_2level_tapbuf_size10 mux_left_track_7 (
     .in ( { chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] , 
         chany_bottom_in[13] , chany_bottom_in[24] , left_top_grid_pin_1_[0] , 
@@ -42628,17 +56773,20 @@
     .sram ( mux_2level_tapbuf_size10_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
         SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
-    .out ( chanx_left_out[3] ) , .p0 ( optlc_net_216 ) ) ;
+    .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_216 ) ) ;
 sb_1__2__mux_2level_tapbuf_size10_mem_0 mem_right_track_6 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size8_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size10_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size10_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size10_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size10_mem mem_left_track_7 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size8_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size10_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size10_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size10_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size9_0 mux_right_track_10 (
     .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , 
         right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_42_[0] , 
@@ -42648,7 +56796,7 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
         SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
     .out ( { aps_rename_508_ } ) ,
-    .p0 ( optlc_net_212 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_212 ) ) ;
 sb_1__2__mux_2level_tapbuf_size9 mux_left_track_11 (
     .in ( { chanx_left_out[11] , ropt_net_231 , chany_bottom_in[3] , 
         chany_bottom_in[14] , chany_bottom_in[25] , 
@@ -42657,38 +56805,44 @@
     .sram ( mux_2level_tapbuf_size9_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
         SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
-    .out ( chanx_left_out[5] ) , .p0 ( optlc_net_216 ) ) ;
+    .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_216 ) ) ;
 sb_1__2__mux_2level_tapbuf_size9_mem_0 mem_right_track_10 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size10_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size9_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size9_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size9_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size9_mem mem_left_track_11 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size10_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size9_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size9_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size9_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size5_0 mux_right_track_36 (
     .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] , 
         chany_bottom_in[12] , chany_bottom_in[23] , chanx_right_out[16] } ) ,
     .sram ( mux_2level_tapbuf_size5_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , 
         SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
-    .out ( chanx_right_out[18] ) , .p0 ( optlc_net_215 ) ) ;
+    .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_215 ) ) ;
 sb_1__2__mux_2level_tapbuf_size5_1 mux_right_track_44 (
     .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , 
         chany_bottom_in[11] , chany_bottom_in[22] , chanx_right_out[17] } ) ,
     .sram ( mux_2level_tapbuf_size5_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , 
         SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
-    .out ( chanx_right_out[22] ) , .p0 ( optlc_net_215 ) ) ;
+    .out ( chanx_right_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_215 ) ) ;
 sb_1__2__mux_2level_tapbuf_size5_2 mux_bottom_track_5 (
     .in ( { chanx_left_out[8] , bottom_left_grid_pin_46_[0] , 
         bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_right_out[8] } ) ,
     .sram ( mux_2level_tapbuf_size5_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , 
         SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
-    .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_214 ) ) ;
+    .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_214 ) ) ;
 sb_1__2__mux_2level_tapbuf_size5_3 mux_bottom_track_11 (
     .in ( { chanx_left_out[12] , bottom_left_grid_pin_46_[0] , 
         bottom_left_grid_pin_49_[0] , chanx_right_out[12] , 
@@ -42696,135 +56850,158 @@
     .sram ( mux_2level_tapbuf_size5_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , 
         SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
-    .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_218 ) ) ;
+    .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_218 ) ) ;
 sb_1__2__mux_2level_tapbuf_size5 mux_left_track_37 (
     .in ( { chanx_left_out[16] , chany_bottom_in[7] , chany_bottom_in[18] , 
         chany_bottom_in[29] , left_bottom_grid_pin_38_[0] } ) ,
     .sram ( mux_2level_tapbuf_size5_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , 
         SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
-    .out ( chanx_left_out[18] ) , .p0 ( optlc_net_213 ) ) ;
+    .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_213 ) ) ;
 sb_1__2__mux_2level_tapbuf_size5_mem_0 mem_right_track_36 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size7_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size5_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size5_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size5_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size5_mem_1 mem_right_track_44 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size5_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size5_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size5_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size5_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size5_mem_2 mem_bottom_track_5 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size5_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size5_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size5_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size5_mem_3 mem_bottom_track_11 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size5_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size5_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size5_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size5_mem mem_left_track_37 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size7_mem_8_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size5_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size5_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size5_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size4_0 mux_right_track_52 (
     .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[10] , 
         chany_bottom_in[21] , chanx_right_out[19] } ) ,
     .sram ( mux_2level_tapbuf_size4_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , 
         SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
-    .out ( chanx_right_out[26] ) , .p0 ( optlc_net_212 ) ) ;
+    .out ( chanx_right_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_212 ) ) ;
 sb_1__2__mux_2level_tapbuf_size4_1 mux_bottom_track_13 (
     .in ( { chanx_left_out[13] , bottom_left_grid_pin_44_[0] , 
         chanx_right_out[13] , chanx_left_in[17] } ) ,
     .sram ( mux_2level_tapbuf_size4_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , 
         SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
-    .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_218 ) ) ;
+    .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_218 ) ) ;
 sb_1__2__mux_2level_tapbuf_size4_2 mux_bottom_track_15 (
     .in ( { chanx_left_out[15] , bottom_left_grid_pin_45_[0] , 
         chanx_right_out[15] , chanx_left_in[21] } ) ,
     .sram ( mux_2level_tapbuf_size4_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , 
         SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
-    .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_218 ) ) ;
+    .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_218 ) ) ;
 sb_1__2__mux_2level_tapbuf_size4_3 mux_bottom_track_17 (
     .in ( { chanx_left_out[16] , bottom_left_grid_pin_46_[0] , 
         chanx_right_out[16] , chanx_left_in[25] } ) ,
     .sram ( mux_2level_tapbuf_size4_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , 
         SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) ,
-    .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_218 ) ) ;
+    .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_218 ) ) ;
 sb_1__2__mux_2level_tapbuf_size4_4 mux_bottom_track_19 (
     .in ( { chanx_left_out[17] , bottom_left_grid_pin_47_[0] , 
         chanx_right_out[17] , chanx_left_in[29] } ) ,
     .sram ( mux_2level_tapbuf_size4_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , 
         SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) ,
-    .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_214 ) ) ;
+    .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_214 ) ) ;
 sb_1__2__mux_2level_tapbuf_size4_5 mux_bottom_track_37 (
     .in ( { chanx_left_out[29] , chanx_right_in[29] , 
         bottom_left_grid_pin_44_[0] , chanx_right_out[29] } ) ,
     .sram ( mux_2level_tapbuf_size4_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , 
         SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) ,
-    .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_218 ) ) ;
+    .out ( chany_bottom_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_218 ) ) ;
 sb_1__2__mux_2level_tapbuf_size4_6 mux_left_track_45 (
     .in ( { chanx_left_out[17] , chany_bottom_in[8] , chany_bottom_in[19] , 
         left_bottom_grid_pin_39_[0] } ) ,
     .sram ( mux_2level_tapbuf_size4_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 , 
         SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) ,
-    .out ( chanx_left_out[22] ) , .p0 ( optlc_net_213 ) ) ;
+    .out ( chanx_left_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_213 ) ) ;
 sb_1__2__mux_2level_tapbuf_size4 mux_left_track_53 (
     .in ( { chanx_left_out[19] , chany_bottom_in[9] , chany_bottom_in[20] , 
         left_bottom_grid_pin_40_[0] } ) ,
     .sram ( mux_2level_tapbuf_size4_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 , 
         SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) ,
-    .out ( chanx_left_out[26] ) , .p0 ( optlc_net_217 ) ) ;
+    .out ( chanx_left_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_217 ) ) ;
 sb_1__2__mux_2level_tapbuf_size4_mem_0 mem_right_track_52 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size5_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size4_mem_1 mem_bottom_track_13 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size5_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size4_mem_2 mem_bottom_track_15 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size4_mem_3 mem_bottom_track_17 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size4_mem_4 mem_bottom_track_19 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size4_mem_5 mem_bottom_track_37 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_5_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_5_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size4_mem_6 mem_left_track_45 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size5_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_6_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_6_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size4_mem mem_left_track_53 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_6_ccff_tail ) ,
     .ccff_tail ( { copt_net_230 } ) ,
-    .mem_out ( mux_2level_tapbuf_size4_7_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_7_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size6_0 mux_bottom_track_1 (
     .in ( { chanx_left_out[4] , bottom_left_grid_pin_44_[0] , 
         bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , 
@@ -42832,7 +57009,8 @@
     .sram ( mux_2level_tapbuf_size6_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 , 
         SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) ,
-    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_217 ) ) ;
+    .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_217 ) ) ;
 sb_1__2__mux_2level_tapbuf_size6_1 mux_bottom_track_3 (
     .in ( { chanx_left_out[7] , bottom_left_grid_pin_45_[0] , 
         bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , 
@@ -42840,7 +57018,8 @@
     .sram ( mux_2level_tapbuf_size6_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 , 
         SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) ,
-    .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_217 ) ) ;
+    .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_217 ) ) ;
 sb_1__2__mux_2level_tapbuf_size6_2 mux_bottom_track_7 (
     .in ( { chanx_left_out[9] , bottom_left_grid_pin_44_[0] , 
         bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , 
@@ -42848,7 +57027,8 @@
     .sram ( mux_2level_tapbuf_size6_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 , 
         SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) ,
-    .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_214 ) ) ;
+    .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_214 ) ) ;
 sb_1__2__mux_2level_tapbuf_size6 mux_bottom_track_9 (
     .in ( { chanx_left_out[11] , bottom_left_grid_pin_45_[0] , 
         bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , 
@@ -42856,647 +57036,841 @@
     .sram ( mux_2level_tapbuf_size6_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 , 
         SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) ,
-    .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_217 ) ) ;
+    .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_217 ) ) ;
 sb_1__2__mux_2level_tapbuf_size6_mem_0 mem_bottom_track_1 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size6_mem_1 mem_bottom_track_3 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size6_mem_2 mem_bottom_track_7 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size5_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size6_mem mem_bottom_track_9 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size3_0 mux_bottom_track_21 (
     .in ( { chanx_left_out[19] , bottom_left_grid_pin_48_[0] , 
         chanx_right_out[19] } ) ,
     .sram ( mux_2level_tapbuf_size3_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) ,
-    .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_211 ) ) ;
+    .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_211 ) ) ;
 sb_1__2__mux_2level_tapbuf_size3_1 mux_bottom_track_23 (
     .in ( { chanx_left_out[20] , bottom_left_grid_pin_49_[0] , 
         chanx_right_out[20] } ) ,
     .sram ( mux_2level_tapbuf_size3_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) ,
-    .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_217 ) ) ;
+    .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_217 ) ) ;
 sb_1__2__mux_2level_tapbuf_size3_2 mux_bottom_track_25 (
     .in ( { chanx_left_out[21] , bottom_left_grid_pin_50_[0] , 
         chanx_right_out[21] } ) ,
     .sram ( mux_2level_tapbuf_size3_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 } ) ,
-    .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_211 ) ) ;
+    .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_211 ) ) ;
 sb_1__2__mux_2level_tapbuf_size3 mux_bottom_track_27 (
     .in ( { chanx_left_out[23] , bottom_left_grid_pin_51_[0] , 
         chanx_right_out[23] } ) ,
     .sram ( mux_2level_tapbuf_size3_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) ,
-    .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_211 ) ) ;
+    .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_211 ) ) ;
 sb_1__2__mux_2level_tapbuf_size3_mem_0 mem_bottom_track_21 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size3_mem_1 mem_bottom_track_23 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size3_mem_2 mem_bottom_track_25 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size3_mem mem_bottom_track_27 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size2_0 mux_bottom_track_29 (
     .in ( { chanx_left_out[24] , chanx_right_out[24] } ) ,
     .sram ( mux_2level_tapbuf_size2_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 } ) ,
-    .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_211 ) ) ;
+    .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_211 ) ) ;
 sb_1__2__mux_2level_tapbuf_size2_1 mux_bottom_track_31 (
     .in ( { ropt_net_231 , chanx_right_out[25] } ) ,
     .sram ( mux_2level_tapbuf_size2_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_143 , SYNOPSYS_UNCONNECTED_144 } ) ,
-    .out ( chany_bottom_out[15] ) , .p0 ( optlc_net_210 ) ) ;
+    .out ( chany_bottom_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_210 ) ) ;
 sb_1__2__mux_2level_tapbuf_size2_2 mux_bottom_track_33 (
     .in ( { chanx_left_out[27] , chanx_right_out[27] } ) ,
     .sram ( mux_2level_tapbuf_size2_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_145 , SYNOPSYS_UNCONNECTED_146 } ) ,
-    .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_214 ) ) ;
+    .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_214 ) ) ;
 sb_1__2__mux_2level_tapbuf_size2_3 mux_bottom_track_35 (
     .in ( { chanx_left_out[28] , chanx_right_out[28] } ) ,
     .sram ( mux_2level_tapbuf_size2_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 } ) ,
-    .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_214 ) ) ;
+    .out ( chany_bottom_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_214 ) ) ;
 sb_1__2__mux_2level_tapbuf_size2_4 mux_bottom_track_39 (
     .in ( { chanx_right_in[25] , bottom_left_grid_pin_45_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_149 , SYNOPSYS_UNCONNECTED_150 } ) ,
-    .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_214 ) ) ;
+    .out ( chany_bottom_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_214 ) ) ;
 sb_1__2__mux_2level_tapbuf_size2_5 mux_bottom_track_41 (
     .in ( { chanx_right_in[21] , bottom_left_grid_pin_46_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_151 , SYNOPSYS_UNCONNECTED_152 } ) ,
-    .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_210 ) ) ;
+    .out ( chany_bottom_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_210 ) ) ;
 sb_1__2__mux_2level_tapbuf_size2_6 mux_bottom_track_43 (
     .in ( { chanx_right_in[17] , bottom_left_grid_pin_47_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 } ) ,
-    .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_211 ) ) ;
+    .out ( chany_bottom_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_211 ) ) ;
 sb_1__2__mux_2level_tapbuf_size2_7 mux_bottom_track_45 (
     .in ( { chanx_right_in[13] , bottom_left_grid_pin_48_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_155 , SYNOPSYS_UNCONNECTED_156 } ) ,
-    .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_211 ) ) ;
+    .out ( chany_bottom_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_211 ) ) ;
 sb_1__2__mux_2level_tapbuf_size2_8 mux_bottom_track_47 (
     .in ( { chanx_right_in[9] , bottom_left_grid_pin_49_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_8_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_157 , SYNOPSYS_UNCONNECTED_158 } ) ,
-    .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_211 ) ) ;
+    .out ( chany_bottom_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_211 ) ) ;
 sb_1__2__mux_2level_tapbuf_size2_9 mux_bottom_track_49 (
     .in ( { chanx_right_in[5] , bottom_left_grid_pin_50_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_9_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 } ) ,
-    .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_211 ) ) ;
+    .out ( chany_bottom_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_211 ) ) ;
 sb_1__2__mux_2level_tapbuf_size2 mux_bottom_track_51 (
     .in ( { chanx_right_in[4] , bottom_left_grid_pin_51_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_10_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_161 , SYNOPSYS_UNCONNECTED_162 } ) ,
-    .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_211 ) ) ;
+    .out ( chany_bottom_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_211 ) ) ;
 sb_1__2__mux_2level_tapbuf_size2_mem_0 mem_bottom_track_29 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size2_mem_1 mem_bottom_track_31 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size2_mem_2 mem_bottom_track_33 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size2_mem_3 mem_bottom_track_35 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size2_mem_4 mem_bottom_track_39 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size2_mem_5 mem_bottom_track_41 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_5_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_5_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size2_mem_6 mem_bottom_track_43 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_6_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_6_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size2_mem_7 mem_bottom_track_45 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_7_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_7_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size2_mem_8 mem_bottom_track_47 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_8_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_8_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_8_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size2_mem_9 mem_bottom_track_49 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_8_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_9_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_9_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_9_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__2__mux_2level_tapbuf_size2_mem mem_bottom_track_51 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_9_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_10_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_10_sram ) ) ;
-sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_10_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_E_in ) , 
-    .X ( aps_rename_509_ ) ) ;
+    .X ( aps_rename_509_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_E_in ) , 
-    .X ( net_net_207 ) ) ;
+    .X ( net_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , 
-    .X ( prog_clk[0] ) ) ;
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_107__106 ( .A ( chanx_right_in[0] ) , 
-    .X ( ropt_net_234 ) ) ;
+    .X ( ropt_net_234 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_108__107 ( .A ( chanx_right_in[1] ) , 
-    .X ( chany_bottom_out[27] ) ) ;
+    .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_109__108 ( .A ( chanx_right_in[2] ) , 
-    .X ( ropt_net_233 ) ) ;
+    .X ( ropt_net_233 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_110__109 ( .A ( chanx_right_in[3] ) , 
-    .X ( chanx_left_out[4] ) ) ;
+    .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_111__110 ( .A ( chanx_right_in[6] ) , 
-    .X ( chanx_left_out[7] ) ) ;
+    .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_112__111 ( .A ( chanx_right_in[7] ) , 
-    .X ( chanx_left_out[8] ) ) ;
+    .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_113__112 ( .A ( chanx_right_in[8] ) , 
-    .X ( chanx_left_out[9] ) ) ;
+    .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_114__113 ( .A ( chanx_right_in[10] ) , 
-    .X ( chanx_left_out[11] ) ) ;
+    .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_115__114 ( .A ( chanx_right_in[11] ) , 
-    .X ( chanx_left_out[12] ) ) ;
+    .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_116__115 ( .A ( chanx_right_in[12] ) , 
-    .X ( chanx_left_out[13] ) ) ;
+    .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_117__116 ( .A ( chanx_right_in[14] ) , 
-    .X ( chanx_left_out[15] ) ) ;
+    .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_118__117 ( .A ( chanx_right_in[15] ) , 
-    .X ( chanx_left_out[16] ) ) ;
+    .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_119__118 ( .A ( chanx_right_in[16] ) , 
-    .X ( chanx_left_out[17] ) ) ;
+    .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_120__119 ( .A ( chanx_right_in[18] ) , 
-    .X ( chanx_left_out[19] ) ) ;
+    .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_121__120 ( .A ( chanx_right_in[19] ) , 
-    .X ( chanx_left_out[20] ) ) ;
+    .X ( chanx_left_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_122__121 ( .A ( chanx_right_in[20] ) , 
-    .X ( chanx_left_out[21] ) ) ;
+    .X ( chanx_left_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_123__122 ( .A ( chanx_right_in[22] ) , 
-    .X ( chanx_left_out[23] ) ) ;
+    .X ( chanx_left_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_124__123 ( .A ( chanx_right_in[23] ) , 
-    .X ( chanx_left_out[24] ) ) ;
+    .X ( chanx_left_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_125__124 ( .A ( chanx_right_in[24] ) , 
-    .X ( ropt_net_231 ) ) ;
+    .X ( ropt_net_231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_126__125 ( .A ( chanx_right_in[26] ) , 
-    .X ( chanx_left_out[27] ) ) ;
+    .X ( chanx_left_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_127__126 ( .A ( chanx_right_in[27] ) , 
-    .X ( chanx_left_out[28] ) ) ;
+    .X ( chanx_left_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_128__127 ( .A ( chanx_right_in[28] ) , 
-    .X ( chanx_left_out[29] ) ) ;
+    .X ( chanx_left_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_129__128 ( .A ( chanx_left_in[0] ) , 
-    .X ( ropt_net_235 ) ) ;
+    .X ( ropt_net_235 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_130__129 ( .A ( chanx_left_in[3] ) , 
-    .X ( chanx_right_out[4] ) ) ;
+    .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_131__130 ( .A ( chanx_left_in[6] ) , 
-    .X ( chanx_right_out[7] ) ) ;
+    .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_132__131 ( .A ( chanx_left_in[7] ) , 
-    .X ( chanx_right_out[8] ) ) ;
+    .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_133__132 ( .A ( chanx_left_in[8] ) , 
-    .X ( chanx_right_out[9] ) ) ;
+    .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_134__133 ( .A ( chanx_left_in[10] ) , 
-    .X ( chanx_right_out[11] ) ) ;
+    .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_135__134 ( .A ( chanx_left_in[11] ) , 
-    .X ( chanx_right_out[12] ) ) ;
+    .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_136__135 ( .A ( chanx_left_in[12] ) , 
-    .X ( chanx_right_out[13] ) ) ;
+    .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_137__136 ( .A ( chanx_left_in[14] ) , 
-    .X ( chanx_right_out[15] ) ) ;
+    .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_138__137 ( .A ( chanx_left_in[15] ) , 
-    .X ( chanx_right_out[16] ) ) ;
+    .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_139__138 ( .A ( chanx_left_in[16] ) , 
-    .X ( chanx_right_out[17] ) ) ;
+    .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_140__139 ( .A ( chanx_left_in[18] ) , 
-    .X ( chanx_right_out[19] ) ) ;
+    .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_141__140 ( .A ( chanx_left_in[19] ) , 
-    .X ( chanx_right_out[20] ) ) ;
+    .X ( chanx_right_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_142__141 ( .A ( chanx_left_in[20] ) , 
-    .X ( chanx_right_out[21] ) ) ;
+    .X ( chanx_right_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_143__142 ( .A ( chanx_left_in[22] ) , 
-    .X ( chanx_right_out[23] ) ) ;
+    .X ( chanx_right_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_144__143 ( .A ( chanx_left_in[23] ) , 
-    .X ( chanx_right_out[24] ) ) ;
+    .X ( chanx_right_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_145__144 ( .A ( chanx_left_in[24] ) , 
-    .X ( chanx_right_out[25] ) ) ;
+    .X ( chanx_right_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_146__145 ( .A ( chanx_left_in[26] ) , 
-    .X ( chanx_right_out[27] ) ) ;
+    .X ( chanx_right_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_147__146 ( .A ( chanx_left_in[27] ) , 
-    .X ( chanx_right_out[28] ) ) ;
+    .X ( chanx_right_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_148__147 ( .A ( chanx_left_in[28] ) , 
-    .X ( chanx_right_out[29] ) ) ;
-sky130_fd_sc_hd__buf_6 FTB_149__148 ( .A ( SC_IN_BOT ) , .X ( ropt_net_232 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_205 ( .A ( BUF_net_206 ) , .Y ( pReset_W_out ) ) ;
+    .X ( chanx_right_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_149__148 ( .A ( SC_IN_BOT ) , .X ( ropt_net_232 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_205 ( .A ( BUF_net_206 ) , .Y ( pReset_W_out ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_206 ( .A ( aps_rename_509_ ) , 
-    .Y ( BUF_net_206 ) ) ;
+    .Y ( BUF_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_207 ( .A ( net_net_207 ) , 
-    .X ( pReset_E_out ) ) ;
+    .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_212 ( .LO ( SYNOPSYS_UNCONNECTED_163 ) , 
-    .HI ( optlc_net_210 ) ) ;
+    .HI ( optlc_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_214 ( .LO ( SYNOPSYS_UNCONNECTED_164 ) , 
-    .HI ( optlc_net_211 ) ) ;
+    .HI ( optlc_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_216 ( .LO ( SYNOPSYS_UNCONNECTED_165 ) , 
-    .HI ( optlc_net_212 ) ) ;
+    .HI ( optlc_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_218 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) , 
-    .HI ( optlc_net_213 ) ) ;
+    .HI ( optlc_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_220 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , 
-    .HI ( optlc_net_214 ) ) ;
+    .HI ( optlc_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_222 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , 
-    .HI ( optlc_net_215 ) ) ;
+    .HI ( optlc_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_224 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , 
-    .HI ( optlc_net_216 ) ) ;
+    .HI ( optlc_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_226 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , 
-    .HI ( optlc_net_217 ) ) ;
+    .HI ( optlc_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_228 ( .LO ( SYNOPSYS_UNCONNECTED_171 ) , 
-    .HI ( optlc_net_218 ) ) ;
+    .HI ( optlc_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_229 ( .A ( aps_rename_507_ ) , 
-    .X ( chanx_right_out[3] ) ) ;
+    .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_230 ( .A ( aps_rename_508_ ) , 
-    .X ( chanx_right_out[5] ) ) ;
+    .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__bufbuf_8 copt_h_inst_1461 ( .A ( copt_net_230 ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1462 ( .A ( ropt_net_231 ) , 
-    .X ( chanx_left_out[25] ) ) ;
+    .X ( chanx_left_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1463 ( .A ( ropt_net_232 ) , 
-    .X ( SC_OUT_BOT ) ) ;
+    .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1464 ( .A ( ropt_net_233 ) , 
-    .X ( chany_bottom_out[26] ) ) ;
+    .X ( chany_bottom_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1465 ( .A ( ropt_net_234 ) , 
-    .X ( chany_bottom_out[28] ) ) ;
+    .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1466 ( .A ( ropt_net_235 ) , 
-    .X ( chany_bottom_out[29] ) ) ;
+    .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size6_mem_10 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_67__66 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_67__66 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size6_mem_9 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_66__65 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_66__65 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size6_mem_8 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_65__64 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_65__64 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size6_mem_7 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_64__63 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_64__63 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size6_mem_6 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_63__62 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_63__62 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size6_mem_5 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_62__61 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_62__61 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size6_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_61__60 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_61__60 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size6_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_60__59 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_60__59 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size6_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size6_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size6_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_57__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_57__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_42 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_41 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to3 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_56__55 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_56__55 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to3_22 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to3_22 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -43506,125 +57880,167 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to3_22 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_41 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_42 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_40 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_39 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_38 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to3_21 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to3_21 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to3_20 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to3_20 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size6_10 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size6_10 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -43634,126 +58050,169 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__1__local_encoder2to3_20 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to3_21 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_38 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_39 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_40 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_195 ( .A ( BUF_net_196 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_195 ( .A ( BUF_net_196 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_196 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_196 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_196 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_37 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_36 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_35 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to3_19 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to3_19 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to3_18 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to3_18 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size6_9 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size6_9 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -43763,125 +58222,167 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to3_18 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to3_19 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_35 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_36 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_37 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_34 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_33 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_32 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to3_17 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to3_17 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to3_16 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to3_16 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size6_8 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size6_8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -43891,126 +58392,169 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__1__local_encoder2to3_16 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to3_17 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_32 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_33 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_34 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_185 ( .A ( BUF_net_186 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_185 ( .A ( BUF_net_186 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_186 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_186 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_186 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_31 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_30 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_29 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to3_15 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to3_15 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to3_14 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to3_14 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size6_7 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size6_7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -44020,126 +58564,169 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__1__local_encoder2to3_14 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to3_15 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_29 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_30 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_31 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_183 ( .A ( BUF_net_184 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_183 ( .A ( BUF_net_184 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_184 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_184 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_184 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_28 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_27 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_26 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to3_13 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to3_13 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to3_12 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to3_12 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size6_6 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size6_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -44149,126 +58736,169 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__1__local_encoder2to3_12 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to3_13 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_26 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_27 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_28 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_181 ( .A ( BUF_net_182 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_181 ( .A ( BUF_net_182 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_182 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_182 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_182 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_25 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_24 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_23 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to3_11 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to3_11 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to3_10 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to3_10 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size6_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -44278,126 +58908,169 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__1__local_encoder2to3_10 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to3_11 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_23 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_24 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_25 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_179 ( .A ( BUF_net_180 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_179 ( .A ( BUF_net_180 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_180 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_180 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_180 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_22 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_21 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_20 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to3_9 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to3_9 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to3_8 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to3_8 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size6_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -44407,125 +59080,167 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to3_8 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to3_9 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_20 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_21 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_22 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_19 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_18 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_17 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to3_7 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to3_7 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to3_6 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to3_6 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size6_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -44535,125 +59250,167 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to3_7 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_17 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_18 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_19 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_16 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_15 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_14 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to3_5 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to3_5 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to3_4 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to3_4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -44663,126 +59420,169 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__1__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to3_5 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_14 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_15 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_16 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_197 ( .A ( BUF_net_198 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_197 ( .A ( BUF_net_198 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_198 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_198 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_198 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_13 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_12 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_11 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to3_3 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to3_3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to3_2 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to3_2 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -44792,126 +59592,169 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__1__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to3_3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_11 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_12 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_13 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_193 ( .A ( BUF_net_194 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_193 ( .A ( BUF_net_194 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_194 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_194 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_194 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_10 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_9 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_8 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to3_1 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to3_1 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to3_0 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to3_0 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -44921,225 +59764,314 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to3_1 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_8 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_9 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_10 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size9_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size9_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size9_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size9_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_102 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_101 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_62 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_62 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size9 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:8] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -45149,149 +60081,198 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
     .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , 
-    .X ( aps_rename_521_ ) ) ;
+    .X ( aps_rename_521_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_62 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_101 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_102 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , in[8] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_177 ( .A ( BUF_net_178 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_177 ( .A ( BUF_net_178 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_178 ( .A ( aps_rename_521_ ) , 
-    .Y ( BUF_net_178 ) ) ;
+    .Y ( BUF_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_100 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_99 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_98 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_61 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_61 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_60 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_60 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size9_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size9_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:8] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -45301,149 +60282,198 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
     .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , 
-    .X ( aps_rename_520_ ) ) ;
+    .X ( aps_rename_520_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_60 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_61 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_98 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_99 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_100 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , in[8] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_175 ( .A ( BUF_net_176 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_175 ( .A ( BUF_net_176 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_176 ( .A ( aps_rename_520_ ) , 
-    .Y ( BUF_net_176 ) ) ;
+    .Y ( BUF_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_97 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_96 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_95 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_59 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_59 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_58 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_58 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size9_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:8] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -45453,149 +60483,198 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
     .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , 
-    .X ( aps_rename_519_ ) ) ;
+    .X ( aps_rename_519_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_58 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_59 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_95 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_96 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_97 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , in[8] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_173 ( .A ( BUF_net_174 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_173 ( .A ( BUF_net_174 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_174 ( .A ( aps_rename_519_ ) , 
-    .Y ( BUF_net_174 ) ) ;
+    .Y ( BUF_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_94 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_93 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_92 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_57 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_57 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_56 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_56 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:8] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -45605,331 +60684,466 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
     .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , 
-    .X ( aps_rename_518_ ) ) ;
+    .X ( aps_rename_518_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_56 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_57 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_92 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_93 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_94 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , in[8] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_171 ( .A ( BUF_net_172 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_171 ( .A ( BUF_net_172 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_172 ( .A ( aps_rename_518_ ) , 
-    .Y ( BUF_net_172 ) ) ;
+    .Y ( BUF_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size12_mem_6 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size12_mem_5 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size12_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size12_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size12_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size12_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size12_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_91 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_90 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_89 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_88 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_55 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_55 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_54 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_54 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size12 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -45940,28 +61154,33 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
     .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , 
-    .X ( aps_rename_517_ ) ) ;
+    .X ( aps_rename_517_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_54 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_55 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_88 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_89 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_90 mux_l1_in_2_ ( 
     .in ( in[8:11] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_91 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -45969,147 +61188,198 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_169 ( .A ( BUF_net_170 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_169 ( .A ( BUF_net_170 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_170 ( .A ( aps_rename_517_ ) , 
-    .Y ( BUF_net_170 ) ) ;
+    .Y ( BUF_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_87 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_86 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_85 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_84 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_53 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_53 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_52 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_52 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size12_6 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -46120,28 +61390,33 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
     .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , 
-    .X ( aps_rename_516_ ) ) ;
+    .X ( aps_rename_516_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_52 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_53 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_84 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_85 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_86 mux_l1_in_2_ ( 
     .in ( in[8:11] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_87 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -46149,147 +61424,198 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_167 ( .A ( BUF_net_168 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_167 ( .A ( BUF_net_168 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_168 ( .A ( aps_rename_516_ ) , 
-    .Y ( BUF_net_168 ) ) ;
+    .Y ( BUF_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_83 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_82 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_81 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_80 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_51 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_51 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_50 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_50 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size12_5 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -46300,27 +61626,33 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , .X ( net_net_166 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , .X ( net_net_166 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_50 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_51 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_80 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_81 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_82 mux_l1_in_2_ ( 
     .in ( in[8:11] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_83 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -46328,145 +61660,196 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_166 ( .A ( net_net_166 ) , .X ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_166 ( .A ( net_net_166 ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_79 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_78 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_77 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_76 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_49 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_49 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_48 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_48 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size12_4 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -46477,27 +61860,33 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_48 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_49 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_76 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_77 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_78 mux_l1_in_2_ ( 
     .in ( in[8:11] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_79 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -46505,144 +61894,194 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_75 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_74 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_73 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_72 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_47 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_47 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_46 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_46 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size12_3 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -46653,28 +62092,33 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
     .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , 
-    .X ( aps_rename_515_ ) ) ;
+    .X ( aps_rename_515_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_46 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_47 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_72 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_73 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_74 mux_l1_in_2_ ( 
     .in ( in[8:11] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_75 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -46682,147 +62126,198 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_165 ( .A ( aps_rename_515_ ) , 
-    .Y ( BUF_net_165 ) ) ;
+    .Y ( BUF_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_71 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_70 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_69 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_68 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_45 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_45 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_44 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_44 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size12_2 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -46833,28 +62328,33 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
     .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , 
-    .X ( aps_rename_514_ ) ) ;
+    .X ( aps_rename_514_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_44 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_45 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_68 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_69 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_70 mux_l1_in_2_ ( 
     .in ( in[8:11] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_71 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -46862,147 +62362,198 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_163 ( .A ( aps_rename_514_ ) , 
-    .Y ( BUF_net_163 ) ) ;
+    .Y ( BUF_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_67 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_66 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_65 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_64 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_43 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_43 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_42 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_42 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size12_1 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -47013,28 +62564,33 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
     .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , 
-    .X ( aps_rename_513_ ) ) ;
+    .X ( aps_rename_513_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_42 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_43 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_64 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_65 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_66 mux_l1_in_2_ ( 
     .in ( in[8:11] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_67 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -47042,147 +62598,198 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_161 ( .A ( aps_rename_513_ ) , 
-    .Y ( BUF_net_161 ) ) ;
+    .Y ( BUF_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_63 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_62 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_61 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_60 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_41 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_41 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_40 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_40 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size12_0 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:11] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -47193,28 +62800,33 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
     .A ( mux_2level_tapbuf_basis_input4_mem4_3_out[0] ) , 
-    .X ( aps_rename_512_ ) ) ;
+    .X ( aps_rename_512_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_40 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_41 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_60 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_61 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_62 mux_l1_in_2_ ( 
     .in ( in[8:11] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_63 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -47222,382 +62834,552 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_159 ( .A ( aps_rename_512_ ) , 
-    .Y ( BUF_net_159 ) ) ;
+    .Y ( BUF_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size10_mem_10 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size10_mem_9 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size10_mem_8 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size10_mem_7 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size10_mem_6 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size10_mem_5 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size10_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size10_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size10_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size10_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size10_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input2_mem2 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_59 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_58 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_57 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_39 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_39 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_38 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_38 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size10 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -47608,24 +63390,28 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
     .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , 
-    .X ( aps_rename_511_ ) ) ;
+    .X ( aps_rename_511_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_38 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_39 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_57 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_58 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_59 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -47633,147 +63419,197 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_156 ( .A ( BUF_net_157 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_157 ( .A ( aps_rename_511_ ) , 
-    .Y ( BUF_net_157 ) ) ;
+    .Y ( BUF_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input2_mem2_10 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_56 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_55 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_54 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_37 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_37 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_36 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_36 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size10_10 ( in , sram , sram_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -47784,24 +63620,28 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
     .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , 
-    .X ( aps_rename_510_ ) ) ;
+    .X ( aps_rename_510_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_36 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_37 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_54 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_55 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_56 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -47809,146 +63649,197 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input2_mem2_10 mux_l1_in_2_ ( 
     .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_155 ( .A ( aps_rename_510_ ) , 
-    .Y ( BUF_net_155 ) ) ;
+    .Y ( BUF_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input2_mem2_9 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_53 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_52 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_51 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_35 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_35 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_34 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_34 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size10_9 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size10_9 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -47959,24 +63850,28 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
     .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , 
-    .X ( aps_rename_509_ ) ) ;
+    .X ( aps_rename_509_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_34 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_35 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_51 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_52 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_53 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -47984,146 +63879,197 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input2_mem2_9 mux_l1_in_2_ ( 
     .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_153 ( .A ( aps_rename_509_ ) , 
-    .Y ( BUF_net_153 ) ) ;
+    .Y ( BUF_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input2_mem2_8 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_50 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_49 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_48 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_33 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_33 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_32 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_32 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size10_8 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size10_8 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -48134,23 +64080,28 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_32 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_33 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_48 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_49 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_50 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -48158,143 +64109,193 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input2_mem2_8 mux_l1_in_2_ ( 
     .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input2_mem2_7 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_47 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_46 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_45 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_31 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_31 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_30 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_30 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size10_7 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -48305,23 +64306,28 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_30 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_31 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_45 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_46 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_47 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -48329,143 +64335,193 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input2_mem2_7 mux_l1_in_2_ ( 
     .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input2_mem2_6 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_44 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_43 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_42 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_29 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_29 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_28 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_28 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size10_6 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -48476,23 +64532,28 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( net_net_151 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( net_net_151 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_28 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_29 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_42 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_43 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_44 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -48500,144 +64561,195 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input2_mem2_6 mux_l1_in_2_ ( 
     .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_151 ( .A ( net_net_151 ) , .X ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_151 ( .A ( net_net_151 ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input2_mem2_5 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_41 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_40 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_39 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_27 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_27 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_26 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_26 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size10_5 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -48648,24 +64760,28 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
     .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , 
-    .X ( aps_rename_508_ ) ) ;
+    .X ( aps_rename_508_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_26 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_27 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_39 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_40 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_41 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -48673,146 +64789,197 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input2_mem2_5 mux_l1_in_2_ ( 
     .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_150 ( .A ( aps_rename_508_ ) , 
-    .Y ( BUF_net_150 ) ) ;
+    .Y ( BUF_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input2_mem2_4 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_38 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_37 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_36 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_25 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_25 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_24 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_24 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size10_4 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -48823,24 +64990,28 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
     .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , 
-    .X ( aps_rename_507_ ) ) ;
+    .X ( aps_rename_507_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_24 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_25 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_36 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_37 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_38 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -48848,146 +65019,197 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input2_mem2_4 mux_l1_in_2_ ( 
     .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_148 ( .A ( aps_rename_507_ ) , 
-    .Y ( BUF_net_148 ) ) ;
+    .Y ( BUF_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input2_mem2_3 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_35 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_34 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_33 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_23 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_23 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_22 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_22 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size10_3 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -48998,23 +65220,28 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_22 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_23 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_33 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_34 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_35 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -49022,143 +65249,193 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input2_mem2_3 mux_l1_in_2_ ( 
     .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input2_mem2_2 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_32 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_31 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_30 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_21 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_21 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_20 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_20 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size10_2 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -49169,24 +65446,28 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
     .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , 
-    .X ( aps_rename_506_ ) ) ;
+    .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_20 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_21 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_30 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_31 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_32 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -49194,146 +65475,197 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input2_mem2_2 mux_l1_in_2_ ( 
     .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_146 ( .A ( aps_rename_506_ ) , 
-    .Y ( BUF_net_146 ) ) ;
+    .Y ( BUF_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input2_mem2_1 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_29 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_28 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_27 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_19 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_19 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_18 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_18 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size10_1 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -49344,23 +65676,28 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_18 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_19 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_27 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_28 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_29 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -49368,143 +65705,193 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input2_mem2_1 mux_l1_in_2_ ( 
     .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input2_mem2_0 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_26 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_25 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_24 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_17 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_17 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_16 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_16 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size10_0 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -49515,24 +65902,28 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
     .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , 
-    .X ( aps_rename_505_ ) ) ;
+    .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_16 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_17 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_24 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_25 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_26 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -49540,321 +65931,452 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input2_mem2_0 mux_l1_in_2_ ( 
     .in ( in[8:9] ) , .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_191 ( .A ( BUF_net_192 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_191 ( .A ( BUF_net_192 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_192 ( .A ( aps_rename_505_ ) , 
-    .Y ( BUF_net_192 ) ) ;
+    .Y ( BUF_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size11_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size11_mem_6 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size11_mem_5 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size11_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size11_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size11_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size11_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_size11_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_224 ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1433 ( .A ( ccff_head[0] ) , 
-    .X ( copt_net_209 ) ) ;
+    .X ( copt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1440 ( .A ( copt_net_217 ) , 
-    .X ( copt_net_216 ) ) ;
+    .X ( copt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1441 ( .A ( copt_net_220 ) , 
-    .X ( copt_net_217 ) ) ;
+    .X ( copt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1442 ( .A ( copt_net_209 ) , 
-    .X ( copt_net_218 ) ) ;
+    .X ( copt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1443 ( .A ( copt_net_218 ) , 
-    .X ( copt_net_219 ) ) ;
+    .X ( copt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1444 ( .A ( copt_net_219 ) , 
-    .X ( copt_net_220 ) ) ;
+    .X ( copt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1445 ( .A ( copt_net_216 ) , 
-    .X ( ropt_net_224 ) ) ;
+    .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_7 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_23 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_22 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_21 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_15 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_15 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_14 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_14 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__inv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size11 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size11 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:10] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -49865,23 +66387,28 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__bufbuf_16 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_14 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_15 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_21 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_22 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_23 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -49889,144 +66416,194 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_7 mux_l1_in_2_ ( 
     .in ( in[8:10] ) , .mem ( local_encoder2to4_0_data[0:2] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:2] ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_6 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_20 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_19 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_18 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_13 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_13 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_12 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_12 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__inv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size11_6 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size11_6 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:10] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -50037,23 +66614,28 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_12 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_13 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_18 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_19 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_20 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -50061,144 +66643,194 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_6 mux_l1_in_2_ ( 
     .in ( in[8:10] ) , .mem ( local_encoder2to4_0_data[0:2] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:2] ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_5 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_17 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_16 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_15 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_11 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_11 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_10 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_10 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size11_5 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size11_5 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:10] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -50209,23 +66841,28 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( net_net_144 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( net_net_144 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_10 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_11 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_15 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_16 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_17 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -50233,145 +66870,196 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_5 mux_l1_in_2_ ( 
     .in ( in[8:10] ) , .mem ( local_encoder2to4_0_data[0:2] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:2] ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_144 ( .A ( net_net_144 ) , .X ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_144 ( .A ( net_net_144 ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_4 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_14 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_13 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_12 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_9 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_9 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_8 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_8 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size11_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size11_4 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:10] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -50382,23 +67070,28 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_8 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_9 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_12 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_13 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_14 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -50406,144 +67099,194 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_4 mux_l1_in_2_ ( 
     .in ( in[8:10] ) , .mem ( local_encoder2to4_0_data[0:2] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:2] ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_3 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_11 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_10 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_9 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_7 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_7 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_6 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_6 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size11_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size11_3 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:10] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -50554,23 +67297,28 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_7 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_9 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_10 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_11 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -50578,144 +67326,194 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_3 mux_l1_in_2_ ( 
     .in ( in[8:10] ) , .mem ( local_encoder2to4_0_data[0:2] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:2] ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_2 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_8 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_7 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_6 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_5 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_5 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_4 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size11_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size11_2 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:10] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -50726,23 +67524,28 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_5 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_6 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_7 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_8 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -50750,144 +67553,194 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_2 mux_l1_in_2_ ( 
     .in ( in[8:10] ) , .mem ( local_encoder2to4_0_data[0:2] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:2] ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_1 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_5 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_4 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_3 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_3 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_2 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_2 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__inv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size11_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size11_1 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:10] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -50898,23 +67751,28 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_3 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_3 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_4 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_5 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -50922,144 +67780,194 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_1 mux_l1_in_2_ ( 
     .in ( in[8:10] ) , .mem ( local_encoder2to4_0_data[0:2] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:2] ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input3_mem3_0 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_2 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_1 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__1__mux_2level_tapbuf_basis_input4_mem4_0 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_1 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_1 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__local_encoder2to4_0 ( addr , data , data_inv ) ;
+module sb_1__1__local_encoder2to4_0 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__1__mux_2level_tapbuf_size11_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__1__mux_2level_tapbuf_size11_0 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:10] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -51070,23 +67978,28 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__1__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__local_encoder2to4_1 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_0 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_1 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input4_mem4_2 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -51094,11 +68007,13 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__1__mux_2level_tapbuf_basis_input3_mem3_0 mux_l1_in_2_ ( 
     .in ( in[8:10] ) , .mem ( local_encoder2to4_0_data[0:2] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:2] ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
@@ -51130,7 +68045,7 @@
     clk_2_N_in , clk_2_E_in , clk_2_S_in , clk_2_W_in , clk_2_W_out , 
     clk_2_S_out , clk_2_N_out , clk_2_E_out , clk_3_W_in , clk_3_E_in , 
     clk_3_S_in , clk_3_N_in , clk_3_E_out , clk_3_W_out , clk_3_N_out , 
-    clk_3_S_out ) ;
+    clk_3_S_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:29] chany_top_in ;
 input  [0:0] top_left_grid_pin_44_ ;
@@ -51225,6 +68140,8 @@
 output clk_3_W_out ;
 output clk_3_N_out ;
 output clk_3_S_out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] prog_clk ;
 wire prog_clk_0 ;
@@ -51315,6 +68232,8 @@
 wire [0:0] mux_2level_tapbuf_size9_mem_1_ccff_tail ;
 wire [0:0] mux_2level_tapbuf_size9_mem_2_ccff_tail ;
 wire [0:0] mux_2level_tapbuf_size9_mem_3_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 assign prog_clk_1_E_out = prog_clk_1_S_in ;
 assign prog_clk_1_W_out = prog_clk_1_S_in ;
@@ -51362,7 +68281,8 @@
     .sram ( mux_2level_tapbuf_size11_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
         SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( chany_top_out[0] ) , .p0 ( optlc_net_204 ) ) ;
+    .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_204 ) ) ;
 sb_1__1__mux_2level_tapbuf_size11_1 mux_top_track_2 (
     .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , 
         top_left_grid_pin_51_[0] , chanx_right_in[2] , chanx_left_out[7] , 
@@ -51372,7 +68292,7 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
         SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
     .out ( { ropt_net_225 } ) ,
-    .p0 ( optlc_net_199 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_199 ) ) ;
 sb_1__1__mux_2level_tapbuf_size11_2 mux_right_track_0 (
     .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chany_top_in[29] , 
         right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , 
@@ -51382,7 +68302,7 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
         SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
     .out ( { aps_rename_522_ } ) ,
-    .p0 ( optlc_net_203 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_203 ) ) ;
 sb_1__1__mux_2level_tapbuf_size11_3 mux_right_track_2 (
     .in ( { chany_top_in[0] , chany_bottom_out[7] , chany_bottom_out[21] , 
         right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , 
@@ -51392,7 +68312,7 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
         SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
     .out ( { ZBUF_6_f_0 } ) ,
-    .p0 ( optlc_net_200 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_200 ) ) ;
 sb_1__1__mux_2level_tapbuf_size11_4 mux_bottom_track_1 (
     .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_left_out[4] , 
         chanx_left_out[20] , chanx_right_in[25] , 
@@ -51403,7 +68323,7 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
         SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
     .out ( { aps_rename_523_ } ) ,
-    .p0 ( optlc_net_205 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_205 ) ) ;
 sb_1__1__mux_2level_tapbuf_size11_5 mux_bottom_track_3 (
     .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_left_out[7] , 
         chanx_left_out[21] , chanx_right_in[21] , 
@@ -51413,7 +68333,8 @@
     .sram ( mux_2level_tapbuf_size11_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
         SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
-    .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_201 ) ) ;
+    .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_201 ) ) ;
 sb_1__1__mux_2level_tapbuf_size11_6 mux_left_track_1 (
     .in ( { chany_top_in[0] , chany_bottom_out[4] , chany_bottom_out[20] , 
         chanx_left_out[4] , chanx_left_out[20] , chany_top_out[4] , 
@@ -51424,7 +68345,7 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
         SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
     .out ( { aps_rename_525_ } ) ,
-    .p0 ( optlc_net_205 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_205 ) ) ;
 sb_1__1__mux_2level_tapbuf_size11 mux_left_track_3 (
     .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chany_top_in[29] , 
         chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] , 
@@ -51433,46 +68354,55 @@
     .sram ( mux_2level_tapbuf_size11_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
         SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
-    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_205 ) ) ;
+    .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_205 ) ) ;
 sb_1__1__mux_2level_tapbuf_size11_mem_0 mem_top_track_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
     .ccff_tail ( mux_2level_tapbuf_size11_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size11_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size11_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size11_mem_1 mem_top_track_2 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size11_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size11_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size11_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size11_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size11_mem_2 mem_right_track_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size11_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size11_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size11_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size11_mem_3 mem_right_track_2 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size11_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size11_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size11_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size11_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size11_mem_4 mem_bottom_track_1 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size11_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size11_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size11_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size11_mem_5 mem_bottom_track_3 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size11_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size11_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size11_5_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size11_5_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size11_mem_6 mem_left_track_1 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_8_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size11_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size11_6_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size11_6_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size11_mem mem_left_track_3 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size11_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size11_mem_7_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size11_7_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size11_7_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size10_0 mux_top_track_4 (
     .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , 
         chanx_right_in[4] , chanx_left_out[8] , chanx_left_out[23] , 
@@ -51481,7 +68411,8 @@
     .sram ( mux_2level_tapbuf_size10_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
         SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
-    .out ( chany_top_out[2] ) , .p0 ( optlc_net_199 ) ) ;
+    .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_199 ) ) ;
 sb_1__1__mux_2level_tapbuf_size10_1 mux_top_track_12 (
     .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_50_[0] , 
         chanx_left_out[12] , chanx_right_in[13] , chanx_left_out[27] , 
@@ -51490,7 +68421,8 @@
     .sram ( mux_2level_tapbuf_size10_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
         SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
-    .out ( chany_top_out[6] ) , .p0 ( optlc_net_207 ) ) ;
+    .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_207 ) ) ;
 sb_1__1__mux_2level_tapbuf_size10_2 mux_top_track_20 (
     .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_51_[0] , 
         chanx_left_out[13] , chanx_right_in[17] , chanx_left_out[28] , 
@@ -51499,7 +68431,8 @@
     .sram ( mux_2level_tapbuf_size10_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
         SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
-    .out ( chany_top_out[10] ) , .p0 ( optlc_net_202 ) ) ;
+    .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_202 ) ) ;
 sb_1__1__mux_2level_tapbuf_size10_3 mux_right_track_4 (
     .in ( { chany_top_in[1] , chany_bottom_out[8] , chany_bottom_out[23] , 
         right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , 
@@ -51509,7 +68442,7 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
         SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
     .out ( { ZBUF_39_0 } ) ,
-    .p0 ( optlc_net_203 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_203 ) ) ;
 sb_1__1__mux_2level_tapbuf_size10_4 mux_right_track_12 (
     .in ( { chany_top_in[5] , chany_bottom_out[12] , chany_bottom_out[27] , 
         right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] , 
@@ -51518,7 +68451,8 @@
     .sram ( mux_2level_tapbuf_size10_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
         SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
-    .out ( chanx_right_out[6] ) , .p0 ( optlc_net_202 ) ) ;
+    .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_202 ) ) ;
 sb_1__1__mux_2level_tapbuf_size10_5 mux_right_track_20 (
     .in ( { chany_top_in[9] , chany_bottom_out[13] , chany_bottom_out[28] , 
         right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_43_[0] , 
@@ -51527,7 +68461,8 @@
     .sram ( mux_2level_tapbuf_size10_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
         SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
-    .out ( chanx_right_out[10] ) , .p0 ( optlc_net_202 ) ) ;
+    .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_202 ) ) ;
 sb_1__1__mux_2level_tapbuf_size10_6 mux_bottom_track_5 (
     .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chanx_left_out[8] , 
         chanx_right_in[17] , chanx_left_out[23] , 
@@ -51536,7 +68471,8 @@
     .sram ( mux_2level_tapbuf_size10_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
         SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
-    .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_199 ) ) ;
+    .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_199 ) ) ;
 sb_1__1__mux_2level_tapbuf_size10_7 mux_bottom_track_13 (
     .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[5] , 
         chanx_left_out[12] , chanx_left_out[27] , 
@@ -51545,7 +68481,8 @@
     .sram ( mux_2level_tapbuf_size10_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
         SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
-    .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_204 ) ) ;
+    .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_204 ) ) ;
 sb_1__1__mux_2level_tapbuf_size10_8 mux_bottom_track_21 (
     .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[4] , 
         chanx_left_out[13] , chanx_left_out[28] , 
@@ -51555,7 +68492,7 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , 
         SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
     .out ( { ZBUF_35_0 } ) ,
-    .p0 ( optlc_net_202 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_202 ) ) ;
 sb_1__1__mux_2level_tapbuf_size10_9 mux_left_track_5 (
     .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chany_top_in[25] , 
         chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] , 
@@ -51564,7 +68501,8 @@
     .sram ( mux_2level_tapbuf_size10_9_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , 
         SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
-    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_199 ) ) ;
+    .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_199 ) ) ;
 sb_1__1__mux_2level_tapbuf_size10_10 mux_left_track_13 (
     .in ( { chany_bottom_out[12] , chany_top_in[13] , chany_bottom_out[27] , 
         chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[5] , 
@@ -51573,7 +68511,8 @@
     .sram ( mux_2level_tapbuf_size10_10_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , 
         SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
-    .out ( chanx_left_out[6] ) , .p0 ( optlc_net_207 ) ) ;
+    .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_207 ) ) ;
 sb_1__1__mux_2level_tapbuf_size10 mux_left_track_21 (
     .in ( { chany_top_in[9] , chany_bottom_out[13] , chany_bottom_out[28] , 
         chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[9] , 
@@ -51582,67 +68521,80 @@
     .sram ( mux_2level_tapbuf_size10_11_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , 
         SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
-    .out ( chanx_left_out[10] ) , .p0 ( optlc_net_207 ) ) ;
+    .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_207 ) ) ;
 sb_1__1__mux_2level_tapbuf_size10_mem_0 mem_top_track_4 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size11_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size10_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size10_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size10_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size10_mem_1 mem_top_track_12 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size12_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size10_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size10_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size10_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size10_mem_2 mem_top_track_20 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size10_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size10_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size10_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size10_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size10_mem_3 mem_right_track_4 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size11_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size10_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size10_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size10_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size10_mem_4 mem_right_track_12 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size12_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size10_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size10_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size10_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size10_mem_5 mem_right_track_20 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size10_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size10_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size10_5_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size10_5_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size10_mem_6 mem_bottom_track_5 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size11_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size10_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size10_6_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size10_6_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size10_mem_7 mem_bottom_track_13 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size12_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size10_mem_7_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size10_7_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size10_7_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size10_mem_8 mem_bottom_track_21 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size10_mem_7_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size10_mem_8_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size10_8_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size10_8_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size10_mem_9 mem_left_track_5 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size11_mem_7_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size10_mem_9_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size10_9_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size10_9_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size10_mem_10 mem_left_track_13 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size12_mem_7_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size10_mem_10_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size10_10_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size10_10_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size10_mem mem_left_track_21 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size10_mem_10_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size10_mem_11_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size10_11_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size10_11_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size12_0 mux_top_track_6 (
     .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , 
         top_left_grid_pin_48_[0] , top_left_grid_pin_50_[0] , 
@@ -51652,7 +68604,8 @@
     .sram ( mux_2level_tapbuf_size12_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , 
         SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
-    .out ( chany_top_out[3] ) , .p0 ( optlc_net_207 ) ) ;
+    .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_207 ) ) ;
 sb_1__1__mux_2level_tapbuf_size12_1 mux_top_track_10 (
     .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , 
         top_left_grid_pin_49_[0] , top_left_grid_pin_51_[0] , 
@@ -51662,7 +68615,8 @@
     .sram ( mux_2level_tapbuf_size12_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , 
         SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
-    .out ( chany_top_out[5] ) , .p0 ( optlc_net_208 ) ) ;
+    .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_208 ) ) ;
 sb_1__1__mux_2level_tapbuf_size12_2 mux_right_track_6 (
     .in ( { chany_top_in[2] , chany_bottom_out[9] , chany_bottom_out[24] , 
         right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , 
@@ -51672,7 +68626,8 @@
     .sram ( mux_2level_tapbuf_size12_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , 
         SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
-    .out ( chanx_right_out[3] ) , .p0 ( optlc_net_206 ) ) ;
+    .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_206 ) ) ;
 sb_1__1__mux_2level_tapbuf_size12_3 mux_right_track_10 (
     .in ( { chany_top_in[4] , chany_bottom_out[11] , chany_bottom_out[25] , 
         right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , 
@@ -51682,7 +68637,8 @@
     .sram ( mux_2level_tapbuf_size12_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , 
         SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
-    .out ( chanx_right_out[5] ) , .p0 ( optlc_net_202 ) ) ;
+    .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_202 ) ) ;
 sb_1__1__mux_2level_tapbuf_size12_4 mux_bottom_track_7 (
     .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_left_out[9] , 
         chanx_right_in[13] , chanx_left_out[24] , 
@@ -51693,7 +68649,7 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , 
         SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) ,
     .out ( { aps_rename_524_ } ) ,
-    .p0 ( optlc_net_199 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_199 ) ) ;
 sb_1__1__mux_2level_tapbuf_size12_5 mux_bottom_track_11 (
     .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[9] , 
         chanx_left_out[11] , chanx_left_out[25] , 
@@ -51703,7 +68659,8 @@
     .sram ( mux_2level_tapbuf_size12_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , 
         SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) ,
-    .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_207 ) ) ;
+    .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_207 ) ) ;
 sb_1__1__mux_2level_tapbuf_size12_6 mux_left_track_7 (
     .in ( { chany_bottom_out[9] , chany_top_in[21] , chany_bottom_out[24] , 
         chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] , 
@@ -51713,7 +68670,8 @@
     .sram ( mux_2level_tapbuf_size12_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , 
         SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) ,
-    .out ( chanx_left_out[3] ) , .p0 ( optlc_net_199 ) ) ;
+    .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_199 ) ) ;
 sb_1__1__mux_2level_tapbuf_size12 mux_left_track_11 (
     .in ( { chany_bottom_out[11] , chany_top_in[17] , chany_bottom_out[25] , 
         chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[4] , 
@@ -51723,47 +68681,56 @@
     .sram ( mux_2level_tapbuf_size12_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 , 
         SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) ,
-    .out ( chanx_left_out[5] ) , .p0 ( optlc_net_208 ) ) ;
+    .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_208 ) ) ;
 sb_1__1__mux_2level_tapbuf_size12_mem_0 mem_top_track_6 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size10_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size12_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size12_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size12_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size12_mem_1 mem_top_track_10 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size12_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size12_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size12_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size12_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size12_mem_2 mem_right_track_6 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size10_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size12_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size12_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size12_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size12_mem_3 mem_right_track_10 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size12_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size12_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size12_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size12_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size12_mem_4 mem_bottom_track_7 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size10_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size12_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size12_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size12_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size12_mem_5 mem_bottom_track_11 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size12_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size12_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size12_5_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size12_5_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size12_mem_6 mem_left_track_7 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size10_mem_9_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size12_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size12_6_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size12_6_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size12_mem mem_left_track_11 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size12_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size12_mem_7_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size12_7_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size12_7_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size9_0 mux_top_track_28 (
     .in ( { top_left_grid_pin_46_[0] , chanx_left_out[15] , 
         chanx_right_in[21] , chanx_left_out[29] , chany_top_out[15] , 
@@ -51772,7 +68739,8 @@
     .sram ( mux_2level_tapbuf_size9_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 , 
         SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) ,
-    .out ( chany_top_out[14] ) , .p0 ( optlc_net_202 ) ) ;
+    .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_202 ) ) ;
 sb_1__1__mux_2level_tapbuf_size9_1 mux_right_track_28 (
     .in ( { chany_top_in[13] , chany_bottom_out[15] , chany_bottom_out[29] , 
         right_bottom_grid_pin_38_[0] , chany_bottom_in[2] , 
@@ -51781,7 +68749,8 @@
     .sram ( mux_2level_tapbuf_size9_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 , 
         SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) ,
-    .out ( chanx_right_out[14] ) , .p0 ( optlc_net_206 ) ) ;
+    .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_206 ) ) ;
 sb_1__1__mux_2level_tapbuf_size9_2 mux_bottom_track_29 (
     .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] , 
         chanx_left_out[15] , chanx_left_out[29] , 
@@ -51790,7 +68759,8 @@
     .sram ( mux_2level_tapbuf_size9_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 , 
         SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) ,
-    .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_206 ) ) ;
+    .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_206 ) ) ;
 sb_1__1__mux_2level_tapbuf_size9 mux_left_track_29 (
     .in ( { chany_top_in[5] , chany_bottom_out[15] , chany_bottom_out[29] , 
         chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[13] , 
@@ -51798,27 +68768,32 @@
     .sram ( mux_2level_tapbuf_size9_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 , 
         SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) ,
-    .out ( chanx_left_out[14] ) , .p0 ( optlc_net_204 ) ) ;
+    .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_204 ) ) ;
 sb_1__1__mux_2level_tapbuf_size9_mem_0 mem_top_track_28 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size10_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size9_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size9_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size9_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size9_mem_1 mem_right_track_28 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size10_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size9_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size9_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size9_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size9_mem_2 mem_bottom_track_29 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size10_mem_8_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size9_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size9_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size9_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size9_mem mem_left_track_29 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size10_mem_11_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size9_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size9_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size9_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size6_0 mux_top_track_36 (
     .in ( { top_left_grid_pin_47_[0] , chanx_left_out[16] , 
         chanx_right_in[25] , chany_top_out[16] , chanx_left_in[4] , 
@@ -51826,7 +68801,8 @@
     .sram ( mux_2level_tapbuf_size6_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 , 
         SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) ,
-    .out ( chany_top_out[18] ) , .p0 ( optlc_net_206 ) ) ;
+    .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_206 ) ) ;
 sb_1__1__mux_2level_tapbuf_size6_1 mux_top_track_44 (
     .in ( { top_left_grid_pin_48_[0] , chanx_left_out[17] , 
         chanx_right_in[29] , chany_top_out[17] , chanx_left_in[2] , 
@@ -51834,7 +68810,8 @@
     .sram ( mux_2level_tapbuf_size6_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 , 
         SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) ,
-    .out ( chany_top_out[22] ) , .p0 ( optlc_net_199 ) ) ;
+    .out ( chany_top_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_199 ) ) ;
 sb_1__1__mux_2level_tapbuf_size6_2 mux_top_track_52 (
     .in ( { top_left_grid_pin_49_[0] , chanx_right_in[0] , 
         chanx_left_out[19] , chany_top_out[19] , chanx_left_in[1] , 
@@ -51842,7 +68819,8 @@
     .sram ( mux_2level_tapbuf_size6_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 , 
         SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) ,
-    .out ( chany_top_out[26] ) , .p0 ( optlc_net_205 ) ) ;
+    .out ( chany_top_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_205 ) ) ;
 sb_1__1__mux_2level_tapbuf_size6_3 mux_right_track_36 (
     .in ( { chany_bottom_out[16] , chany_top_in[17] , 
         right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , 
@@ -51850,7 +68828,8 @@
     .sram ( mux_2level_tapbuf_size6_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 , 
         SYNOPSYS_UNCONNECTED_143 , SYNOPSYS_UNCONNECTED_144 } ) ,
-    .out ( chanx_right_out[18] ) , .p0 ( optlc_net_206 ) ) ;
+    .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_206 ) ) ;
 sb_1__1__mux_2level_tapbuf_size6_4 mux_right_track_44 (
     .in ( { chany_bottom_out[17] , chany_top_in[21] , 
         right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , 
@@ -51858,7 +68837,8 @@
     .sram ( mux_2level_tapbuf_size6_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_145 , SYNOPSYS_UNCONNECTED_146 , 
         SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 } ) ,
-    .out ( chanx_right_out[22] ) , .p0 ( optlc_net_200 ) ) ;
+    .out ( chanx_right_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_200 ) ) ;
 sb_1__1__mux_2level_tapbuf_size6_5 mux_right_track_52 (
     .in ( { chany_bottom_out[19] , chany_top_in[25] , 
         right_bottom_grid_pin_41_[0] , chany_top_out[19] , 
@@ -51866,7 +68846,8 @@
     .sram ( mux_2level_tapbuf_size6_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_149 , SYNOPSYS_UNCONNECTED_150 , 
         SYNOPSYS_UNCONNECTED_151 , SYNOPSYS_UNCONNECTED_152 } ) ,
-    .out ( chanx_right_out[26] ) , .p0 ( optlc_net_200 ) ) ;
+    .out ( chanx_right_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_200 ) ) ;
 sb_1__1__mux_2level_tapbuf_size6_6 mux_bottom_track_37 (
     .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_left_out[16] , 
         bottom_left_grid_pin_47_[0] , chanx_right_out[16] , 
@@ -51874,7 +68855,8 @@
     .sram ( mux_2level_tapbuf_size6_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 , 
         SYNOPSYS_UNCONNECTED_155 , SYNOPSYS_UNCONNECTED_156 } ) ,
-    .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_203 ) ) ;
+    .out ( chany_bottom_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_203 ) ) ;
 sb_1__1__mux_2level_tapbuf_size6_7 mux_bottom_track_45 (
     .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_left_out[17] , 
         bottom_left_grid_pin_48_[0] , chanx_right_out[17] , 
@@ -51882,14 +68864,16 @@
     .sram ( mux_2level_tapbuf_size6_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_157 , SYNOPSYS_UNCONNECTED_158 , 
         SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 } ) ,
-    .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_201 ) ) ;
+    .out ( chany_bottom_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_201 ) ) ;
 sb_1__1__mux_2level_tapbuf_size6_8 mux_bottom_track_53 (
     .in ( { chany_bottom_out[19] , chanx_left_out[19] , chanx_right_in[29] , 
         bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_right_out[19] } ) ,
     .sram ( mux_2level_tapbuf_size6_8_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_161 , SYNOPSYS_UNCONNECTED_162 , 
         SYNOPSYS_UNCONNECTED_163 , SYNOPSYS_UNCONNECTED_164 } ) ,
-    .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_201 ) ) ;
+    .out ( chany_bottom_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_201 ) ) ;
 sb_1__1__mux_2level_tapbuf_size6_9 mux_left_track_37 (
     .in ( { chany_top_in[4] , chany_bottom_out[16] , chanx_left_out[16] , 
         chany_top_out[16] , chany_bottom_in[17] , 
@@ -51897,7 +68881,8 @@
     .sram ( mux_2level_tapbuf_size6_9_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_165 , SYNOPSYS_UNCONNECTED_166 , 
         SYNOPSYS_UNCONNECTED_167 , SYNOPSYS_UNCONNECTED_168 } ) ,
-    .out ( chanx_left_out[18] ) , .p0 ( optlc_net_204 ) ) ;
+    .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_204 ) ) ;
 sb_1__1__mux_2level_tapbuf_size6_10 mux_left_track_45 (
     .in ( { chany_top_in[2] , chany_bottom_out[17] , chanx_left_out[17] , 
         chany_top_out[17] , chany_bottom_in[21] , 
@@ -51905,7 +68890,8 @@
     .sram ( mux_2level_tapbuf_size6_10_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_169 , SYNOPSYS_UNCONNECTED_170 , 
         SYNOPSYS_UNCONNECTED_171 , SYNOPSYS_UNCONNECTED_172 } ) ,
-    .out ( chanx_left_out[22] ) , .p0 ( optlc_net_205 ) ) ;
+    .out ( chanx_left_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_205 ) ) ;
 sb_1__1__mux_2level_tapbuf_size6 mux_left_track_53 (
     .in ( { chany_top_in[1] , chany_bottom_out[19] , chanx_left_out[19] , 
         chany_top_out[19] , chany_bottom_in[25] , 
@@ -51913,451 +68899,537 @@
     .sram ( mux_2level_tapbuf_size6_11_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_173 , SYNOPSYS_UNCONNECTED_174 , 
         SYNOPSYS_UNCONNECTED_175 , SYNOPSYS_UNCONNECTED_176 } ) ,
-    .out ( chanx_left_out[26] ) , .p0 ( optlc_net_201 ) ) ;
+    .out ( chanx_left_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_201 ) ) ;
 sb_1__1__mux_2level_tapbuf_size6_mem_0 mem_top_track_36 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size9_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size6_mem_1 mem_top_track_44 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size6_mem_2 mem_top_track_52 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size6_mem_3 mem_right_track_36 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size9_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size6_mem_4 mem_right_track_44 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size6_mem_5 mem_right_track_52 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_5_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_5_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size6_mem_6 mem_bottom_track_37 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size9_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_6_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_6_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size6_mem_7 mem_bottom_track_45 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_7_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_7_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_7_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size6_mem_8 mem_bottom_track_53 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_7_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_8_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_8_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_8_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size6_mem_9 mem_left_track_37 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size9_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_9_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_9_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_9_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size6_mem_10 mem_left_track_45 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_9_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_10_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_10_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_10_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__1__mux_2level_tapbuf_size6_mem mem_left_track_53 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_10_ccff_tail ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_tapbuf_size6_11_sram ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_tapbuf_size6_11_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 Test_en_N_FTB01 ( .A ( Test_en_S_in ) , 
-    .X ( Test_en_N_out ) ) ;
-sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ;
+    .X ( Test_en_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) , 
-    .X ( aps_rename_526_ ) ) ;
+    .X ( aps_rename_526_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_E_in ) , 
-    .X ( aps_rename_527_ ) ) ;
+    .X ( aps_rename_527_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__bufbuf_16 pReset_E_FTB01 ( .A ( pReset_E_in ) , 
-    .X ( pReset_E_out ) ) ;
+    .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_4 Reset_N_FTB01 ( .A ( Reset_S_in ) , 
-    .X ( Reset_N_out ) ) ;
+    .X ( Reset_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
-    .X ( prog_clk[0] ) ) ;
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[3] ) , 
-    .X ( chany_bottom_out[4] ) ) ;
+    .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[6] ) , 
-    .X ( chany_bottom_out[7] ) ) ;
+    .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[7] ) , 
-    .X ( chany_bottom_out[8] ) ) ;
+    .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[8] ) , 
-    .X ( chany_bottom_out[9] ) ) ;
+    .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[10] ) , 
-    .X ( chany_bottom_out[11] ) ) ;
+    .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[11] ) , 
-    .X ( chany_bottom_out[12] ) ) ;
+    .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[12] ) , 
-    .X ( chany_bottom_out[13] ) ) ;
+    .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[14] ) , 
-    .X ( chany_bottom_out[15] ) ) ;
+    .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_top_in[15] ) , 
-    .X ( chany_bottom_out[16] ) ) ;
+    .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_top_in[16] ) , 
-    .X ( chany_bottom_out[17] ) ) ;
+    .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chany_top_in[18] ) , 
-    .X ( chany_bottom_out[19] ) ) ;
+    .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chany_top_in[19] ) , 
-    .X ( chany_bottom_out[20] ) ) ;
+    .X ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chany_top_in[20] ) , 
-    .X ( chany_bottom_out[21] ) ) ;
+    .X ( chany_bottom_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chany_top_in[22] ) , 
-    .X ( chany_bottom_out[23] ) ) ;
+    .X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_top_in[23] ) , 
-    .X ( chany_bottom_out[24] ) ) ;
+    .X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chany_top_in[24] ) , 
-    .X ( chany_bottom_out[25] ) ) ;
+    .X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_top_in[26] ) , 
-    .X ( chany_bottom_out[27] ) ) ;
+    .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_top_in[27] ) , 
-    .X ( chany_bottom_out[28] ) ) ;
+    .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chany_top_in[28] ) , 
-    .X ( chany_bottom_out[29] ) ) ;
+    .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chanx_right_in[3] ) , 
-    .X ( chanx_left_out[4] ) ) ;
+    .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chanx_right_in[6] ) , 
-    .X ( chanx_left_out[7] ) ) ;
+    .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chanx_right_in[7] ) , 
-    .X ( chanx_left_out[8] ) ) ;
+    .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_91__90 ( .A ( chanx_right_in[8] ) , 
-    .X ( chanx_left_out[9] ) ) ;
+    .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_92__91 ( .A ( chanx_right_in[10] ) , 
-    .X ( chanx_left_out[11] ) ) ;
+    .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_93__92 ( .A ( chanx_right_in[11] ) , 
-    .X ( chanx_left_out[12] ) ) ;
+    .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_94__93 ( .A ( chanx_right_in[12] ) , 
-    .X ( chanx_left_out[13] ) ) ;
+    .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_95__94 ( .A ( chanx_right_in[14] ) , 
-    .X ( chanx_left_out[15] ) ) ;
+    .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_96__95 ( .A ( chanx_right_in[15] ) , 
-    .X ( chanx_left_out[16] ) ) ;
+    .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_97__96 ( .A ( chanx_right_in[16] ) , 
-    .X ( chanx_left_out[17] ) ) ;
+    .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_98__97 ( .A ( chanx_right_in[18] ) , 
-    .X ( chanx_left_out[19] ) ) ;
+    .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_99__98 ( .A ( chanx_right_in[19] ) , 
-    .X ( chanx_left_out[20] ) ) ;
+    .X ( chanx_left_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_100__99 ( .A ( chanx_right_in[20] ) , 
-    .X ( chanx_left_out[21] ) ) ;
+    .X ( chanx_left_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_101__100 ( .A ( chanx_right_in[22] ) , 
-    .X ( chanx_left_out[23] ) ) ;
+    .X ( chanx_left_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_102__101 ( .A ( chanx_right_in[23] ) , 
-    .X ( chanx_left_out[24] ) ) ;
+    .X ( chanx_left_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_103__102 ( .A ( chanx_right_in[24] ) , 
-    .X ( chanx_left_out[25] ) ) ;
+    .X ( chanx_left_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_104__103 ( .A ( chanx_right_in[26] ) , 
-    .X ( chanx_left_out[27] ) ) ;
+    .X ( chanx_left_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_105__104 ( .A ( chanx_right_in[27] ) , 
-    .X ( chanx_left_out[28] ) ) ;
+    .X ( chanx_left_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_106__105 ( .A ( chanx_right_in[28] ) , 
-    .X ( chanx_left_out[29] ) ) ;
+    .X ( chanx_left_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_107__106 ( .A ( chany_bottom_in[3] ) , 
-    .X ( chany_top_out[4] ) ) ;
+    .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_108__107 ( .A ( chany_bottom_in[6] ) , 
-    .X ( chany_top_out[7] ) ) ;
+    .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_109__108 ( .A ( chany_bottom_in[7] ) , 
-    .X ( chany_top_out[8] ) ) ;
+    .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_110__109 ( .A ( chany_bottom_in[8] ) , 
-    .X ( chany_top_out[9] ) ) ;
+    .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_111__110 ( .A ( chany_bottom_in[10] ) , 
-    .X ( chany_top_out[11] ) ) ;
+    .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_112__111 ( .A ( chany_bottom_in[11] ) , 
-    .X ( chany_top_out[12] ) ) ;
+    .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_113__112 ( .A ( chany_bottom_in[12] ) , 
-    .X ( chany_top_out[13] ) ) ;
+    .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_114__113 ( .A ( chany_bottom_in[14] ) , 
-    .X ( chany_top_out[15] ) ) ;
+    .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_115__114 ( .A ( chany_bottom_in[15] ) , 
-    .X ( chany_top_out[16] ) ) ;
+    .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_116__115 ( .A ( chany_bottom_in[16] ) , 
-    .X ( chany_top_out[17] ) ) ;
+    .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_117__116 ( .A ( chany_bottom_in[18] ) , 
-    .X ( chany_top_out[19] ) ) ;
+    .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_118__117 ( .A ( chany_bottom_in[19] ) , 
-    .X ( chany_top_out[20] ) ) ;
+    .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_119__118 ( .A ( chany_bottom_in[20] ) , 
-    .X ( chany_top_out[21] ) ) ;
+    .X ( chany_top_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_120__119 ( .A ( chany_bottom_in[22] ) , 
-    .X ( chany_top_out[23] ) ) ;
+    .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_121__120 ( .A ( chany_bottom_in[23] ) , 
-    .X ( chany_top_out[24] ) ) ;
+    .X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_122__121 ( .A ( chany_bottom_in[24] ) , 
-    .X ( chany_top_out[25] ) ) ;
+    .X ( chany_top_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_123__122 ( .A ( chany_bottom_in[26] ) , 
-    .X ( chany_top_out[27] ) ) ;
+    .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_124__123 ( .A ( chany_bottom_in[27] ) , 
-    .X ( chany_top_out[28] ) ) ;
+    .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_125__124 ( .A ( chany_bottom_in[28] ) , 
-    .X ( chany_top_out[29] ) ) ;
+    .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_126__125 ( .A ( chanx_left_in[3] ) , 
-    .X ( chanx_right_out[4] ) ) ;
+    .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_127__126 ( .A ( chanx_left_in[6] ) , 
-    .X ( chanx_right_out[7] ) ) ;
+    .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_128__127 ( .A ( chanx_left_in[7] ) , 
-    .X ( chanx_right_out[8] ) ) ;
+    .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_129__128 ( .A ( chanx_left_in[8] ) , 
-    .X ( chanx_right_out[9] ) ) ;
+    .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_130__129 ( .A ( chanx_left_in[10] ) , 
-    .X ( chanx_right_out[11] ) ) ;
+    .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_131__130 ( .A ( chanx_left_in[11] ) , 
-    .X ( chanx_right_out[12] ) ) ;
+    .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_132__131 ( .A ( chanx_left_in[12] ) , 
-    .X ( chanx_right_out[13] ) ) ;
+    .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_133__132 ( .A ( chanx_left_in[14] ) , 
-    .X ( chanx_right_out[15] ) ) ;
+    .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_134__133 ( .A ( chanx_left_in[15] ) , 
-    .X ( chanx_right_out[16] ) ) ;
+    .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_135__134 ( .A ( chanx_left_in[16] ) , 
-    .X ( chanx_right_out[17] ) ) ;
+    .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_136__135 ( .A ( chanx_left_in[18] ) , 
-    .X ( chanx_right_out[19] ) ) ;
+    .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_137__136 ( .A ( chanx_left_in[19] ) , 
-    .X ( chanx_right_out[20] ) ) ;
+    .X ( chanx_right_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_138__137 ( .A ( chanx_left_in[20] ) , 
-    .X ( chanx_right_out[21] ) ) ;
+    .X ( chanx_right_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_139__138 ( .A ( chanx_left_in[22] ) , 
-    .X ( chanx_right_out[23] ) ) ;
+    .X ( chanx_right_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_140__139 ( .A ( chanx_left_in[23] ) , 
-    .X ( chanx_right_out[24] ) ) ;
+    .X ( chanx_right_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_141__140 ( .A ( chanx_left_in[24] ) , 
-    .X ( chanx_right_out[25] ) ) ;
+    .X ( chanx_right_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_142__141 ( .A ( chanx_left_in[26] ) , 
-    .X ( chanx_right_out[27] ) ) ;
+    .X ( chanx_right_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_143__142 ( .A ( chanx_left_in[27] ) , 
-    .X ( chanx_right_out[28] ) ) ;
+    .X ( chanx_right_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_144__143 ( .A ( chanx_left_in[28] ) , 
-    .X ( chanx_right_out[29] ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_187 ( .A ( BUF_net_188 ) , .Y ( pReset_N_out ) ) ;
+    .X ( chanx_right_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_187 ( .A ( BUF_net_188 ) , .Y ( pReset_N_out ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_188 ( .A ( aps_rename_526_ ) , 
-    .Y ( BUF_net_188 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_189 ( .A ( BUF_net_190 ) , .Y ( pReset_W_out ) ) ;
+    .Y ( BUF_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_189 ( .A ( BUF_net_190 ) , .Y ( pReset_W_out ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_190 ( .A ( aps_rename_527_ ) , 
-    .Y ( BUF_net_190 ) ) ;
+    .Y ( BUF_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_201 ( .LO ( SYNOPSYS_UNCONNECTED_177 ) , 
-    .HI ( optlc_net_199 ) ) ;
+    .HI ( optlc_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_203 ( .LO ( SYNOPSYS_UNCONNECTED_178 ) , 
-    .HI ( optlc_net_200 ) ) ;
+    .HI ( optlc_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_205 ( .LO ( SYNOPSYS_UNCONNECTED_179 ) , 
-    .HI ( optlc_net_201 ) ) ;
+    .HI ( optlc_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_207 ( .LO ( SYNOPSYS_UNCONNECTED_180 ) , 
-    .HI ( optlc_net_202 ) ) ;
+    .HI ( optlc_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_209 ( .LO ( SYNOPSYS_UNCONNECTED_181 ) , 
-    .HI ( optlc_net_203 ) ) ;
+    .HI ( optlc_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_211 ( .LO ( SYNOPSYS_UNCONNECTED_182 ) , 
-    .HI ( optlc_net_204 ) ) ;
+    .HI ( optlc_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_213 ( .LO ( SYNOPSYS_UNCONNECTED_183 ) , 
-    .HI ( optlc_net_205 ) ) ;
+    .HI ( optlc_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_215 ( .LO ( SYNOPSYS_UNCONNECTED_184 ) , 
-    .HI ( optlc_net_206 ) ) ;
+    .HI ( optlc_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_218 ( .LO ( SYNOPSYS_UNCONNECTED_185 ) , 
-    .HI ( optlc_net_207 ) ) ;
+    .HI ( optlc_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_220 ( .LO ( SYNOPSYS_UNCONNECTED_186 ) , 
-    .HI ( optlc_net_208 ) ) ;
+    .HI ( optlc_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_39_inst_221 ( .A ( aps_rename_522_ ) , 
-    .X ( chanx_right_out[0] ) ) ;
+    .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_726 ( .A ( aps_rename_524_ ) , 
-    .X ( chany_bottom_out[3] ) ) ;
+    .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_727 ( .A ( aps_rename_525_ ) , 
-    .X ( chanx_left_out[0] ) ) ;
+    .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_728 ( .A ( aps_rename_523_ ) , 
-    .X ( chany_bottom_out[0] ) ) ;
+    .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1430 ( .A ( ZBUF_6_f_0 ) , 
-    .X ( chanx_right_out[1] ) ) ;
+    .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_35_inst_1431 ( .A ( ZBUF_35_0 ) , 
-    .X ( chany_bottom_out[10] ) ) ;
+    .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_39_inst_1432 ( .A ( ZBUF_39_0 ) , 
-    .X ( chanx_right_out[2] ) ) ;
+    .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ropt_mt_inst_1462 ( .A ( ropt_net_225 ) , 
-    .X ( chany_top_out[1] ) ) ;
+    .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size9_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_104__103 ( .A ( mem_out[3] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size9_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_103__102 ( .A ( mem_out[3] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size9_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_102__101 ( .A ( mem_out[3] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input4_mem4 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input4_mem4_10 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input4_mem4_9 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to4 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to4_6 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to4_6 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size9 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:8] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -52367,145 +69439,194 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__0__local_encoder2to4_6 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to4 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input4_mem4_9 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input4_mem4_10 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input4_mem4 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , in[8] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input4_mem4_8 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input4_mem4_7 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input4_mem4_6 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to4_5 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to4_5 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to4_4 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to4_4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size9_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:8] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -52515,146 +69636,196 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( net_net_199 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( net_net_199 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__0__local_encoder2to4_4 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to4_5 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input4_mem4_6 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input4_mem4_7 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input4_mem4_8 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , in[8] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_199 ( .A ( net_net_199 ) , .X ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_199 ( .A ( net_net_199 ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input4_mem4_5 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input4_mem4_4 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input4_mem4_3 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to4_3 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to4_3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to4_2 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to4_2 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:8] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -52664,183 +69835,246 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__0__local_encoder2to4_2 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to4_3 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input4_mem4_3 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input4_mem4_4 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input4_mem4_5 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , in[8] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_101__100 ( .A ( mem_out[3] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem2 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input4_mem4_2 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( p0 ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input4_mem4_1 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input4_mem4_0 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:3] mem ;
 input  [0:3] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_1 ( 
     .Q1 ( in[2] ) , .Q2 ( in[3] ) , .S0 ( mem[2] ) , .S0B ( mem_inv[2] ) , 
-    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[3] ) , .S1B ( mem_inv[3] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower1 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to4_1 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to4_1 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to4_0 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to4_0 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:3] data ;
 output [0:3] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__nor2_1 U13 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U14 ( .A ( data[1] ) , .Y ( data_inv[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U15 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U16 ( .A ( data_inv[2] ) , .Y ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U17 ( .A ( addr[1] ) , .B ( n9 ) , 
-    .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) ) ;
-sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) ) ;
+    .Y ( data_inv[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U18 ( .A ( n9 ) , .B ( addr[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 U19 ( .A ( addr[0] ) , .Y ( n9 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U20 ( .A ( data_inv[3] ) , .Y ( data[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U21 ( .A ( addr[1] ) , .B ( addr[0] ) , 
-    .Y ( data_inv[3] ) ) ;
+    .Y ( data_inv[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size10 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:9] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:3] local_encoder2to4_0_data ;
@@ -52851,24 +70085,28 @@
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input4_mem4_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_4_0_ ( 
     .A ( mux_2level_tapbuf_basis_input4_mem4_2_out[0] ) , 
-    .X ( aps_rename_505_ ) ) ;
+    .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__0__local_encoder2to4_0 local_encoder2to4_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to4_0_data ) , 
-    .data_inv ( local_encoder2to4_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to4_1 local_encoder2to4_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to4_1_data ) , 
-    .data_inv ( local_encoder2to4_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to4_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input4_mem4_0 mux_l1_in_0_ ( 
     .in ( in[0:3] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input4_mem4_1 mux_l1_in_1_ ( 
     .in ( in[4:7] ) , .mem ( local_encoder2to4_0_data ) , 
     .mem_inv ( local_encoder2to4_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input4_mem4_2 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input4_mem4_0_out[0] , 
         mux_2level_tapbuf_basis_input4_mem4_1_out[0] , 
@@ -52876,187 +70114,261 @@
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to4_1_data ) , 
     .mem_inv ( local_encoder2to4_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input4_mem4_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem2 mux_l1_in_2_ ( .in ( in[8:9] ) , 
     .mem ( local_encoder2to4_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to4_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_197 ( .A ( BUF_net_198 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_197 ( .A ( BUF_net_198 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_198 ( .A ( aps_rename_505_ ) , 
-    .Y ( BUF_net_198 ) ) ;
+    .Y ( BUF_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size8_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_100__99 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_100__99 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size8_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_99__98 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_99__98 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size8_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_98__97 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_98__97 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_73 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_72 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_71 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_97__96 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_97__96 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_54 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_54 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_96__95 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_96__95 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:7] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -53067,149 +70379,198 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__0__local_encoder2to3_54 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_71 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_72 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_73 mux_l1_in_2_ (
     .in ( { in[6] , in[7] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_2_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_195 ( .A ( BUF_net_196 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_195 ( .A ( BUF_net_196 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_196 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_196 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_196 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_70 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_69 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_68 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_67 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_53 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_53 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_95__94 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_95__94 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_52 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_52 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_94__93 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_94__93 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:7] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -53220,149 +70581,198 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__0__local_encoder2to3_52 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to3_53 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_67 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_68 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_69 mux_l1_in_2_ (
     .in ( { in[6] , in[7] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_70 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_2_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_193 ( .A ( BUF_net_194 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_193 ( .A ( BUF_net_194 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_194 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_194 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_194 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_66 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_65 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_64 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_63 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_51 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_51 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_93__92 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_93__92 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_50 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_50 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_92__91 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_92__91 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:7] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -53373,1386 +70783,1975 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_3_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__0__local_encoder2to3_50 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to3_51 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_63 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_64 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_65 mux_l1_in_2_ (
     .in ( { in[6] , in[7] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_66 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_2_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_191 ( .A ( BUF_net_192 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_3_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_191 ( .A ( BUF_net_192 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_192 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_192 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_3_out[0] ) , .Y ( BUF_net_192 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_91__90 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_91__90 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size2_mem_9 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_90__89 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_90__89 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size2_mem_8 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_89__88 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_89__88 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size2_mem_7 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_88__87 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_88__87 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size2_mem_6 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_87__86 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_87__86 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size2_mem_5 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_86__85 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_86__85 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size2_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_85__84 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_85__84 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size2_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_84__83 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_84__83 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size2_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_83__82 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_83__82 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size2_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_82__81 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_82__81 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size2_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_81__80 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_81__80 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_35 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_35 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_190 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_34 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_33 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_33 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_34 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_32 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_31 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_31 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_32 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_189 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_30 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_29 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_29 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_30 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_187 ( .A ( BUF_net_188 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_187 ( .A ( BUF_net_188 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_188 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_188 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_188 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_28 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_27 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_27 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_28 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_185 ( .A ( BUF_net_186 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_185 ( .A ( BUF_net_186 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_186 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_186 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_186 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_26 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_25 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_25 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_26 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_183 ( .A ( BUF_net_184 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_183 ( .A ( BUF_net_184 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_184 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_184 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_184 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_24 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_23 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_23 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_24 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_22 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_21 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_21 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_22 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_20 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_19 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_19 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_20 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_18 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_17 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_17 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_18 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_16 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_15 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_15 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_16 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_181 ( .A ( BUF_net_182 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_181 ( .A ( BUF_net_182 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_182 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_182 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_182 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_80__79 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_80__79 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size3_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_79__78 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_79__78 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size3_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_78__77 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_78__77 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size3_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_77__76 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_77__76 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size3_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_76__75 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_76__75 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_14 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_13 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_12 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_13 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_14 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_11 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_10 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_9 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_9 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_10 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_8 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_7 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_6 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_7 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_8 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_179 ( .A ( BUF_net_180 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_179 ( .A ( BUF_net_180 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_180 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_180 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_180 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_5 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_4 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_3 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_3 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_4 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_177 ( .A ( BUF_net_178 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_177 ( .A ( BUF_net_178 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_178 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_178 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_178 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_2 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_1 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem1_0 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_0 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_1 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem1_2 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_175 ( .A ( BUF_net_176 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_175 ( .A ( BUF_net_176 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_176 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_176 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_176 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_75__74 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_75__74 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size4_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_74__73 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_74__73 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size4_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_73__72 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_73__72 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size4_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_72__71 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_72__71 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size4_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_71__70 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_71__70 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size4_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_62 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_61 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_49 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_49 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_69__68 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_69__68 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_48 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_48 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_68__67 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_68__67 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -54761,102 +72760,138 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__0__local_encoder2to3_48 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to3_49 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_61 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_62 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_60 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_59 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_47 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_47 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_67__66 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_67__66 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_46 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_46 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_66__65 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_66__65 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -54865,102 +72900,138 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__0__local_encoder2to3_46 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to3_47 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_59 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_60 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_58 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_57 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_45 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_45 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_65__64 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_65__64 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_44 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_44 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_64__63 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_64__63 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -54969,102 +73040,138 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__0__local_encoder2to3_44 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to3_45 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_57 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_58 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_56 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_55 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_43 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_43 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_63__62 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_63__62 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_42 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_42 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_62__61 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_62__61 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -55073,103 +73180,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__0__local_encoder2to3_42 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to3_43 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_55 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_56 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_173 ( .A ( BUF_net_174 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_173 ( .A ( BUF_net_174 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_174 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_174 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_174 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_54 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_53 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_41 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_41 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_61__60 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_61__60 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_40 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_40 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_60__59 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_60__59 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -55178,103 +73322,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__0__local_encoder2to3_40 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to3_41 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_53 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_54 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_171 ( .A ( BUF_net_172 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_171 ( .A ( BUF_net_172 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_172 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_172 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_172 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_52 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_51 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_39 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_39 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_38 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_38 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -55283,239 +73464,340 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__0__local_encoder2to3_38 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to3_39 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_51 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_52 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_170 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size5_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size5_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_56__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_56__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size5_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size5_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size5_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size5_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_15 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_50 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_49 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_37 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_37 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_36 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_36 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -55525,125 +73807,168 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__0__local_encoder2to3_36 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to3_37 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_49 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_50 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem2_15 mux_l1_in_1_ ( 
     .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_168 ( .A ( BUF_net_169 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_168 ( .A ( BUF_net_169 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_169 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_169 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_169 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_14 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_48 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_47 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_35 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_35 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_34 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_34 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size5_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -55653,125 +73978,168 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__0__local_encoder2to3_34 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to3_35 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_47 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_48 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem2_14 mux_l1_in_1_ ( 
     .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_166 ( .A ( BUF_net_167 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_167 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_167 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_167 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_13 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_46 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_45 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_33 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_33 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_32 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_32 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size5_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -55781,125 +74149,168 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__0__local_encoder2to3_32 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to3_33 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_45 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_46 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem2_13 mux_l1_in_1_ ( 
     .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_164 ( .A ( BUF_net_165 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_165 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_165 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_165 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_12 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_44 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_43 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_31 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_31 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_30 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_30 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -55909,125 +74320,168 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__0__local_encoder2to3_30 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to3_31 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_43 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_44 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem2_12 mux_l1_in_1_ ( 
     .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_162 ( .A ( BUF_net_163 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_163 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_163 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_163 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_11 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_42 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_41 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_29 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_29 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_28 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_28 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -56037,124 +74491,166 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__0__local_encoder2to3_28 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to3_29 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_41 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_42 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem2_11 mux_l1_in_1_ ( 
     .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_10 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_40 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_39 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_27 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_27 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_26 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_26 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -56164,186 +74660,259 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__0__local_encoder2to3_26 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to3_27 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_39 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_40 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem2_10 mux_l1_in_1_ ( 
     .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_160 ( .A ( BUF_net_161 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_161 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_161 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_161 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size6_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size6_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_38 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_37 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_36 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_25 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_25 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_24 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_24 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -56353,126 +74922,169 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__0__local_encoder2to3_24 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to3_25 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_36 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_37 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_38 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_158 ( .A ( BUF_net_159 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_159 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_159 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_159 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_35 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_34 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_33 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_23 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_23 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_22 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_22 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -56482,125 +75094,167 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__0__local_encoder2to3_22 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to3_23 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_33 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_34 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_35 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_157 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_32 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_31 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_30 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_21 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_21 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_20 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_20 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -56610,369 +75264,517 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__0__local_encoder2to3_20 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to3_21 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_30 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_31 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_32 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_155 ( .A ( BUF_net_156 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_155 ( .A ( BUF_net_156 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_156 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_156 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_156 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size7_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size7_mem_8 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size7_mem_7 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size7_mem_6 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size7_mem_5 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size7_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size7_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size7_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size7_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_size7_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_254 ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1434 ( .A ( copt_net_225 ) , 
-    .X ( copt_net_220 ) ) ;
+    .X ( copt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1435 ( .A ( copt_net_223 ) , 
-    .X ( copt_net_221 ) ) ;
+    .X ( copt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1436 ( .A ( ccff_head[0] ) , 
-    .X ( copt_net_222 ) ) ;
+    .X ( copt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1437 ( .A ( copt_net_222 ) , 
-    .X ( copt_net_223 ) ) ;
+    .X ( copt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1438 ( .A ( copt_net_220 ) , 
-    .X ( copt_net_224 ) ) ;
+    .X ( copt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1439 ( .A ( copt_net_221 ) , 
-    .X ( copt_net_225 ) ) ;
+    .X ( copt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1461 ( .A ( copt_net_224 ) , 
-    .X ( ropt_net_248 ) ) ;
+    .X ( ropt_net_248 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1462 ( .A ( ropt_net_248 ) , 
-    .X ( ropt_net_249 ) ) ;
+    .X ( ropt_net_249 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1463 ( .A ( ropt_net_249 ) , 
-    .X ( ropt_net_250 ) ) ;
+    .X ( ropt_net_250 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1464 ( .A ( ropt_net_250 ) , 
-    .X ( ropt_net_251 ) ) ;
+    .X ( ropt_net_251 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1465 ( .A ( ropt_net_251 ) , 
-    .X ( ropt_net_252 ) ) ;
+    .X ( ropt_net_252 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1466 ( .A ( ropt_net_252 ) , 
-    .X ( ropt_net_253 ) ) ;
+    .X ( ropt_net_253 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1467 ( .A ( ropt_net_253 ) , 
-    .X ( ropt_net_254 ) ) ;
+    .X ( ropt_net_254 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_9 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_29 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_28 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_27 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_19 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_19 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_18 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_18 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:6] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -56983,147 +75785,195 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__0__local_encoder2to3_18 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to3_19 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_27 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_28 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_29 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem2_9 mux_l1_in_2_ (
     .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_8 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_26 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_25 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_24 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_17 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_17 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_16 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_16 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size7_8 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size7_8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:6] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -57134,148 +75984,197 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__0__local_encoder2to3_16 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to3_17 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_24 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_25 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_26 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem2_8 mux_l1_in_2_ (
     .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_153 ( .A ( BUF_net_154 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_153 ( .A ( BUF_net_154 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_154 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_154 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_154 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_7 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_23 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_22 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_21 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_15 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_15 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_14 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_14 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size7_7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:6] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -57286,147 +76185,195 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__0__local_encoder2to3_14 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to3_15 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_21 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_22 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_23 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem2_7 mux_l1_in_2_ (
     .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_6 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_20 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_19 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_18 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_13 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_13 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_12 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_12 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size7_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:6] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -57437,147 +76384,195 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__0__local_encoder2to3_12 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to3_13 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_18 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_19 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_20 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem2_6 mux_l1_in_2_ (
     .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_152 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_5 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_17 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_16 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_15 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_11 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_11 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_10 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_10 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:6] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -57588,148 +76583,197 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__0__local_encoder2to3_10 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to3_11 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_15 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_16 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_17 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem2_5 mux_l1_in_2_ (
     .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_150 ( .A ( BUF_net_151 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_150 ( .A ( BUF_net_151 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_151 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_151 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_151 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_4 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_14 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_13 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_12 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_9 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_9 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_8 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_8 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:6] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -57740,147 +76784,195 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__0__local_encoder2to3_8 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to3_9 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_12 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_13 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_14 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem2_4 mux_l1_in_2_ (
     .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_3 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_11 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_10 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_9 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_7 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_7 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_6 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_6 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:6] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -57891,147 +76983,195 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__0__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to3_7 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_9 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_10 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_11 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem2_3 mux_l1_in_2_ (
     .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_2 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_8 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_7 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_6 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_5 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_5 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_4 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:6] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -58042,147 +77182,195 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_1__0__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to3_5 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_6 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_7 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_8 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem2_2 mux_l1_in_2_ (
     .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_1 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_5 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_4 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_3 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_3 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_2 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_2 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:6] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -58193,148 +77381,197 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__0__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to3_3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_3 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_4 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_5 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem2_1 mux_l1_in_2_ (
     .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_148 ( .A ( BUF_net_149 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_148 ( .A ( BUF_net_149 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_149 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_149 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_149 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input2_mem2_0 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( p0 ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_2 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_1 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_1__0__mux_2level_tapbuf_basis_input3_mem3_0 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_1 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_1 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__local_encoder2to3_0 ( addr , data , data_inv ) ;
+module sb_1__0__local_encoder2to3_0 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_1__0__mux_2level_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_1__0__mux_2level_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:6] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -58345,35 +77582,42 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_1__0__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__local_encoder2to3_1 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_0 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_1 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input3_mem3_2 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_basis_input2_mem2_0 mux_l1_in_2_ (
     .in ( { in[6] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_147 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
@@ -58393,7 +77637,8 @@
     chanx_left_out , ccff_tail , SC_IN_TOP , SC_OUT_TOP , Test_en_S_in , 
     Test_en_N_out , pReset_S_in , pReset_E_in , pReset_W_in , pReset_N_out , 
     pReset_W_out , pReset_E_out , Reset_S_in , Reset_N_out , prog_clk_0_N_in , 
-    prog_clk_3_S_in , prog_clk_3_N_out , clk_3_S_in , clk_3_N_out ) ;
+    prog_clk_3_S_in , prog_clk_3_N_out , clk_3_S_in , clk_3_N_out , VDD , 
+    VSS ) ;
 input  [0:0] pReset ;
 input  [0:29] chany_top_in ;
 input  [0:0] top_left_grid_pin_44_ ;
@@ -58446,6 +77691,8 @@
 output prog_clk_3_N_out ;
 input  clk_3_S_in ;
 output clk_3_N_out ;
+input  VDD ;
+input  VSS ;
 
 wire ropt_net_238 ;
 wire [0:0] prog_clk ;
@@ -58545,6 +77792,8 @@
 wire [0:0] mux_2level_tapbuf_size9_mem_0_ccff_tail ;
 wire [0:0] mux_2level_tapbuf_size9_mem_1_ccff_tail ;
 wire [0:0] mux_2level_tapbuf_size9_mem_2_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 assign pReset_E_in = pReset_S_in ;
 assign pReset_E_in = pReset_W_in ;
@@ -58557,7 +77806,8 @@
     .sram ( mux_2level_tapbuf_size7_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
         SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( chany_top_out[0] ) , .p0 ( optlc_net_216 ) ) ;
+    .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_216 ) ) ;
 sb_1__0__mux_2level_tapbuf_size7_1 mux_right_track_0 (
     .in ( { chany_top_in[10] , chany_top_in[21] , 
         right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_7_[0] , 
@@ -58566,7 +77816,8 @@
     .sram ( mux_2level_tapbuf_size7_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
         SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
-    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_216 ) ) ;
+    .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_216 ) ) ;
 sb_1__0__mux_2level_tapbuf_size7_2 mux_right_track_12 (
     .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] , 
         right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_13_[0] , 
@@ -58574,7 +77825,8 @@
     .sram ( mux_2level_tapbuf_size7_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
         SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
-    .out ( chanx_right_out[6] ) , .p0 ( optlc_net_213 ) ) ;
+    .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_213 ) ) ;
 sb_1__0__mux_2level_tapbuf_size7_3 mux_right_track_20 (
     .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] , 
         right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_15_[0] , 
@@ -58582,7 +77834,8 @@
     .sram ( mux_2level_tapbuf_size7_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
         SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
-    .out ( chanx_right_out[10] ) , .p0 ( optlc_net_213 ) ) ;
+    .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_213 ) ) ;
 sb_1__0__mux_2level_tapbuf_size7_4 mux_right_track_28 (
     .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] , 
         right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_17_[0] , 
@@ -58590,7 +77843,8 @@
     .sram ( mux_2level_tapbuf_size7_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
         SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
-    .out ( chanx_right_out[14] ) , .p0 ( optlc_net_213 ) ) ;
+    .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_213 ) ) ;
 sb_1__0__mux_2level_tapbuf_size7_5 mux_left_track_3 (
     .in ( { chany_top_in[10] , chany_top_in[21] , chanx_left_out[7] , 
         chanx_left_out[21] , left_bottom_grid_pin_3_[0] , 
@@ -58598,7 +77852,8 @@
     .sram ( mux_2level_tapbuf_size7_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
         SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
-    .out ( chanx_left_out[1] ) , .p0 ( optlc_net_217 ) ) ;
+    .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_217 ) ) ;
 sb_1__0__mux_2level_tapbuf_size7_6 mux_left_track_5 (
     .in ( { chany_top_in[9] , chany_top_in[20] , chanx_left_out[8] , 
         chanx_left_out[23] , left_bottom_grid_pin_5_[0] , 
@@ -58606,7 +77861,8 @@
     .sram ( mux_2level_tapbuf_size7_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
         SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
-    .out ( chanx_left_out[2] ) , .p0 ( optlc_net_217 ) ) ;
+    .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_217 ) ) ;
 sb_1__0__mux_2level_tapbuf_size7_7 mux_left_track_13 (
     .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] , 
         chanx_left_out[12] , chanx_left_out[27] , left_bottom_grid_pin_1_[0] , 
@@ -58614,7 +77870,8 @@
     .sram ( mux_2level_tapbuf_size7_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
         SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
-    .out ( chanx_left_out[6] ) , .p0 ( optlc_net_212 ) ) ;
+    .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_212 ) ) ;
 sb_1__0__mux_2level_tapbuf_size7_8 mux_left_track_21 (
     .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] , 
         chanx_left_out[13] , chanx_left_out[28] , left_bottom_grid_pin_3_[0] , 
@@ -58622,7 +77879,8 @@
     .sram ( mux_2level_tapbuf_size7_8_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
         SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
-    .out ( chanx_left_out[10] ) , .p0 ( optlc_net_211 ) ) ;
+    .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_211 ) ) ;
 sb_1__0__mux_2level_tapbuf_size7 mux_left_track_29 (
     .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] , 
         chanx_left_out[15] , chanx_left_out[29] , left_bottom_grid_pin_5_[0] , 
@@ -58630,56 +77888,67 @@
     .sram ( mux_2level_tapbuf_size7_9_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
         SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
-    .out ( chanx_left_out[14] ) , .p0 ( optlc_net_214 ) ) ;
+    .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_214 ) ) ;
 sb_1__0__mux_2level_tapbuf_size7_mem_0 mem_top_track_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
     .ccff_tail ( mux_2level_tapbuf_size7_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size7_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size7_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size7_mem_1 mem_right_track_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_10_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size7_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size7_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size7_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size7_mem_2 mem_right_track_12 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size9_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size7_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size7_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size7_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size7_mem_3 mem_right_track_20 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size7_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size7_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size7_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size7_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size7_mem_4 mem_right_track_28 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size7_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size7_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size7_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size7_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size7_mem_5 mem_left_track_3 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size8_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size7_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size7_5_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size7_5_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size7_mem_6 mem_left_track_5 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size7_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size7_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size7_6_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size7_6_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size7_mem_7 mem_left_track_13 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size9_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size7_mem_7_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size7_7_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size7_7_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size7_mem_8 mem_left_track_21 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size7_mem_7_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size7_mem_8_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size7_8_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size7_8_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size7_mem mem_left_track_29 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size7_mem_8_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size7_mem_9_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size7_9_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size7_9_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size6_0 mux_top_track_2 (
     .in ( { chany_top_out[19] , top_left_grid_pin_48_[0] , 
         top_left_grid_pin_51_[0] , chanx_right_in[2] , chanx_left_out[7] , 
@@ -58687,7 +77956,8 @@
     .sram ( mux_2level_tapbuf_size6_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
         SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
-    .out ( chany_top_out[1] ) , .p0 ( optlc_net_219 ) ) ;
+    .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_219 ) ) ;
 sb_1__0__mux_2level_tapbuf_size6_1 mux_top_track_6 (
     .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , 
         top_left_grid_pin_50_[0] , chanx_right_in[5] , chanx_left_out[9] , 
@@ -58695,7 +77965,8 @@
     .sram ( mux_2level_tapbuf_size6_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
         SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
-    .out ( chany_top_out[3] ) , .p0 ( optlc_net_216 ) ) ;
+    .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_216 ) ) ;
 sb_1__0__mux_2level_tapbuf_size6 mux_top_track_8 (
     .in ( { chany_top_out[19] , top_left_grid_pin_48_[0] , 
         top_left_grid_pin_51_[0] , chanx_right_in[9] , chanx_left_out[11] , 
@@ -58703,330 +77974,390 @@
     .sram ( mux_2level_tapbuf_size6_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
         SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
-    .out ( chany_top_out[4] ) , .p0 ( optlc_net_219 ) ) ;
+    .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_219 ) ) ;
 sb_1__0__mux_2level_tapbuf_size6_mem_0 mem_top_track_2 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size7_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size6_mem_1 mem_top_track_6 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size5_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size6_mem mem_top_track_8 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size5_0 mux_top_track_4 (
     .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , 
         chanx_right_in[4] , chanx_left_out[8] , chanx_right_out[8] } ) ,
     .sram ( mux_2level_tapbuf_size5_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
         SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
-    .out ( chany_top_out[2] ) , .p0 ( optlc_net_216 ) ) ;
+    .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_216 ) ) ;
 sb_1__0__mux_2level_tapbuf_size5_1 mux_top_track_10 (
     .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , 
         chanx_left_out[12] , chanx_right_in[13] , chanx_right_out[12] } ) ,
     .sram ( mux_2level_tapbuf_size5_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
         SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
-    .out ( chany_top_out[5] ) , .p0 ( optlc_net_212 ) ) ;
+    .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_212 ) ) ;
 sb_1__0__mux_2level_tapbuf_size5_2 mux_right_track_36 (
     .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] , 
         right_bottom_grid_pin_7_[0] , chanx_right_out[16] } ) ,
     .sram ( mux_2level_tapbuf_size5_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
         SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
-    .out ( chanx_right_out[18] ) , .p0 ( optlc_net_213 ) ) ;
+    .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_213 ) ) ;
 sb_1__0__mux_2level_tapbuf_size5_3 mux_left_track_37 (
     .in ( { chany_top_in[3] , chany_top_in[14] , chany_top_in[25] , 
         chanx_left_out[16] , left_bottom_grid_pin_7_[0] } ) ,
     .sram ( mux_2level_tapbuf_size5_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , 
         SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
-    .out ( chanx_left_out[18] ) , .p0 ( optlc_net_212 ) ) ;
+    .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_212 ) ) ;
 sb_1__0__mux_2level_tapbuf_size5_4 mux_left_track_45 (
     .in ( { chany_top_in[2] , chany_top_in[13] , chany_top_in[24] , 
         chanx_left_out[17] , left_bottom_grid_pin_9_[0] } ) ,
     .sram ( mux_2level_tapbuf_size5_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , 
         SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
-    .out ( chanx_left_out[22] ) , .p0 ( optlc_net_219 ) ) ;
+    .out ( chanx_left_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_219 ) ) ;
 sb_1__0__mux_2level_tapbuf_size5 mux_left_track_53 (
     .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] , 
         chanx_left_out[19] , left_bottom_grid_pin_11_[0] } ) ,
     .sram ( mux_2level_tapbuf_size5_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , 
         SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
-    .out ( chanx_left_out[26] ) , .p0 ( optlc_net_219 ) ) ;
+    .out ( chanx_left_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_219 ) ) ;
 sb_1__0__mux_2level_tapbuf_size5_mem_0 mem_top_track_4 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size5_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size5_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size5_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size5_mem_1 mem_top_track_10 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size5_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size5_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size5_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size5_mem_2 mem_right_track_36 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size7_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size5_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size5_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size5_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size5_mem_3 mem_left_track_37 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size7_mem_9_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size5_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size5_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size5_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size5_mem_4 mem_left_track_45 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size5_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size5_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size5_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size5_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size5_mem mem_left_track_53 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size5_mem_4_ccff_tail ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_tapbuf_size5_5_sram ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_tapbuf_size5_5_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size4_0 mux_top_track_12 (
     .in ( { top_left_grid_pin_44_[0] , chanx_left_out[13] , 
         chanx_right_in[17] , chanx_right_out[13] } ) ,
     .sram ( mux_2level_tapbuf_size4_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , 
         SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
-    .out ( chany_top_out[6] ) , .p0 ( optlc_net_216 ) ) ;
+    .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_216 ) ) ;
 sb_1__0__mux_2level_tapbuf_size4_1 mux_top_track_14 (
     .in ( { chany_top_out[19] , chanx_left_out[15] , chanx_right_in[21] , 
         chanx_right_out[15] } ) ,
     .sram ( mux_2level_tapbuf_size4_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , 
         SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
-    .out ( chany_top_out[7] ) , .p0 ( optlc_net_213 ) ) ;
+    .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_213 ) ) ;
 sb_1__0__mux_2level_tapbuf_size4_2 mux_top_track_16 (
     .in ( { top_left_grid_pin_46_[0] , chanx_left_out[16] , 
         chanx_right_in[25] , chanx_right_out[16] } ) ,
     .sram ( mux_2level_tapbuf_size4_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , 
         SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
-    .out ( chany_top_out[8] ) , .p0 ( optlc_net_211 ) ) ;
+    .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_211 ) ) ;
 sb_1__0__mux_2level_tapbuf_size4_3 mux_top_track_18 (
     .in ( { top_left_grid_pin_47_[0] , chanx_left_out[17] , 
         chanx_right_in[29] , chanx_right_out[17] } ) ,
     .sram ( mux_2level_tapbuf_size4_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , 
         SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
-    .out ( chany_top_out[9] ) , .p0 ( optlc_net_213 ) ) ;
+    .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_213 ) ) ;
 sb_1__0__mux_2level_tapbuf_size4_4 mux_right_track_44 (
     .in ( { chany_top_in[8] , chany_top_in[19] , right_bottom_grid_pin_9_[0] , 
         chanx_right_out[17] } ) ,
     .sram ( mux_2level_tapbuf_size4_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , 
         SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
-    .out ( chanx_right_out[22] ) , .p0 ( optlc_net_213 ) ) ;
+    .out ( chanx_right_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_213 ) ) ;
 sb_1__0__mux_2level_tapbuf_size4 mux_right_track_52 (
     .in ( { chany_top_in[9] , chany_top_in[20] , 
         right_bottom_grid_pin_11_[0] , chanx_right_out[19] } ) ,
     .sram ( mux_2level_tapbuf_size4_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , 
         SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) ,
-    .out ( chanx_right_out[26] ) , .p0 ( optlc_net_213 ) ) ;
+    .out ( chanx_right_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_213 ) ) ;
 sb_1__0__mux_2level_tapbuf_size4_mem_0 mem_top_track_12 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size5_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size4_mem_1 mem_top_track_14 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size4_mem_2 mem_top_track_16 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size4_mem_3 mem_top_track_18 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size4_mem_4 mem_right_track_44 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size5_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size4_mem mem_right_track_52 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_5_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_5_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size3_0 mux_top_track_20 (
     .in ( { top_left_grid_pin_48_[0] , chanx_left_out[19] , 
         chanx_right_out[19] } ) ,
     .sram ( mux_2level_tapbuf_size3_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) ,
-    .out ( chany_top_out[10] ) , .p0 ( optlc_net_218 ) ) ;
+    .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_218 ) ) ;
 sb_1__0__mux_2level_tapbuf_size3_1 mux_top_track_22 (
     .in ( { top_left_grid_pin_49_[0] , chanx_left_out[20] , 
         chanx_right_out[20] } ) ,
     .sram ( mux_2level_tapbuf_size3_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) ,
-    .out ( chany_top_out[11] ) , .p0 ( optlc_net_214 ) ) ;
+    .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_214 ) ) ;
 sb_1__0__mux_2level_tapbuf_size3_2 mux_top_track_24 (
     .in ( { top_left_grid_pin_50_[0] , chanx_left_out[21] , 
         chanx_right_out[21] } ) ,
     .sram ( mux_2level_tapbuf_size3_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) ,
-    .out ( chany_top_out[12] ) , .p0 ( optlc_net_218 ) ) ;
+    .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_218 ) ) ;
 sb_1__0__mux_2level_tapbuf_size3_3 mux_top_track_26 (
     .in ( { top_left_grid_pin_51_[0] , chanx_left_out[23] , 
         chanx_right_out[23] } ) ,
     .sram ( mux_2level_tapbuf_size3_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) ,
-    .out ( chany_top_out[13] ) , .p0 ( optlc_net_211 ) ) ;
+    .out ( chany_top_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_211 ) ) ;
 sb_1__0__mux_2level_tapbuf_size3 mux_top_track_36 (
     .in ( { top_left_grid_pin_44_[0] , chanx_left_out[29] , 
         chanx_right_out[29] } ) ,
     .sram ( mux_2level_tapbuf_size3_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) ,
-    .out ( chany_top_out[18] ) , .p0 ( optlc_net_211 ) ) ;
+    .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_211 ) ) ;
 sb_1__0__mux_2level_tapbuf_size3_mem_0 mem_top_track_20 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size3_mem_1 mem_top_track_22 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size3_mem_2 mem_top_track_24 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size3_mem_3 mem_top_track_26 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size3_mem mem_top_track_36 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size2_0 mux_top_track_28 (
     .in ( { chanx_left_out[24] , chanx_right_out[24] } ) ,
     .sram ( mux_2level_tapbuf_size2_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) ,
-    .out ( chany_top_out[14] ) , .p0 ( optlc_net_211 ) ) ;
+    .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_211 ) ) ;
 sb_1__0__mux_2level_tapbuf_size2_1 mux_top_track_30 (
     .in ( { chanx_left_out[25] , chanx_right_out[25] } ) ,
     .sram ( mux_2level_tapbuf_size2_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) ,
-    .out ( chany_top_out[15] ) , .p0 ( optlc_net_211 ) ) ;
+    .out ( chany_top_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_211 ) ) ;
 sb_1__0__mux_2level_tapbuf_size2_2 mux_top_track_32 (
     .in ( { chanx_left_out[27] , chanx_right_out[27] } ) ,
     .sram ( mux_2level_tapbuf_size2_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) ,
-    .out ( chany_top_out[16] ) , .p0 ( optlc_net_211 ) ) ;
+    .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_211 ) ) ;
 sb_1__0__mux_2level_tapbuf_size2_3 mux_top_track_34 (
     .in ( { chanx_left_out[28] , chanx_right_out[28] } ) ,
     .sram ( mux_2level_tapbuf_size2_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) ,
-    .out ( chany_top_out[17] ) , .p0 ( optlc_net_211 ) ) ;
+    .out ( chany_top_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_211 ) ) ;
 sb_1__0__mux_2level_tapbuf_size2_4 mux_top_track_40 (
     .in ( { top_left_grid_pin_46_[0] , chanx_left_in[29] } ) ,
     .sram ( mux_2level_tapbuf_size2_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) ,
-    .out ( chany_top_out[20] ) , .p0 ( optlc_net_211 ) ) ;
+    .out ( chany_top_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_211 ) ) ;
 sb_1__0__mux_2level_tapbuf_size2_5 mux_top_track_42 (
     .in ( { top_left_grid_pin_47_[0] , chanx_left_in[25] } ) ,
     .sram ( mux_2level_tapbuf_size2_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) ,
-    .out ( chany_top_out[21] ) , .p0 ( optlc_net_218 ) ) ;
+    .out ( chany_top_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_218 ) ) ;
 sb_1__0__mux_2level_tapbuf_size2_6 mux_top_track_44 (
     .in ( { top_left_grid_pin_48_[0] , chanx_left_in[21] } ) ,
     .sram ( mux_2level_tapbuf_size2_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) ,
-    .out ( chany_top_out[22] ) , .p0 ( optlc_net_218 ) ) ;
+    .out ( chany_top_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_218 ) ) ;
 sb_1__0__mux_2level_tapbuf_size2_7 mux_top_track_46 (
     .in ( { top_left_grid_pin_49_[0] , chanx_left_in[17] } ) ,
     .sram ( mux_2level_tapbuf_size2_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) ,
-    .out ( chany_top_out[23] ) , .p0 ( optlc_net_218 ) ) ;
+    .out ( chany_top_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_218 ) ) ;
 sb_1__0__mux_2level_tapbuf_size2_8 mux_top_track_48 (
     .in ( { top_left_grid_pin_50_[0] , chanx_left_in[13] } ) ,
     .sram ( mux_2level_tapbuf_size2_8_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) ,
-    .out ( chany_top_out[24] ) , .p0 ( optlc_net_218 ) ) ;
+    .out ( chany_top_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_218 ) ) ;
 sb_1__0__mux_2level_tapbuf_size2_9 mux_top_track_50 (
     .in ( { top_left_grid_pin_51_[0] , chanx_left_in[9] } ) ,
     .sram ( mux_2level_tapbuf_size2_9_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) ,
-    .out ( chany_top_out[25] ) , .p0 ( optlc_net_218 ) ) ;
+    .out ( chany_top_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_218 ) ) ;
 sb_1__0__mux_2level_tapbuf_size2 mux_top_track_58 (
     .in ( { chanx_right_in[0] , chanx_left_in[1] } ) ,
     .sram ( mux_2level_tapbuf_size2_10_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) ,
-    .out ( chany_top_out[29] ) , .p0 ( optlc_net_211 ) ) ;
+    .out ( chany_top_out[29] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_211 ) ) ;
 sb_1__0__mux_2level_tapbuf_size2_mem_0 mem_top_track_28 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size2_mem_1 mem_top_track_30 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size2_mem_2 mem_top_track_32 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size2_mem_3 mem_top_track_34 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size2_mem_4 mem_top_track_40 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size2_mem_5 mem_top_track_42 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_5_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_5_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size2_mem_6 mem_top_track_44 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_6_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_6_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size2_mem_7 mem_top_track_46 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_7_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_7_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size2_mem_8 mem_top_track_48 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_8_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_8_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_8_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size2_mem_9 mem_top_track_50 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_8_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_9_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_9_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_9_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size2_mem mem_top_track_58 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_9_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_10_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_10_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_10_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size8_0 mux_right_track_2 (
     .in ( { chany_top_in[0] , chany_top_in[11] , chany_top_in[22] , 
         right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_9_[0] , 
@@ -59035,7 +78366,8 @@
     .sram ( mux_2level_tapbuf_size8_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 , 
         SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) ,
-    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_212 ) ) ;
+    .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_212 ) ) ;
 sb_1__0__mux_2level_tapbuf_size8_1 mux_right_track_4 (
     .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] , 
         right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] , 
@@ -59044,7 +78376,8 @@
     .sram ( mux_2level_tapbuf_size8_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 , 
         SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) ,
-    .out ( chanx_right_out[2] ) , .p0 ( optlc_net_215 ) ) ;
+    .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_215 ) ) ;
 sb_1__0__mux_2level_tapbuf_size8 mux_left_track_1 (
     .in ( { chany_top_in[0] , chany_top_in[11] , chany_top_in[22] , 
         chanx_left_out[4] , chanx_left_out[20] , left_bottom_grid_pin_1_[0] , 
@@ -59052,22 +78385,26 @@
     .sram ( mux_2level_tapbuf_size8_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 , 
         SYNOPSYS_UNCONNECTED_143 , SYNOPSYS_UNCONNECTED_144 } ) ,
-    .out ( chanx_left_out[0] ) , .p0 ( optlc_net_212 ) ) ;
+    .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_212 ) ) ;
 sb_1__0__mux_2level_tapbuf_size8_mem_0 mem_right_track_2 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size7_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size8_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size8_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size8_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size8_mem_1 mem_right_track_4 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size8_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size8_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size8_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size8_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size8_mem mem_left_track_1 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size8_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size8_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size8_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size10 mux_right_track_6 (
     .in ( { chany_top_in[2] , chany_top_in[13] , chany_top_in[24] , 
         right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , 
@@ -59077,12 +78414,14 @@
     .sram ( mux_2level_tapbuf_size10_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_145 , SYNOPSYS_UNCONNECTED_146 , 
         SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 } ) ,
-    .out ( chanx_right_out[3] ) , .p0 ( optlc_net_215 ) ) ;
+    .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_215 ) ) ;
 sb_1__0__mux_2level_tapbuf_size10_mem mem_right_track_6 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size8_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size10_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size10_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size10_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size9_0 mux_right_track_10 (
     .in ( { chany_top_in[3] , chany_top_in[14] , chany_top_in[25] , 
         right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , 
@@ -59092,7 +78431,7 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_149 , SYNOPSYS_UNCONNECTED_150 , 
         SYNOPSYS_UNCONNECTED_151 , SYNOPSYS_UNCONNECTED_152 } ) ,
     .out ( { aps_rename_506_ } ) ,
-    .p0 ( optlc_net_215 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_215 ) ) ;
 sb_1__0__mux_2level_tapbuf_size9_1 mux_left_track_7 (
     .in ( { chany_top_in[8] , chany_top_in[19] , chanx_left_out[9] , 
         chanx_left_out[24] , left_bottom_grid_pin_1_[0] , 
@@ -59101,7 +78440,8 @@
     .sram ( mux_2level_tapbuf_size9_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 , 
         SYNOPSYS_UNCONNECTED_155 , SYNOPSYS_UNCONNECTED_156 } ) ,
-    .out ( chanx_left_out[3] ) , .p0 ( optlc_net_214 ) ) ;
+    .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_214 ) ) ;
 sb_1__0__mux_2level_tapbuf_size9 mux_left_track_11 (
     .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] , 
         chanx_left_out[11] , chanx_left_out[25] , left_bottom_grid_pin_3_[0] , 
@@ -59111,2338 +78451,3267 @@
     .sram_inv ( { SYNOPSYS_UNCONNECTED_157 , SYNOPSYS_UNCONNECTED_158 , 
         SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 } ) ,
     .out ( { aps_rename_507_ } ) ,
-    .p0 ( optlc_net_217 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_217 ) ) ;
 sb_1__0__mux_2level_tapbuf_size9_mem_0 mem_right_track_10 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size10_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size9_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size9_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size9_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size9_mem_1 mem_left_track_7 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size7_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size9_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size9_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size9_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_1__0__mux_2level_tapbuf_size9_mem mem_left_track_11 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size9_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size9_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size9_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size9_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_213 ( .LO ( SYNOPSYS_UNCONNECTED_161 ) , 
-    .HI ( optlc_net_211 ) ) ;
-sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ;
+    .HI ( optlc_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) , 
-    .X ( aps_rename_508_ ) ) ;
+    .X ( aps_rename_508_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_E_in ) , 
-    .X ( net_net_204 ) ) ;
+    .X ( net_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_E_in ) , 
-    .X ( aps_rename_509_ ) ) ;
+    .X ( aps_rename_509_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_215 ( .LO ( SYNOPSYS_UNCONNECTED_162 ) , 
-    .HI ( optlc_net_212 ) ) ;
+    .HI ( optlc_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , 
-    .X ( prog_clk[0] ) ) ;
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) , 
-    .X ( aps_rename_510_ ) ) ;
+    .X ( aps_rename_510_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_S_in ) , 
-    .X ( aps_rename_511_ ) ) ;
+    .X ( aps_rename_511_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_105__104 ( .A ( top_left_grid_pin_45_[0] ) , 
-    .X ( chany_top_out[19] ) ) ;
+    .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_106__105 ( .A ( chanx_right_in[3] ) , 
-    .X ( chanx_left_out[4] ) ) ;
+    .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_107__106 ( .A ( chanx_right_in[6] ) , 
-    .X ( chanx_left_out[7] ) ) ;
+    .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_108__107 ( .A ( chanx_right_in[7] ) , 
-    .X ( chanx_left_out[8] ) ) ;
+    .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_109__108 ( .A ( chanx_right_in[8] ) , 
-    .X ( chanx_left_out[9] ) ) ;
+    .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_110__109 ( .A ( chanx_right_in[10] ) , 
-    .X ( chanx_left_out[11] ) ) ;
+    .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_111__110 ( .A ( chanx_right_in[11] ) , 
-    .X ( chanx_left_out[12] ) ) ;
+    .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_112__111 ( .A ( chanx_right_in[12] ) , 
-    .X ( chanx_left_out[13] ) ) ;
+    .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_113__112 ( .A ( chanx_right_in[14] ) , 
-    .X ( chanx_left_out[15] ) ) ;
+    .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_114__113 ( .A ( chanx_right_in[15] ) , 
-    .X ( chanx_left_out[16] ) ) ;
+    .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_115__114 ( .A ( chanx_right_in[16] ) , 
-    .X ( chanx_left_out[17] ) ) ;
+    .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_116__115 ( .A ( chanx_right_in[18] ) , 
-    .X ( chanx_left_out[19] ) ) ;
+    .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_117__116 ( .A ( chanx_right_in[19] ) , 
-    .X ( chanx_left_out[20] ) ) ;
+    .X ( chanx_left_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_118__117 ( .A ( chanx_right_in[20] ) , 
-    .X ( chanx_left_out[21] ) ) ;
+    .X ( chanx_left_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_119__118 ( .A ( chanx_right_in[22] ) , 
-    .X ( chanx_left_out[23] ) ) ;
+    .X ( chanx_left_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_120__119 ( .A ( chanx_right_in[23] ) , 
-    .X ( chanx_left_out[24] ) ) ;
+    .X ( chanx_left_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_121__120 ( .A ( chanx_right_in[24] ) , 
-    .X ( chanx_left_out[25] ) ) ;
+    .X ( chanx_left_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_122__121 ( .A ( chanx_right_in[26] ) , 
-    .X ( chanx_left_out[27] ) ) ;
+    .X ( chanx_left_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_123__122 ( .A ( chanx_right_in[27] ) , 
-    .X ( chanx_left_out[28] ) ) ;
+    .X ( chanx_left_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_124__123 ( .A ( chanx_right_in[28] ) , 
-    .X ( chanx_left_out[29] ) ) ;
+    .X ( chanx_left_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_125__124 ( .A ( chanx_left_in[2] ) , 
-    .X ( ropt_net_238 ) ) ;
+    .X ( ropt_net_238 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_126__125 ( .A ( chanx_left_in[3] ) , 
-    .X ( chanx_right_out[4] ) ) ;
+    .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_127__126 ( .A ( chanx_left_in[4] ) , 
-    .X ( chany_top_out[27] ) ) ;
+    .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_128__127 ( .A ( chanx_left_in[5] ) , 
-    .X ( chany_top_out[26] ) ) ;
+    .X ( chany_top_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_129__128 ( .A ( chanx_left_in[6] ) , 
-    .X ( chanx_right_out[7] ) ) ;
+    .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_130__129 ( .A ( chanx_left_in[7] ) , 
-    .X ( chanx_right_out[8] ) ) ;
+    .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_131__130 ( .A ( chanx_left_in[8] ) , 
-    .X ( chanx_right_out[9] ) ) ;
+    .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_132__131 ( .A ( chanx_left_in[10] ) , 
-    .X ( chanx_right_out[11] ) ) ;
+    .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_133__132 ( .A ( chanx_left_in[11] ) , 
-    .X ( chanx_right_out[12] ) ) ;
+    .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_134__133 ( .A ( chanx_left_in[12] ) , 
-    .X ( chanx_right_out[13] ) ) ;
+    .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_135__134 ( .A ( chanx_left_in[14] ) , 
-    .X ( chanx_right_out[15] ) ) ;
+    .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_136__135 ( .A ( chanx_left_in[15] ) , 
-    .X ( chanx_right_out[16] ) ) ;
+    .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_137__136 ( .A ( chanx_left_in[16] ) , 
-    .X ( chanx_right_out[17] ) ) ;
+    .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_138__137 ( .A ( chanx_left_in[18] ) , 
-    .X ( chanx_right_out[19] ) ) ;
+    .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_139__138 ( .A ( chanx_left_in[19] ) , 
-    .X ( chanx_right_out[20] ) ) ;
+    .X ( chanx_right_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_140__139 ( .A ( chanx_left_in[20] ) , 
-    .X ( chanx_right_out[21] ) ) ;
+    .X ( chanx_right_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_141__140 ( .A ( chanx_left_in[22] ) , 
-    .X ( chanx_right_out[23] ) ) ;
+    .X ( chanx_right_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_142__141 ( .A ( chanx_left_in[23] ) , 
-    .X ( chanx_right_out[24] ) ) ;
+    .X ( chanx_right_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_143__142 ( .A ( chanx_left_in[24] ) , 
-    .X ( chanx_right_out[25] ) ) ;
+    .X ( chanx_right_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_144__143 ( .A ( chanx_left_in[26] ) , 
-    .X ( chanx_right_out[27] ) ) ;
+    .X ( chanx_right_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_145__144 ( .A ( chanx_left_in[27] ) , 
-    .X ( chanx_right_out[28] ) ) ;
+    .X ( chanx_right_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_146__145 ( .A ( chanx_left_in[28] ) , 
-    .X ( chanx_right_out[29] ) ) ;
-sky130_fd_sc_hd__buf_8 FTB_147__146 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_TOP ) ) ;
+    .X ( chanx_right_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 FTB_147__146 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_TOP ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_8 BINV_R_200 ( .A ( BUF_net_201 ) , 
-    .Y ( Test_en_N_out ) ) ;
-sky130_fd_sc_hd__inv_1 BINV_R_201 ( .A ( Test_en_S_in ) , .Y ( BUF_net_201 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_202 ( .A ( BUF_net_203 ) , .Y ( pReset_N_out ) ) ;
+    .Y ( Test_en_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_201 ( .A ( Test_en_S_in ) , .Y ( BUF_net_201 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_202 ( .A ( BUF_net_203 ) , .Y ( pReset_N_out ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_203 ( .A ( aps_rename_508_ ) , 
-    .Y ( BUF_net_203 ) ) ;
+    .Y ( BUF_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_204 ( .A ( net_net_204 ) , 
-    .X ( pReset_W_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_205 ( .A ( BUF_net_206 ) , .Y ( Reset_N_out ) ) ;
-sky130_fd_sc_hd__inv_1 BINV_R_206 ( .A ( Reset_S_in ) , .Y ( BUF_net_206 ) ) ;
+    .X ( pReset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_205 ( .A ( BUF_net_206 ) , .Y ( Reset_N_out ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_206 ( .A ( Reset_S_in ) , .Y ( BUF_net_206 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_8 BINV_R_207 ( .A ( BUF_net_208 ) , 
-    .Y ( prog_clk_3_N_out ) ) ;
+    .Y ( prog_clk_3_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_208 ( .A ( aps_rename_510_ ) , 
-    .Y ( BUF_net_208 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_209 ( .A ( BUF_net_210 ) , .Y ( clk_3_N_out ) ) ;
+    .Y ( BUF_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_209 ( .A ( BUF_net_210 ) , .Y ( clk_3_N_out ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_210 ( .A ( aps_rename_511_ ) , 
-    .Y ( BUF_net_210 ) ) ;
+    .Y ( BUF_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_217 ( .LO ( SYNOPSYS_UNCONNECTED_163 ) , 
-    .HI ( optlc_net_213 ) ) ;
+    .HI ( optlc_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_219 ( .LO ( SYNOPSYS_UNCONNECTED_164 ) , 
-    .HI ( optlc_net_214 ) ) ;
+    .HI ( optlc_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_221 ( .LO ( SYNOPSYS_UNCONNECTED_165 ) , 
-    .HI ( optlc_net_215 ) ) ;
+    .HI ( optlc_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_223 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) , 
-    .HI ( optlc_net_216 ) ) ;
+    .HI ( optlc_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_225 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , 
-    .HI ( optlc_net_217 ) ) ;
+    .HI ( optlc_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_227 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , 
-    .HI ( optlc_net_218 ) ) ;
+    .HI ( optlc_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_229 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , 
-    .HI ( optlc_net_219 ) ) ;
+    .HI ( optlc_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_230 ( .A ( aps_rename_507_ ) , 
-    .X ( chanx_left_out[5] ) ) ;
+    .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_231 ( .A ( aps_rename_506_ ) , 
-    .X ( chanx_right_out[5] ) ) ;
+    .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_232 ( .A ( aps_rename_509_ ) , 
-    .X ( pReset_E_out ) ) ;
+    .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1452 ( .A ( ropt_net_238 ) , 
-    .X ( chany_top_out[28] ) ) ;
+    .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size3_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_58 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_57 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_57 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_58 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_56 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_55 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_54 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_54 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_55 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_56 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_45__44 ( .A ( copt_net_103 ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1290 ( .A ( mem_out[1] ) , 
-    .X ( copt_net_101 ) ) ;
+    .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1291 ( .A ( copt_net_101 ) , 
-    .X ( copt_net_102 ) ) ;
+    .X ( copt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1292 ( .A ( copt_net_102 ) , 
-    .X ( copt_net_103 ) ) ;
+    .X ( copt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size2_mem_25 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size2_mem_24 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size2_mem_23 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size2_mem_22 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size2_mem_21 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size2_mem_20 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size2_mem_19 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size2_mem_18 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size2_mem_17 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size2_mem_16 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size2_mem_15 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size2_mem_14 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size2_mem_13 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size2_mem_12 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size2_mem_11 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size2_mem_10 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size2_mem_9 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size2_mem_8 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size2_mem_7 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size2_mem_6 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size2_mem_5 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size2_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size2_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size2_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size2_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size2_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_53 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_52 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_52 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_53 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_51 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_50 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size2_25 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size2_25 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_50 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_51 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_87 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_87 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_87 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_49 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_48 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size2_24 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size2_24 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_48 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_49 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_47 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_46 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size2_23 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_46 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_47 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_45 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_44 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size2_22 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_44 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_45 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_43 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_42 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size2_21 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_42 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_43 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_41 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_40 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size2_20 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_40 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_41 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_39 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_38 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size2_19 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_38 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_39 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_37 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_36 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size2_18 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_36 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_37 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_35 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_34 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size2_17 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_34 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_35 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_33 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_32 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size2_16 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_32 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_33 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_31 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_30 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size2_15 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_30 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_31 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_29 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_28 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size2_14 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_28 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_29 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_27 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_26 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size2_13 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_26 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_27 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_25 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_24 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size2_12 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_24 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_25 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_23 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_22 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size2_11 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_22 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_23 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_21 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_20 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size2_10 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_20 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_21 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_6 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 BINV_R_84 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_84 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_84 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_19 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_18 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_18 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_19 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_17 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_16 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_16 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_17 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_15 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_14 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_14 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_15 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_13 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_12 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_13 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_11 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_10 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_10 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_9 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_8 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_8 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_9 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_7 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_6 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_7 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_5 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_4 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_4 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_6 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 BINV_R_81 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_81 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_81 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_3 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_2 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_2 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_3 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_1 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input2_mem1_0 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_0 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input2_mem1_1 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size4_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size4_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size4_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size4_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_size4_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_171 ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1283 ( .A ( ccff_head[0] ) , 
-    .X ( copt_net_94 ) ) ;
+    .X ( copt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1284 ( .A ( copt_net_94 ) , 
-    .X ( copt_net_95 ) ) ;
+    .X ( copt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1285 ( .A ( copt_net_95 ) , 
-    .X ( copt_net_96 ) ) ;
+    .X ( copt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1286 ( .A ( copt_net_96 ) , 
-    .X ( copt_net_97 ) ) ;
+    .X ( copt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1287 ( .A ( copt_net_97 ) , 
-    .X ( copt_net_98 ) ) ;
+    .X ( copt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1288 ( .A ( copt_net_98 ) , 
-    .X ( copt_net_99 ) ) ;
+    .X ( copt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1358 ( .A ( copt_net_99 ) , 
-    .X ( ropt_net_169 ) ) ;
+    .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1359 ( .A ( ropt_net_169 ) , 
-    .X ( ropt_net_170 ) ) ;
+    .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( ropt_net_170 ) , 
-    .X ( ropt_net_171 ) ) ;
+    .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input3_mem3 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input3_mem3_10 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__local_encoder2to3 ( addr , data , data_inv ) ;
+module sb_0__2__local_encoder2to3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__local_encoder2to3_10 ( addr , data , data_inv ) ;
+module sb_0__2__local_encoder2to3_10 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -61451,103 +81720,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__2__local_encoder2to3_10 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__2__local_encoder2to3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input3_mem3_10 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_6 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_79 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_79 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_79 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input3_mem3_9 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input3_mem3_8 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__local_encoder2to3_9 ( addr , data , data_inv ) ;
+module sb_0__2__local_encoder2to3_9 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__local_encoder2to3_8 ( addr , data , data_inv ) ;
+module sb_0__2__local_encoder2to3_8 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -61556,103 +81862,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__2__local_encoder2to3_8 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__2__local_encoder2to3_9 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input3_mem3_8 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input3_mem3_9 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_77 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_77 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_77 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input3_mem3_7 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input3_mem3_6 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__local_encoder2to3_7 ( addr , data , data_inv ) ;
+module sb_0__2__local_encoder2to3_7 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__local_encoder2to3_6 ( addr , data , data_inv ) ;
+module sb_0__2__local_encoder2to3_6 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -61661,102 +82004,138 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__2__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__2__local_encoder2to3_7 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input3_mem3_6 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input3_mem3_7 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input3_mem3_5 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input3_mem3_4 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__local_encoder2to3_5 ( addr , data , data_inv ) ;
+module sb_0__2__local_encoder2to3_5 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__local_encoder2to3_4 ( addr , data , data_inv ) ;
+module sb_0__2__local_encoder2to3_4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -61765,102 +82144,138 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__2__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__2__local_encoder2to3_5 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input3_mem3_4 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input3_mem3_5 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input3_mem3_3 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input3_mem3_2 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__local_encoder2to3_3 ( addr , data , data_inv ) ;
+module sb_0__2__local_encoder2to3_3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__local_encoder2to3_2 ( addr , data , data_inv ) ;
+module sb_0__2__local_encoder2to3_2 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -61869,103 +82284,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__2__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__2__local_encoder2to3_3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input3_mem3_2 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input3_mem3_3 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_6 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_6 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_75 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_75 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_75 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input3_mem3_1 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__2__mux_2level_tapbuf_basis_input3_mem3_0 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__local_encoder2to3_1 ( addr , data , data_inv ) ;
+module sb_0__2__local_encoder2to3_1 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__local_encoder2to3_0 ( addr , data , data_inv ) ;
+module sb_0__2__local_encoder2to3_0 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__2__mux_2level_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__2__mux_2level_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -61974,25 +82426,30 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__2__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__2__local_encoder2to3_1 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input3_mem3_0 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_basis_input3_mem3_1 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_73 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
@@ -62003,7 +82460,7 @@
     right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in , 
     bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , 
     ccff_tail , SC_IN_TOP , SC_OUT_BOT , pReset_E_in , pReset_S_out , 
-    prog_clk_0_E_in ) ;
+    prog_clk_0_E_in , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:29] chanx_right_in ;
 input  [0:0] right_top_grid_pin_1_ ;
@@ -62026,6 +82483,8 @@
 input  pReset_E_in ;
 output pReset_S_out ;
 input  prog_clk_0_E_in ;
+input  VDD ;
+input  VSS ;
 
 wire ropt_net_127 ;
 wire [0:0] prog_clk ;
@@ -62099,6 +82558,8 @@
 wire [0:0] mux_2level_tapbuf_size4_mem_3_ccff_tail ;
 wire [0:0] mux_2level_tapbuf_size4_mem_4_ccff_tail ;
 wire [0:0] mux_2level_tapbuf_size4_mem_5_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 assign prog_clk_0 = prog_clk[0] ;
 
@@ -62108,2132 +82569,2924 @@
     .sram ( mux_2level_tapbuf_size4_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
         SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_93 ) ) ;
+    .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
 sb_0__2__mux_2level_tapbuf_size4_1 mux_right_track_2 (
     .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , 
         right_bottom_grid_pin_42_[0] , chany_bottom_in[27] } ) ,
     .sram ( mux_2level_tapbuf_size4_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
         SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
-    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_93 ) ) ;
+    .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
 sb_0__2__mux_2level_tapbuf_size4_2 mux_right_track_4 (
     .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , 
         right_bottom_grid_pin_43_[0] , chany_bottom_in[26] } ) ,
     .sram ( mux_2level_tapbuf_size4_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
         SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
-    .out ( chanx_right_out[2] ) , .p0 ( optlc_net_93 ) ) ;
+    .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
 sb_0__2__mux_2level_tapbuf_size4_3 mux_right_track_6 (
     .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] , 
         right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) ,
     .sram ( mux_2level_tapbuf_size4_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
         SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
-    .out ( chanx_right_out[3] ) , .p0 ( optlc_net_93 ) ) ;
+    .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
 sb_0__2__mux_2level_tapbuf_size4_4 mux_right_track_8 (
     .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , 
         right_bottom_grid_pin_42_[0] , chany_bottom_in[24] } ) ,
     .sram ( mux_2level_tapbuf_size4_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
         SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
-    .out ( chanx_right_out[4] ) , .p0 ( optlc_net_92 ) ) ;
+    .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_92 ) ) ;
 sb_0__2__mux_2level_tapbuf_size4 mux_right_track_10 (
     .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , 
         right_bottom_grid_pin_43_[0] , chany_bottom_in[23] } ) ,
     .sram ( mux_2level_tapbuf_size4_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
         SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
-    .out ( chanx_right_out[5] ) , .p0 ( optlc_net_92 ) ) ;
+    .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_92 ) ) ;
 sb_0__2__mux_2level_tapbuf_size4_mem_0 mem_right_track_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size4_mem_1 mem_right_track_2 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size4_mem_2 mem_right_track_4 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size4_mem_3 mem_right_track_6 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size4_mem_4 mem_right_track_8 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size4_mem mem_right_track_10 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_5_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_5_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_0 mux_right_track_12 (
     .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[22] } ) ,
     .sram ( mux_2level_tapbuf_size2_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
-    .out ( chanx_right_out[6] ) , .p0 ( optlc_net_93 ) ) ;
+    .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_1 mux_right_track_14 (
     .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[21] } ) ,
     .sram ( mux_2level_tapbuf_size2_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
-    .out ( chanx_right_out[7] ) , .p0 ( optlc_net_91 ) ) ;
+    .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_91 ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_2 mux_right_track_16 (
     .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[20] } ) ,
     .sram ( mux_2level_tapbuf_size2_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
-    .out ( chanx_right_out[8] ) , .p0 ( optlc_net_91 ) ) ;
+    .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_91 ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_3 mux_right_track_18 (
     .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[19] } ) ,
     .sram ( mux_2level_tapbuf_size2_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
-    .out ( chanx_right_out[9] ) , .p0 ( optlc_net_93 ) ) ;
+    .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_4 mux_right_track_20 (
     .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[18] } ) ,
     .sram ( mux_2level_tapbuf_size2_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
-    .out ( chanx_right_out[10] ) , .p0 ( optlc_net_93 ) ) ;
+    .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_5 mux_right_track_22 (
     .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) ,
     .sram ( mux_2level_tapbuf_size2_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
-    .out ( chanx_right_out[11] ) , .p0 ( optlc_net_91 ) ) ;
+    .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_91 ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_6 mux_right_track_24 (
     .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) ,
     .sram ( mux_2level_tapbuf_size2_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
-    .out ( chanx_right_out[12] ) , .p0 ( optlc_net_93 ) ) ;
+    .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_7 mux_right_track_26 (
     .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[15] } ) ,
     .sram ( mux_2level_tapbuf_size2_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
-    .out ( chanx_right_out[13] ) , .p0 ( optlc_net_91 ) ) ;
+    .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_91 ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_8 mux_right_track_30 (
     .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) ,
     .sram ( mux_2level_tapbuf_size2_8_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
-    .out ( chanx_right_out[15] ) , .p0 ( optlc_net_93 ) ) ;
+    .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_9 mux_right_track_32 (
     .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) ,
     .sram ( mux_2level_tapbuf_size2_9_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
-    .out ( chanx_right_out[16] ) , .p0 ( optlc_net_91 ) ) ;
+    .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_91 ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_10 mux_right_track_34 (
     .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[11] } ) ,
     .sram ( mux_2level_tapbuf_size2_10_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
-    .out ( chanx_right_out[17] ) , .p0 ( optlc_net_91 ) ) ;
+    .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_91 ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_11 mux_right_track_36 (
     .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[10] } ) ,
     .sram ( mux_2level_tapbuf_size2_11_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
-    .out ( chanx_right_out[18] ) , .p0 ( optlc_net_91 ) ) ;
+    .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_91 ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_12 mux_right_track_38 (
     .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[9] } ) ,
     .sram ( mux_2level_tapbuf_size2_12_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
-    .out ( chanx_right_out[19] ) , .p0 ( optlc_net_91 ) ) ;
+    .out ( chanx_right_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_91 ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_13 mux_right_track_40 (
     .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[8] } ) ,
     .sram ( mux_2level_tapbuf_size2_13_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
-    .out ( chanx_right_out[20] ) , .p0 ( optlc_net_91 ) ) ;
+    .out ( chanx_right_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_91 ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_14 mux_right_track_42 (
     .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[7] } ) ,
     .sram ( mux_2level_tapbuf_size2_14_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) ,
-    .out ( chanx_right_out[21] ) , .p0 ( optlc_net_91 ) ) ;
+    .out ( chanx_right_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_91 ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_15 mux_right_track_44 (
     .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) ,
     .sram ( mux_2level_tapbuf_size2_15_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
-    .out ( chanx_right_out[22] ) , .p0 ( optlc_net_91 ) ) ;
+    .out ( chanx_right_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_91 ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_16 mux_right_track_46 (
     .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[5] } ) ,
     .sram ( mux_2level_tapbuf_size2_16_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) ,
-    .out ( chanx_right_out[23] ) , .p0 ( optlc_net_91 ) ) ;
+    .out ( chanx_right_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_91 ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_17 mux_right_track_48 (
     .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[4] } ) ,
     .sram ( mux_2level_tapbuf_size2_17_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
-    .out ( chanx_right_out[24] ) , .p0 ( optlc_net_93 ) ) ;
+    .out ( chanx_right_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_18 mux_right_track_50 (
     .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) ,
     .sram ( mux_2level_tapbuf_size2_18_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
-    .out ( chanx_right_out[25] ) , .p0 ( optlc_net_93 ) ) ;
+    .out ( chanx_right_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_19 mux_right_track_54 (
     .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[1] } ) ,
     .sram ( mux_2level_tapbuf_size2_19_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
-    .out ( chanx_right_out[27] ) , .p0 ( optlc_net_93 ) ) ;
+    .out ( chanx_right_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_20 mux_right_track_56 (
     .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_20_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) ,
-    .out ( chanx_right_out[28] ) , .p0 ( optlc_net_91 ) ) ;
+    .out ( chanx_right_out[28] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_91 ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_21 mux_right_track_58 (
     .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[29] } ) ,
     .sram ( mux_2level_tapbuf_size2_21_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
-    .out ( chanx_right_out[29] ) , .p0 ( optlc_net_91 ) ) ;
+    .out ( chanx_right_out[29] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_91 ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_22 mux_bottom_track_1 (
     .in ( { chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_22_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
-    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_92 ) ) ;
+    .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_92 ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_23 mux_bottom_track_7 (
     .in ( { chanx_right_in[25] , bottom_left_grid_pin_1_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_23_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
-    .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_92 ) ) ;
+    .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_92 ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_24 mux_bottom_track_13 (
     .in ( { chanx_right_in[22] , bottom_left_grid_pin_1_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_24_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
-    .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_92 ) ) ;
+    .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_92 ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_25 mux_bottom_track_29 (
     .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_25_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
-    .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_92 ) ) ;
+    .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_92 ) ) ;
 sb_0__2__mux_2level_tapbuf_size2 mux_bottom_track_45 (
     .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_26_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
-    .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_92 ) ) ;
+    .out ( chany_bottom_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_92 ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_mem_0 mem_right_track_12 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_mem_1 mem_right_track_14 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_mem_2 mem_right_track_16 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_mem_3 mem_right_track_18 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_mem_4 mem_right_track_20 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_mem_5 mem_right_track_22 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_5_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_5_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_mem_6 mem_right_track_24 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_6_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_6_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_mem_7 mem_right_track_26 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_7_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_7_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_mem_8 mem_right_track_30 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_8_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_8_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_8_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_mem_9 mem_right_track_32 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_8_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_9_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_9_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_9_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_mem_10 mem_right_track_34 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_9_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_10_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_10_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_10_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_mem_11 mem_right_track_36 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_10_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_11_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_11_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_11_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_mem_12 mem_right_track_38 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_11_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_12_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_12_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_12_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_mem_13 mem_right_track_40 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_12_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_13_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_13_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_13_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_mem_14 mem_right_track_42 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_13_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_14_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_14_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_14_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_mem_15 mem_right_track_44 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_14_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_15_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_15_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_15_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_mem_16 mem_right_track_46 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_15_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_16_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_16_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_16_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_mem_17 mem_right_track_48 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_16_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_17_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_17_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_17_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_mem_18 mem_right_track_50 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_17_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_18_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_18_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_18_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_mem_19 mem_right_track_54 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_19_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_19_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_19_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_mem_20 mem_right_track_56 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_19_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_20_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_20_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_20_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_mem_21 mem_right_track_58 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_20_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_21_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_21_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_21_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_mem_22 mem_bottom_track_1 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_21_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_22_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_22_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_22_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_mem_23 mem_bottom_track_7 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_22_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_23_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_23_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_23_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_mem_24 mem_bottom_track_13 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_23_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_24_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_24_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_24_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_mem_25 mem_bottom_track_29 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_24_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_25_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_25_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_25_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size2_mem mem_bottom_track_45 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_25_ccff_tail ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_tapbuf_size2_26_sram ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_tapbuf_size2_26_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size3_0 mux_right_track_28 (
     .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_43_[0] , 
         chany_bottom_in[14] } ) ,
     .sram ( mux_2level_tapbuf_size3_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
-    .out ( chanx_right_out[14] ) , .p0 ( optlc_net_91 ) ) ;
+    .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_91 ) ) ;
 sb_0__2__mux_2level_tapbuf_size3 mux_right_track_52 (
     .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] , 
         chany_bottom_in[2] } ) ,
     .sram ( mux_2level_tapbuf_size3_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
-    .out ( chanx_right_out[26] ) , .p0 ( optlc_net_93 ) ) ;
+    .out ( chanx_right_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_93 ) ) ;
 sb_0__2__mux_2level_tapbuf_size3_mem_0 mem_right_track_28 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__2__mux_2level_tapbuf_size3_mem mem_right_track_52 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_18_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_1_sram ) ) ;
-sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_83 ) , 
-    .HI ( optlc_net_91 ) ) ;
+    .HI ( optlc_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , 
-    .X ( prog_clk[0] ) ) ;
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[0] ) , 
-    .X ( chany_bottom_out[28] ) ) ;
+    .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[1] ) , 
-    .X ( chany_bottom_out[27] ) ) ;
+    .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[2] ) , 
-    .X ( chany_bottom_out[26] ) ) ;
+    .X ( chany_bottom_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[3] ) , 
-    .X ( chany_bottom_out[25] ) ) ;
+    .X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[4] ) , 
-    .X ( chany_bottom_out[24] ) ) ;
+    .X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[5] ) , 
-    .X ( chany_bottom_out[23] ) ) ;
+    .X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[7] ) , 
-    .X ( chany_bottom_out[21] ) ) ;
+    .X ( chany_bottom_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[8] ) , 
-    .X ( chany_bottom_out[20] ) ) ;
+    .X ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[9] ) , 
-    .X ( chany_bottom_out[19] ) ) ;
+    .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[10] ) , 
-    .X ( chany_bottom_out[18] ) ) ;
+    .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[11] ) , 
-    .X ( chany_bottom_out[17] ) ) ;
+    .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[12] ) , 
-    .X ( chany_bottom_out[16] ) ) ;
+    .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[13] ) , 
-    .X ( chany_bottom_out[15] ) ) ;
+    .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[15] ) , 
-    .X ( chany_bottom_out[13] ) ) ;
+    .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[16] ) , 
-    .X ( chany_bottom_out[12] ) ) ;
+    .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_63__62 ( .A ( chanx_right_in[17] ) , 
-    .X ( chany_bottom_out[11] ) ) ;
+    .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[18] ) , 
-    .X ( chany_bottom_out[10] ) ) ;
+    .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[19] ) , 
-    .X ( chany_bottom_out[9] ) ) ;
+    .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[20] ) , 
-    .X ( chany_bottom_out[8] ) ) ;
+    .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[21] ) , 
-    .X ( chany_bottom_out[7] ) ) ;
+    .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( chanx_right_in[23] ) , 
-    .X ( ropt_net_127 ) ) ;
+    .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[24] ) , 
-    .X ( chany_bottom_out[4] ) ) ;
+    .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[26] ) , 
-    .X ( chany_bottom_out[2] ) ) ;
+    .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[27] ) , 
-    .X ( chany_bottom_out[1] ) ) ;
+    .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[29] ) , 
-    .X ( chany_bottom_out[29] ) ) ;
-sky130_fd_sc_hd__buf_6 FTB_73__72 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( pReset_S_out ) ) ;
-sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( pReset_E_in ) , .Y ( BUF_net_90 ) ) ;
+    .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_73__72 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( pReset_S_out ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( pReset_E_in ) , .Y ( BUF_net_90 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_84 ) , 
-    .HI ( optlc_net_92 ) ) ;
+    .HI ( optlc_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_85 ) , 
-    .HI ( optlc_net_93 ) ) ;
+    .HI ( optlc_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1316 ( .A ( ropt_net_127 ) , 
-    .X ( chany_bottom_out[5] ) ) ;
+    .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_114__113 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size2_mem_6 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_113__112 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size2_mem_5 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_112__111 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size2_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_111__110 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size2_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_110__109 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size2_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_109__108 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size2_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_108__107 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size2_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_107__106 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_44 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_44 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_203 ( .A ( BUF_net_204 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_203 ( .A ( BUF_net_204 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_204 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_204 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_204 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_43 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_42 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_42 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_43 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_201 ( .A ( BUF_net_202 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_201 ( .A ( BUF_net_202 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_202 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_202 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_202 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_41 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_40 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_40 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_41 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_199 ( .A ( BUF_net_200 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_199 ( .A ( BUF_net_200 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_200 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_200 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_200 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_39 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_38 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_38 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_39 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_37 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_36 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_36 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_37 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_35 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_34 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_34 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_35 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_33 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_32 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_32 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_33 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_31 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_30 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_30 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_31 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_106__105 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size3_mem_8 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_105__104 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size3_mem_7 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_104__103 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size3_mem_6 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_103__102 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size3_mem_5 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_102__101 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size3_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_101__100 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size3_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_100__99 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_100__99 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size3_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_99__98 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_99__98 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size3_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_98__97 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_98__97 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size3_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_97__96 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_97__96 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_29 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_28 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_27 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_27 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_28 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_29 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_26 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_25 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_24 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size3_8 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size3_8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_24 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_25 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_26 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_23 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_22 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_21 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size3_7 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size3_7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_21 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_22 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_23 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_197 ( .A ( BUF_net_198 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_197 ( .A ( BUF_net_198 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_198 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_198 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_198 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_20 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_19 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_18 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size3_6 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size3_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_18 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_19 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_20 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_196 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_17 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_16 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_15 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size3_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_15 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_16 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_17 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_195 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_14 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_13 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_12 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size3_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_13 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_14 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_11 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_10 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_9 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_9 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_10 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_193 ( .A ( BUF_net_194 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_193 ( .A ( BUF_net_194 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_194 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_194 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_194 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_8 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_7 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_6 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_7 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_8 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_5 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_4 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_3 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_3 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_4 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_191 ( .A ( BUF_net_192 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_191 ( .A ( BUF_net_192 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_192 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_192 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_192 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_2 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_1 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem1_0 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_0 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_1 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem1_2 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_189 ( .A ( BUF_net_190 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_189 ( .A ( BUF_net_190 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_190 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_190 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_190 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_96__95 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_96__95 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size4_mem_10 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_95__94 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_95__94 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size4_mem_9 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_94__93 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_94__93 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size4_mem_8 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_93__92 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_93__92 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size4_mem_7 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_92__91 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_92__91 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size4_mem_6 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_91__90 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_91__90 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size4_mem_5 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_90__89 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_90__89 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size4_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_89__88 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_89__88 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size4_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_88__87 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_88__87 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size4_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_87__86 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_87__86 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size4_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_86__85 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_86__85 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size4_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_85__84 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_85__84 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_70 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_84__83 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_84__83 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_62 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_62 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_83__82 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_83__82 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -64242,103 +85495,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__local_encoder2to3_62 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_70 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_207 ( .A ( BUF_net_208 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_207 ( .A ( BUF_net_208 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_208 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_208 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_208 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_69 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_68 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_61 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_61 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_82__81 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_82__81 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_60 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_60 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_81__80 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_81__80 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size4_10 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size4_10 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -64347,103 +85637,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__local_encoder2to3_60 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_61 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_68 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_69 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_187 ( .A ( BUF_net_188 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_187 ( .A ( BUF_net_188 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_188 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_188 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_188 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_67 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_66 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_59 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_59 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_80__79 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_80__79 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_58 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_58 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_79__78 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_79__78 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size4_9 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size4_9 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -64452,103 +85779,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__local_encoder2to3_58 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_59 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_66 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_67 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_185 ( .A ( BUF_net_186 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_185 ( .A ( BUF_net_186 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_186 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_186 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_186 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_65 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_64 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_57 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_57 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_78__77 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_78__77 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_56 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_56 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_77__76 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_77__76 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size4_8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -64557,103 +85921,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__local_encoder2to3_56 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_57 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_64 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_65 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_183 ( .A ( BUF_net_184 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_183 ( .A ( BUF_net_184 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_184 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_184 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_184 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_63 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_62 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_55 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_55 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_76__75 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_76__75 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_54 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_54 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_75__74 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_75__74 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size4_7 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size4_7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -64662,103 +86063,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__local_encoder2to3_54 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_55 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_62 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_63 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_181 ( .A ( BUF_net_182 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_181 ( .A ( BUF_net_182 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_182 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_182 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_182 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_61 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_60 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_53 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_53 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_74__73 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_74__73 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_52 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_52 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_73__72 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_73__72 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size4_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -64767,103 +86205,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__local_encoder2to3_52 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_53 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_60 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_61 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_179 ( .A ( BUF_net_180 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_179 ( .A ( BUF_net_180 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_180 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_180 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_180 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_59 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_58 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_51 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_51 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_72__71 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_72__71 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_50 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_50 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_71__70 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_71__70 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size4_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -64872,103 +86347,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__local_encoder2to3_50 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_51 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_58 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_59 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_177 ( .A ( BUF_net_178 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_177 ( .A ( BUF_net_178 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_178 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_178 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_178 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_57 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_56 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_49 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_49 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_48 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_48 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_69__68 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_69__68 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -64977,103 +86489,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__local_encoder2to3_48 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_49 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_56 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_57 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_175 ( .A ( BUF_net_176 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_175 ( .A ( BUF_net_176 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_176 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_176 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_176 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_55 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_54 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_47 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_47 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_68__67 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_68__67 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_46 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_46 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_67__66 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_67__66 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -65082,103 +86631,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__local_encoder2to3_46 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_47 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_54 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_55 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_173 ( .A ( BUF_net_174 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_173 ( .A ( BUF_net_174 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_174 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_174 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_174 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_53 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_52 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_45 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_45 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_66__65 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_66__65 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_44 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_44 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_65__64 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_65__64 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -65187,103 +86773,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__local_encoder2to3_44 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_45 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_52 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_53 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_171 ( .A ( BUF_net_172 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_171 ( .A ( BUF_net_172 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_172 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_172 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_172 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_51 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_50 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_43 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_43 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_64__63 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_64__63 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_42 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_42 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_63__62 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_63__62 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -65292,103 +86915,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__local_encoder2to3_42 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_43 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_50 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_51 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_169 ( .A ( BUF_net_170 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_169 ( .A ( BUF_net_170 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_170 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_170 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_170 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_49 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_48 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_41 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_41 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_62__61 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_62__61 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_40 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_40 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_61__60 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_61__60 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -65397,360 +87057,522 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__local_encoder2to3_40 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_41 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_48 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_49 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_167 ( .A ( BUF_net_168 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_167 ( .A ( BUF_net_168 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_168 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_168 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_168 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size5_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_60__59 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_60__59 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size5_mem_10 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size5_mem_9 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size5_mem_8 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_57__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_57__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size5_mem_7 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_56__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_56__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size5_mem_6 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size5_mem_5 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size5_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size5_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size5_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size5_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size5_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem2 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_47 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_46 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_39 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_39 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_38 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_38 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -65760,125 +87582,168 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__local_encoder2to3_38 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_39 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_46 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_47 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem2 mux_l1_in_1_ ( .in ( in[3:4] ) , 
     .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_165 ( .A ( BUF_net_166 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_165 ( .A ( BUF_net_166 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_166 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_166 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_166 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem2_10 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_45 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_44 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_37 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_37 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_36 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_36 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size5_10 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size5_10 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -65888,124 +87753,166 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__1__local_encoder2to3_36 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_37 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_44 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_45 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem2_10 mux_l1_in_1_ ( 
     .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem2_9 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_43 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_42 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_35 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_35 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_34 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_34 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size5_9 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size5_9 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -66015,125 +87922,168 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__local_encoder2to3_34 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_35 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_42 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_43 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem2_9 mux_l1_in_1_ ( 
     .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_163 ( .A ( BUF_net_164 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_163 ( .A ( BUF_net_164 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_164 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_164 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_164 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem2_8 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_41 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_40 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_33 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_33 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_32 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_32 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size5_8 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size5_8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -66143,124 +88093,166 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__1__local_encoder2to3_32 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_33 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_40 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_41 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem2_8 mux_l1_in_1_ ( 
     .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem2_7 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_39 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_38 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_31 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_31 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_30 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_30 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size5_7 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size5_7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -66270,124 +88262,166 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__1__local_encoder2to3_30 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_31 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_38 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_39 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem2_7 mux_l1_in_1_ ( 
     .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem2_6 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_37 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_36 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_29 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_29 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_28 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_28 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size5_6 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size5_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -66397,125 +88431,168 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__local_encoder2to3_28 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_29 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_36 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_37 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem2_6 mux_l1_in_1_ ( 
     .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_161 ( .A ( BUF_net_162 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_161 ( .A ( BUF_net_162 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_162 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_162 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_162 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem2_5 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_35 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_34 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_27 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_27 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_26 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_26 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size5_5 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size5_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -66525,125 +88602,168 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__local_encoder2to3_26 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_27 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_34 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_35 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem2_5 mux_l1_in_1_ ( 
     .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_159 ( .A ( BUF_net_160 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_159 ( .A ( BUF_net_160 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_160 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_160 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_160 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem2_4 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_33 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_32 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_25 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_25 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_24 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_24 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size5_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -66653,124 +88773,166 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__1__local_encoder2to3_24 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_25 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_32 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_33 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem2_4 mux_l1_in_1_ ( 
     .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem2_3 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_31 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_30 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_23 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_23 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_22 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_22 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size5_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -66780,124 +88942,166 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__local_encoder2to3_22 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_23 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_30 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_31 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem2_3 mux_l1_in_1_ ( 
     .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_158 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem2_2 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_29 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_28 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_21 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_21 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_20 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_20 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -66907,124 +89111,166 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__1__local_encoder2to3_20 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_21 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_28 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_29 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem2_2 mux_l1_in_1_ ( 
     .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem2_1 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_27 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_26 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_19 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_19 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_18 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_18 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -67034,124 +89280,166 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__1__local_encoder2to3_18 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_19 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_26 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_27 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem2_1 mux_l1_in_1_ ( 
     .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input2_mem2_0 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:1] mem ;
 input  [0:1] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux2_1 sky130_uuopenfpga_cc_hd_invmux2_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .S0 ( mem[0] ) , .S0B ( mem_inv[0] ) , 
-    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) ) ;
+    .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux2_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_25 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_24 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_17 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_17 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_16 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_16 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:4] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -67161,315 +89449,437 @@
 wire [0:0] mux_2level_tapbuf_basis_input2_mem2_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__1__local_encoder2to3_16 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_17 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_24 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_25 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem2_0_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input2_mem2_0 mux_l1_in_1_ ( 
     .in ( in[3:4] ) , .mem ( local_encoder2to3_0_data[0:1] ) , 
     .mem_inv ( local_encoder2to3_0_data_inv[0:1] ) , 
-    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem2_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size6_mem_6 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size6_mem_5 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size6_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size6_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size6_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size6_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_size6_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_231 ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1411 ( .A ( ropt_net_233 ) , 
-    .X ( copt_net_216 ) ) ;
+    .X ( copt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1412 ( .A ( ropt_net_237 ) , 
-    .X ( copt_net_217 ) ) ;
+    .X ( copt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1413 ( .A ( copt_net_217 ) , 
-    .X ( copt_net_218 ) ) ;
+    .X ( copt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1414 ( .A ( copt_net_218 ) , 
-    .X ( copt_net_219 ) ) ;
+    .X ( copt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1415 ( .A ( copt_net_219 ) , 
-    .X ( copt_net_220 ) ) ;
+    .X ( copt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1416 ( .A ( ropt_net_235 ) , 
-    .X ( copt_net_221 ) ) ;
+    .X ( copt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1424 ( .A ( copt_net_221 ) , 
-    .X ( ropt_net_229 ) ) ;
+    .X ( ropt_net_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1425 ( .A ( ropt_net_229 ) , 
-    .X ( ropt_net_230 ) ) ;
+    .X ( ropt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1426 ( .A ( ropt_net_232 ) , 
-    .X ( ropt_net_231 ) ) ;
+    .X ( ropt_net_231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1427 ( .A ( ropt_net_230 ) , 
-    .X ( ropt_net_232 ) ) ;
+    .X ( ropt_net_232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1428 ( .A ( ropt_net_234 ) , 
-    .X ( ropt_net_233 ) ) ;
+    .X ( ropt_net_233 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1429 ( .A ( ccff_head[0] ) , 
-    .X ( ropt_net_234 ) ) ;
+    .X ( ropt_net_234 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_4 ropt_h_inst_1430 ( .A ( copt_net_220 ) , 
-    .X ( ropt_net_235 ) ) ;
+    .X ( ropt_net_235 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1431 ( .A ( copt_net_216 ) , 
-    .X ( ropt_net_236 ) ) ;
+    .X ( ropt_net_236 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 ropt_h_inst_1432 ( .A ( ropt_net_236 ) , 
-    .X ( ropt_net_237 ) ) ;
+    .X ( ropt_net_237 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_23 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_22 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_21 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_15 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_15 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_14 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_14 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -67479,125 +89889,167 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__1__local_encoder2to3_14 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_15 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_21 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_22 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_23 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_20 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_19 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_18 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_13 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_13 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_12 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_12 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size6_6 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size6_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -67607,125 +90059,167 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__1__local_encoder2to3_12 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_13 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_18 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_19 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_20 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_17 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_16 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_15 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_11 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_11 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_10 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_10 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size6_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -67735,125 +90229,167 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__local_encoder2to3_10 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_11 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_15 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_16 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_17 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_157 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_14 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_13 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_12 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_9 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_9 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_8 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_8 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size6_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -67863,126 +90399,169 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__local_encoder2to3_8 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_9 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_12 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_13 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_14 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_155 ( .A ( BUF_net_156 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_155 ( .A ( BUF_net_156 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_156 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_156 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_156 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_11 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_10 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_9 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_7 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_7 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_6 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_6 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size6_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -67992,126 +90571,169 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__1__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_7 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_9 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_10 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_11 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_153 ( .A ( BUF_net_154 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_153 ( .A ( BUF_net_154 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_154 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_154 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .Y ( BUF_net_154 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_8 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_7 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_6 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_5 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_5 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_4 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -68121,125 +90743,167 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__1__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_5 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_6 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_7 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_8 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_5 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_4 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_3 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_3 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_2 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_2 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -68249,125 +90913,167 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__1__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_3 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_4 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_5 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_2 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_1 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__1__mux_2level_tapbuf_basis_input3_mem3_0 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_1 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_1 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__local_encoder2to3_0 ( addr , data , data_inv ) ;
+module sb_0__1__local_encoder2to3_0 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__1__mux_2level_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__1__mux_2level_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:5] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -68377,30 +91083,36 @@
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__1__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__local_encoder2to3_1 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_0 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_1 mux_l1_in_1_ ( 
     .in ( in[3:5] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_basis_input3_mem3_2 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , 
         mux_2level_tapbuf_basis_input3_mem3_1_out[0] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
@@ -68411,7 +91123,7 @@
     right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in , 
     bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , 
     chany_bottom_out , ccff_tail , pReset_E_in , pReset_S_out , 
-    prog_clk_0_E_in ) ;
+    prog_clk_0_E_in , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:29] chany_top_in ;
 input  [0:0] top_left_grid_pin_1_ ;
@@ -68434,6 +91146,8 @@
 input  pReset_E_in ;
 output pReset_S_out ;
 input  prog_clk_0_E_in ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] prog_clk ;
 wire prog_clk_0 ;
@@ -68536,6 +91250,8 @@
 wire [0:0] mux_2level_tapbuf_size6_mem_5_ccff_tail ;
 wire [0:0] mux_2level_tapbuf_size6_mem_6_ccff_tail ;
 wire [0:0] mux_2level_tapbuf_size6_mem_7_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 assign prog_clk_0 = prog_clk[0] ;
 
@@ -68545,21 +91261,24 @@
     .sram ( mux_2level_tapbuf_size6_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
         SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( chany_top_out[0] ) , .p0 ( optlc_net_210 ) ) ;
+    .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_210 ) ) ;
 sb_0__1__mux_2level_tapbuf_size6_1 mux_top_track_6 (
     .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[15] , 
         chanx_right_in[26] , chany_top_out[9] , chany_top_out[24] } ) ,
     .sram ( mux_2level_tapbuf_size6_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , 
         SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
-    .out ( chany_top_out[3] ) , .p0 ( optlc_net_215 ) ) ;
+    .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_215 ) ) ;
 sb_0__1__mux_2level_tapbuf_size6_2 mux_top_track_12 (
     .in ( { top_left_grid_pin_1_[0] , chanx_right_in[6] , chanx_right_in[17] , 
         chanx_right_in[28] , chany_top_out[12] , chany_top_out[27] } ) ,
     .sram ( mux_2level_tapbuf_size6_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , 
         SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
-    .out ( chany_top_out[6] ) , .p0 ( optlc_net_215 ) ) ;
+    .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_215 ) ) ;
 sb_0__1__mux_2level_tapbuf_size6_3 mux_right_track_2 (
     .in ( { chany_top_in[0] , chany_bottom_out[7] , 
         right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , 
@@ -68567,7 +91286,8 @@
     .sram ( mux_2level_tapbuf_size6_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , 
         SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
-    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_213 ) ) ;
+    .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_213 ) ) ;
 sb_0__1__mux_2level_tapbuf_size6_4 mux_right_track_6 (
     .in ( { chany_top_in[2] , chany_bottom_out[9] , 
         right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , 
@@ -68575,7 +91295,8 @@
     .sram ( mux_2level_tapbuf_size6_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , 
         SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
-    .out ( chanx_right_out[3] ) , .p0 ( optlc_net_210 ) ) ;
+    .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_210 ) ) ;
 sb_0__1__mux_2level_tapbuf_size6_5 mux_right_track_8 (
     .in ( { chany_top_in[4] , chany_bottom_out[11] , 
         right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , 
@@ -68583,88 +91304,103 @@
     .sram ( mux_2level_tapbuf_size6_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , 
         SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
-    .out ( chanx_right_out[4] ) , .p0 ( optlc_net_215 ) ) ;
+    .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_215 ) ) ;
 sb_0__1__mux_2level_tapbuf_size6_6 mux_bottom_track_7 (
     .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_right_in[6] , 
         chanx_right_in[17] , chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) ,
     .sram ( mux_2level_tapbuf_size6_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , 
         SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
-    .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_211 ) ) ;
+    .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_211 ) ) ;
 sb_0__1__mux_2level_tapbuf_size6 mux_bottom_track_13 (
     .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[4] , 
         chanx_right_in[15] , chanx_right_in[26] , bottom_left_grid_pin_1_[0] } ) ,
     .sram ( mux_2level_tapbuf_size6_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , 
         SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
-    .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_211 ) ) ;
+    .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_211 ) ) ;
 sb_0__1__mux_2level_tapbuf_size6_mem_0 mem_top_track_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size6_mem_1 mem_top_track_6 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size5_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size6_mem_2 mem_top_track_12 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size5_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size6_mem_3 mem_right_track_2 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size5_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size6_mem_4 mem_right_track_6 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size5_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size6_mem_5 mem_right_track_8 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_5_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_5_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size6_mem_6 mem_bottom_track_7 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size5_mem_8_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_6_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_6_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size6_mem mem_bottom_track_13 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size5_mem_9_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size6_mem_7_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size6_7_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size6_7_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size5_0 mux_top_track_2 (
     .in ( { chanx_right_in[2] , chanx_right_in[13] , chanx_right_in[24] , 
         chany_top_out[7] , chany_top_out[21] } ) ,
     .sram ( mux_2level_tapbuf_size5_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , 
         SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
-    .out ( chany_top_out[1] ) , .p0 ( optlc_net_213 ) ) ;
+    .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_213 ) ) ;
 sb_0__1__mux_2level_tapbuf_size5_1 mux_top_track_4 (
     .in ( { chanx_right_in[3] , chanx_right_in[14] , chanx_right_in[25] , 
         chany_top_out[8] , chany_top_out[23] } ) ,
     .sram ( mux_2level_tapbuf_size5_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , 
         SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
-    .out ( chany_top_out[2] ) , .p0 ( optlc_net_213 ) ) ;
+    .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_213 ) ) ;
 sb_0__1__mux_2level_tapbuf_size5_2 mux_top_track_10 (
     .in ( { chanx_right_in[5] , chanx_right_in[16] , chanx_right_in[27] , 
         chany_top_out[11] , chany_top_out[25] } ) ,
     .sram ( mux_2level_tapbuf_size5_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , 
         SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
-    .out ( chany_top_out[5] ) , .p0 ( optlc_net_215 ) ) ;
+    .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_215 ) ) ;
 sb_0__1__mux_2level_tapbuf_size5_3 mux_top_track_20 (
     .in ( { chanx_right_in[7] , chanx_right_in[18] , chanx_right_in[29] , 
         chany_top_out[13] , chany_top_out[28] } ) ,
     .sram ( mux_2level_tapbuf_size5_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , 
         SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
-    .out ( chany_top_out[10] ) , .p0 ( optlc_net_213 ) ) ;
+    .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_213 ) ) ;
 sb_0__1__mux_2level_tapbuf_size5_4 mux_right_track_0 (
     .in ( { chany_bottom_out[4] , right_bottom_grid_pin_36_[0] , 
         right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , 
@@ -68672,7 +91408,8 @@
     .sram ( mux_2level_tapbuf_size5_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , 
         SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
-    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_210 ) ) ;
+    .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_210 ) ) ;
 sb_0__1__mux_2level_tapbuf_size5_5 mux_right_track_4 (
     .in ( { chany_top_in[1] , chany_bottom_out[8] , 
         right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , 
@@ -68680,7 +91417,8 @@
     .sram ( mux_2level_tapbuf_size5_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
         SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
-    .out ( chanx_right_out[2] ) , .p0 ( optlc_net_210 ) ) ;
+    .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_210 ) ) ;
 sb_0__1__mux_2level_tapbuf_size5_6 mux_right_track_10 (
     .in ( { chany_top_in[5] , chany_bottom_out[12] , 
         right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , 
@@ -68688,979 +91426,1257 @@
     .sram ( mux_2level_tapbuf_size5_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
         SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
-    .out ( chanx_right_out[5] ) , .p0 ( optlc_net_214 ) ) ;
+    .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_214 ) ) ;
 sb_0__1__mux_2level_tapbuf_size5_7 mux_bottom_track_1 (
     .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_right_in[9] , 
         chanx_right_in[20] , bottom_left_grid_pin_1_[0] } ) ,
     .sram ( mux_2level_tapbuf_size5_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
         SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
-    .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_211 ) ) ;
+    .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_211 ) ) ;
 sb_0__1__mux_2level_tapbuf_size5_8 mux_bottom_track_5 (
     .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chanx_right_in[7] , 
         chanx_right_in[18] , chanx_right_in[29] } ) ,
     .sram ( mux_2level_tapbuf_size5_8_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , 
         SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
-    .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_211 ) ) ;
+    .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_211 ) ) ;
 sb_0__1__mux_2level_tapbuf_size5_9 mux_bottom_track_11 (
     .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[5] , 
         chanx_right_in[16] , chanx_right_in[27] } ) ,
     .sram ( mux_2level_tapbuf_size5_9_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , 
         SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
-    .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_211 ) ) ;
+    .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_211 ) ) ;
 sb_0__1__mux_2level_tapbuf_size5_10 mux_bottom_track_21 (
     .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[3] , 
         chanx_right_in[14] , chanx_right_in[25] } ) ,
     .sram ( mux_2level_tapbuf_size5_10_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , 
         SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
-    .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_212 ) ) ;
+    .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_212 ) ) ;
 sb_0__1__mux_2level_tapbuf_size5 mux_bottom_track_29 (
     .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] , 
         chanx_right_in[13] , chanx_right_in[24] } ) ,
     .sram ( mux_2level_tapbuf_size5_11_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , 
         SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
-    .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_212 ) ) ;
+    .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_212 ) ) ;
 sb_0__1__mux_2level_tapbuf_size5_mem_0 mem_top_track_2 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size5_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size5_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size5_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size5_mem_1 mem_top_track_4 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size5_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size5_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size5_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size5_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size5_mem_2 mem_top_track_10 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size5_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size5_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size5_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size5_mem_3 mem_top_track_20 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size5_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size5_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size5_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size5_mem_4 mem_right_track_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size5_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size5_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size5_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size5_mem_5 mem_right_track_4 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size5_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size5_5_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size5_5_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size5_mem_6 mem_right_track_10 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size5_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size5_6_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size5_6_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size5_mem_7 mem_bottom_track_1 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size5_mem_7_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size5_7_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size5_7_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size5_mem_8 mem_bottom_track_5 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_9_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size5_mem_8_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size5_8_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size5_8_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size5_mem_9 mem_bottom_track_11 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size5_mem_9_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size5_9_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size5_9_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size5_mem_10 mem_bottom_track_21 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size6_mem_7_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size5_mem_10_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size5_10_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size5_10_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size5_mem mem_bottom_track_29 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size5_mem_10_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size5_mem_11_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size5_11_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size5_11_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size4_0 mux_top_track_28 (
     .in ( { chanx_right_in[8] , chanx_right_in[19] , chany_top_out[15] , 
         chany_top_out[29] } ) ,
     .sram ( mux_2level_tapbuf_size4_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , 
         SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
-    .out ( chany_top_out[14] ) , .p0 ( optlc_net_213 ) ) ;
+    .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_213 ) ) ;
 sb_0__1__mux_2level_tapbuf_size4_1 mux_top_track_52 (
     .in ( { chanx_right_in[0] , chanx_right_in[11] , chanx_right_in[22] , 
         chany_top_out[19] } ) ,
     .sram ( mux_2level_tapbuf_size4_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , 
         SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
-    .out ( chany_top_out[26] ) , .p0 ( optlc_net_213 ) ) ;
+    .out ( chany_top_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_213 ) ) ;
 sb_0__1__mux_2level_tapbuf_size4_2 mux_right_track_12 (
     .in ( { chany_top_in[9] , chany_bottom_out[13] , 
         right_bottom_grid_pin_36_[0] , chany_top_out[13] } ) ,
     .sram ( mux_2level_tapbuf_size4_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , 
         SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
-    .out ( chanx_right_out[6] ) , .p0 ( optlc_net_214 ) ) ;
+    .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_214 ) ) ;
 sb_0__1__mux_2level_tapbuf_size4_3 mux_right_track_14 (
     .in ( { chany_top_in[13] , chany_bottom_out[15] , 
         right_bottom_grid_pin_37_[0] , chany_top_out[15] } ) ,
     .sram ( mux_2level_tapbuf_size4_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , 
         SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
-    .out ( chanx_right_out[7] ) , .p0 ( optlc_net_214 ) ) ;
+    .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_214 ) ) ;
 sb_0__1__mux_2level_tapbuf_size4_4 mux_right_track_16 (
     .in ( { chany_bottom_out[16] , chany_top_in[17] , 
         right_bottom_grid_pin_38_[0] , chany_top_out[16] } ) ,
     .sram ( mux_2level_tapbuf_size4_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , 
         SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) ,
-    .out ( chanx_right_out[8] ) , .p0 ( optlc_net_210 ) ) ;
+    .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_210 ) ) ;
 sb_0__1__mux_2level_tapbuf_size4_5 mux_right_track_18 (
     .in ( { chany_bottom_out[17] , chany_top_in[21] , 
         right_bottom_grid_pin_39_[0] , chany_top_out[17] } ) ,
     .sram ( mux_2level_tapbuf_size4_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , 
         SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) ,
-    .out ( chanx_right_out[9] ) , .p0 ( optlc_net_210 ) ) ;
+    .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_210 ) ) ;
 sb_0__1__mux_2level_tapbuf_size4_6 mux_right_track_20 (
     .in ( { chany_bottom_out[19] , chany_top_in[25] , 
         right_bottom_grid_pin_40_[0] , chany_top_out[19] } ) ,
     .sram ( mux_2level_tapbuf_size4_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , 
         SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) ,
-    .out ( chanx_right_out[10] ) , .p0 ( optlc_net_214 ) ) ;
+    .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_214 ) ) ;
 sb_0__1__mux_2level_tapbuf_size4_7 mux_right_track_22 (
     .in ( { chany_bottom_out[20] , chany_top_in[29] , 
         right_bottom_grid_pin_41_[0] , chany_top_out[20] } ) ,
     .sram ( mux_2level_tapbuf_size4_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 , 
         SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) ,
-    .out ( chanx_right_out[11] ) , .p0 ( optlc_net_213 ) ) ;
+    .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_213 ) ) ;
 sb_0__1__mux_2level_tapbuf_size4_8 mux_right_track_36 (
     .in ( { chany_bottom_out[29] , right_bottom_grid_pin_40_[0] , 
         chany_top_out[29] , chany_bottom_in[29] } ) ,
     .sram ( mux_2level_tapbuf_size4_8_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 , 
         SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) ,
-    .out ( chanx_right_out[18] ) , .p0 ( optlc_net_209 ) ) ;
+    .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_209 ) ) ;
 sb_0__1__mux_2level_tapbuf_size4_9 mux_bottom_track_3 (
     .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_right_in[8] , 
         chanx_right_in[19] } ) ,
     .sram ( mux_2level_tapbuf_size4_9_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 , 
         SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) ,
-    .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_213 ) ) ;
+    .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_213 ) ) ;
 sb_0__1__mux_2level_tapbuf_size4_10 mux_bottom_track_37 (
     .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_right_in[12] , 
         chanx_right_in[23] } ) ,
     .sram ( mux_2level_tapbuf_size4_10_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 , 
         SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) ,
-    .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_212 ) ) ;
+    .out ( chany_bottom_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_212 ) ) ;
 sb_0__1__mux_2level_tapbuf_size4 mux_bottom_track_45 (
     .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_right_in[11] , 
         chanx_right_in[22] } ) ,
     .sram ( mux_2level_tapbuf_size4_11_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 , 
         SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) ,
-    .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_209 ) ) ;
+    .out ( chany_bottom_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_209 ) ) ;
 sb_0__1__mux_2level_tapbuf_size4_mem_0 mem_top_track_28 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size5_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size4_mem_1 mem_top_track_52 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size4_mem_2 mem_right_track_12 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size5_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size4_mem_3 mem_right_track_14 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size4_mem_4 mem_right_track_16 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size4_mem_5 mem_right_track_18 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_5_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_5_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size4_mem_6 mem_right_track_20 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_6_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_6_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size4_mem_7 mem_right_track_22 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_7_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_7_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_7_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size4_mem_8 mem_right_track_36 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_7_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_8_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_8_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_8_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size4_mem_9 mem_bottom_track_3 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size5_mem_7_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_9_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_9_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_9_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size4_mem_10 mem_bottom_track_37 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size5_mem_11_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_10_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_10_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_10_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size4_mem mem_bottom_track_45 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_10_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_11_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_11_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_11_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size3_0 mux_top_track_36 (
     .in ( { chanx_right_in[9] , chanx_right_in[20] , chany_top_out[16] } ) ,
     .sram ( mux_2level_tapbuf_size3_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) ,
-    .out ( chany_top_out[18] ) , .p0 ( optlc_net_212 ) ) ;
+    .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_212 ) ) ;
 sb_0__1__mux_2level_tapbuf_size3_1 mux_top_track_44 (
     .in ( { chanx_right_in[10] , chanx_right_in[21] , chany_top_out[17] } ) ,
     .sram ( mux_2level_tapbuf_size3_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) ,
-    .out ( chany_top_out[22] ) , .p0 ( optlc_net_212 ) ) ;
+    .out ( chany_top_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_212 ) ) ;
 sb_0__1__mux_2level_tapbuf_size3_2 mux_right_track_24 (
     .in ( { chany_bottom_out[21] , right_bottom_grid_pin_42_[0] , 
         chany_top_out[21] } ) ,
     .sram ( mux_2level_tapbuf_size3_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) ,
-    .out ( chanx_right_out[12] ) , .p0 ( optlc_net_212 ) ) ;
+    .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_212 ) ) ;
 sb_0__1__mux_2level_tapbuf_size3_3 mux_right_track_26 (
     .in ( { chany_bottom_out[23] , right_bottom_grid_pin_43_[0] , 
         chany_top_out[23] } ) ,
     .sram ( mux_2level_tapbuf_size3_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) ,
-    .out ( chanx_right_out[13] ) , .p0 ( optlc_net_212 ) ) ;
+    .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_212 ) ) ;
 sb_0__1__mux_2level_tapbuf_size3_4 mux_right_track_28 (
     .in ( { chany_bottom_out[24] , right_bottom_grid_pin_36_[0] , 
         chany_top_out[24] } ) ,
     .sram ( mux_2level_tapbuf_size3_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 } ) ,
-    .out ( chanx_right_out[14] ) , .p0 ( optlc_net_211 ) ) ;
+    .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_211 ) ) ;
 sb_0__1__mux_2level_tapbuf_size3_5 mux_right_track_30 (
     .in ( { chany_bottom_out[25] , right_bottom_grid_pin_37_[0] , 
         chany_top_out[25] } ) ,
     .sram ( mux_2level_tapbuf_size3_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) ,
-    .out ( chanx_right_out[15] ) , .p0 ( optlc_net_211 ) ) ;
+    .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_211 ) ) ;
 sb_0__1__mux_2level_tapbuf_size3_6 mux_right_track_32 (
     .in ( { chany_bottom_out[27] , right_bottom_grid_pin_38_[0] , 
         chany_top_out[27] } ) ,
     .sram ( mux_2level_tapbuf_size3_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 } ) ,
-    .out ( chanx_right_out[16] ) , .p0 ( optlc_net_211 ) ) ;
+    .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_211 ) ) ;
 sb_0__1__mux_2level_tapbuf_size3_7 mux_right_track_34 (
     .in ( { chany_bottom_out[28] , right_bottom_grid_pin_39_[0] , 
         chany_top_out[28] } ) ,
     .sram ( mux_2level_tapbuf_size3_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_143 , SYNOPSYS_UNCONNECTED_144 } ) ,
-    .out ( chanx_right_out[17] ) , .p0 ( optlc_net_211 ) ) ;
+    .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_211 ) ) ;
 sb_0__1__mux_2level_tapbuf_size3_8 mux_right_track_50 (
     .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] , 
         chany_bottom_in[4] } ) ,
     .sram ( mux_2level_tapbuf_size3_8_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_145 , SYNOPSYS_UNCONNECTED_146 } ) ,
-    .out ( chanx_right_out[25] ) , .p0 ( optlc_net_209 ) ) ;
+    .out ( chanx_right_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_209 ) ) ;
 sb_0__1__mux_2level_tapbuf_size3 mux_bottom_track_53 (
     .in ( { chany_bottom_out[19] , chanx_right_in[10] , chanx_right_in[21] } ) ,
     .sram ( mux_2level_tapbuf_size3_9_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 } ) ,
-    .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_209 ) ) ;
+    .out ( chany_bottom_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_209 ) ) ;
 sb_0__1__mux_2level_tapbuf_size3_mem_0 mem_top_track_36 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size3_mem_1 mem_top_track_44 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size3_mem_2 mem_right_track_24 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_7_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size3_mem_3 mem_right_track_26 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size3_mem_4 mem_right_track_28 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size3_mem_5 mem_right_track_30 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_5_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_5_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size3_mem_6 mem_right_track_32 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_6_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_6_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size3_mem_7 mem_right_track_34 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_7_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_7_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_7_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size3_mem_8 mem_right_track_50 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_8_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_8_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_8_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size3_mem mem_bottom_track_53 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_11_ccff_tail ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_tapbuf_size3_9_sram ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_tapbuf_size3_9_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size2_0 mux_right_track_38 (
     .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) ,
     .sram ( mux_2level_tapbuf_size2_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_149 , SYNOPSYS_UNCONNECTED_150 } ) ,
-    .out ( chanx_right_out[19] ) , .p0 ( optlc_net_209 ) ) ;
+    .out ( chanx_right_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_209 ) ) ;
 sb_0__1__mux_2level_tapbuf_size2_1 mux_right_track_40 (
     .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[21] } ) ,
     .sram ( mux_2level_tapbuf_size2_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_151 , SYNOPSYS_UNCONNECTED_152 } ) ,
-    .out ( chanx_right_out[20] ) , .p0 ( optlc_net_209 ) ) ;
+    .out ( chanx_right_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_209 ) ) ;
 sb_0__1__mux_2level_tapbuf_size2_2 mux_right_track_44 (
     .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) ,
     .sram ( mux_2level_tapbuf_size2_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 } ) ,
-    .out ( chanx_right_out[22] ) , .p0 ( optlc_net_209 ) ) ;
+    .out ( chanx_right_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_209 ) ) ;
 sb_0__1__mux_2level_tapbuf_size2_3 mux_right_track_46 (
     .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[9] } ) ,
     .sram ( mux_2level_tapbuf_size2_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_155 , SYNOPSYS_UNCONNECTED_156 } ) ,
-    .out ( chanx_right_out[23] ) , .p0 ( optlc_net_209 ) ) ;
+    .out ( chanx_right_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_209 ) ) ;
 sb_0__1__mux_2level_tapbuf_size2_4 mux_right_track_48 (
     .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[5] } ) ,
     .sram ( mux_2level_tapbuf_size2_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_157 , SYNOPSYS_UNCONNECTED_158 } ) ,
-    .out ( chanx_right_out[24] ) , .p0 ( optlc_net_212 ) ) ;
+    .out ( chanx_right_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_212 ) ) ;
 sb_0__1__mux_2level_tapbuf_size2_5 mux_right_track_52 (
     .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) ,
     .sram ( mux_2level_tapbuf_size2_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 } ) ,
-    .out ( chanx_right_out[26] ) , .p0 ( optlc_net_209 ) ) ;
+    .out ( chanx_right_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_209 ) ) ;
 sb_0__1__mux_2level_tapbuf_size2_6 mux_right_track_54 (
     .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[1] } ) ,
     .sram ( mux_2level_tapbuf_size2_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_161 , SYNOPSYS_UNCONNECTED_162 } ) ,
-    .out ( chanx_right_out[27] ) , .p0 ( optlc_net_209 ) ) ;
+    .out ( chanx_right_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_209 ) ) ;
 sb_0__1__mux_2level_tapbuf_size2 mux_right_track_56 (
     .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_163 , SYNOPSYS_UNCONNECTED_164 } ) ,
-    .out ( chanx_right_out[28] ) , .p0 ( optlc_net_209 ) ) ;
+    .out ( chanx_right_out[28] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_209 ) ) ;
 sb_0__1__mux_2level_tapbuf_size2_mem_0 mem_right_track_38 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_8_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size2_mem_1 mem_right_track_40 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size2_mem_2 mem_right_track_44 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size2_mem_3 mem_right_track_46 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size2_mem_4 mem_right_track_48 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size2_mem_5 mem_right_track_52 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_8_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_5_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_5_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size2_mem_6 mem_right_track_54 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_6_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_6_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__1__mux_2level_tapbuf_size2_mem mem_right_track_56 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_7_sram ) ) ;
-sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_7_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_212 ( .LO ( SYNOPSYS_UNCONNECTED_165 ) , 
-    .HI ( optlc_net_209 ) ) ;
+    .HI ( optlc_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , 
-    .X ( prog_clk[0] ) ) ;
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_115__114 ( .A ( chany_top_in[3] ) , 
-    .X ( chany_bottom_out[4] ) ) ;
+    .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_116__115 ( .A ( chany_top_in[6] ) , 
-    .X ( chany_bottom_out[7] ) ) ;
+    .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_117__116 ( .A ( chany_top_in[7] ) , 
-    .X ( chany_bottom_out[8] ) ) ;
+    .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_118__117 ( .A ( chany_top_in[8] ) , 
-    .X ( chany_bottom_out[9] ) ) ;
+    .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_119__118 ( .A ( chany_top_in[10] ) , 
-    .X ( chany_bottom_out[11] ) ) ;
+    .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_120__119 ( .A ( chany_top_in[11] ) , 
-    .X ( chany_bottom_out[12] ) ) ;
+    .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_121__120 ( .A ( chany_top_in[12] ) , 
-    .X ( chany_bottom_out[13] ) ) ;
+    .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_122__121 ( .A ( chany_top_in[14] ) , 
-    .X ( chany_bottom_out[15] ) ) ;
+    .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_123__122 ( .A ( chany_top_in[15] ) , 
-    .X ( chany_bottom_out[16] ) ) ;
+    .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_124__123 ( .A ( chany_top_in[16] ) , 
-    .X ( chany_bottom_out[17] ) ) ;
+    .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_125__124 ( .A ( chany_top_in[18] ) , 
-    .X ( chany_bottom_out[19] ) ) ;
+    .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_126__125 ( .A ( chany_top_in[19] ) , 
-    .X ( chany_bottom_out[20] ) ) ;
+    .X ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_127__126 ( .A ( chany_top_in[20] ) , 
-    .X ( chany_bottom_out[21] ) ) ;
+    .X ( chany_bottom_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_128__127 ( .A ( chany_top_in[22] ) , 
-    .X ( chany_bottom_out[23] ) ) ;
+    .X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_129__128 ( .A ( chany_top_in[23] ) , 
-    .X ( chany_bottom_out[24] ) ) ;
+    .X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_130__129 ( .A ( chany_top_in[24] ) , 
-    .X ( chany_bottom_out[25] ) ) ;
+    .X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_131__130 ( .A ( chany_top_in[26] ) , 
-    .X ( chany_bottom_out[27] ) ) ;
+    .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_132__131 ( .A ( chany_top_in[27] ) , 
-    .X ( chany_bottom_out[28] ) ) ;
+    .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_133__132 ( .A ( chany_top_in[28] ) , 
-    .X ( chany_bottom_out[29] ) ) ;
+    .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_134__133 ( .A ( chany_bottom_in[3] ) , 
-    .X ( chany_top_out[4] ) ) ;
+    .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_135__134 ( .A ( chany_bottom_in[6] ) , 
-    .X ( chany_top_out[7] ) ) ;
+    .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_136__135 ( .A ( chany_bottom_in[7] ) , 
-    .X ( chany_top_out[8] ) ) ;
+    .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_137__136 ( .A ( chany_bottom_in[8] ) , 
-    .X ( chany_top_out[9] ) ) ;
+    .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_138__137 ( .A ( chany_bottom_in[10] ) , 
-    .X ( chany_top_out[11] ) ) ;
+    .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_139__138 ( .A ( chany_bottom_in[11] ) , 
-    .X ( chany_top_out[12] ) ) ;
+    .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_140__139 ( .A ( chany_bottom_in[12] ) , 
-    .X ( chany_top_out[13] ) ) ;
+    .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_141__140 ( .A ( chany_bottom_in[14] ) , 
-    .X ( chany_top_out[15] ) ) ;
+    .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_142__141 ( .A ( chany_bottom_in[15] ) , 
-    .X ( chany_top_out[16] ) ) ;
+    .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_143__142 ( .A ( chany_bottom_in[16] ) , 
-    .X ( chany_top_out[17] ) ) ;
+    .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_144__143 ( .A ( chany_bottom_in[17] ) , 
-    .X ( chanx_right_out[21] ) ) ;
+    .X ( chanx_right_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_145__144 ( .A ( chany_bottom_in[18] ) , 
-    .X ( chany_top_out[19] ) ) ;
+    .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_146__145 ( .A ( chany_bottom_in[19] ) , 
-    .X ( chany_top_out[20] ) ) ;
+    .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_147__146 ( .A ( chany_bottom_in[20] ) , 
-    .X ( chany_top_out[21] ) ) ;
+    .X ( chany_top_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_148__147 ( .A ( chany_bottom_in[22] ) , 
-    .X ( chany_top_out[23] ) ) ;
+    .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_149__148 ( .A ( chany_bottom_in[23] ) , 
-    .X ( chany_top_out[24] ) ) ;
+    .X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_150__149 ( .A ( chany_bottom_in[24] ) , 
-    .X ( chany_top_out[25] ) ) ;
+    .X ( chany_top_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_151__150 ( .A ( chany_bottom_in[26] ) , 
-    .X ( chany_top_out[27] ) ) ;
+    .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_152__151 ( .A ( chany_bottom_in[27] ) , 
-    .X ( chany_top_out[28] ) ) ;
+    .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_153__152 ( .A ( chany_bottom_in[28] ) , 
-    .X ( chany_top_out[29] ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_205 ( .A ( BUF_net_206 ) , .Y ( pReset_S_out ) ) ;
-sky130_fd_sc_hd__inv_1 BINV_R_206 ( .A ( pReset_E_in ) , .Y ( BUF_net_206 ) ) ;
+    .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_205 ( .A ( BUF_net_206 ) , .Y ( pReset_S_out ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_206 ( .A ( pReset_E_in ) , .Y ( BUF_net_206 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_214 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) , 
-    .HI ( optlc_net_210 ) ) ;
+    .HI ( optlc_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_216 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , 
-    .HI ( optlc_net_211 ) ) ;
+    .HI ( optlc_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_218 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , 
-    .HI ( optlc_net_212 ) ) ;
+    .HI ( optlc_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_221 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , 
-    .HI ( optlc_net_213 ) ) ;
+    .HI ( optlc_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_223 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , 
-    .HI ( optlc_net_214 ) ) ;
+    .HI ( optlc_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_225 ( .LO ( SYNOPSYS_UNCONNECTED_171 ) , 
-    .HI ( optlc_net_215 ) ) ;
+    .HI ( optlc_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size3_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size3_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_59 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_58 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_58 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_59 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_94 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_94 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .Y ( BUF_net_94 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_57 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_56 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_55 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_55 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_56 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_57 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_54 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_53 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_52 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_2_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_2_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_52 mux_l1_in_0_ ( 
     .in ( in[0:1] ) , .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_53 mux_l1_in_1_ (
     .in ( { in[2] , SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_54 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         mux_2level_tapbuf_basis_input2_mem1_1_out[0] } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_2_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size4_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size4_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size4_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size4_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size4_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:3] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input3_mem3 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input3_mem3_10 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__local_encoder2to3 ( addr , data , data_inv ) ;
+module sb_0__0__local_encoder2to3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__local_encoder2to3_10 ( addr , data , data_inv ) ;
+module sb_0__0__local_encoder2to3_10 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -69669,103 +92685,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__0__local_encoder2to3_10 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__0__local_encoder2to3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input3_mem3_10 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input3_mem3 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_92 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_92 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_92 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input3_mem3_9 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input3_mem3_8 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__local_encoder2to3_9 ( addr , data , data_inv ) ;
+module sb_0__0__local_encoder2to3_9 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__local_encoder2to3_8 ( addr , data , data_inv ) ;
+module sb_0__0__local_encoder2to3_8 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -69774,102 +92827,138 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__0__local_encoder2to3_8 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__0__local_encoder2to3_9 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input3_mem3_8 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input3_mem3_9 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input3_mem3_7 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input3_mem3_6 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__local_encoder2to3_7 ( addr , data , data_inv ) ;
+module sb_0__0__local_encoder2to3_7 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__local_encoder2to3_6 ( addr , data , data_inv ) ;
+module sb_0__0__local_encoder2to3_6 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -69878,103 +92967,140 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__0__local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__0__local_encoder2to3_7 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input3_mem3_6 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input3_mem3_7 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_90 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_90 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .Y ( BUF_net_90 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input3_mem3_5 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input3_mem3_4 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__local_encoder2to3_5 ( addr , data , data_inv ) ;
+module sb_0__0__local_encoder2to3_5 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__local_encoder2to3_4 ( addr , data , data_inv ) ;
+module sb_0__0__local_encoder2to3_4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -69983,102 +93109,138 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__0__local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__0__local_encoder2to3_5 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input3_mem3_4 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input3_mem3_5 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input3_mem3_3 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input3_mem3_2 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__local_encoder2to3_3 ( addr , data , data_inv ) ;
+module sb_0__0__local_encoder2to3_3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__local_encoder2to3_2 ( addr , data , data_inv ) ;
+module sb_0__0__local_encoder2to3_2 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -70087,102 +93249,138 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__0__local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__0__local_encoder2to3_3 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input3_mem3_2 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input3_mem3_3 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input3_mem3_1 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_2 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input3_mem3_0 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] out_inv ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( in[2] ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out_inv[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_uuopenfpga_cc_hd_invmux3_1_inv_follower0 ( 
-    .A ( out_inv[0] ) , .Y ( out[0] ) ) ;
+    .A ( out_inv[0] ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__local_encoder2to3_1 ( addr , data , data_inv ) ;
+module sb_0__0__local_encoder2to3_1 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__local_encoder2to3_0 ( addr , data , data_inv ) ;
+module sb_0__0__local_encoder2to3_0 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:3] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
@@ -70191,1774 +93389,2514 @@
 wire [0:2] local_encoder2to3_1_data_inv ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input3_mem3_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__0__local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram[0:1] ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__0__local_encoder2to3_1 local_encoder2to3_1_ ( .addr ( sram[2:3] ) , 
     .data ( local_encoder2to3_1_data ) , 
-    .data_inv ( local_encoder2to3_1_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_1_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input3_mem3_0 mux_l1_in_0_ ( 
     .in ( in[0:2] ) , .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input3_mem3_1 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input3_mem3_0_out[0] , in[3] , 
         SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_1_data ) , 
     .mem_inv ( local_encoder2to3_1_data_inv ) , 
-    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input3_mem3_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( 
-    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input3_mem3_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( copt_net_114 ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1301 ( .A ( mem_out[1] ) , 
-    .X ( copt_net_110 ) ) ;
+    .X ( copt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1304 ( .A ( copt_net_110 ) , 
-    .X ( copt_net_113 ) ) ;
+    .X ( copt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1305 ( .A ( copt_net_113 ) , 
-    .X ( copt_net_114 ) ) ;
+    .X ( copt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size2_mem_24 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size2_mem_23 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size2_mem_22 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size2_mem_21 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size2_mem_20 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size2_mem_19 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size2_mem_18 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size2_mem_17 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size2_mem_16 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size2_mem_15 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size2_mem_14 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size2_mem_13 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size2_mem_12 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size2_mem_11 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size2_mem_10 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size2_mem_9 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size2_mem_8 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size2_mem_7 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size2_mem_6 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size2_mem_5 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size2_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size2_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size2_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size2_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_size2_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_174 ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1294 ( .A ( copt_net_105 ) , 
-    .X ( copt_net_103 ) ) ;
+    .X ( copt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1295 ( .A ( copt_net_103 ) , 
-    .X ( copt_net_104 ) ) ;
+    .X ( copt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1296 ( .A ( ccff_head[0] ) , 
-    .X ( copt_net_105 ) ) ;
+    .X ( copt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1297 ( .A ( copt_net_104 ) , 
-    .X ( copt_net_106 ) ) ;
+    .X ( copt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1298 ( .A ( copt_net_106 ) , 
-    .X ( copt_net_107 ) ) ;
+    .X ( copt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1299 ( .A ( copt_net_107 ) , 
-    .X ( copt_net_108 ) ) ;
+    .X ( copt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1363 ( .A ( copt_net_108 ) , 
-    .X ( ropt_net_173 ) ) ;
+    .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1364 ( .A ( ropt_net_175 ) , 
-    .X ( ropt_net_174 ) ) ;
+    .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( ropt_net_173 ) , 
-    .X ( ropt_net_175 ) ) ;
+    .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_51 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_50 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_50 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_51 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_49 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_48 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size2_24 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size2_24 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_48 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_49 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_47 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_46 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size2_23 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_46 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_47 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_45 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_44 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size2_22 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_44 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_45 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_43 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_42 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size2_21 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_42 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_43 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_41 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_40 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size2_20 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_40 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_41 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_87 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_87 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_87 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_39 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_38 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size2_19 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_38 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_39 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_37 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_36 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size2_18 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_36 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_37 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_35 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_34 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size2_17 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_34 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_35 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_85 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_85 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_85 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_33 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_32 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size2_16 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_32 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_33 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_31 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_30 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size2_15 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_30 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_31 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_83 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_83 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_83 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_29 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_28 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size2_14 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_28 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_29 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_27 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_26 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size2_13 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_26 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_27 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_81 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_81 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_81 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_25 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_24 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size2_12 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_24 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_25 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_96 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_96 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_96 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_23 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_22 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size2_11 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_22 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_23 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_21 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_2 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_20 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size2_10 ( in , sram , sram_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_20 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_21 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_19 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_18 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_18 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_19 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_17 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_16 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_16 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_17 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_78 ( .A ( BUF_net_79 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_79 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_79 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_79 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_15 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_14 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_14 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_15 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_13 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_12 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_12 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_13 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_11 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_10 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_10 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_11 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_9 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_8 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_8 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_9 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_76 ( .A ( BUF_net_77 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_77 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_77 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_77 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_7 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_6 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_6 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_7 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 BINV_R_75 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_75 ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .Y ( BUF_net_75 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_5 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_4 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_4 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_5 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_73 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_3 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_2 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_2 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_3 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_1 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( p0 ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module sb_0__0__mux_2level_tapbuf_basis_input2_mem1_0 ( in , mem , mem_inv , 
-    out ) ;
+    out , VDD , VSS ) ;
 input  [0:1] in ;
 input  [0:0] mem ;
 input  [0:0] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 sky130_fd_sc_hd__mux2_1_0 ( .A0 ( in[1] ) , 
-    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) ) ;
+    .A1 ( in[0] ) , .S ( mem[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module sb_0__0__mux_2level_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+module sb_0__0__mux_2level_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_0_out ;
 wire [0:0] mux_2level_tapbuf_basis_input2_mem1_1_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_0 mux_l1_in_0_ ( .in ( in ) , 
     .mem ( sram[0] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_basis_input2_mem1_1 mux_l2_in_0_ (
     .in ( { mux_2level_tapbuf_basis_input2_mem1_0_out[0] , 
         SYNOPSYS_UNCONNECTED_2 } ) ,
     .mem ( sram[1] ) ,
     .mem_inv ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_2level_tapbuf_basis_input2_mem1_1_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 sky130_fd_sc_hd__buf_6 BUFT_RR_72 ( 
-    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) ) ;
+    .A ( mux_2level_tapbuf_basis_input2_mem1_1_out[0] ) , .X ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
@@ -71968,7 +95906,7 @@
     right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ , 
     right_bottom_grid_pin_13_ , right_bottom_grid_pin_15_ , 
     right_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out , 
-    ccff_tail , pReset_E_in , prog_clk_0_E_in ) ;
+    ccff_tail , pReset_E_in , prog_clk_0_E_in , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:29] chany_top_in ;
 input  [0:0] top_left_grid_pin_1_ ;
@@ -71988,6 +95926,8 @@
 output [0:0] ccff_tail ;
 input  pReset_E_in ;
 input  prog_clk_0_E_in ;
+input  VDD ;
+input  VSS ;
 
 wire ropt_net_135 ;
 wire ropt_net_132 ;
@@ -72062,6 +96002,8 @@
 wire [0:0] mux_2level_tapbuf_size4_mem_3_ccff_tail ;
 wire [0:0] mux_2level_tapbuf_size4_mem_4_ccff_tail ;
 wire [0:0] mux_2level_tapbuf_size4_mem_5_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 assign prog_clk_0 = prog_clk[0] ;
 
@@ -72069,1002 +96011,1304 @@
     .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) ,
     .sram ( mux_2level_tapbuf_size2_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
-    .out ( chany_top_out[0] ) , .p0 ( optlc_net_97 ) ) ;
+    .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_97 ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_1 mux_top_track_6 (
     .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] } ) ,
     .sram ( mux_2level_tapbuf_size2_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
-    .out ( chany_top_out[3] ) , .p0 ( optlc_net_100 ) ) ;
+    .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_100 ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_2 mux_top_track_12 (
     .in ( { top_left_grid_pin_1_[0] , chanx_right_in[7] } ) ,
     .sram ( mux_2level_tapbuf_size2_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
-    .out ( chany_top_out[6] ) , .p0 ( optlc_net_100 ) ) ;
+    .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_100 ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_3 mux_top_track_28 (
     .in ( { top_left_grid_pin_1_[0] , chanx_right_in[15] } ) ,
     .sram ( mux_2level_tapbuf_size2_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
-    .out ( chany_top_out[14] ) , .p0 ( optlc_net_99 ) ) ;
+    .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_99 ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_4 mux_top_track_44 (
     .in ( { top_left_grid_pin_1_[0] , chanx_right_in[23] } ) ,
     .sram ( mux_2level_tapbuf_size2_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 } ) ,
-    .out ( chany_top_out[22] ) , .p0 ( optlc_net_97 ) ) ;
+    .out ( chany_top_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_97 ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_5 mux_right_track_14 (
     .in ( { chany_top_in[6] , right_bottom_grid_pin_3_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
-    .out ( chanx_right_out[7] ) , .p0 ( optlc_net_97 ) ) ;
+    .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_97 ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_6 mux_right_track_16 (
     .in ( { chany_top_in[7] , right_bottom_grid_pin_5_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_6_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) ,
-    .out ( chanx_right_out[8] ) , .p0 ( optlc_net_97 ) ) ;
+    .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_97 ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_7 mux_right_track_18 (
     .in ( { chany_top_in[8] , right_bottom_grid_pin_7_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_7_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
-    .out ( chanx_right_out[9] ) , .p0 ( optlc_net_100 ) ) ;
+    .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_100 ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_8 mux_right_track_20 (
     .in ( { chany_top_in[9] , right_bottom_grid_pin_9_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_8_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) ,
-    .out ( chanx_right_out[10] ) , .p0 ( optlc_net_100 ) ) ;
+    .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_100 ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_9 mux_right_track_22 (
     .in ( { chany_top_in[10] , right_bottom_grid_pin_11_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_9_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
-    .out ( chanx_right_out[11] ) , .p0 ( optlc_net_99 ) ) ;
+    .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_99 ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_10 mux_right_track_24 (
     .in ( { chany_top_in[11] , right_bottom_grid_pin_13_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_10_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) ,
-    .out ( chanx_right_out[12] ) , .p0 ( optlc_net_102 ) ) ;
+    .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_102 ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_11 mux_right_track_26 (
     .in ( { chany_top_in[12] , right_bottom_grid_pin_15_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_11_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
-    .out ( chanx_right_out[13] ) , .p0 ( optlc_net_102 ) ) ;
+    .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_102 ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_12 mux_right_track_30 (
     .in ( { chany_top_in[14] , right_bottom_grid_pin_3_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_12_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
-    .out ( chanx_right_out[15] ) , .p0 ( optlc_net_101 ) ) ;
+    .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_101 ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_13 mux_right_track_32 (
     .in ( { chany_top_in[15] , right_bottom_grid_pin_5_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_13_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
-    .out ( chanx_right_out[16] ) , .p0 ( optlc_net_102 ) ) ;
+    .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_102 ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_14 mux_right_track_34 (
     .in ( { chany_top_in[16] , right_bottom_grid_pin_7_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_14_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
-    .out ( chanx_right_out[17] ) , .p0 ( optlc_net_99 ) ) ;
+    .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_99 ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_15 mux_right_track_36 (
     .in ( { chany_top_in[17] , right_bottom_grid_pin_9_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_15_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
-    .out ( chanx_right_out[18] ) , .p0 ( optlc_net_99 ) ) ;
+    .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_99 ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_16 mux_right_track_38 (
     .in ( { chany_top_in[18] , right_bottom_grid_pin_11_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_16_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
-    .out ( chanx_right_out[19] ) , .p0 ( optlc_net_99 ) ) ;
+    .out ( chanx_right_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_99 ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_17 mux_right_track_40 (
     .in ( { chany_top_in[19] , right_bottom_grid_pin_13_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_17_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
-    .out ( chanx_right_out[20] ) , .p0 ( optlc_net_102 ) ) ;
+    .out ( chanx_right_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_102 ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_18 mux_right_track_42 (
     .in ( { chany_top_in[20] , right_bottom_grid_pin_15_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_18_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
-    .out ( chanx_right_out[21] ) , .p0 ( optlc_net_102 ) ) ;
+    .out ( chanx_right_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_102 ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_19 mux_right_track_46 (
     .in ( { chany_top_in[22] , right_bottom_grid_pin_3_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_19_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
-    .out ( chanx_right_out[23] ) , .p0 ( optlc_net_97 ) ) ;
+    .out ( chanx_right_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_97 ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_20 mux_right_track_48 (
     .in ( { chany_top_in[23] , right_bottom_grid_pin_5_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_20_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
-    .out ( chanx_right_out[24] ) , .p0 ( optlc_net_97 ) ) ;
+    .out ( chanx_right_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_97 ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_21 mux_right_track_50 (
     .in ( { chany_top_in[24] , right_bottom_grid_pin_7_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_21_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
-    .out ( chanx_right_out[25] ) , .p0 ( optlc_net_100 ) ) ;
+    .out ( chanx_right_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_100 ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_22 mux_right_track_52 (
     .in ( { chany_top_in[25] , right_bottom_grid_pin_9_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_22_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
-    .out ( chanx_right_out[26] ) , .p0 ( optlc_net_99 ) ) ;
+    .out ( chanx_right_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_99 ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_23 mux_right_track_54 (
     .in ( { chany_top_in[26] , right_bottom_grid_pin_11_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_23_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
-    .out ( chanx_right_out[27] ) , .p0 ( optlc_net_99 ) ) ;
+    .out ( chanx_right_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_99 ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_24 mux_right_track_56 (
     .in ( { chany_top_in[27] , right_bottom_grid_pin_13_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_24_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
-    .out ( chanx_right_out[28] ) , .p0 ( optlc_net_102 ) ) ;
+    .out ( chanx_right_out[28] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_102 ) ) ;
 sb_0__0__mux_2level_tapbuf_size2 mux_right_track_58 (
     .in ( { chany_top_in[28] , right_bottom_grid_pin_15_[0] } ) ,
     .sram ( mux_2level_tapbuf_size2_25_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
-    .out ( chanx_right_out[29] ) , .p0 ( optlc_net_101 ) ) ;
+    .out ( chanx_right_out[29] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_101 ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_mem_0 mem_top_track_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_mem_1 mem_top_track_6 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_mem_2 mem_top_track_12 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_mem_3 mem_top_track_28 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_mem_4 mem_top_track_44 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_mem_5 mem_right_track_14 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_5_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_5_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_mem_6 mem_right_track_16 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_6_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_6_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_6_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_mem_7 mem_right_track_18 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_6_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_7_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_7_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_mem_8 mem_right_track_20 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_7_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_8_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_8_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_8_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_mem_9 mem_right_track_22 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_8_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_9_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_9_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_9_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_mem_10 mem_right_track_24 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_9_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_10_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_10_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_10_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_mem_11 mem_right_track_26 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_10_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_11_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_11_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_11_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_mem_12 mem_right_track_30 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_12_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_12_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_12_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_mem_13 mem_right_track_32 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_12_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_13_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_13_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_13_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_mem_14 mem_right_track_34 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_13_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_14_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_14_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_14_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_mem_15 mem_right_track_36 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_14_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_15_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_15_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_15_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_mem_16 mem_right_track_38 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_15_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_16_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_16_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_16_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_mem_17 mem_right_track_40 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_16_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_17_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_17_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_17_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_mem_18 mem_right_track_42 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_17_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_18_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_18_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_18_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_mem_19 mem_right_track_46 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size3_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_19_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_19_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_19_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_mem_20 mem_right_track_48 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_19_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_20_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_20_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_20_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_mem_21 mem_right_track_50 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_20_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_21_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_21_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_21_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_mem_22 mem_right_track_52 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_21_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_22_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_22_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_22_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_mem_23 mem_right_track_54 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_22_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_23_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_23_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_23_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_mem_24 mem_right_track_56 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_23_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size2_mem_24_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size2_24_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size2_24_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size2_mem mem_right_track_58 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_24_ccff_tail ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_tapbuf_size2_25_sram ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_2level_tapbuf_size2_25_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size4_0 mux_right_track_0 (
     .in ( { chany_top_in[29] , right_bottom_grid_pin_1_[0] , 
         right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_13_[0] } ) ,
     .sram ( mux_2level_tapbuf_size4_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , 
         SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
-    .out ( chanx_right_out[0] ) , .p0 ( optlc_net_101 ) ) ;
+    .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_101 ) ) ;
 sb_0__0__mux_2level_tapbuf_size4_1 mux_right_track_2 (
     .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , 
         right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_15_[0] } ) ,
     .sram ( mux_2level_tapbuf_size4_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , 
         SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
-    .out ( chanx_right_out[1] ) , .p0 ( optlc_net_98 ) ) ;
+    .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_98 ) ) ;
 sb_0__0__mux_2level_tapbuf_size4_2 mux_right_track_4 (
     .in ( { chany_top_in[1] , right_bottom_grid_pin_5_[0] , 
         right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) ,
     .sram ( mux_2level_tapbuf_size4_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , 
         SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
-    .out ( chanx_right_out[2] ) , .p0 ( optlc_net_101 ) ) ;
+    .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_101 ) ) ;
 sb_0__0__mux_2level_tapbuf_size4_3 mux_right_track_6 (
     .in ( { chany_top_in[2] , right_bottom_grid_pin_1_[0] , 
         right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_13_[0] } ) ,
     .sram ( mux_2level_tapbuf_size4_3_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , 
         SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
-    .out ( chanx_right_out[3] ) , .p0 ( optlc_net_101 ) ) ;
+    .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_101 ) ) ;
 sb_0__0__mux_2level_tapbuf_size4_4 mux_right_track_8 (
     .in ( { chany_top_in[3] , right_bottom_grid_pin_3_[0] , 
         right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_15_[0] } ) ,
     .sram ( mux_2level_tapbuf_size4_4_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , 
         SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
-    .out ( chanx_right_out[4] ) , .p0 ( optlc_net_98 ) ) ;
+    .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_98 ) ) ;
 sb_0__0__mux_2level_tapbuf_size4 mux_right_track_10 (
     .in ( { chany_top_in[4] , right_bottom_grid_pin_5_[0] , 
         right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) ,
     .sram ( mux_2level_tapbuf_size4_5_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , 
         SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
-    .out ( chanx_right_out[5] ) , .p0 ( optlc_net_102 ) ) ;
+    .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_102 ) ) ;
 sb_0__0__mux_2level_tapbuf_size4_mem_0 mem_right_track_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size4_mem_1 mem_right_track_2 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size4_mem_2 mem_right_track_4 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_2_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size4_mem_3 mem_right_track_6 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_2_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_3_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_3_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size4_mem_4 mem_right_track_8 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_3_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_4_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_4_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size4_mem mem_right_track_10 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_4_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size4_5_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size4_5_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size3_0 mux_right_track_12 (
     .in ( { chany_top_in[5] , right_bottom_grid_pin_1_[0] , 
         right_bottom_grid_pin_17_[0] } ) ,
     .sram ( mux_2level_tapbuf_size3_0_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
-    .out ( chanx_right_out[6] ) , .p0 ( optlc_net_102 ) ) ;
+    .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_102 ) ) ;
 sb_0__0__mux_2level_tapbuf_size3_1 mux_right_track_28 (
     .in ( { chany_top_in[13] , right_bottom_grid_pin_1_[0] , 
         right_bottom_grid_pin_17_[0] } ) ,
     .sram ( mux_2level_tapbuf_size3_1_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
-    .out ( chanx_right_out[14] ) , .p0 ( optlc_net_101 ) ) ;
+    .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_101 ) ) ;
 sb_0__0__mux_2level_tapbuf_size3 mux_right_track_44 (
     .in ( { chany_top_in[21] , right_bottom_grid_pin_1_[0] , 
         right_bottom_grid_pin_17_[0] } ) ,
     .sram ( mux_2level_tapbuf_size3_2_sram ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
-    .out ( chanx_right_out[22] ) , .p0 ( optlc_net_102 ) ) ;
+    .out ( chanx_right_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( optlc_net_102 ) ) ;
 sb_0__0__mux_2level_tapbuf_size3_mem_0 mem_right_track_12 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size4_mem_5_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_0_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_0_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size3_mem_1 mem_right_track_28 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_11_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_1_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_1_sram ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sb_0__0__mux_2level_tapbuf_size3_mem mem_right_track_44 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_2level_tapbuf_size2_mem_18_ccff_tail ) , 
     .ccff_tail ( mux_2level_tapbuf_size3_mem_2_ccff_tail ) , 
-    .mem_out ( mux_2level_tapbuf_size3_2_sram ) ) ;
-sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ;
+    .mem_out ( mux_2level_tapbuf_size3_2_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , 
-    .X ( prog_clk[0] ) ) ;
+    .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[0] ) , 
-    .X ( chany_top_out[29] ) ) ;
+    .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[2] ) , 
-    .X ( chany_top_out[1] ) ) ;
+    .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[3] ) , 
-    .X ( chany_top_out[2] ) ) ;
+    .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_51__50 ( .A ( chanx_right_in[5] ) , 
-    .X ( ropt_net_135 ) ) ;
+    .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[6] ) , 
-    .X ( chany_top_out[5] ) ) ;
+    .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[8] ) , 
-    .X ( chany_top_out[7] ) ) ;
+    .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_54__53 ( .A ( chanx_right_in[9] ) , 
-    .X ( chany_top_out[8] ) ) ;
+    .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[10] ) , 
-    .X ( chany_top_out[9] ) ) ;
+    .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[11] ) , 
-    .X ( chany_top_out[10] ) ) ;
+    .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[12] ) , 
-    .X ( chany_top_out[11] ) ) ;
+    .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_58__57 ( .A ( chanx_right_in[13] ) , 
-    .X ( chany_top_out[12] ) ) ;
+    .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[14] ) , 
-    .X ( chany_top_out[13] ) ) ;
+    .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[16] ) , 
-    .X ( chany_top_out[15] ) ) ;
+    .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[17] ) , 
-    .X ( chany_top_out[16] ) ) ;
+    .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[18] ) , 
-    .X ( chany_top_out[17] ) ) ;
+    .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[19] ) , 
-    .X ( chany_top_out[18] ) ) ;
+    .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[20] ) , 
-    .X ( chany_top_out[19] ) ) ;
+    .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[21] ) , 
-    .X ( chany_top_out[20] ) ) ;
+    .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[22] ) , 
-    .X ( chany_top_out[21] ) ) ;
+    .X ( chany_top_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[24] ) , 
-    .X ( chany_top_out[23] ) ) ;
+    .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( chanx_right_in[25] ) , 
-    .X ( chany_top_out[24] ) ) ;
+    .X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( chanx_right_in[26] ) , 
-    .X ( chany_top_out[25] ) ) ;
+    .X ( chany_top_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[27] ) , 
-    .X ( chany_top_out[26] ) ) ;
+    .X ( chany_top_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[28] ) , 
-    .X ( chany_top_out[27] ) ) ;
+    .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_72__71 ( .A ( chanx_right_in[29] ) , 
-    .X ( ropt_net_132 ) ) ;
+    .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_83 ) , 
-    .HI ( optlc_net_97 ) ) ;
+    .HI ( optlc_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_84 ) , 
-    .HI ( optlc_net_98 ) ) ;
+    .HI ( optlc_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_85 ) , 
-    .HI ( optlc_net_99 ) ) ;
+    .HI ( optlc_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_86 ) , 
-    .HI ( optlc_net_100 ) ) ;
+    .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_87 ) , 
-    .HI ( optlc_net_101 ) ) ;
+    .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_88 ) , 
-    .HI ( optlc_net_102 ) ) ;
+    .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1323 ( .A ( ropt_net_132 ) , 
-    .X ( chany_top_out[28] ) ) ;
+    .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_8 ropt_mt_inst_1326 ( .A ( ropt_net_135 ) , 
-    .X ( chany_top_out[4] ) ) ;
+    .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_6 FTB_111__110 ( .A ( copt_net_242 ) , 
-    .X ( ccff_tail[0] ) ) ;
-sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1699 ( .A ( mem_out[1] ) , 
-    .X ( copt_net_239 ) ) ;
-sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1700 ( .A ( copt_net_244 ) , 
-    .X ( copt_net_240 ) ) ;
-sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1701 ( .A ( copt_net_240 ) , 
-    .X ( copt_net_241 ) ) ;
-sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1702 ( .A ( copt_net_241 ) , 
-    .X ( copt_net_242 ) ) ;
-sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1703 ( .A ( copt_net_239 ) , 
-    .X ( copt_net_243 ) ) ;
-sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1704 ( .A ( copt_net_243 ) , 
-    .X ( copt_net_244 ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_111__110 ( .A ( copt_net_245 ) , 
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1727 ( .A ( copt_net_247 ) , 
+    .X ( copt_net_243 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1728 ( .A ( copt_net_243 ) , 
+    .X ( copt_net_244 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1729 ( .A ( copt_net_244 ) , 
+    .X ( copt_net_245 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1730 ( .A ( mem_out[1] ) , 
+    .X ( copt_net_246 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1731 ( .A ( copt_net_246 ) , 
+    .X ( copt_net_247 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_30 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_110__109 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_basis_input3_mem3 ( in , mem , mem_inv , out , p0 ) ;
+module grid_clb_mux_1level_basis_input3_mem3 ( in , mem , mem_inv , out , 
+    VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_109__108 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_109__108 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2 ( in , sram , sram_inv , out , p0 ) ;
+module grid_clb_mux_1level_size2 ( in , sram , sram_inv , out , VDD , VSS , 
+    p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_30 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_46 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_46 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_108__107 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_108__107 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_30 ( in , sram , sram_inv , out , p0 ) ;
+module grid_clb_mux_1level_size2_30 ( in , sram , sram_inv , out , VDD , VSS , 
+    p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3_46 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3_30 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_107__106 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_tapbuf_size2_mem_14 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_106__105 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_tapbuf_basis_input3_mem3 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_45 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_45 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_105__104 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_105__104 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_tapbuf_size2 ( in , sram , sram_inv , out , 
-    p_abuf0 , p0 ) ;
+module grid_clb_mux_1level_tapbuf_size2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p_abuf0 , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_local_encoder2to3_45 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_tapbuf_basis_input3_mem3 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_175 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
-sky130_fd_sc_hd__inv_2 BINV_R_176 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
+    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_176 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_177 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_tapbuf_basis_input3_mem3_14 ( in , mem , mem_inv , 
-    out , p3 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
-input  p3 ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
-    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p3 ) , .S0 ( mem[0] ) , 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_44 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_44 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_104__103 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_104__103 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_tapbuf_size2_14 ( in , sram , sram_inv , out , 
-    p_abuf0 , p3 ) ;
+    VDD , VSS , p_abuf0 , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
-input  p3 ;
+input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_local_encoder2to3_44 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_tapbuf_basis_input3_mem3_14 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ;
-sky130_fd_sc_hd__inv_2 BINV_R_172 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_173 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
+    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_173 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_174 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff ( 
-    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , p_abuf0 , p_abuf1 ) ;
+    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS , p_abuf0 , 
+    p_abuf1 , p_abuf2 ) ;
 input  [0:0] Test_en ;
 input  [0:0] ff_D ;
 input  [0:0] ff_DI ;
 input  [0:0] ff_reset ;
 output [0:0] ff_Q ;
 input  [0:0] ff_clk ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
 output p_abuf1 ;
+output p_abuf2 ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , 
     .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , 
-    .RESET_B ( ff_reset[0] ) , .Q ( p_abuf1 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_131 ) , .Y ( ff_Q[0] ) ) ;
-sky130_fd_sc_hd__inv_2 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( p_abuf0 ) ) ;
-sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( p_abuf1 ) , .Y ( BUF_net_131 ) ) ;
+    .RESET_B ( ff_reset[0] ) , .Q ( p_abuf2 ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( BUF_net_132 ) , .Y ( ff_Q[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_130 ( .A ( BUF_net_132 ) , .Y ( p_abuf0 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( p_abuf1 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( p_abuf2 ) , .Y ( BUF_net_132 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 ( 
-    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ;
 input  [0:0] Test_en ;
 input  [0:0] ff_D ;
 input  [0:0] ff_DI ;
 input  [0:0] ff_reset ;
 output [0:0] ff_Q ;
 input  [0:0] ff_clk ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , 
     .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , 
-    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_29 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_103__102 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_28 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_102__101 ( .A ( mem_out[1] ) , 
-    .X ( ccff_tail[0] ) ) ;
+    .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_29 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_43 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_43 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_101__100 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_101__100 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_29 ( in , sram , sram_inv , out , p0 ) ;
+module grid_clb_mux_1level_size2_29 ( in , sram , sram_inv , out , VDD , VSS , 
+    p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3_43 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3_29 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_28 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_42 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_42 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_100__99 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_100__99 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_28 ( in , sram , sram_inv , out , p0 ) ;
+module grid_clb_mux_1level_size2_28 ( in , sram , sram_inv , out , VDD , VSS , 
+    p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3_42 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3_28 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
-module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper ( A0 , A1 , S , X ) ;
+module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper ( A0 , A1 , S , X , VDD , 
+    VSS ) ;
 input  A0 ;
 input  A1 ;
 input  S ;
 output X ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , 
-    .X ( X_gOb22 ) ) ;
+    .X ( net_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_179 ( .A ( net_net_179 ) , .X ( X ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower ( 
     carry_follower_a , carry_follower_b , carry_follower_cin , 
-    carry_follower_cout ) ;
+    carry_follower_cout , VDD , VSS ) ;
 input  [0:0] carry_follower_a ;
 input  [0:0] carry_follower_b ;
 input  [0:0] carry_follower_cin ;
 output [0:0] carry_follower_cout ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_sky130_fd_sc_hd__mux2_1_wrapper sky130_fd_sc_hd__mux2_1_wrapper_0_ ( 
     .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , 
-    .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ;
+    .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:16] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_99__98 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_99__98 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_frac_lut4_mux ( in , sram , sram_inv , lut2_out , lut3_out , 
-    lut4_out ) ;
+    lut4_out , VDD , VSS ) ;
 input  [0:15] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:1] lut2_out ;
 output [0:1] lut3_out ;
 output [0:0] lut4_out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
 wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
@@ -73076,52 +97320,64 @@
 wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
 wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
 wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
-    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
-    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
-    .X ( lut2_out[0] ) ) ;
+    .X ( lut2_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
-    .X ( lut2_out[1] ) ) ;
+    .X ( lut2_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , 
-    .X ( lut3_out[0] ) ) ;
+    .X ( lut3_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , 
-    .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ;
+    .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , 
-    .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+    .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_frac_lut4 ( in , sram , sram_inv , mode , mode_inv , 
-    lut2_out , lut3_out , lut4_out ) ;
+    lut2_out , lut3_out , lut4_out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:15] sram ;
 input  [0:15] sram_inv ;
@@ -73130,35 +97386,41 @@
 output [0:1] lut2_out ;
 output [0:1] lut3_out ;
 output [0:0] lut4_out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
 wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
 wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
 wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
 wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , 
-    .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+    .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+    .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
-sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+    .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , 
+    .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( 
     .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+    .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_frac_lut4_mux frac_lut4_mux_0_ ( .in ( sram ) ,
     .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
         SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
-    .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+    .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 ( 
     pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , 
-    frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ;
+    frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:3] frac_lut4_in ;
@@ -73167,9 +97429,13 @@
 output [0:1] frac_lut4_lut3_out ;
 output [0:0] frac_lut4_lut4_out ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] frac_lut4_0_mode ;
 wire [0:15] frac_lut4_0_sram ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_frac_lut4 frac_lut4_0_ ( .in ( frac_lut4_in ) , 
     .sram ( frac_lut4_0_sram ) ,
@@ -73184,7 +97450,7 @@
     .mode ( frac_lut4_0_mode ) ,
     .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
     .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , 
-    .lut4_out ( frac_lut4_lut4_out ) ) ;
+    .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
     .ccff_tail ( ccff_tail ) ,
@@ -73193,13 +97459,14 @@
         frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , 
         frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , 
         frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , 
-        frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+        frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ,
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic ( 
     pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , 
-    frac_logic_out , frac_logic_cout , ccff_tail , p0 ) ;
+    frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p0 ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:3] frac_logic_in ;
@@ -73208,6 +97475,8 @@
 output [0:1] frac_logic_out ;
 output [0:0] frac_logic_cout ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:0] direct_interc_5_out ;
@@ -73219,6 +97488,8 @@
 wire [0:0] mux_1level_size2_1_out ;
 wire [0:1] mux_1level_size2_1_sram ;
 wire [0:0] mux_1level_size2_mem_0_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
@@ -73231,41 +97502,44 @@
         frac_logic_out[1] } ) ,
     
     .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , 
-    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( 
     .carry_follower_a ( direct_interc_5_out ) , 
     .carry_follower_b ( frac_logic_cin ) , 
-    .carry_follower_cin ( direct_interc_7_out ) ,
-    .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+    .carry_follower_cin ( direct_interc_7_out ) , 
+    .carry_follower_cout ( frac_logic_cout ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_size2_28 mux_frac_logic_out_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
          } ) ,
     .sram ( mux_1level_size2_0_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+    .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ;
 grid_clb_mux_1level_size2_29 mux_frac_lut4_0_in_2 (
     .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) ,
     .sram ( mux_1level_size2_1_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) ,
-    .out ( mux_1level_size2_1_out ) , .p0 ( p0 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( mux_1level_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( p0 ) ) ;
 grid_clb_mux_1level_size2_mem_28 mem_frac_logic_out_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , 
     .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_1level_size2_0_sram ) ) ;
+    .mem_out ( mux_1level_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_size2_mem_29 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric ( 
     pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , 
     fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , 
-    fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , 
-    p_abuf2 , p_abuf3 , p0 , p3 ) ;
+    fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , 
+    p_abuf1 , p_abuf3 , p_abuf4 , p0 ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] Test_en ;
@@ -73281,16 +97555,17 @@
 output [0:0] fabric_sc_out ;
 output [0:0] fabric_cout ;
 output [0:0] ccff_tail ;
-output p_abuf0 ;
-output p_abuf2 ;
+input  VDD ;
+input  VSS ;
+output p_abuf1 ;
 output p_abuf3 ;
+output p_abuf4 ;
 input  p0 ;
-input  p3 ;
 
+wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q ;
 wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
 wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
 wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
-wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ;
 wire [0:0] mux_1level_size2_0_out ;
 wire [0:1] mux_1level_size2_0_sram ;
 wire [0:0] mux_1level_size2_1_out ;
@@ -73300,84 +97575,95 @@
 wire [0:1] mux_1level_tapbuf_size2_1_sram ;
 wire [0:0] mux_1level_tapbuf_size2_mem_0_ccff_tail ;
 wire [0:0] mux_1level_tapbuf_size2_mem_1_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
-    .frac_logic_in ( fabric_in ) , 
-    .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , 
+    .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , 
     .ccff_head ( ccff_head ) , 
-    .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
-    .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    
+    .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , 
+    .frac_logic_cout ( fabric_cout ) , 
     .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
-    .p0 ( p0 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( 
     .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) , 
     .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , 
     .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , 
-    .ff_clk ( fabric_clk ) ) ;
+    .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( 
     .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_1_out ) , 
     .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , 
-    .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , 
-    .ff_clk ( fabric_clk ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ;
+    .ff_reset ( fabric_reset ) , 
+    .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q ) , 
+    .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p_abuf0 ( fabric_sc_out[0] ) , .p_abuf1 ( p_abuf1 ) , 
+    .p_abuf2 ( p_abuf2 ) ) ;
 grid_clb_mux_1level_tapbuf_size2_14 mux_fabric_out_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
          } ) ,
     .sram ( mux_1level_tapbuf_size2_0_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf2 ) , .p3 ( p3 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+    .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p_abuf0 ( p_abuf3 ) , .p0 ( p0 ) ) ;
 grid_clb_mux_1level_tapbuf_size2 mux_fabric_out_1 (
-    .in ( { p_abuf1 , 
+    .in ( { 
+        logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
          } ) ,
     .sram ( mux_1level_tapbuf_size2_1_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) ,
-    .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf3 ) , .p0 ( p0 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p_abuf0 ( p_abuf4 ) , .p0 ( p0 ) ) ;
 grid_clb_mux_1level_tapbuf_size2_mem_14 mem_fabric_out_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
     .ccff_tail ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_1level_tapbuf_size2_0_sram ) ) ;
+    .mem_out ( mux_1level_tapbuf_size2_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 grid_clb_mux_1level_tapbuf_size2_mem mem_fabric_out_1 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , 
-    .mem_out ( mux_1level_tapbuf_size2_1_sram ) ) ;
-sky130_fd_sc_hd__buf_6 FTB_112__111 ( .A ( p_abuf1 ) , 
-    .X ( fabric_reg_out[0] ) ) ;
+    .mem_out ( mux_1level_tapbuf_size2_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_112__111 ( .A ( p_abuf2 ) , 
+    .X ( fabric_reg_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_mux_1level_size2_30 mux_ff_0_D_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , 
         fabric_reg_in[0] } ) ,
     .sram ( mux_1level_size2_0_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) ,
-    .out ( mux_1level_size2_0_out ) , .p0 ( p0 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+    .out ( mux_1level_size2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( p0 ) ) ;
 grid_clb_mux_1level_size2 mux_ff_1_D_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
          } ) ,
     .sram ( mux_1level_size2_1_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) ,
-    .out ( mux_1level_size2_1_out ) , .p0 ( p0 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( mux_1level_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( p0 ) ) ;
 grid_clb_mux_1level_size2_mem_30 mem_ff_0_D_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_1level_size2_0_sram ) ) ;
+    .mem_out ( mux_1level_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_size2_mem mem_ff_1_D_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle ( pReset , prog_clk , 
     Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , 
     fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , 
-    ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , p3 ) ;
+    ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p0 ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] Test_en ;
@@ -73393,565 +97679,797 @@
 output [0:0] fle_sc_out ;
 output [0:0] fle_cout ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
 output p_abuf1 ;
 output p_abuf2 ;
 input  p0 ;
-input  p3 ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , 
     .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , 
-    .fabric_sc_in ( fle_sc_in ) ,
-    .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+    .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , 
     .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , 
     .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , 
     .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , 
-    .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , 
-    .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf1 ) , .p_abuf3 ( p_abuf2 ) , 
-    .p0 ( p0 ) , .p3 ( p3 ) ) ;
+    .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p_abuf1 ( p_abuf0 ) , .p_abuf3 ( p_abuf1 ) , 
+    .p_abuf4 ( p_abuf2 ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_27 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_97__96 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_97__96 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_26 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_96__95 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_96__95 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_27 ( in , mem , mem_inv , out , 
-    p3 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
-input  p3 ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
-    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p3 ) , .S0 ( mem[0] ) , 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_41 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_41 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_95__94 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_95__94 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_27 ( in , sram , sram_inv , out , p3 ) ;
+module grid_clb_mux_1level_size2_27 ( in , sram , sram_inv , out , VDD , VSS , 
+    p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
-input  p3 ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3_41 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3_27 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_26 ( in , mem , mem_inv , out , 
-    p3 ) ;
+    VDD , VSS , p3 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p3 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p3 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_40 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_40 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_94__93 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_94__93 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_26 ( in , sram , sram_inv , out , p3 ) ;
+module grid_clb_mux_1level_size2_26 ( in , sram , sram_inv , out , VDD , VSS , 
+    p3 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p3 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3_40 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3_26 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p3 ( p3 ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_tapbuf_size2_mem_13 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_93__92 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_93__92 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_tapbuf_size2_mem_12 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_92__91 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_92__91 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_tapbuf_basis_input3_mem3_13 ( in , mem , mem_inv , 
-    out , p3 ) ;
+    out , VDD , VSS , p3 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p3 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p3 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_39 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_39 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_91__90 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_91__90 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_tapbuf_size2_13 ( in , sram , sram_inv , out , 
-    p_abuf0 , p3 ) ;
+    VDD , VSS , p3 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p3 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__inv_8 sky130_fd_sc_hd__inv_4_0_ ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+grid_clb_local_encoder2to3_39 local_encoder2to3_0_ ( .addr ( sram ) , 
+    .data ( local_encoder2to3_0_data ) , 
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+grid_clb_mux_1level_tapbuf_basis_input3_mem3_13 mux_l1_in_0_ (
+    .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to3_0_data ) , 
+    .mem_inv ( local_encoder2to3_0_data_inv ) , 
+    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p3 ( p3 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_basis_input3_mem3_12 ( in , mem , mem_inv , 
+    out , VDD , VSS , p3 ) ;
+input  [0:2] in ;
+input  [0:2] mem ;
+input  [0:2] mem_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p3 ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p3 ) , .S0 ( mem[0] ) , 
+    .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_38 ( addr , data , data_inv , VDD , VSS ) ;
+input  [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_90__89 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_12 ( in , sram , sram_inv , out , 
+    VDD , VSS , p_abuf0 , p3 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
 input  p3 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
-grid_clb_local_encoder2to3_39 local_encoder2to3_0_ ( .addr ( sram ) , 
-    .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
-grid_clb_mux_1level_tapbuf_basis_input3_mem3_13 mux_l1_in_0_ (
-    .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
-    .mem ( local_encoder2to3_0_data ) , 
-    .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_169 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
-sky130_fd_sc_hd__inv_2 BINV_R_170 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
-endmodule
-
-
-module grid_clb_mux_1level_tapbuf_basis_input3_mem3_12 ( in , mem , mem_inv , 
-    out , p3 ) ;
-input  [0:2] in ;
-input  [0:2] mem ;
-input  [0:2] mem_inv ;
-output [0:0] out ;
-input  p3 ;
-
-sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
-    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p3 ) , .S0 ( mem[0] ) , 
-    .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
-endmodule
-
-
-module grid_clb_local_encoder2to3_38 ( addr , data , data_inv ) ;
-input  [0:1] addr ;
-output [0:2] data ;
-output [0:2] data_inv ;
-
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_90__89 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
-endmodule
-
-
-module grid_clb_mux_1level_tapbuf_size2_12 ( in , sram , sram_inv , out , p3 ) ;
-input  [0:1] in ;
-input  [0:1] sram ;
-input  [0:1] sram_inv ;
-output [0:0] out ;
-input  p3 ;
-
-wire [0:2] local_encoder2to3_0_data ;
-wire [0:2] local_encoder2to3_0_data_inv ;
-wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
-
-sky130_fd_sc_hd__inv_8 sky130_fd_sc_hd__inv_4_0_ ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
 grid_clb_local_encoder2to3_38 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_tapbuf_basis_input3_mem3_12 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ;
+    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p3 ( p3 ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_169 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_170 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 ( 
-    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ;
 input  [0:0] Test_en ;
 input  [0:0] ff_D ;
 input  [0:0] ff_DI ;
 input  [0:0] ff_reset ;
 output [0:0] ff_Q ;
 input  [0:0] ff_clk ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , 
     .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , 
-    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 ( 
-    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ;
 input  [0:0] Test_en ;
 input  [0:0] ff_D ;
 input  [0:0] ff_DI ;
 input  [0:0] ff_reset ;
 output [0:0] ff_Q ;
 input  [0:0] ff_clk ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , 
     .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , 
-    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_25 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_89__88 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_89__88 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_24 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_88__87 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_88__87 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_25 ( in , mem , mem_inv , out , 
-    p3 ) ;
+    VDD , VSS , p3 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p3 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p3 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_37 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_37 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_87__86 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_87__86 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_25 ( in , sram , sram_inv , out , p3 ) ;
+module grid_clb_mux_1level_size2_25 ( in , sram , sram_inv , out , VDD , VSS , 
+    p3 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p3 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3_37 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3_25 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p3 ( p3 ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_24 ( in , mem , mem_inv , out , 
-    p3 ) ;
+    VDD , VSS , p3 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p3 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p3 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_36 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_36 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_86__85 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_86__85 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_24 ( in , sram , sram_inv , out , p3 ) ;
+module grid_clb_mux_1level_size2_24 ( in , sram , sram_inv , out , VDD , VSS , 
+    p3 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p3 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3_36 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3_24 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p3 ( p3 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p3 ( p3 ) ) ;
 endmodule
 
 
-module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_6 ( A0 , A1 , S , X ) ;
+module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_6 ( A0 , A1 , S , X , VDD , 
+    VSS ) ;
 input  A0 ;
 input  A1 ;
 input  S ;
 output X ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , 
-    .X ( X_gOb19 ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_6 ( 
     carry_follower_a , carry_follower_b , carry_follower_cin , 
-    carry_follower_cout ) ;
+    carry_follower_cout , VDD , VSS ) ;
 input  [0:0] carry_follower_a ;
 input  [0:0] carry_follower_b ;
 input  [0:0] carry_follower_cin ;
 output [0:0] carry_follower_cout ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_6 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( 
     .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , 
-    .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ;
+    .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_6 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:16] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_85__84 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_85__84 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_frac_lut4_mux_6 ( in , sram , sram_inv , lut2_out , lut3_out , 
-    lut4_out ) ;
+    lut4_out , VDD , VSS ) ;
 input  [0:15] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:1] lut2_out ;
 output [0:1] lut3_out ;
 output [0:0] lut4_out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
 wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
@@ -73963,52 +98481,64 @@
 wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
 wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
 wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
-    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
-    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
-    .X ( lut2_out[0] ) ) ;
+    .X ( lut2_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
-    .X ( lut2_out[1] ) ) ;
+    .X ( lut2_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , 
-    .X ( lut3_out[0] ) ) ;
+    .X ( lut3_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , 
-    .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ;
+    .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , 
-    .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+    .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_frac_lut4_6 ( in , sram , sram_inv , mode , mode_inv , 
-    lut2_out , lut3_out , lut4_out ) ;
+    lut2_out , lut3_out , lut4_out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:15] sram ;
 input  [0:15] sram_inv ;
@@ -74017,35 +98547,41 @@
 output [0:1] lut2_out ;
 output [0:1] lut3_out ;
 output [0:0] lut4_out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
 wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
 wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
 wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
 wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , 
-    .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+    .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+    .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
-sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+    .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , 
+    .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( 
     .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+    .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_frac_lut4_mux_6 frac_lut4_mux_0_ ( .in ( sram ) ,
     .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
         SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
-    .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+    .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 ( 
     pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , 
-    frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ;
+    frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:3] frac_lut4_in ;
@@ -74054,9 +98590,13 @@
 output [0:1] frac_lut4_lut3_out ;
 output [0:0] frac_lut4_lut4_out ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] frac_lut4_0_mode ;
 wire [0:15] frac_lut4_0_sram ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_frac_lut4_6 frac_lut4_0_ ( .in ( frac_lut4_in ) , 
     .sram ( frac_lut4_0_sram ) ,
@@ -74071,7 +98611,7 @@
     .mode ( frac_lut4_0_mode ) ,
     .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
     .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , 
-    .lut4_out ( frac_lut4_lut4_out ) ) ;
+    .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
     .ccff_tail ( ccff_tail ) ,
@@ -74080,13 +98620,14 @@
         frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , 
         frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , 
         frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , 
-        frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+        frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ,
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( 
     pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , 
-    frac_logic_out , frac_logic_cout , ccff_tail , p3 ) ;
+    frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p3 ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:3] frac_logic_in ;
@@ -74095,6 +98636,8 @@
 output [0:1] frac_logic_out ;
 output [0:0] frac_logic_cout ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 input  p3 ;
 
 wire [0:0] direct_interc_5_out ;
@@ -74106,6 +98649,8 @@
 wire [0:0] mux_1level_size2_1_out ;
 wire [0:1] mux_1level_size2_1_sram ;
 wire [0:0] mux_1level_size2_mem_0_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
@@ -74118,40 +98663,44 @@
         frac_logic_out[1] } ) ,
     
     .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , 
-    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( 
     .carry_follower_a ( direct_interc_5_out ) , 
     .carry_follower_b ( frac_logic_cin ) , 
-    .carry_follower_cin ( direct_interc_7_out ) ,
-    .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+    .carry_follower_cin ( direct_interc_7_out ) , 
+    .carry_follower_cout ( frac_logic_cout ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_size2_24 mux_frac_logic_out_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
          } ) ,
     .sram ( mux_1level_size2_0_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+    .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ;
 grid_clb_mux_1level_size2_25 mux_frac_lut4_0_in_2 (
     .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) ,
     .sram ( mux_1level_size2_1_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) ,
-    .out ( mux_1level_size2_1_out ) , .p3 ( p3 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( mux_1level_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p3 ( p3 ) ) ;
 grid_clb_mux_1level_size2_mem_24 mem_frac_logic_out_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , 
     .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_1level_size2_0_sram ) ) ;
+    .mem_out ( mux_1level_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_size2_mem_25 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( 
     pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , 
     fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , 
-    fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , p3 ) ;
+    fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , 
+    p_abuf0 , p0 , p3 ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] Test_en ;
@@ -74167,13 +98716,15 @@
 output [0:0] fabric_sc_out ;
 output [0:0] fabric_cout ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
+input  p0 ;
 input  p3 ;
 
 wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
 wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
 wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
-wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ;
 wire [0:0] mux_1level_size2_0_out ;
 wire [0:1] mux_1level_size2_0_sram ;
 wire [0:0] mux_1level_size2_1_out ;
@@ -74183,84 +98734,90 @@
 wire [0:1] mux_1level_tapbuf_size2_1_sram ;
 wire [0:0] mux_1level_tapbuf_size2_mem_0_ccff_tail ;
 wire [0:0] mux_1level_tapbuf_size2_mem_1_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
-    .frac_logic_in ( fabric_in ) , 
-    .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , 
+    .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , 
     .ccff_head ( ccff_head ) , 
-    .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
-    .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    
+    .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , 
+    .frac_logic_cout ( fabric_cout ) , 
     .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
-    .p3 ( p3 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( 
     .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) , 
     .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , 
     .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , 
-    .ff_clk ( fabric_clk ) ) ;
+    .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( 
     .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_1_out ) , 
     .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , 
     .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , 
-    .ff_clk ( fabric_clk ) ) ;
+    .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_tapbuf_size2_12 mux_fabric_out_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
          } ) ,
     .sram ( mux_1level_tapbuf_size2_0_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( fabric_out[0] ) , .p3 ( p3 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+    .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ;
 grid_clb_mux_1level_tapbuf_size2_13 mux_fabric_out_1 (
     .in ( { fabric_sc_out[0] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
          } ) ,
     .sram ( mux_1level_tapbuf_size2_1_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) ,
-    .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ;
 grid_clb_mux_1level_tapbuf_size2_mem_12 mem_fabric_out_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
     .ccff_tail ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_1level_tapbuf_size2_0_sram ) ) ;
+    .mem_out ( mux_1level_tapbuf_size2_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 grid_clb_mux_1level_tapbuf_size2_mem_13 mem_fabric_out_1 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , 
-    .mem_out ( mux_1level_tapbuf_size2_1_sram ) ) ;
+    .mem_out ( mux_1level_tapbuf_size2_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_98__97 ( .A ( fabric_sc_out[0] ) , 
-    .X ( fabric_reg_out[0] ) ) ;
+    .X ( fabric_reg_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_mux_1level_size2_26 mux_ff_0_D_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , 
         fabric_reg_in[0] } ) ,
     .sram ( mux_1level_size2_0_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) ,
-    .out ( mux_1level_size2_0_out ) , .p3 ( p3 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+    .out ( mux_1level_size2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p3 ( p3 ) ) ;
 grid_clb_mux_1level_size2_27 mux_ff_1_D_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
          } ) ,
     .sram ( mux_1level_size2_1_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) ,
-    .out ( mux_1level_size2_1_out ) , .p3 ( p3 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( mux_1level_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( p0 ) ) ;
 grid_clb_mux_1level_size2_mem_26 mem_ff_0_D_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_1level_size2_0_sram ) ) ;
+    .mem_out ( mux_1level_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_size2_mem_27 mem_ff_1_D_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_6 ( pReset , prog_clk , 
     Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , 
     fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , 
-    ccff_tail , p_abuf0 , p3 ) ;
+    ccff_tail , VDD , VSS , p_abuf0 , p0 , p3 ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] Test_en ;
@@ -74276,565 +98833,799 @@
 output [0:0] fle_sc_out ;
 output [0:0] fle_cout ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
+input  p0 ;
 input  p3 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , 
     .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , 
-    .fabric_sc_in ( fle_sc_in ) ,
-    .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+    .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , 
     .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , 
     .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , 
-    .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) ,
-    .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) ,
-    .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ;
+    .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , 
+    .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) , .p3 ( p3 ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_23 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_83__82 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_83__82 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_22 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_82__81 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_82__81 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_23 ( in , mem , mem_inv , out , 
-    p6 ) ;
+    VDD , VSS , p6 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p6 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p6 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_35 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_35 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_81__80 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_81__80 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_23 ( in , sram , sram_inv , out , p6 ) ;
+module grid_clb_mux_1level_size2_23 ( in , sram , sram_inv , out , VDD , VSS , 
+    p6 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p6 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3_35 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3_23 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p6 ( p6 ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_22 ( in , mem , mem_inv , out , 
-    p6 ) ;
+    VDD , VSS , p6 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p6 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p6 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_34 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_34 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_80__79 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_80__79 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_22 ( in , sram , sram_inv , out , p6 ) ;
+module grid_clb_mux_1level_size2_22 ( in , sram , sram_inv , out , VDD , VSS , 
+    p6 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p6 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3_34 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3_22 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p6 ( p6 ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_tapbuf_size2_mem_11 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_79__78 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_79__78 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_tapbuf_size2_mem_10 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_78__77 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_78__77 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_tapbuf_basis_input3_mem3_11 ( in , mem , mem_inv , 
-    out , p6 ) ;
+    out , VDD , VSS , p3 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
-input  p6 ;
+input  VDD ;
+input  VSS ;
+input  p3 ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
-    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p6 ) , .S0 ( mem[0] ) , 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p3 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_33 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_33 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_77__76 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_77__76 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_tapbuf_size2_11 ( in , sram , sram_inv , out , 
-    p_abuf0 , p6 ) ;
+    VDD , VSS , p_abuf0 , p3 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
-input  p6 ;
+input  p3 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_local_encoder2to3_33 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_tapbuf_basis_input3_mem3_11 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ;
-sky130_fd_sc_hd__inv_2 BINV_R_165 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_166 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
+    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p3 ( p3 ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_166 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_167 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_tapbuf_basis_input3_mem3_10 ( in , mem , mem_inv , 
-    out , p6 ) ;
+    out , VDD , VSS , p6 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p6 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p6 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_32 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_32 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_76__75 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_76__75 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_tapbuf_size2_10 ( in , sram , sram_inv , out , 
-    p_abuf0 , p6 ) ;
+    VDD , VSS , p_abuf0 , p6 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
 input  p6 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_local_encoder2to3_32 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_tapbuf_basis_input3_mem3_10 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ;
-sky130_fd_sc_hd__inv_2 BINV_R_162 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_163 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
+    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p6 ( p6 ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_163 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_164 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 ( 
-    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ;
 input  [0:0] Test_en ;
 input  [0:0] ff_D ;
 input  [0:0] ff_DI ;
 input  [0:0] ff_reset ;
 output [0:0] ff_Q ;
 input  [0:0] ff_clk ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , 
     .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , 
-    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 ( 
-    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ;
 input  [0:0] Test_en ;
 input  [0:0] ff_D ;
 input  [0:0] ff_DI ;
 input  [0:0] ff_reset ;
 output [0:0] ff_Q ;
 input  [0:0] ff_clk ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , 
     .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , 
-    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_21 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_75__74 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_75__74 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_20 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_74__73 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_74__73 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_21 ( in , mem , mem_inv , out , 
-    p6 ) ;
+    VDD , VSS , p6 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p6 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p6 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_31 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_31 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_73__72 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_73__72 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_21 ( in , sram , sram_inv , out , p6 ) ;
+module grid_clb_mux_1level_size2_21 ( in , sram , sram_inv , out , VDD , VSS , 
+    p6 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p6 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3_31 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3_21 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p6 ( p6 ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_20 ( in , mem , mem_inv , out , 
-    p6 ) ;
+    VDD , VSS , p6 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p6 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p6 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_30 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_30 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_72__71 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_72__71 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_20 ( in , sram , sram_inv , out , p6 ) ;
+module grid_clb_mux_1level_size2_20 ( in , sram , sram_inv , out , VDD , VSS , 
+    p6 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p6 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3_30 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3_20 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p6 ( p6 ) ) ;
 endmodule
 
 
-module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_5 ( A0 , A1 , S , X ) ;
+module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_5 ( A0 , A1 , S , X , VDD , 
+    VSS ) ;
 input  A0 ;
 input  A1 ;
 input  S ;
 output X ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , 
-    .X ( X_gOb16 ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_5 ( 
     carry_follower_a , carry_follower_b , carry_follower_cin , 
-    carry_follower_cout ) ;
+    carry_follower_cout , VDD , VSS ) ;
 input  [0:0] carry_follower_a ;
 input  [0:0] carry_follower_b ;
 input  [0:0] carry_follower_cin ;
 output [0:0] carry_follower_cout ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_5 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( 
     .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , 
-    .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ;
+    .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_5 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:16] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_71__70 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_71__70 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_frac_lut4_mux_5 ( in , sram , sram_inv , lut2_out , lut3_out , 
-    lut4_out ) ;
+    lut4_out , VDD , VSS ) ;
 input  [0:15] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:1] lut2_out ;
 output [0:1] lut3_out ;
 output [0:0] lut4_out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
 wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
@@ -74846,52 +99637,64 @@
 wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
 wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
 wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
-    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
-    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
-    .X ( lut2_out[0] ) ) ;
+    .X ( lut2_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
-    .X ( lut2_out[1] ) ) ;
+    .X ( lut2_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , 
-    .X ( lut3_out[0] ) ) ;
+    .X ( lut3_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , 
-    .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ;
+    .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , 
-    .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+    .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_frac_lut4_5 ( in , sram , sram_inv , mode , mode_inv , 
-    lut2_out , lut3_out , lut4_out ) ;
+    lut2_out , lut3_out , lut4_out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:15] sram ;
 input  [0:15] sram_inv ;
@@ -74900,35 +99703,41 @@
 output [0:1] lut2_out ;
 output [0:1] lut3_out ;
 output [0:0] lut4_out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
 wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
 wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
 wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
 wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , 
-    .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+    .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+    .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
-sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+    .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , 
+    .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( 
     .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+    .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_frac_lut4_mux_5 frac_lut4_mux_0_ ( .in ( sram ) ,
     .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
         SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
-    .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+    .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 ( 
     pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , 
-    frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ;
+    frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:3] frac_lut4_in ;
@@ -74937,9 +99746,13 @@
 output [0:1] frac_lut4_lut3_out ;
 output [0:0] frac_lut4_lut4_out ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] frac_lut4_0_mode ;
 wire [0:15] frac_lut4_0_sram ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_frac_lut4_5 frac_lut4_0_ ( .in ( frac_lut4_in ) , 
     .sram ( frac_lut4_0_sram ) ,
@@ -74954,7 +99767,7 @@
     .mode ( frac_lut4_0_mode ) ,
     .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
     .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , 
-    .lut4_out ( frac_lut4_lut4_out ) ) ;
+    .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
     .ccff_tail ( ccff_tail ) ,
@@ -74963,13 +99776,14 @@
         frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , 
         frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , 
         frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , 
-        frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+        frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ,
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 ( 
     pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , 
-    frac_logic_out , frac_logic_cout , ccff_tail , p6 ) ;
+    frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p6 ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:3] frac_logic_in ;
@@ -74978,6 +99792,8 @@
 output [0:1] frac_logic_out ;
 output [0:0] frac_logic_cout ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 input  p6 ;
 
 wire [0:0] direct_interc_5_out ;
@@ -74989,6 +99805,8 @@
 wire [0:0] mux_1level_size2_1_out ;
 wire [0:1] mux_1level_size2_1_sram ;
 wire [0:0] mux_1level_size2_mem_0_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
@@ -75001,41 +99819,44 @@
         frac_logic_out[1] } ) ,
     
     .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , 
-    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( 
     .carry_follower_a ( direct_interc_5_out ) , 
     .carry_follower_b ( frac_logic_cin ) , 
-    .carry_follower_cin ( direct_interc_7_out ) ,
-    .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+    .carry_follower_cin ( direct_interc_7_out ) , 
+    .carry_follower_cout ( frac_logic_cout ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_size2_20 mux_frac_logic_out_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
          } ) ,
     .sram ( mux_1level_size2_0_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( frac_logic_out[0] ) , .p6 ( p6 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+    .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p6 ( p6 ) ) ;
 grid_clb_mux_1level_size2_21 mux_frac_lut4_0_in_2 (
     .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) ,
     .sram ( mux_1level_size2_1_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) ,
-    .out ( mux_1level_size2_1_out ) , .p6 ( p6 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( mux_1level_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p6 ( p6 ) ) ;
 grid_clb_mux_1level_size2_mem_20 mem_frac_logic_out_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , 
     .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_1level_size2_0_sram ) ) ;
+    .mem_out ( mux_1level_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_size2_mem_21 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( 
     pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , 
     fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , 
-    fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , 
-    p_abuf1 , p6 ) ;
+    fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , 
+    p_abuf0 , p_abuf1 , p3 , p6 ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] Test_en ;
@@ -75051,14 +99872,16 @@
 output [0:0] fabric_sc_out ;
 output [0:0] fabric_cout ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
 output p_abuf1 ;
+input  p3 ;
 input  p6 ;
 
 wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
 wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
 wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
-wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ;
 wire [0:0] mux_1level_size2_0_out ;
 wire [0:1] mux_1level_size2_0_sram ;
 wire [0:0] mux_1level_size2_1_out ;
@@ -75068,84 +99891,91 @@
 wire [0:1] mux_1level_tapbuf_size2_1_sram ;
 wire [0:0] mux_1level_tapbuf_size2_mem_0_ccff_tail ;
 wire [0:0] mux_1level_tapbuf_size2_mem_1_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
-    .frac_logic_in ( fabric_in ) , 
-    .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , 
+    .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , 
     .ccff_head ( ccff_head ) , 
-    .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
-    .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    
+    .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , 
+    .frac_logic_cout ( fabric_cout ) , 
     .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
-    .p6 ( p6 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p6 ( p6 ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( 
     .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) , 
     .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , 
     .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , 
-    .ff_clk ( fabric_clk ) ) ;
+    .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( 
     .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_1_out ) , 
     .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , 
     .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , 
-    .ff_clk ( fabric_clk ) ) ;
+    .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_tapbuf_size2_10 mux_fabric_out_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
          } ) ,
     .sram ( mux_1level_tapbuf_size2_0_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p6 ( p6 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+    .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p_abuf0 ( p_abuf0 ) , .p6 ( p6 ) ) ;
 grid_clb_mux_1level_tapbuf_size2_11 mux_fabric_out_1 (
     .in ( { fabric_sc_out[0] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
          } ) ,
     .sram ( mux_1level_tapbuf_size2_1_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) ,
-    .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p6 ( p6 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p_abuf0 ( p_abuf1 ) , .p3 ( p3 ) ) ;
 grid_clb_mux_1level_tapbuf_size2_mem_10 mem_fabric_out_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
     .ccff_tail ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_1level_tapbuf_size2_0_sram ) ) ;
+    .mem_out ( mux_1level_tapbuf_size2_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 grid_clb_mux_1level_tapbuf_size2_mem_11 mem_fabric_out_1 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , 
-    .mem_out ( mux_1level_tapbuf_size2_1_sram ) ) ;
+    .mem_out ( mux_1level_tapbuf_size2_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_84__83 ( .A ( fabric_sc_out[0] ) , 
-    .X ( fabric_reg_out[0] ) ) ;
+    .X ( fabric_reg_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_mux_1level_size2_22 mux_ff_0_D_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , 
         fabric_reg_in[0] } ) ,
     .sram ( mux_1level_size2_0_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) ,
-    .out ( mux_1level_size2_0_out ) , .p6 ( p6 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+    .out ( mux_1level_size2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p6 ( p6 ) ) ;
 grid_clb_mux_1level_size2_23 mux_ff_1_D_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
          } ) ,
     .sram ( mux_1level_size2_1_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) ,
-    .out ( mux_1level_size2_1_out ) , .p6 ( p6 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( mux_1level_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p6 ( p6 ) ) ;
 grid_clb_mux_1level_size2_mem_22 mem_ff_0_D_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_1level_size2_0_sram ) ) ;
+    .mem_out ( mux_1level_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_size2_mem_23 mem_ff_1_D_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_5 ( pReset , prog_clk , 
     Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , 
     fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , 
-    ccff_tail , p_abuf0 , p_abuf1 , p6 ) ;
+    ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p3 , p6 ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] Test_en ;
@@ -75161,567 +99991,801 @@
 output [0:0] fle_sc_out ;
 output [0:0] fle_cout ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
 output p_abuf1 ;
+input  p3 ;
 input  p6 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , 
     .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , 
-    .fabric_sc_in ( fle_sc_in ) ,
-    .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+    .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , 
     .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , 
     .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , 
-    .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) ,
-    .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) ,
-    .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , 
+    .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , 
+    .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p3 ( p3 ) , 
     .p6 ( p6 ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_19 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_69__68 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_69__68 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_18 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_68__67 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_68__67 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_19 ( in , mem , mem_inv , out , 
-    p4 ) ;
+    VDD , VSS , p6 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
-input  p4 ;
+input  VDD ;
+input  VSS ;
+input  p6 ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
-    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p4 ) , .S0 ( mem[0] ) , 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p6 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_29 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_29 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_67__66 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_67__66 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_19 ( in , sram , sram_inv , out , p4 ) ;
+module grid_clb_mux_1level_size2_19 ( in , sram , sram_inv , out , VDD , VSS , 
+    p6 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
-input  p4 ;
+input  VDD ;
+input  VSS ;
+input  p6 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3_29 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3_19 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p4 ( p4 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p6 ( p6 ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_18 ( in , mem , mem_inv , out , 
-    p4 ) ;
+    VDD , VSS , p4 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p4 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p4 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_28 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_28 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_66__65 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_66__65 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_18 ( in , sram , sram_inv , out , p4 ) ;
+module grid_clb_mux_1level_size2_18 ( in , sram , sram_inv , out , VDD , VSS , 
+    p4 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p4 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3_28 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3_18 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p4 ( p4 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p4 ( p4 ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_tapbuf_size2_mem_9 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_65__64 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_65__64 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_tapbuf_size2_mem_8 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_64__63 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_64__63 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_tapbuf_basis_input3_mem3_9 ( in , mem , mem_inv , 
-    out , p4 ) ;
+    out , VDD , VSS , p6 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
-input  p4 ;
+input  VDD ;
+input  VSS ;
+input  p6 ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
-    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p4 ) , .S0 ( mem[0] ) , 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p6 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_27 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_27 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_63__62 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_63__62 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_tapbuf_size2_9 ( in , sram , sram_inv , out , 
-    p_abuf0 , p4 ) ;
+module grid_clb_mux_1level_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , 
+    VSS , p_abuf0 , p6 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
-input  p4 ;
+input  p6 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_local_encoder2to3_27 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_tapbuf_basis_input3_mem3_9 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p4 ( p4 ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_159 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
-sky130_fd_sc_hd__inv_2 BINV_R_160 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
+    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p6 ( p6 ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_160 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_161 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_tapbuf_basis_input3_mem3_8 ( in , mem , mem_inv , 
-    out , p4 ) ;
+    out , VDD , VSS , p6 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
-input  p4 ;
+input  VDD ;
+input  VSS ;
+input  p6 ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
-    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p4 ) , .S0 ( mem[0] ) , 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p6 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_26 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_26 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_62__61 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_62__61 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_tapbuf_size2_8 ( in , sram , sram_inv , out , 
-    p_abuf0 , p4 ) ;
+module grid_clb_mux_1level_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , 
+    VSS , p_abuf0 , p6 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
-input  p4 ;
+input  p6 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_local_encoder2to3_26 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_tapbuf_basis_input3_mem3_8 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p4 ( p4 ) ) ;
-sky130_fd_sc_hd__inv_2 BINV_R_156 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_157 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
+    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p6 ( p6 ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_157 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_158 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 ( 
-    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ;
 input  [0:0] Test_en ;
 input  [0:0] ff_D ;
 input  [0:0] ff_DI ;
 input  [0:0] ff_reset ;
 output [0:0] ff_Q ;
 input  [0:0] ff_clk ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , 
     .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , 
-    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 ( 
-    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ;
 input  [0:0] Test_en ;
 input  [0:0] ff_D ;
 input  [0:0] ff_DI ;
 input  [0:0] ff_reset ;
 output [0:0] ff_Q ;
 input  [0:0] ff_clk ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , 
     .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , 
-    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_17 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_61__60 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_61__60 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_16 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_60__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_60__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_17 ( in , mem , mem_inv , out , 
-    p4 ) ;
+    VDD , VSS , p4 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p4 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p4 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_25 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_25 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_17 ( in , sram , sram_inv , out , p4 ) ;
+module grid_clb_mux_1level_size2_17 ( in , sram , sram_inv , out , VDD , VSS , 
+    p4 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p4 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3_25 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3_17 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p4 ( p4 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p4 ( p4 ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_16 ( in , mem , mem_inv , out , 
-    p4 ) ;
+    VDD , VSS , p4 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p4 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p4 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_24 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_24 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_16 ( in , sram , sram_inv , out , p4 ) ;
+module grid_clb_mux_1level_size2_16 ( in , sram , sram_inv , out , VDD , VSS , 
+    p4 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p4 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3_24 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3_16 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p4 ( p4 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p4 ( p4 ) ) ;
 endmodule
 
 
-module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_4 ( A0 , A1 , S , X ) ;
+module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_4 ( A0 , A1 , S , X , VDD , 
+    VSS ) ;
 input  A0 ;
 input  A1 ;
 input  S ;
 output X ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , 
-    .X ( X_gOb13 ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_4 ( 
     carry_follower_a , carry_follower_b , carry_follower_cin , 
-    carry_follower_cout ) ;
+    carry_follower_cout , VDD , VSS ) ;
 input  [0:0] carry_follower_a ;
 input  [0:0] carry_follower_b ;
 input  [0:0] carry_follower_cin ;
 output [0:0] carry_follower_cout ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_4 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( 
     .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , 
-    .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ;
+    .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:16] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_57__56 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_57__56 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_frac_lut4_mux_4 ( in , sram , sram_inv , lut2_out , lut3_out , 
-    lut4_out ) ;
+    lut4_out , VDD , VSS ) ;
 input  [0:15] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:1] lut2_out ;
 output [0:1] lut3_out ;
 output [0:0] lut4_out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
 wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
@@ -75733,52 +100797,64 @@
 wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
 wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
 wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
-    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
-    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
-    .X ( lut2_out[0] ) ) ;
+    .X ( lut2_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
-    .X ( lut2_out[1] ) ) ;
+    .X ( lut2_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , 
-    .X ( lut3_out[0] ) ) ;
+    .X ( lut3_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , 
-    .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ;
+    .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , 
-    .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+    .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_frac_lut4_4 ( in , sram , sram_inv , mode , mode_inv , 
-    lut2_out , lut3_out , lut4_out ) ;
+    lut2_out , lut3_out , lut4_out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:15] sram ;
 input  [0:15] sram_inv ;
@@ -75787,35 +100863,41 @@
 output [0:1] lut2_out ;
 output [0:1] lut3_out ;
 output [0:0] lut4_out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
 wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
 wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
 wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
 wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , 
-    .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+    .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+    .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
-sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+    .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , 
+    .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( 
     .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+    .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_frac_lut4_mux_4 frac_lut4_mux_0_ ( .in ( sram ) ,
     .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
         SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
-    .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+    .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 ( 
     pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , 
-    frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ;
+    frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:3] frac_lut4_in ;
@@ -75824,9 +100906,13 @@
 output [0:1] frac_lut4_lut3_out ;
 output [0:0] frac_lut4_lut4_out ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] frac_lut4_0_mode ;
 wire [0:15] frac_lut4_0_sram ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_frac_lut4_4 frac_lut4_0_ ( .in ( frac_lut4_in ) , 
     .sram ( frac_lut4_0_sram ) ,
@@ -75841,7 +100927,7 @@
     .mode ( frac_lut4_0_mode ) ,
     .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
     .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , 
-    .lut4_out ( frac_lut4_lut4_out ) ) ;
+    .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
     .ccff_tail ( ccff_tail ) ,
@@ -75850,13 +100936,14 @@
         frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , 
         frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , 
         frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , 
-        frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+        frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ,
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( 
     pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , 
-    frac_logic_out , frac_logic_cout , ccff_tail , p4 ) ;
+    frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p4 ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:3] frac_logic_in ;
@@ -75865,6 +100952,8 @@
 output [0:1] frac_logic_out ;
 output [0:0] frac_logic_cout ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 input  p4 ;
 
 wire [0:0] direct_interc_5_out ;
@@ -75876,6 +100965,8 @@
 wire [0:0] mux_1level_size2_1_out ;
 wire [0:1] mux_1level_size2_1_sram ;
 wire [0:0] mux_1level_size2_mem_0_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
@@ -75888,41 +100979,44 @@
         frac_logic_out[1] } ) ,
     
     .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , 
-    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( 
     .carry_follower_a ( direct_interc_5_out ) , 
     .carry_follower_b ( frac_logic_cin ) , 
-    .carry_follower_cin ( direct_interc_7_out ) ,
-    .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+    .carry_follower_cin ( direct_interc_7_out ) , 
+    .carry_follower_cout ( frac_logic_cout ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_size2_16 mux_frac_logic_out_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
          } ) ,
     .sram ( mux_1level_size2_0_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( frac_logic_out[0] ) , .p4 ( p4 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+    .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p4 ( p4 ) ) ;
 grid_clb_mux_1level_size2_17 mux_frac_lut4_0_in_2 (
     .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) ,
     .sram ( mux_1level_size2_1_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) ,
-    .out ( mux_1level_size2_1_out ) , .p4 ( p4 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( mux_1level_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p4 ( p4 ) ) ;
 grid_clb_mux_1level_size2_mem_16 mem_frac_logic_out_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , 
     .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_1level_size2_0_sram ) ) ;
+    .mem_out ( mux_1level_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_size2_mem_17 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( 
     pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , 
     fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , 
-    fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , 
-    p_abuf1 , p4 ) ;
+    fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , 
+    p_abuf0 , p_abuf1 , p4 , p6 ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] Test_en ;
@@ -75938,14 +101032,16 @@
 output [0:0] fabric_sc_out ;
 output [0:0] fabric_cout ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
 output p_abuf1 ;
 input  p4 ;
+input  p6 ;
 
 wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
 wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
 wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
-wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ;
 wire [0:0] mux_1level_size2_0_out ;
 wire [0:1] mux_1level_size2_0_sram ;
 wire [0:0] mux_1level_size2_1_out ;
@@ -75955,84 +101051,91 @@
 wire [0:1] mux_1level_tapbuf_size2_1_sram ;
 wire [0:0] mux_1level_tapbuf_size2_mem_0_ccff_tail ;
 wire [0:0] mux_1level_tapbuf_size2_mem_1_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
-    .frac_logic_in ( fabric_in ) , 
-    .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , 
+    .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , 
     .ccff_head ( ccff_head ) , 
-    .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
-    .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    
+    .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , 
+    .frac_logic_cout ( fabric_cout ) , 
     .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
-    .p4 ( p4 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p4 ( p4 ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( 
     .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) , 
     .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , 
     .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , 
-    .ff_clk ( fabric_clk ) ) ;
+    .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( 
     .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_1_out ) , 
     .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , 
     .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , 
-    .ff_clk ( fabric_clk ) ) ;
+    .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_tapbuf_size2_8 mux_fabric_out_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
          } ) ,
     .sram ( mux_1level_tapbuf_size2_0_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p4 ( p4 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+    .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p_abuf0 ( p_abuf0 ) , .p6 ( p6 ) ) ;
 grid_clb_mux_1level_tapbuf_size2_9 mux_fabric_out_1 (
     .in ( { fabric_sc_out[0] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
          } ) ,
     .sram ( mux_1level_tapbuf_size2_1_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) ,
-    .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p4 ( p4 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p_abuf0 ( p_abuf1 ) , .p6 ( p6 ) ) ;
 grid_clb_mux_1level_tapbuf_size2_mem_8 mem_fabric_out_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
     .ccff_tail ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_1level_tapbuf_size2_0_sram ) ) ;
+    .mem_out ( mux_1level_tapbuf_size2_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 grid_clb_mux_1level_tapbuf_size2_mem_9 mem_fabric_out_1 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , 
-    .mem_out ( mux_1level_tapbuf_size2_1_sram ) ) ;
+    .mem_out ( mux_1level_tapbuf_size2_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( fabric_sc_out[0] ) , 
-    .X ( fabric_reg_out[0] ) ) ;
+    .X ( fabric_reg_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_mux_1level_size2_18 mux_ff_0_D_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , 
         fabric_reg_in[0] } ) ,
     .sram ( mux_1level_size2_0_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) ,
-    .out ( mux_1level_size2_0_out ) , .p4 ( p4 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+    .out ( mux_1level_size2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p4 ( p4 ) ) ;
 grid_clb_mux_1level_size2_19 mux_ff_1_D_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
          } ) ,
     .sram ( mux_1level_size2_1_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) ,
-    .out ( mux_1level_size2_1_out ) , .p4 ( p4 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( mux_1level_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p6 ( p6 ) ) ;
 grid_clb_mux_1level_size2_mem_18 mem_ff_0_D_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_1level_size2_0_sram ) ) ;
+    .mem_out ( mux_1level_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_size2_mem_19 mem_ff_1_D_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_4 ( pReset , prog_clk , 
     Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , 
     fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , 
-    ccff_tail , p_abuf0 , p_abuf1 , p4 ) ;
+    ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p4 , p6 ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] Test_en ;
@@ -76048,567 +101151,801 @@
 output [0:0] fle_sc_out ;
 output [0:0] fle_cout ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
 output p_abuf1 ;
 input  p4 ;
+input  p6 ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , 
     .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , 
-    .fabric_sc_in ( fle_sc_in ) ,
-    .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+    .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , 
     .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , 
     .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , 
-    .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) ,
-    .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) ,
-    .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , 
-    .p4 ( p4 ) ) ;
+    .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , 
+    .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p4 ( p4 ) , 
+    .p6 ( p6 ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_15 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_14 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_15 ( in , mem , mem_inv , out , 
-    p6 ) ;
+    VDD , VSS , p6 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p6 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p6 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_23 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_23 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_15 ( in , sram , sram_inv , out , p6 ) ;
+module grid_clb_mux_1level_size2_15 ( in , sram , sram_inv , out , VDD , VSS , 
+    p6 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p6 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3_23 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3_15 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p6 ( p6 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p6 ( p6 ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_14 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p2 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
-input  p0 ;
+input  VDD ;
+input  VSS ;
+input  p2 ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
-    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p2 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_22 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_22 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_14 ( in , sram , sram_inv , out , p0 ) ;
+module grid_clb_mux_1level_size2_14 ( in , sram , sram_inv , out , VDD , VSS , 
+    p2 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
-input  p0 ;
+input  VDD ;
+input  VSS ;
+input  p2 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3_22 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3_14 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p2 ( p2 ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_tapbuf_size2_mem_7 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_tapbuf_size2_mem_6 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_tapbuf_basis_input3_mem3_7 ( in , mem , mem_inv , 
-    out , p2 ) ;
+    out , VDD , VSS , p2 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p2 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p2 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_21 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_21 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_tapbuf_size2_7 ( in , sram , sram_inv , out , 
-    p_abuf0 , p2 ) ;
+module grid_clb_mux_1level_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , 
+    VSS , p_abuf0 , p2 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
 input  p2 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_local_encoder2to3_21 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_tapbuf_basis_input3_mem3_7 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ;
-sky130_fd_sc_hd__inv_2 BINV_R_153 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_154 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
+    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p2 ( p2 ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_154 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_155 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_tapbuf_basis_input3_mem3_6 ( in , mem , mem_inv , 
-    out , p2 ) ;
+    out , VDD , VSS , p2 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p2 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p2 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_20 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_20 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_tapbuf_size2_6 ( in , sram , sram_inv , out , 
-    p_abuf0 , p2 ) ;
+module grid_clb_mux_1level_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , 
+    VSS , p_abuf0 , p2 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
 input  p2 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_local_encoder2to3_20 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_tapbuf_basis_input3_mem3_6 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ;
-sky130_fd_sc_hd__inv_2 BINV_R_150 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_151 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
+    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p2 ( p2 ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_151 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_152 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 ( 
-    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ;
 input  [0:0] Test_en ;
 input  [0:0] ff_D ;
 input  [0:0] ff_DI ;
 input  [0:0] ff_reset ;
 output [0:0] ff_Q ;
 input  [0:0] ff_clk ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , 
     .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , 
-    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 ( 
-    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ;
 input  [0:0] Test_en ;
 input  [0:0] ff_D ;
 input  [0:0] ff_DI ;
 input  [0:0] ff_reset ;
 output [0:0] ff_Q ;
 input  [0:0] ff_clk ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , 
     .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , 
-    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_13 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_12 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_13 ( in , mem , mem_inv , out , 
-    p2 ) ;
+    VDD , VSS , p2 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p2 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p2 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_19 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_19 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_13 ( in , sram , sram_inv , out , p2 ) ;
+module grid_clb_mux_1level_size2_13 ( in , sram , sram_inv , out , VDD , VSS , 
+    p2 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p2 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3_19 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3_13 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p2 ( p2 ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_12 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p2 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
-input  p0 ;
+input  VDD ;
+input  VSS ;
+input  p2 ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
-    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p2 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_18 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_18 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_12 ( in , sram , sram_inv , out , p0 ) ;
+module grid_clb_mux_1level_size2_12 ( in , sram , sram_inv , out , VDD , VSS , 
+    p2 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
-input  p0 ;
+input  VDD ;
+input  VSS ;
+input  p2 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3_18 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3_12 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p2 ( p2 ) ) ;
 endmodule
 
 
-module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_3 ( A0 , A1 , S , X ) ;
+module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_3 ( A0 , A1 , S , X , VDD , 
+    VSS ) ;
 input  A0 ;
 input  A1 ;
 input  S ;
 output X ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , 
-    .X ( X_gOb10 ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_3 ( 
     carry_follower_a , carry_follower_b , carry_follower_cin , 
-    carry_follower_cout ) ;
+    carry_follower_cout , VDD , VSS ) ;
 input  [0:0] carry_follower_a ;
 input  [0:0] carry_follower_b ;
 input  [0:0] carry_follower_cin ;
 output [0:0] carry_follower_cout ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_3 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( 
     .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , 
-    .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ;
+    .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:16] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_frac_lut4_mux_3 ( in , sram , sram_inv , lut2_out , lut3_out , 
-    lut4_out ) ;
+    lut4_out , VDD , VSS ) ;
 input  [0:15] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:1] lut2_out ;
 output [0:1] lut3_out ;
 output [0:0] lut4_out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
 wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
@@ -76620,52 +101957,64 @@
 wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
 wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
 wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
-    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
-    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
-    .X ( lut2_out[0] ) ) ;
+    .X ( lut2_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
-    .X ( lut2_out[1] ) ) ;
+    .X ( lut2_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , 
-    .X ( lut3_out[0] ) ) ;
+    .X ( lut3_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , 
-    .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ;
+    .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , 
-    .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+    .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_frac_lut4_3 ( in , sram , sram_inv , mode , mode_inv , 
-    lut2_out , lut3_out , lut4_out ) ;
+    lut2_out , lut3_out , lut4_out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:15] sram ;
 input  [0:15] sram_inv ;
@@ -76674,35 +102023,41 @@
 output [0:1] lut2_out ;
 output [0:1] lut3_out ;
 output [0:0] lut4_out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
 wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
 wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
 wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
 wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , 
-    .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+    .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+    .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
-sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+    .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , 
+    .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( 
     .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+    .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_frac_lut4_mux_3 frac_lut4_mux_0_ ( .in ( sram ) ,
     .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
         SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
-    .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+    .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 ( 
     pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , 
-    frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ;
+    frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:3] frac_lut4_in ;
@@ -76711,9 +102066,13 @@
 output [0:1] frac_lut4_lut3_out ;
 output [0:0] frac_lut4_lut4_out ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] frac_lut4_0_mode ;
 wire [0:15] frac_lut4_0_sram ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_frac_lut4_3 frac_lut4_0_ ( .in ( frac_lut4_in ) , 
     .sram ( frac_lut4_0_sram ) ,
@@ -76728,7 +102087,7 @@
     .mode ( frac_lut4_0_mode ) ,
     .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
     .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , 
-    .lut4_out ( frac_lut4_lut4_out ) ) ;
+    .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
     .ccff_tail ( ccff_tail ) ,
@@ -76737,13 +102096,14 @@
         frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , 
         frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , 
         frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , 
-        frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+        frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ,
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 ( 
     pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , 
-    frac_logic_out , frac_logic_cout , ccff_tail , p0 , p2 ) ;
+    frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p2 ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:3] frac_logic_in ;
@@ -76752,7 +102112,8 @@
 output [0:1] frac_logic_out ;
 output [0:0] frac_logic_cout ;
 output [0:0] ccff_tail ;
-input  p0 ;
+input  VDD ;
+input  VSS ;
 input  p2 ;
 
 wire [0:0] direct_interc_5_out ;
@@ -76764,6 +102125,8 @@
 wire [0:0] mux_1level_size2_1_out ;
 wire [0:1] mux_1level_size2_1_sram ;
 wire [0:0] mux_1level_size2_mem_0_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
@@ -76776,41 +102139,44 @@
         frac_logic_out[1] } ) ,
     
     .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , 
-    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( 
     .carry_follower_a ( direct_interc_5_out ) , 
     .carry_follower_b ( frac_logic_cin ) , 
-    .carry_follower_cin ( direct_interc_7_out ) ,
-    .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+    .carry_follower_cin ( direct_interc_7_out ) , 
+    .carry_follower_cout ( frac_logic_cout ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_size2_12 mux_frac_logic_out_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
          } ) ,
     .sram ( mux_1level_size2_0_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+    .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ;
 grid_clb_mux_1level_size2_13 mux_frac_lut4_0_in_2 (
     .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) ,
     .sram ( mux_1level_size2_1_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) ,
-    .out ( mux_1level_size2_1_out ) , .p2 ( p2 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( mux_1level_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p2 ( p2 ) ) ;
 grid_clb_mux_1level_size2_mem_12 mem_frac_logic_out_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , 
     .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_1level_size2_0_sram ) ) ;
+    .mem_out ( mux_1level_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_size2_mem_13 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( 
     pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , 
     fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , 
-    fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , 
-    p_abuf1 , p0 , p2 , p6 ) ;
+    fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , 
+    p_abuf0 , p_abuf1 , p2 , p6 ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] Test_en ;
@@ -76826,16 +102192,16 @@
 output [0:0] fabric_sc_out ;
 output [0:0] fabric_cout ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
 output p_abuf1 ;
-input  p0 ;
 input  p2 ;
 input  p6 ;
 
 wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
 wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
 wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
-wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ;
 wire [0:0] mux_1level_size2_0_out ;
 wire [0:1] mux_1level_size2_0_sram ;
 wire [0:0] mux_1level_size2_1_out ;
@@ -76845,84 +102211,91 @@
 wire [0:1] mux_1level_tapbuf_size2_1_sram ;
 wire [0:0] mux_1level_tapbuf_size2_mem_0_ccff_tail ;
 wire [0:0] mux_1level_tapbuf_size2_mem_1_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
-    .frac_logic_in ( fabric_in ) , 
-    .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , 
+    .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , 
     .ccff_head ( ccff_head ) , 
-    .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
-    .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    
+    .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , 
+    .frac_logic_cout ( fabric_cout ) , 
     .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
-    .p0 ( p0 ) , .p2 ( p2 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( 
     .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) , 
     .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , 
     .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , 
-    .ff_clk ( fabric_clk ) ) ;
+    .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( 
     .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_1_out ) , 
     .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , 
     .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , 
-    .ff_clk ( fabric_clk ) ) ;
+    .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_tapbuf_size2_6 mux_fabric_out_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
          } ) ,
     .sram ( mux_1level_tapbuf_size2_0_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+    .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ;
 grid_clb_mux_1level_tapbuf_size2_7 mux_fabric_out_1 (
     .in ( { fabric_sc_out[0] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
          } ) ,
     .sram ( mux_1level_tapbuf_size2_1_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) ,
-    .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p2 ( p2 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p_abuf0 ( p_abuf1 ) , .p2 ( p2 ) ) ;
 grid_clb_mux_1level_tapbuf_size2_mem_6 mem_fabric_out_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
     .ccff_tail ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_1level_tapbuf_size2_0_sram ) ) ;
+    .mem_out ( mux_1level_tapbuf_size2_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 grid_clb_mux_1level_tapbuf_size2_mem_7 mem_fabric_out_1 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , 
-    .mem_out ( mux_1level_tapbuf_size2_1_sram ) ) ;
+    .mem_out ( mux_1level_tapbuf_size2_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_56__55 ( .A ( fabric_sc_out[0] ) , 
-    .X ( fabric_reg_out[0] ) ) ;
+    .X ( fabric_reg_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_mux_1level_size2_14 mux_ff_0_D_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , 
         fabric_reg_in[0] } ) ,
     .sram ( mux_1level_size2_0_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) ,
-    .out ( mux_1level_size2_0_out ) , .p0 ( p0 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+    .out ( mux_1level_size2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p2 ( p2 ) ) ;
 grid_clb_mux_1level_size2_15 mux_ff_1_D_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
          } ) ,
     .sram ( mux_1level_size2_1_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) ,
-    .out ( mux_1level_size2_1_out ) , .p6 ( p6 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( mux_1level_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p6 ( p6 ) ) ;
 grid_clb_mux_1level_size2_mem_14 mem_ff_0_D_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_1level_size2_0_sram ) ) ;
+    .mem_out ( mux_1level_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_size2_mem_15 mem_ff_1_D_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_3 ( pReset , prog_clk , 
     Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , 
     fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , 
-    ccff_tail , p_abuf0 , p_abuf1 , p0 , p2 , p6 ) ;
+    ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p2 , p6 ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] Test_en ;
@@ -76938,569 +102311,801 @@
 output [0:0] fle_sc_out ;
 output [0:0] fle_cout ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
 output p_abuf1 ;
-input  p0 ;
 input  p2 ;
 input  p6 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , 
     .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , 
-    .fabric_sc_in ( fle_sc_in ) ,
-    .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+    .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , 
     .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , 
     .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , 
-    .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) ,
-    .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) ,
-    .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , 
-    .p0 ( p0 ) , .p2 ( p2 ) , .p6 ( p6 ) ) ;
+    .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , 
+    .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) , 
+    .p6 ( p6 ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_11 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_10 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_11 ( in , mem , mem_inv , out , 
-    p2 ) ;
+    VDD , VSS , p2 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p2 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p2 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_17 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_17 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_11 ( in , sram , sram_inv , out , p2 ) ;
+module grid_clb_mux_1level_size2_11 ( in , sram , sram_inv , out , VDD , VSS , 
+    p2 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p2 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3_17 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3_11 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p2 ( p2 ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_10 ( in , mem , mem_inv , out , 
-    p2 ) ;
+    VDD , VSS , p5 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
-input  p2 ;
-
-sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
-    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p2 ) , .S0 ( mem[0] ) , 
-    .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
-endmodule
-
-
-module grid_clb_local_encoder2to3_16 ( addr , data , data_inv ) ;
-input  [0:1] addr ;
-output [0:2] data ;
-output [0:2] data_inv ;
-
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
-endmodule
-
-
-module grid_clb_mux_1level_size2_10 ( in , sram , sram_inv , out , p2 ) ;
-input  [0:1] in ;
-input  [0:1] sram ;
-input  [0:1] sram_inv ;
-output [0:0] out ;
-input  p2 ;
-
-wire [0:2] local_encoder2to3_0_data ;
-wire [0:2] local_encoder2to3_0_data_inv ;
-wire [0:0] mux_1level_basis_input3_mem3_0_out ;
-
-sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
-grid_clb_local_encoder2to3_16 local_encoder2to3_0_ ( .addr ( sram ) , 
-    .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
-grid_clb_mux_1level_basis_input3_mem3_10 mux_l1_in_0_ (
-    .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
-    .mem ( local_encoder2to3_0_data ) , 
-    .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ;
-endmodule
-
-
-module grid_clb_mux_1level_tapbuf_size2_mem_5 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
-input  [0:0] pReset ;
-input  [0:0] prog_clk ;
-input  [0:0] ccff_head ;
-output [0:0] ccff_tail ;
-output [0:1] mem_out ;
-
-sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
-sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
-endmodule
-
-
-module grid_clb_mux_1level_tapbuf_size2_mem_4 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
-input  [0:0] pReset ;
-input  [0:0] prog_clk ;
-input  [0:0] ccff_head ;
-output [0:0] ccff_tail ;
-output [0:1] mem_out ;
-
-sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
-sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
-endmodule
-
-
-module grid_clb_mux_1level_tapbuf_basis_input3_mem3_5 ( in , mem , mem_inv , 
-    out , p2 ) ;
-input  [0:2] in ;
-input  [0:2] mem ;
-input  [0:2] mem_inv ;
-output [0:0] out ;
-input  p2 ;
-
-sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
-    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p2 ) , .S0 ( mem[0] ) , 
-    .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
-endmodule
-
-
-module grid_clb_local_encoder2to3_15 ( addr , data , data_inv ) ;
-input  [0:1] addr ;
-output [0:2] data ;
-output [0:2] data_inv ;
-
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
-endmodule
-
-
-module grid_clb_mux_1level_tapbuf_size2_5 ( in , sram , sram_inv , out , 
-    p_abuf0 , p2 ) ;
-input  [0:1] in ;
-input  [0:1] sram ;
-input  [0:1] sram_inv ;
-output [0:0] out ;
-output p_abuf0 ;
-input  p2 ;
-
-wire [0:2] local_encoder2to3_0_data ;
-wire [0:2] local_encoder2to3_0_data_inv ;
-wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
-
-grid_clb_local_encoder2to3_15 local_encoder2to3_0_ ( .addr ( sram ) , 
-    .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
-grid_clb_mux_1level_tapbuf_basis_input3_mem3_5 mux_l1_in_0_ (
-    .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
-    .mem ( local_encoder2to3_0_data ) , 
-    .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ;
-sky130_fd_sc_hd__inv_2 BINV_R_147 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_148 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
-endmodule
-
-
-module grid_clb_mux_1level_tapbuf_basis_input3_mem3_4 ( in , mem , mem_inv , 
-    out , p2 ) ;
-input  [0:2] in ;
-input  [0:2] mem ;
-input  [0:2] mem_inv ;
-output [0:0] out ;
-input  p2 ;
-
-sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
-    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p2 ) , .S0 ( mem[0] ) , 
-    .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
-endmodule
-
-
-module grid_clb_local_encoder2to3_14 ( addr , data , data_inv ) ;
-input  [0:1] addr ;
-output [0:2] data ;
-output [0:2] data_inv ;
-
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
-endmodule
-
-
-module grid_clb_mux_1level_tapbuf_size2_4 ( in , sram , sram_inv , out , 
-    p_abuf0 , p2 ) ;
-input  [0:1] in ;
-input  [0:1] sram ;
-input  [0:1] sram_inv ;
-output [0:0] out ;
-output p_abuf0 ;
-input  p2 ;
-
-wire [0:2] local_encoder2to3_0_data ;
-wire [0:2] local_encoder2to3_0_data_inv ;
-wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
-
-grid_clb_local_encoder2to3_14 local_encoder2to3_0_ ( .addr ( sram ) , 
-    .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
-grid_clb_mux_1level_tapbuf_basis_input3_mem3_4 mux_l1_in_0_ (
-    .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
-    .mem ( local_encoder2to3_0_data ) , 
-    .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ;
-sky130_fd_sc_hd__inv_2 BINV_R_144 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_145 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
-endmodule
-
-
-module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 ( 
-    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
-input  [0:0] Test_en ;
-input  [0:0] ff_D ;
-input  [0:0] ff_DI ;
-input  [0:0] ff_reset ;
-output [0:0] ff_Q ;
-input  [0:0] ff_clk ;
-
-sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , 
-    .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , 
-    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
-endmodule
-
-
-module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 ( 
-    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
-input  [0:0] Test_en ;
-input  [0:0] ff_D ;
-input  [0:0] ff_DI ;
-input  [0:0] ff_reset ;
-output [0:0] ff_Q ;
-input  [0:0] ff_clk ;
-
-sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , 
-    .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , 
-    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
-endmodule
-
-
-module grid_clb_mux_1level_size2_mem_9 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
-input  [0:0] pReset ;
-input  [0:0] prog_clk ;
-input  [0:0] ccff_head ;
-output [0:0] ccff_tail ;
-output [0:1] mem_out ;
-
-sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
-sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
-endmodule
-
-
-module grid_clb_mux_1level_size2_mem_8 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
-input  [0:0] pReset ;
-input  [0:0] prog_clk ;
-input  [0:0] ccff_head ;
-output [0:0] ccff_tail ;
-output [0:1] mem_out ;
-
-sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
-sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
-endmodule
-
-
-module grid_clb_mux_1level_basis_input3_mem3_9 ( in , mem , mem_inv , out , 
-    p5 ) ;
-input  [0:2] in ;
-input  [0:2] mem ;
-input  [0:2] mem_inv ;
-output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p5 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p5 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_13 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_16 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_9 ( in , sram , sram_inv , out , p5 ) ;
+module grid_clb_mux_1level_size2_10 ( in , sram , sram_inv , out , VDD , VSS , 
+    p5 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p5 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
-grid_clb_local_encoder2to3_13 local_encoder2to3_0_ ( .addr ( sram ) , 
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+grid_clb_local_encoder2to3_16 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
-grid_clb_mux_1level_basis_input3_mem3_9 mux_l1_in_0_ (
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_10 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p5 ( p5 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p5 ( p5 ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_basis_input3_mem3_8 ( in , mem , mem_inv , out , 
-    p2 ) ;
+module grid_clb_mux_1level_tapbuf_size2_mem_5 ( pReset , prog_clk , 
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_mem_4 ( pReset , prog_clk , 
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_basis_input3_mem3_5 ( in , mem , mem_inv , 
+    out , VDD , VSS , p2 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p2 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p2 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_12 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_15 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_8 ( in , sram , sram_inv , out , p2 ) ;
+module grid_clb_mux_1level_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , 
+    VSS , p_abuf0 , p2 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+output p_abuf0 ;
+input  p2 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
+
+grid_clb_local_encoder2to3_15 local_encoder2to3_0_ ( .addr ( sram ) , 
+    .data ( local_encoder2to3_0_data ) , 
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+grid_clb_mux_1level_tapbuf_basis_input3_mem3_5 mux_l1_in_0_ (
+    .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to3_0_data ) , 
+    .mem_inv ( local_encoder2to3_0_data_inv ) , 
+    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p2 ( p2 ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_148 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_149 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_basis_input3_mem3_4 ( in , mem , mem_inv , 
+    out , VDD , VSS , p5 ) ;
+input  [0:2] in ;
+input  [0:2] mem ;
+input  [0:2] mem_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p5 ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p5 ) , .S0 ( mem[0] ) , 
+    .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_14 ( addr , data , data_inv , VDD , VSS ) ;
+input  [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , 
+    VSS , p_abuf0 , p5 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+output p_abuf0 ;
+input  p5 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
+
+grid_clb_local_encoder2to3_14 local_encoder2to3_0_ ( .addr ( sram ) , 
+    .data ( local_encoder2to3_0_data ) , 
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+grid_clb_mux_1level_tapbuf_basis_input3_mem3_4 mux_l1_in_0_ (
+    .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to3_0_data ) , 
+    .mem_inv ( local_encoder2to3_0_data_inv ) , 
+    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p5 ( p5 ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_145 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_146 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 ( 
+    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ;
+input  [0:0] Test_en ;
+input  [0:0] ff_D ;
+input  [0:0] ff_DI ;
+input  [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input  [0:0] ff_clk ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , 
+    .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , 
+    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+endmodule
+
+
+module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 ( 
+    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ;
+input  [0:0] Test_en ;
+input  [0:0] ff_D ;
+input  [0:0] ff_DI ;
+input  [0:0] ff_reset ;
+output [0:0] ff_Q ;
+input  [0:0] ff_clk ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , 
+    .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , 
+    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_9 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_mem_8 ( pReset , prog_clk , ccff_head , 
+    ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_9 ( in , mem , mem_inv , out , 
+    VDD , VSS , p5 ) ;
+input  [0:2] in ;
+input  [0:2] mem ;
+input  [0:2] mem_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p5 ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p5 ) , .S0 ( mem[0] ) , 
+    .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_13 ( addr , data , data_inv , VDD , VSS ) ;
+input  [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_9 ( in , sram , sram_inv , out , VDD , VSS , 
+    p5 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p5 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+grid_clb_local_encoder2to3_13 local_encoder2to3_0_ ( .addr ( sram ) , 
+    .data ( local_encoder2to3_0_data ) , 
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_9 mux_l1_in_0_ (
+    .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to3_0_data ) , 
+    .mem_inv ( local_encoder2to3_0_data_inv ) , 
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p5 ( p5 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_basis_input3_mem3_8 ( in , mem , mem_inv , out , 
+    VDD , VSS , p2 ) ;
+input  [0:2] in ;
+input  [0:2] mem ;
+input  [0:2] mem_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p2 ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p2 ) , .S0 ( mem[0] ) , 
+    .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_12 ( addr , data , data_inv , VDD , VSS ) ;
+input  [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_size2_8 ( in , sram , sram_inv , out , VDD , VSS , 
+    p2 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p2 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3_12 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3_8 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p2 ( p2 ) ) ;
 endmodule
 
 
-module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_2 ( A0 , A1 , S , X ) ;
+module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_2 ( A0 , A1 , S , X , VDD , 
+    VSS ) ;
 input  A0 ;
 input  A1 ;
 input  S ;
 output X ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , 
-    .X ( X_gOb7 ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_2 ( 
     carry_follower_a , carry_follower_b , carry_follower_cin , 
-    carry_follower_cout ) ;
+    carry_follower_cout , VDD , VSS ) ;
 input  [0:0] carry_follower_a ;
 input  [0:0] carry_follower_b ;
 input  [0:0] carry_follower_cin ;
 output [0:0] carry_follower_cout ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_2 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( 
     .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , 
-    .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ;
+    .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:16] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_frac_lut4_mux_2 ( in , sram , sram_inv , lut2_out , lut3_out , 
-    lut4_out ) ;
+    lut4_out , VDD , VSS ) ;
 input  [0:15] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:1] lut2_out ;
 output [0:1] lut3_out ;
 output [0:0] lut4_out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
 wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
@@ -77512,52 +103117,64 @@
 wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
 wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
 wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
-    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
-    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
-    .X ( lut2_out[0] ) ) ;
+    .X ( lut2_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
-    .X ( lut2_out[1] ) ) ;
+    .X ( lut2_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , 
-    .X ( lut3_out[0] ) ) ;
+    .X ( lut3_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , 
-    .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ;
+    .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , 
-    .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+    .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_frac_lut4_2 ( in , sram , sram_inv , mode , mode_inv , 
-    lut2_out , lut3_out , lut4_out ) ;
+    lut2_out , lut3_out , lut4_out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:15] sram ;
 input  [0:15] sram_inv ;
@@ -77566,35 +103183,41 @@
 output [0:1] lut2_out ;
 output [0:1] lut3_out ;
 output [0:0] lut4_out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
 wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
 wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
 wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
 wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , 
-    .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+    .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+    .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
-sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+    .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , 
+    .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( 
     .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+    .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_frac_lut4_mux_2 frac_lut4_mux_0_ ( .in ( sram ) ,
     .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
         SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
-    .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+    .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 ( 
     pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , 
-    frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ;
+    frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:3] frac_lut4_in ;
@@ -77603,9 +103226,13 @@
 output [0:1] frac_lut4_lut3_out ;
 output [0:0] frac_lut4_lut4_out ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] frac_lut4_0_mode ;
 wire [0:15] frac_lut4_0_sram ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_frac_lut4_2 frac_lut4_0_ ( .in ( frac_lut4_in ) , 
     .sram ( frac_lut4_0_sram ) ,
@@ -77620,7 +103247,7 @@
     .mode ( frac_lut4_0_mode ) ,
     .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
     .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , 
-    .lut4_out ( frac_lut4_lut4_out ) ) ;
+    .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
     .ccff_tail ( ccff_tail ) ,
@@ -77629,13 +103256,14 @@
         frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , 
         frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , 
         frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , 
-        frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+        frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ,
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( 
     pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , 
-    frac_logic_out , frac_logic_cout , ccff_tail , p2 , p5 ) ;
+    frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p2 , p5 ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:3] frac_logic_in ;
@@ -77644,6 +103272,8 @@
 output [0:1] frac_logic_out ;
 output [0:0] frac_logic_cout ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 input  p2 ;
 input  p5 ;
 
@@ -77656,6 +103286,8 @@
 wire [0:0] mux_1level_size2_1_out ;
 wire [0:1] mux_1level_size2_1_sram ;
 wire [0:0] mux_1level_size2_mem_0_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
@@ -77668,41 +103300,44 @@
         frac_logic_out[1] } ) ,
     
     .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , 
-    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( 
     .carry_follower_a ( direct_interc_5_out ) , 
     .carry_follower_b ( frac_logic_cin ) , 
-    .carry_follower_cin ( direct_interc_7_out ) ,
-    .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+    .carry_follower_cin ( direct_interc_7_out ) , 
+    .carry_follower_cout ( frac_logic_cout ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_size2_8 mux_frac_logic_out_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
          } ) ,
     .sram ( mux_1level_size2_0_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+    .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ;
 grid_clb_mux_1level_size2_9 mux_frac_lut4_0_in_2 (
     .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) ,
     .sram ( mux_1level_size2_1_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) ,
-    .out ( mux_1level_size2_1_out ) , .p5 ( p5 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( mux_1level_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p5 ( p5 ) ) ;
 grid_clb_mux_1level_size2_mem_8 mem_frac_logic_out_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , 
     .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_1level_size2_0_sram ) ) ;
+    .mem_out ( mux_1level_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_size2_mem_9 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( 
     pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , 
     fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , 
-    fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , 
-    p_abuf1 , p2 , p5 ) ;
+    fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , 
+    p_abuf0 , p_abuf1 , p2 , p5 ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] Test_en ;
@@ -77718,6 +103353,8 @@
 output [0:0] fabric_sc_out ;
 output [0:0] fabric_cout ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
 output p_abuf1 ;
 input  p2 ;
@@ -77726,7 +103363,6 @@
 wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
 wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
 wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
-wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ;
 wire [0:0] mux_1level_size2_0_out ;
 wire [0:1] mux_1level_size2_0_sram ;
 wire [0:0] mux_1level_size2_1_out ;
@@ -77736,84 +103372,91 @@
 wire [0:1] mux_1level_tapbuf_size2_1_sram ;
 wire [0:0] mux_1level_tapbuf_size2_mem_0_ccff_tail ;
 wire [0:0] mux_1level_tapbuf_size2_mem_1_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
-    .frac_logic_in ( fabric_in ) , 
-    .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , 
+    .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , 
     .ccff_head ( ccff_head ) , 
-    .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
-    .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    
+    .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , 
+    .frac_logic_cout ( fabric_cout ) , 
     .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
-    .p2 ( p2 ) , .p5 ( p5 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) , .p5 ( p5 ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( 
     .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) , 
     .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , 
     .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , 
-    .ff_clk ( fabric_clk ) ) ;
+    .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( 
     .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_1_out ) , 
     .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , 
     .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , 
-    .ff_clk ( fabric_clk ) ) ;
+    .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_tapbuf_size2_4 mux_fabric_out_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
          } ) ,
     .sram ( mux_1level_tapbuf_size2_0_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+    .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p_abuf0 ( p_abuf0 ) , .p5 ( p5 ) ) ;
 grid_clb_mux_1level_tapbuf_size2_5 mux_fabric_out_1 (
     .in ( { fabric_sc_out[0] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
          } ) ,
     .sram ( mux_1level_tapbuf_size2_1_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) ,
-    .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p2 ( p2 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p_abuf0 ( p_abuf1 ) , .p2 ( p2 ) ) ;
 grid_clb_mux_1level_tapbuf_size2_mem_4 mem_fabric_out_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
     .ccff_tail ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_1level_tapbuf_size2_0_sram ) ) ;
+    .mem_out ( mux_1level_tapbuf_size2_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 grid_clb_mux_1level_tapbuf_size2_mem_5 mem_fabric_out_1 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , 
-    .mem_out ( mux_1level_tapbuf_size2_1_sram ) ) ;
+    .mem_out ( mux_1level_tapbuf_size2_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( fabric_sc_out[0] ) , 
-    .X ( fabric_reg_out[0] ) ) ;
+    .X ( fabric_reg_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_mux_1level_size2_10 mux_ff_0_D_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , 
         fabric_reg_in[0] } ) ,
     .sram ( mux_1level_size2_0_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) ,
-    .out ( mux_1level_size2_0_out ) , .p2 ( p2 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+    .out ( mux_1level_size2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p5 ( p5 ) ) ;
 grid_clb_mux_1level_size2_11 mux_ff_1_D_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
          } ) ,
     .sram ( mux_1level_size2_1_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) ,
-    .out ( mux_1level_size2_1_out ) , .p2 ( p2 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( mux_1level_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p2 ( p2 ) ) ;
 grid_clb_mux_1level_size2_mem_10 mem_ff_0_D_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_1level_size2_0_sram ) ) ;
+    .mem_out ( mux_1level_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_size2_mem_11 mem_ff_1_D_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_2 ( pReset , prog_clk , 
     Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , 
     fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , 
-    ccff_tail , p_abuf0 , p_abuf1 , p2 , p5 ) ;
+    ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p2 , p5 ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] Test_en ;
@@ -77829,568 +103472,801 @@
 output [0:0] fle_sc_out ;
 output [0:0] fle_cout ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
 output p_abuf1 ;
 input  p2 ;
 input  p5 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , 
     .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , 
-    .fabric_sc_in ( fle_sc_in ) ,
-    .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+    .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , 
     .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , 
     .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , 
-    .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) ,
-    .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) ,
-    .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , 
-    .p2 ( p2 ) , .p5 ( p5 ) ) ;
+    .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , 
+    .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) , 
+    .p5 ( p5 ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_7 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_6 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_7 ( in , mem , mem_inv , out , 
-    p2 ) ;
+    VDD , VSS , p5 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
-input  p2 ;
+input  VDD ;
+input  VSS ;
+input  p5 ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
-    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p2 ) , .S0 ( mem[0] ) , 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p5 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_11 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_11 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_7 ( in , sram , sram_inv , out , p2 ) ;
+module grid_clb_mux_1level_size2_7 ( in , sram , sram_inv , out , VDD , VSS , 
+    p5 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
-input  p2 ;
+input  VDD ;
+input  VSS ;
+input  p5 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3_11 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3_7 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p2 ( p2 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p5 ( p5 ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_6 ( in , mem , mem_inv , out , 
-    p5 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
-input  p5 ;
-
-sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
-    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p5 ) , .S0 ( mem[0] ) , 
-    .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
-endmodule
-
-
-module grid_clb_local_encoder2to3_10 ( addr , data , data_inv ) ;
-input  [0:1] addr ;
-output [0:2] data ;
-output [0:2] data_inv ;
-
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
-endmodule
-
-
-module grid_clb_mux_1level_size2_6 ( in , sram , sram_inv , out , p5 ) ;
-input  [0:1] in ;
-input  [0:1] sram ;
-input  [0:1] sram_inv ;
-output [0:0] out ;
-input  p5 ;
-
-wire [0:2] local_encoder2to3_0_data ;
-wire [0:2] local_encoder2to3_0_data_inv ;
-wire [0:0] mux_1level_basis_input3_mem3_0_out ;
-
-sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
-grid_clb_local_encoder2to3_10 local_encoder2to3_0_ ( .addr ( sram ) , 
-    .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
-grid_clb_mux_1level_basis_input3_mem3_6 mux_l1_in_0_ (
-    .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
-    .mem ( local_encoder2to3_0_data ) , 
-    .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p5 ( p5 ) ) ;
-endmodule
-
-
-module grid_clb_mux_1level_tapbuf_size2_mem_3 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
-input  [0:0] pReset ;
-input  [0:0] prog_clk ;
-input  [0:0] ccff_head ;
-output [0:0] ccff_tail ;
-output [0:1] mem_out ;
-
-sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
-sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
-endmodule
-
-
-module grid_clb_mux_1level_tapbuf_size2_mem_2 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
-input  [0:0] pReset ;
-input  [0:0] prog_clk ;
-input  [0:0] ccff_head ;
-output [0:0] ccff_tail ;
-output [0:1] mem_out ;
-
-sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
-sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
-endmodule
-
-
-module grid_clb_mux_1level_tapbuf_basis_input3_mem3_3 ( in , mem , mem_inv , 
-    out , p5 ) ;
-input  [0:2] in ;
-input  [0:2] mem ;
-input  [0:2] mem_inv ;
-output [0:0] out ;
-input  p5 ;
-
-sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
-    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p5 ) , .S0 ( mem[0] ) , 
-    .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
-endmodule
-
-
-module grid_clb_local_encoder2to3_9 ( addr , data , data_inv ) ;
-input  [0:1] addr ;
-output [0:2] data ;
-output [0:2] data_inv ;
-
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
-sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
-sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
-endmodule
-
-
-module grid_clb_mux_1level_tapbuf_size2_3 ( in , sram , sram_inv , out , 
-    p_abuf0 , p5 ) ;
-input  [0:1] in ;
-input  [0:1] sram ;
-input  [0:1] sram_inv ;
-output [0:0] out ;
-output p_abuf0 ;
-input  p5 ;
-
-wire [0:2] local_encoder2to3_0_data ;
-wire [0:2] local_encoder2to3_0_data_inv ;
-wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
-
-grid_clb_local_encoder2to3_9 local_encoder2to3_0_ ( .addr ( sram ) , 
-    .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
-grid_clb_mux_1level_tapbuf_basis_input3_mem3_3 mux_l1_in_0_ (
-    .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
-    .mem ( local_encoder2to3_0_data ) , 
-    .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p5 ( p5 ) ) ;
-sky130_fd_sc_hd__inv_2 BINV_R_141 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_142 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
-endmodule
-
-
-module grid_clb_mux_1level_tapbuf_basis_input3_mem3_2 ( in , mem , mem_inv , 
-    out , p0 ) ;
-input  [0:2] in ;
-input  [0:2] mem ;
-input  [0:2] mem_inv ;
-output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_8 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_10 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_tapbuf_size2_2 ( in , sram , sram_inv , out , 
-    p_abuf0 , p0 ) ;
+module grid_clb_mux_1level_size2_6 ( in , sram , sram_inv , out , VDD , VSS , 
+    p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+grid_clb_local_encoder2to3_10 local_encoder2to3_0_ ( .addr ( sram ) , 
+    .data ( local_encoder2to3_0_data ) , 
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+grid_clb_mux_1level_basis_input3_mem3_6 mux_l1_in_0_ (
+    .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to3_0_data ) , 
+    .mem_inv ( local_encoder2to3_0_data_inv ) , 
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_mem_3 ( pReset , prog_clk , 
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_mem_2 ( pReset , prog_clk , 
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
+input  [0:0] pReset ;
+input  [0:0] prog_clk ;
+input  [0:0] ccff_head ;
+output [0:0] ccff_tail ;
+output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_basis_input3_mem3_3 ( in , mem , mem_inv , 
+    out , VDD , VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:2] mem ;
+input  [0:2] mem_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
+    .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_9 ( addr , data , data_inv , VDD , VSS ) ;
+input  [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , 
+    VSS , p_abuf0 , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
+
+grid_clb_local_encoder2to3_9 local_encoder2to3_0_ ( .addr ( sram ) , 
+    .data ( local_encoder2to3_0_data ) , 
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
+grid_clb_mux_1level_tapbuf_basis_input3_mem3_3 mux_l1_in_0_ (
+    .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
+    .mem ( local_encoder2to3_0_data ) , 
+    .mem_inv ( local_encoder2to3_0_data_inv ) , 
+    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_142 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_143 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_basis_input3_mem3_2 ( in , mem , mem_inv , 
+    out , VDD , VSS , p0 ) ;
+input  [0:2] in ;
+input  [0:2] mem ;
+input  [0:2] mem_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+input  p0 ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
+    .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+endmodule
+
+
+module grid_clb_local_encoder2to3_8 ( addr , data , data_inv , VDD , VSS ) ;
+input  [0:1] addr ;
+output [0:2] data ;
+output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+endmodule
+
+
+module grid_clb_mux_1level_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , 
+    VSS , p_abuf0 , p0 ) ;
+input  [0:1] in ;
+input  [0:1] sram ;
+input  [0:1] sram_inv ;
+output [0:0] out ;
+input  VDD ;
+input  VSS ;
+output p_abuf0 ;
+input  p0 ;
+
+wire [0:2] local_encoder2to3_0_data ;
+wire [0:2] local_encoder2to3_0_data_inv ;
+wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_local_encoder2to3_8 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_tapbuf_basis_input3_mem3_2 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_2 BINV_R_138 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_139 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
+    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_2 BINV_R_139 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_140 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 ( 
-    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ;
 input  [0:0] Test_en ;
 input  [0:0] ff_D ;
 input  [0:0] ff_DI ;
 input  [0:0] ff_reset ;
 output [0:0] ff_Q ;
 input  [0:0] ff_clk ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , 
     .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , 
-    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 ( 
-    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ;
 input  [0:0] Test_en ;
 input  [0:0] ff_D ;
 input  [0:0] ff_DI ;
 input  [0:0] ff_reset ;
 output [0:0] ff_Q ;
 input  [0:0] ff_clk ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , 
     .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , 
-    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_5 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_4 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_5 ( in , mem , mem_inv , out , 
-    p1 ) ;
+    VDD , VSS , p1 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p1 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p1 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_7 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_7 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_5 ( in , sram , sram_inv , out , p1 ) ;
+module grid_clb_mux_1level_size2_5 ( in , sram , sram_inv , out , VDD , VSS , 
+    p1 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p1 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3_7 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3_5 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p1 ( p1 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p1 ( p1 ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_4 ( in , mem , mem_inv , out , 
-    p5 ) ;
+    VDD , VSS , p1 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
-input  p5 ;
+input  VDD ;
+input  VSS ;
+input  p1 ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
-    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p5 ) , .S0 ( mem[0] ) , 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p1 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_6 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_6 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_4 ( in , sram , sram_inv , out , p5 ) ;
+module grid_clb_mux_1level_size2_4 ( in , sram , sram_inv , out , VDD , VSS , 
+    p1 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
-input  p5 ;
+input  VDD ;
+input  VSS ;
+input  p1 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3_6 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3_4 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p5 ( p5 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p1 ( p1 ) ) ;
 endmodule
 
 
-module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_1 ( A0 , A1 , S , X ) ;
+module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_1 ( A0 , A1 , S , X , VDD , 
+    VSS ) ;
 input  A0 ;
 input  A1 ;
 input  S ;
 output X ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , 
-    .X ( X_gOb4 ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_1 ( 
     carry_follower_a , carry_follower_b , carry_follower_cin , 
-    carry_follower_cout ) ;
+    carry_follower_cout , VDD , VSS ) ;
 input  [0:0] carry_follower_a ;
 input  [0:0] carry_follower_b ;
 input  [0:0] carry_follower_cin ;
 output [0:0] carry_follower_cout ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_1 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( 
     .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , 
-    .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ;
+    .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:16] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_frac_lut4_mux_1 ( in , sram , sram_inv , lut2_out , lut3_out , 
-    lut4_out ) ;
+    lut4_out , VDD , VSS ) ;
 input  [0:15] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:1] lut2_out ;
 output [0:1] lut3_out ;
 output [0:0] lut4_out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
 wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
@@ -78402,52 +104278,64 @@
 wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
 wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
 wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
-    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
-    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
-    .X ( lut2_out[0] ) ) ;
+    .X ( lut2_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
-    .X ( lut2_out[1] ) ) ;
+    .X ( lut2_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , 
-    .X ( lut3_out[0] ) ) ;
+    .X ( lut3_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , 
-    .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ;
+    .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , 
-    .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+    .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_frac_lut4_1 ( in , sram , sram_inv , mode , mode_inv , 
-    lut2_out , lut3_out , lut4_out ) ;
+    lut2_out , lut3_out , lut4_out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:15] sram ;
 input  [0:15] sram_inv ;
@@ -78456,35 +104344,41 @@
 output [0:1] lut2_out ;
 output [0:1] lut3_out ;
 output [0:0] lut4_out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
 wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
 wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
 wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
 wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , 
-    .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+    .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+    .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
+    .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+    .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( 
     .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+    .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_frac_lut4_mux_1 frac_lut4_mux_0_ ( .in ( sram ) ,
     .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
         SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
-    .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+    .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 ( 
     pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , 
-    frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ;
+    frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:3] frac_lut4_in ;
@@ -78493,9 +104387,13 @@
 output [0:1] frac_lut4_lut3_out ;
 output [0:0] frac_lut4_lut4_out ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] frac_lut4_0_mode ;
 wire [0:15] frac_lut4_0_sram ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_frac_lut4_1 frac_lut4_0_ ( .in ( frac_lut4_in ) , 
     .sram ( frac_lut4_0_sram ) ,
@@ -78510,7 +104408,7 @@
     .mode ( frac_lut4_0_mode ) ,
     .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
     .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , 
-    .lut4_out ( frac_lut4_lut4_out ) ) ;
+    .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
     .ccff_tail ( ccff_tail ) ,
@@ -78519,13 +104417,14 @@
         frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , 
         frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , 
         frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , 
-        frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+        frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ,
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 ( 
     pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , 
-    frac_logic_out , frac_logic_cout , ccff_tail , p1 , p5 ) ;
+    frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p1 ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:3] frac_logic_in ;
@@ -78534,8 +104433,9 @@
 output [0:1] frac_logic_out ;
 output [0:0] frac_logic_cout ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 input  p1 ;
-input  p5 ;
 
 wire [0:0] direct_interc_5_out ;
 wire [0:0] direct_interc_7_out ;
@@ -78546,6 +104446,8 @@
 wire [0:0] mux_1level_size2_1_out ;
 wire [0:1] mux_1level_size2_1_sram ;
 wire [0:0] mux_1level_size2_mem_0_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
@@ -78558,41 +104460,44 @@
         frac_logic_out[1] } ) ,
     
     .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , 
-    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( 
     .carry_follower_a ( direct_interc_5_out ) , 
     .carry_follower_b ( frac_logic_cin ) , 
-    .carry_follower_cin ( direct_interc_7_out ) ,
-    .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+    .carry_follower_cin ( direct_interc_7_out ) , 
+    .carry_follower_cout ( frac_logic_cout ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_size2_4 mux_frac_logic_out_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
          } ) ,
     .sram ( mux_1level_size2_0_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( frac_logic_out[0] ) , .p5 ( p5 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+    .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ;
 grid_clb_mux_1level_size2_5 mux_frac_lut4_0_in_2 (
     .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) ,
     .sram ( mux_1level_size2_1_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) ,
-    .out ( mux_1level_size2_1_out ) , .p1 ( p1 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( mux_1level_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p1 ( p1 ) ) ;
 grid_clb_mux_1level_size2_mem_4 mem_frac_logic_out_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , 
     .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_1level_size2_0_sram ) ) ;
+    .mem_out ( mux_1level_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_size2_mem_5 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 ( 
     pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , 
     fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , 
-    fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , 
-    p_abuf1 , p0 , p1 , p2 , p5 ) ;
+    fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , 
+    p_abuf0 , p_abuf1 , p0 , p1 , p5 ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] Test_en ;
@@ -78608,17 +104513,17 @@
 output [0:0] fabric_sc_out ;
 output [0:0] fabric_cout ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
 output p_abuf1 ;
 input  p0 ;
 input  p1 ;
-input  p2 ;
 input  p5 ;
 
 wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
 wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
 wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
-wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ;
 wire [0:0] mux_1level_size2_0_out ;
 wire [0:1] mux_1level_size2_0_sram ;
 wire [0:0] mux_1level_size2_1_out ;
@@ -78628,84 +104533,91 @@
 wire [0:1] mux_1level_tapbuf_size2_1_sram ;
 wire [0:0] mux_1level_tapbuf_size2_mem_0_ccff_tail ;
 wire [0:0] mux_1level_tapbuf_size2_mem_1_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
-    .frac_logic_in ( fabric_in ) , 
-    .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , 
+    .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , 
     .ccff_head ( ccff_head ) , 
-    .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
-    .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    
+    .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , 
+    .frac_logic_cout ( fabric_cout ) , 
     .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
-    .p1 ( p1 ) , .p5 ( p5 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( 
     .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) , 
     .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , 
     .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , 
-    .ff_clk ( fabric_clk ) ) ;
+    .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( 
     .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_1_out ) , 
     .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , 
     .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , 
-    .ff_clk ( fabric_clk ) ) ;
+    .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_tapbuf_size2_2 mux_fabric_out_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
          } ) ,
     .sram ( mux_1level_tapbuf_size2_0_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+    .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ;
 grid_clb_mux_1level_tapbuf_size2_3 mux_fabric_out_1 (
     .in ( { fabric_sc_out[0] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
          } ) ,
     .sram ( mux_1level_tapbuf_size2_1_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) ,
-    .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p5 ( p5 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ;
 grid_clb_mux_1level_tapbuf_size2_mem_2 mem_fabric_out_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
     .ccff_tail ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_1level_tapbuf_size2_0_sram ) ) ;
+    .mem_out ( mux_1level_tapbuf_size2_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 grid_clb_mux_1level_tapbuf_size2_mem_3 mem_fabric_out_1 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , 
-    .mem_out ( mux_1level_tapbuf_size2_1_sram ) ) ;
+    .mem_out ( mux_1level_tapbuf_size2_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( fabric_sc_out[0] ) , 
-    .X ( fabric_reg_out[0] ) ) ;
+    .X ( fabric_reg_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_mux_1level_size2_6 mux_ff_0_D_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , 
         fabric_reg_in[0] } ) ,
     .sram ( mux_1level_size2_0_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) ,
-    .out ( mux_1level_size2_0_out ) , .p5 ( p5 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+    .out ( mux_1level_size2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( p0 ) ) ;
 grid_clb_mux_1level_size2_7 mux_ff_1_D_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
          } ) ,
     .sram ( mux_1level_size2_1_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) ,
-    .out ( mux_1level_size2_1_out ) , .p2 ( p2 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( mux_1level_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p5 ( p5 ) ) ;
 grid_clb_mux_1level_size2_mem_6 mem_ff_0_D_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_1level_size2_0_sram ) ) ;
+    .mem_out ( mux_1level_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_size2_mem_7 mem_ff_1_D_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_1 ( pReset , prog_clk , 
     Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , 
     fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , 
-    ccff_tail , p_abuf0 , p_abuf1 , p0 , p1 , p2 , p5 ) ;
+    ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p0 , p1 , p5 ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] Test_en ;
@@ -78721,584 +104633,816 @@
 output [0:0] fle_sc_out ;
 output [0:0] fle_cout ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
 output p_abuf1 ;
 input  p0 ;
 input  p1 ;
-input  p2 ;
 input  p5 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , 
     .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , 
-    .fabric_sc_in ( fle_sc_in ) ,
-    .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+    .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , 
     .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , 
     .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , 
-    .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) ,
-    .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) ,
-    .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , 
-    .p0 ( p0 ) , .p1 ( p1 ) , .p2 ( p2 ) , .p5 ( p5 ) ) ;
+    .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , 
+    .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , 
+    .p1 ( p1 ) , .p5 ( p5 ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_3 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_2 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_3 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p4 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
-input  p0 ;
+input  VDD ;
+input  VSS ;
+input  p4 ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
-    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p4 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_5 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_5 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_3 ( in , sram , sram_inv , out , p0 ) ;
+module grid_clb_mux_1level_size2_3 ( in , sram , sram_inv , out , VDD , VSS , 
+    p4 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
-input  p0 ;
+input  VDD ;
+input  VSS ;
+input  p4 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3_5 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3_3 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p4 ( p4 ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_2 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p4 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
-input  p0 ;
+input  VDD ;
+input  VSS ;
+input  p4 ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
-    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p4 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_4 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_4 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_2 ( in , sram , sram_inv , out , p0 ) ;
+module grid_clb_mux_1level_size2_2 ( in , sram , sram_inv , out , VDD , VSS , 
+    p4 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
-input  p0 ;
+input  VDD ;
+input  VSS ;
+input  p4 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3_4 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3_2 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p4 ( p4 ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_tapbuf_size2_mem_1 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_tapbuf_size2_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_tapbuf_basis_input3_mem3_1 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p4 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
-input  p0 ;
+input  VDD ;
+input  VSS ;
+input  p4 ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
-    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p4 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_3 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_3 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_tapbuf_size2_1 ( in , sram , sram_inv , out , 
-    p_abuf0 , p0 ) ;
+module grid_clb_mux_1level_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , 
+    VSS , p_abuf0 , p4 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
-input  p0 ;
+input  p4 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_local_encoder2to3_3 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_tapbuf_basis_input3_mem3_1 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_1 BINV_R_135 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_136 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
+    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p4 ( p4 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_136 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_137 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_tapbuf_basis_input3_mem3_0 ( in , mem , mem_inv , 
-    out , p0 ) ;
+    out , VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_2 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_2 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_tapbuf_size2_0 ( in , sram , sram_inv , out , 
-    p_abuf0 , p0 ) ;
+module grid_clb_mux_1level_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , 
+    VSS , p_abuf0 , p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_tapbuf_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_local_encoder2to3_2 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_tapbuf_basis_input3_mem3_0 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ;
-sky130_fd_sc_hd__inv_1 BINV_R_132 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
-sky130_fd_sc_hd__inv_8 BINV_R_133 ( 
-    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) ) ;
+    .out ( mux_1level_tapbuf_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_133 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_134 ( 
+    .A ( mux_1level_tapbuf_basis_input3_mem3_0_out[0] ) , .Y ( p_abuf0 ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( 
-    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ;
 input  [0:0] Test_en ;
 input  [0:0] ff_D ;
 input  [0:0] ff_DI ;
 input  [0:0] ff_reset ;
 output [0:0] ff_Q ;
 input  [0:0] ff_clk ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , 
     .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , 
-    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( 
-    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ;
+    Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ;
 input  [0:0] Test_en ;
 input  [0:0] ff_D ;
 input  [0:0] ff_DI ;
 input  [0:0] ff_reset ;
 output [0:0] ff_Q ;
 input  [0:0] ff_clk ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , 
     .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , 
-    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ;
+    .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_1 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_size2_mem_0 ( pReset , prog_clk , ccff_head , 
-    ccff_tail , mem_out ) ;
+    ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:1] mem_out ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_1 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p0 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
+supply1 VDD ;
+supply0 VSS ;
+
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
     .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_1 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_1 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_1 ( in , sram , sram_inv , out , p0 ) ;
+module grid_clb_mux_1level_size2_1 ( in , sram , sram_inv , out , VDD , VSS , 
+    p0 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3_1 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3_1 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p0 ( p0 ) ) ;
 endmodule
 
 
 module grid_clb_mux_1level_basis_input3_mem3_0 ( in , mem , mem_inv , out , 
-    p0 ) ;
+    VDD , VSS , p4 ) ;
 input  [0:2] in ;
 input  [0:2] mem ;
 input  [0:2] mem_inv ;
 output [0:0] out ;
-input  p0 ;
+input  VDD ;
+input  VSS ;
+input  p4 ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_uuopenfpga_cc_hd_invmux3_1 sky130_uuopenfpga_cc_hd_invmux3_1_0 ( 
-    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p0 ) , .S0 ( mem[0] ) , 
+    .Q1 ( in[0] ) , .Q2 ( in[1] ) , .Q3 ( p4 ) , .S0 ( mem[0] ) , 
     .S0B ( mem_inv[0] ) , .S1 ( mem[1] ) , .S1B ( mem_inv[1] ) , 
-    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) ) ;
+    .S2 ( mem[2] ) , .S2B ( mem_inv[2] ) , .Z ( out[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_local_encoder2to3_0 ( addr , data , data_inv ) ;
+module grid_clb_local_encoder2to3_0 ( addr , data , data_inv , VDD , VSS ) ;
 input  [0:1] addr ;
 output [0:2] data ;
 output [0:2] data_inv ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__clkinv_1 U8 ( .A ( data[0] ) , .Y ( data_inv[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U9 ( .A ( data_inv[1] ) , .Y ( data[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nand2_1 U10 ( .A ( addr[0] ) , .B ( data_inv[2] ) , 
-    .Y ( data_inv[1] ) ) ;
-sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) ) ;
+    .Y ( data_inv[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkinv_1 U11 ( .A ( data[2] ) , .Y ( data_inv[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__nor2_1 U12 ( .A ( data[2] ) , .B ( addr[0] ) , 
-    .Y ( data[0] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( addr[1] ) , .X ( data[2] ) ) ;
+    .Y ( data[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( addr[1] ) , .X ( data[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
-module grid_clb_mux_1level_size2_0 ( in , sram , sram_inv , out , p0 ) ;
+module grid_clb_mux_1level_size2_0 ( in , sram , sram_inv , out , VDD , VSS , 
+    p4 ) ;
 input  [0:1] in ;
 input  [0:1] sram ;
 input  [0:1] sram_inv ;
 output [0:0] out ;
-input  p0 ;
+input  VDD ;
+input  VSS ;
+input  p4 ;
 
 wire [0:2] local_encoder2to3_0_data ;
 wire [0:2] local_encoder2to3_0_data_inv ;
 wire [0:0] mux_1level_basis_input3_mem3_0_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( 
-    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) ) ;
+    .A ( mux_1level_basis_input3_mem3_0_out[0] ) , .Y ( out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_local_encoder2to3_0 local_encoder2to3_0_ ( .addr ( sram ) , 
     .data ( local_encoder2to3_0_data ) , 
-    .data_inv ( local_encoder2to3_0_data_inv ) ) ;
+    .data_inv ( local_encoder2to3_0_data_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_basis_input3_mem3_0 mux_l1_in_0_ (
     .in ( { in[0] , in[1] , SYNOPSYS_UNCONNECTED_1 } ) ,
     .mem ( local_encoder2to3_0_data ) , 
     .mem_inv ( local_encoder2to3_0_data_inv ) , 
-    .out ( mux_1level_basis_input3_mem3_0_out ) , .p0 ( p0 ) ) ;
+    .out ( mux_1level_basis_input3_mem3_0_out ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p4 ( p4 ) ) ;
 endmodule
 
 
-module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_0 ( A0 , A1 , S , X ) ;
+module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_0 ( A0 , A1 , S , X , VDD , 
+    VSS ) ;
 input  A0 ;
 input  A1 ;
 input  S ;
 output X ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , 
-    .X ( X_gOb1 ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( 
     carry_follower_a , carry_follower_b , carry_follower_cin , 
-    carry_follower_cout ) ;
+    carry_follower_cout , VDD , VSS ) ;
 input  [0:0] carry_follower_a ;
 input  [0:0] carry_follower_b ;
 input  [0:0] carry_follower_cin ;
 output [0:0] carry_follower_cout ;
+input  VDD ;
+input  VSS ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_0 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( 
     .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , 
-    .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ;
+    .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_0 ( pReset , prog_clk , 
-    ccff_head , ccff_tail , mem_out ) ;
+    ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] ccff_head ;
 output [0:0] ccff_tail ;
 output [0:16] mem_out ;
+input  VDD ;
+input  VSS ;
 
-sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_246 ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
+supply1 VDD ;
+supply0 VSS ;
+
+sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_248 ) , 
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , 
-    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ;
-sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ;
-sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1693 ( .A ( ccff_head[0] ) , 
-    .X ( copt_net_233 ) ) ;
-sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1694 ( .A ( copt_net_233 ) , 
-    .X ( copt_net_234 ) ) ;
-sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1695 ( .A ( copt_net_234 ) , 
-    .X ( copt_net_235 ) ) ;
-sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1696 ( .A ( copt_net_235 ) , 
-    .X ( copt_net_236 ) ) ;
-sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1697 ( .A ( copt_net_236 ) , 
-    .X ( copt_net_237 ) ) ;
-sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1698 ( .A ( copt_net_237 ) , 
-    .X ( copt_net_238 ) ) ;
-sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1706 ( .A ( copt_net_238 ) , 
-    .X ( ropt_net_246 ) ) ;
+    .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1720 ( .A ( ccff_head[0] ) , 
+    .X ( copt_net_236 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1721 ( .A ( copt_net_236 ) , 
+    .X ( copt_net_237 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1722 ( .A ( copt_net_237 ) , 
+    .X ( copt_net_238 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1723 ( .A ( copt_net_241 ) , 
+    .X ( copt_net_239 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1724 ( .A ( copt_net_239 ) , 
+    .X ( copt_net_240 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1725 ( .A ( copt_net_238 ) , 
+    .X ( copt_net_241 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1732 ( .A ( copt_net_240 ) , 
+    .X ( ropt_net_248 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_frac_lut4_mux_0 ( in , sram , sram_inv , lut2_out , lut3_out , 
-    lut4_out ) ;
+    lut4_out , VDD , VSS ) ;
 input  [0:15] in ;
 input  [0:3] sram ;
 input  [0:3] sram_inv ;
 output [0:1] lut2_out ;
 output [0:1] lut3_out ;
 output [0:0] lut4_out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
 wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
@@ -79310,52 +105454,64 @@
 wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
 wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
 wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , 
-    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
+    .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , 
-    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
+    .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , 
-    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
+    .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , 
-    .X ( lut2_out[0] ) ) ;
+    .X ( lut2_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , 
-    .X ( lut2_out[1] ) ) ;
+    .X ( lut2_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( 
     .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , 
     .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , 
-    .X ( lut3_out[0] ) ) ;
+    .X ( lut3_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , 
-    .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ;
+    .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , 
-    .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ;
+    .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_frac_lut4_0 ( in , sram , sram_inv , mode , mode_inv , 
-    lut2_out , lut3_out , lut4_out ) ;
+    lut2_out , lut3_out , lut4_out , VDD , VSS ) ;
 input  [0:3] in ;
 input  [0:15] sram ;
 input  [0:15] sram_inv ;
@@ -79364,35 +105520,41 @@
 output [0:1] lut2_out ;
 output [0:1] lut3_out ;
 output [0:0] lut4_out ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ;
 wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ;
 wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ;
 wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ;
 wire [0:0] sky130_fd_sc_hd__or2_1_0_X ;
+supply1 VDD ;
+supply0 VSS ;
 
 sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , 
-    .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ;
+    .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ;
+    .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ;
+    .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ;
+    .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( 
     .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , 
-    .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ;
+    .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_frac_lut4_mux_0 frac_lut4_mux_0_ ( .in ( sram ) ,
     .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) ,
     .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , 
         SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
-    .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ;
+    .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( 
     pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , 
-    frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ;
+    frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:3] frac_lut4_in ;
@@ -79401,9 +105563,13 @@
 output [0:1] frac_lut4_lut3_out ;
 output [0:0] frac_lut4_lut4_out ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 
 wire [0:0] frac_lut4_0_mode ;
 wire [0:15] frac_lut4_0_sram ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_frac_lut4_0 frac_lut4_0_ ( .in ( frac_lut4_in ) , 
     .sram ( frac_lut4_0_sram ) ,
@@ -79418,7 +105584,7 @@
     .mode ( frac_lut4_0_mode ) ,
     .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) ,
     .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , 
-    .lut4_out ( frac_lut4_lut4_out ) ) ;
+    .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , 
     .ccff_tail ( ccff_tail ) ,
@@ -79427,13 +105593,14 @@
         frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , 
         frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , 
         frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , 
-        frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ;
+        frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ,
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( 
     pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , 
-    frac_logic_out , frac_logic_cout , ccff_tail , p0 ) ;
+    frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p0 , p4 ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:3] frac_logic_in ;
@@ -79442,7 +105609,10 @@
 output [0:1] frac_logic_out ;
 output [0:0] frac_logic_cout ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 input  p0 ;
+input  p4 ;
 
 wire [0:0] direct_interc_5_out ;
 wire [0:0] direct_interc_7_out ;
@@ -79453,6 +105623,8 @@
 wire [0:0] mux_1level_size2_1_out ;
 wire [0:1] mux_1level_size2_1_sram ;
 wire [0:0] mux_1level_size2_mem_0_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
@@ -79465,41 +105637,44 @@
         frac_logic_out[1] } ) ,
     
     .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , 
-    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ;
+    .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( 
     .carry_follower_a ( direct_interc_5_out ) , 
     .carry_follower_b ( frac_logic_cin ) , 
-    .carry_follower_cin ( direct_interc_7_out ) ,
-    .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
+    .carry_follower_cin ( direct_interc_7_out ) , 
+    .carry_follower_cout ( frac_logic_cout ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_size2_0 mux_frac_logic_out_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0]
          } ) ,
     .sram ( mux_1level_size2_0_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+    .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p4 ( p4 ) ) ;
 grid_clb_mux_1level_size2_1 mux_frac_lut4_0_in_2 (
     .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) ,
     .sram ( mux_1level_size2_1_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) ,
-    .out ( mux_1level_size2_1_out ) , .p0 ( p0 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( mux_1level_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p0 ( p0 ) ) ;
 grid_clb_mux_1level_size2_mem_0 mem_frac_logic_out_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , 
     .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_1level_size2_0_sram ) ) ;
+    .mem_out ( mux_1level_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_size2_mem_1 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( 
     pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , 
     fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , 
-    fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , 
-    p_abuf1 , p0 ) ;
+    fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , 
+    p_abuf0 , p_abuf1 , p0 , p4 ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] Test_en ;
@@ -79515,14 +105690,16 @@
 output [0:0] fabric_sc_out ;
 output [0:0] fabric_cout ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
 output p_abuf1 ;
 input  p0 ;
+input  p4 ;
 
 wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ;
 wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ;
 wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ;
-wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ;
 wire [0:0] mux_1level_size2_0_out ;
 wire [0:1] mux_1level_size2_0_sram ;
 wire [0:0] mux_1level_size2_1_out ;
@@ -79532,84 +105709,91 @@
 wire [0:1] mux_1level_tapbuf_size2_1_sram ;
 wire [0:0] mux_1level_tapbuf_size2_mem_0_ccff_tail ;
 wire [0:0] mux_1level_tapbuf_size2_mem_1_ccff_tail ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , 
-    .frac_logic_in ( fabric_in ) , 
-    .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , 
+    .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , 
     .ccff_head ( ccff_head ) , 
-    .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) ,
-    .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    
+    .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , 
+    .frac_logic_cout ( fabric_cout ) , 
     .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
-    .p0 ( p0 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) , .p4 ( p4 ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( 
     .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_0_out ) , 
     .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , 
     .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , 
-    .ff_clk ( fabric_clk ) ) ;
+    .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( 
     .Test_en ( Test_en ) , .ff_D ( mux_1level_size2_1_out ) , 
     .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , 
     .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , 
-    .ff_clk ( fabric_clk ) ) ;
+    .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_tapbuf_size2_0 mux_fabric_out_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]
          } ) ,
     .sram ( mux_1level_tapbuf_size2_0_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) ,
-    .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
+    .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ;
 grid_clb_mux_1level_tapbuf_size2_1 mux_fabric_out_1 (
     .in ( { fabric_sc_out[0] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1]
          } ) ,
     .sram ( mux_1level_tapbuf_size2_1_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) ,
-    .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
+    .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p_abuf0 ( p_abuf1 ) , .p4 ( p4 ) ) ;
 grid_clb_mux_1level_tapbuf_size2_mem_0 mem_fabric_out_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , 
     .ccff_tail ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_1level_tapbuf_size2_0_sram ) ) ;
+    .mem_out ( mux_1level_tapbuf_size2_0_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 grid_clb_mux_1level_tapbuf_size2_mem_1 mem_fabric_out_1 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_1level_tapbuf_size2_mem_0_ccff_tail ) , 
     .ccff_tail ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , 
-    .mem_out ( mux_1level_tapbuf_size2_1_sram ) ) ;
+    .mem_out ( mux_1level_tapbuf_size2_1_sram ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( fabric_sc_out[0] ) , 
-    .X ( fabric_reg_out[0] ) ) ;
+    .X ( fabric_reg_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 grid_clb_mux_1level_size2_2 mux_ff_0_D_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , 
         fabric_reg_in[0] } ) ,
     .sram ( mux_1level_size2_0_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) ,
-    .out ( mux_1level_size2_0_out ) , .p0 ( p0 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
+    .out ( mux_1level_size2_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p4 ( p4 ) ) ;
 grid_clb_mux_1level_size2_3 mux_ff_1_D_0 (
     .in ( { 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , 
         logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]
          } ) ,
     .sram ( mux_1level_size2_1_sram ) ,
-    .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) ,
-    .out ( mux_1level_size2_1_out ) , .p0 ( p0 ) ) ;
+    .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
+    .out ( mux_1level_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p4 ( p4 ) ) ;
 grid_clb_mux_1level_size2_mem_2 mem_ff_0_D_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , 
     .ccff_head ( mux_1level_tapbuf_size2_mem_1_ccff_tail ) , 
     .ccff_tail ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .mem_out ( mux_1level_size2_0_sram ) ) ;
+    .mem_out ( mux_1level_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb_mux_1level_size2_mem_3 mem_ff_1_D_0 ( .pReset ( pReset ) , 
     .prog_clk ( prog_clk ) , .ccff_head ( mux_1level_size2_mem_0_ccff_tail ) , 
-    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) ) ;
+    .ccff_tail ( ccff_tail ) , .mem_out ( mux_1level_size2_1_sram ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 endmodule
 
 
 module grid_clb_logical_tile_clb_mode_default__fle_0 ( pReset , prog_clk , 
     Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , 
     fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , 
-    ccff_tail , p_abuf0 , p_abuf1 , p0 ) ;
+    ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p0 , p4 ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] Test_en ;
@@ -79625,21 +105809,26 @@
 output [0:0] fle_sc_out ;
 output [0:0] fle_cout ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
 output p_abuf1 ;
 input  p0 ;
+input  p4 ;
+
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , 
     .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , 
-    .fabric_sc_in ( fle_sc_in ) ,
-    .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) ,
+    .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , 
     .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , 
     .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , 
-    .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) ,
-    .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) ,
-    .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , 
-    .p0 ( p0 ) ) ;
+    .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , 
+    .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , 
+    .p4 ( p4 ) ) ;
 endmodule
 
 
@@ -79648,9 +105837,10 @@
     clb_I3i , clb_I4 , clb_I4i , clb_I5 , clb_I5i , clb_I6 , clb_I6i , 
     clb_I7 , clb_I7i , clb_reg_in , clb_sc_in , clb_cin , clb_reset , 
     clb_clk , ccff_head , clb_O , clb_reg_out , clb_sc_out , clb_cout , 
-    ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , p_abuf5 , 
-    p_abuf6 , p_abuf7 , p_abuf8 , p_abuf9 , p_abuf10 , p_abuf11 , p_abuf12 , 
-    p_abuf13 , p_abuf14 , p_abuf15 , p0 , p1 , p2 , p3 , p4 , p5 , p6 , p7 ) ;
+    ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , 
+    p_abuf5 , p_abuf6 , p_abuf7 , p_abuf8 , p_abuf9 , p_abuf10 , p_abuf11 , 
+    p_abuf12 , p_abuf13 , p_abuf14 , p_abuf15 , p0 , p1 , p2 , p3 , p4 , p5 , 
+    p6 , p7 ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] Test_en ;
@@ -79681,6 +105871,8 @@
 output [0:0] clb_sc_out ;
 output [0:0] clb_cout ;
 output [0:0] ccff_tail ;
+input  VDD ;
+input  VSS ;
 output p_abuf0 ;
 output p_abuf1 ;
 output p_abuf2 ;
@@ -79707,12 +105899,19 @@
 input  p7 ;
 
 wire [0:0] direct_interc_32_out ;
+wire [0:0] direct_interc_34_out ;
 wire [0:0] direct_interc_41_out ;
+wire [0:0] direct_interc_43_out ;
 wire [0:0] direct_interc_50_out ;
+wire [0:0] direct_interc_52_out ;
 wire [0:0] direct_interc_59_out ;
+wire [0:0] direct_interc_61_out ;
 wire [0:0] direct_interc_68_out ;
+wire [0:0] direct_interc_70_out ;
 wire [0:0] direct_interc_77_out ;
+wire [0:0] direct_interc_79_out ;
 wire [0:0] direct_interc_86_out ;
+wire [0:0] direct_interc_88_out ;
 wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail ;
 wire [0:0] logical_tile_clb_mode_default__fle_0_fle_sc_out ;
 wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail ;
@@ -79727,118 +105926,125 @@
 wire [0:0] logical_tile_clb_mode_default__fle_5_fle_sc_out ;
 wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail ;
 wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb_logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
     .fle_in ( { clb_I0[0] , clb_I0[1] , clb_I0i[0] , clb_I0i[1] } ) ,
-    .fle_reg_in ( clb_reg_in ) , .fle_sc_in ( clb_sc_in ) ,
-    .fle_cin ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , 
+    .fle_reg_in ( clb_reg_in ) , .fle_sc_in ( clb_sc_in ) , 
+    .fle_cin ( clb_cin ) , .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , 
     .ccff_head ( ccff_head ) ,
     .fle_out ( { clb_O[1] , clb_O[0] } ) ,
     .fle_reg_out ( direct_interc_32_out ) , 
-    .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) ,
-    .fle_cout ( { SYNOPSYS_UNCONNECTED_2 } ) ,
+    .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , 
+    .fle_cout ( direct_interc_34_out ) , 
     .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , 
-    .p_abuf0 ( p_abuf1 ) , .p_abuf1 ( p_abuf2 ) , .p0 ( p0 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf1 ) , 
+    .p_abuf1 ( p_abuf2 ) , .p0 ( p0 ) , .p4 ( p5 ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
     .fle_in ( { clb_I1[0] , clb_I1[1] , clb_I1i[0] , clb_I1i[1] } ) ,
     .fle_reg_in ( direct_interc_32_out ) , 
-    .fle_sc_in ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) ,
-    .fle_cin ( { SYNOPSYS_UNCONNECTED_3 } ) ,
-    .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , 
+    .fle_sc_in ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , 
+    .fle_cin ( direct_interc_34_out ) , .fle_reset ( clb_reset ) , 
+    .fle_clk ( clb_clk ) , 
     .ccff_head ( logical_tile_clb_mode_default__fle_0_ccff_tail ) ,
     .fle_out ( { clb_O[3] , clb_O[2] } ) ,
     .fle_reg_out ( direct_interc_41_out ) , 
-    .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) ,
-    .fle_cout ( { SYNOPSYS_UNCONNECTED_4 } ) ,
+    .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , 
+    .fle_cout ( direct_interc_43_out ) , 
     .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , 
-    .p_abuf0 ( p_abuf3 ) , .p_abuf1 ( p_abuf4 ) , .p0 ( p0 ) , .p1 ( p2 ) , 
-    .p2 ( p3 ) , .p5 ( p6 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf3 ) , 
+    .p_abuf1 ( p_abuf4 ) , .p0 ( p0 ) , .p1 ( p2 ) , .p5 ( p6 ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
     .fle_in ( { clb_I2[0] , clb_I2[1] , clb_I2i[0] , clb_I2i[1] } ) ,
     .fle_reg_in ( direct_interc_41_out ) , 
-    .fle_sc_in ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) ,
-    .fle_cin ( { SYNOPSYS_UNCONNECTED_5 } ) ,
-    .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , 
+    .fle_sc_in ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , 
+    .fle_cin ( direct_interc_43_out ) , .fle_reset ( clb_reset ) , 
+    .fle_clk ( clb_clk ) , 
     .ccff_head ( logical_tile_clb_mode_default__fle_1_ccff_tail ) ,
     .fle_out ( { clb_O[5] , clb_O[4] } ) ,
     .fle_reg_out ( direct_interc_50_out ) , 
-    .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) ,
-    .fle_cout ( { SYNOPSYS_UNCONNECTED_6 } ) ,
+    .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , 
+    .fle_cout ( direct_interc_52_out ) , 
     .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , 
-    .p_abuf0 ( p_abuf5 ) , .p_abuf1 ( p_abuf6 ) , .p2 ( p3 ) , .p5 ( p6 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf5 ) , 
+    .p_abuf1 ( p_abuf6 ) , .p2 ( p3 ) , .p5 ( p6 ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
     .fle_in ( { clb_I3[0] , clb_I3[1] , clb_I3i[0] , clb_I3i[1] } ) ,
     .fle_reg_in ( direct_interc_50_out ) , 
-    .fle_sc_in ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) ,
-    .fle_cin ( { SYNOPSYS_UNCONNECTED_7 } ) ,
-    .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , 
+    .fle_sc_in ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , 
+    .fle_cin ( direct_interc_52_out ) , .fle_reset ( clb_reset ) , 
+    .fle_clk ( clb_clk ) , 
     .ccff_head ( logical_tile_clb_mode_default__fle_2_ccff_tail ) ,
     .fle_out ( { clb_O[7] , clb_O[6] } ) ,
     .fle_reg_out ( direct_interc_59_out ) , 
-    .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) ,
-    .fle_cout ( { SYNOPSYS_UNCONNECTED_8 } ) ,
+    .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , 
+    .fle_cout ( direct_interc_61_out ) , 
     .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , 
-    .p_abuf0 ( p_abuf7 ) , .p_abuf1 ( p_abuf8 ) , .p0 ( p1 ) , .p2 ( p3 ) , 
-    .p6 ( p7 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf7 ) , 
+    .p_abuf1 ( p_abuf8 ) , .p2 ( p3 ) , .p6 ( p7 ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
     .fle_in ( { clb_I4[0] , clb_I4[1] , clb_I4i[0] , clb_I4i[1] } ) ,
     .fle_reg_in ( direct_interc_59_out ) , 
-    .fle_sc_in ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) ,
-    .fle_cin ( { SYNOPSYS_UNCONNECTED_9 } ) ,
-    .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , 
+    .fle_sc_in ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , 
+    .fle_cin ( direct_interc_61_out ) , .fle_reset ( clb_reset ) , 
+    .fle_clk ( clb_clk ) , 
     .ccff_head ( logical_tile_clb_mode_default__fle_3_ccff_tail ) ,
     .fle_out ( { clb_O[9] , clb_O[8] } ) ,
     .fle_reg_out ( direct_interc_68_out ) , 
-    .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) ,
-    .fle_cout ( { SYNOPSYS_UNCONNECTED_10 } ) ,
+    .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , 
+    .fle_cout ( direct_interc_70_out ) , 
     .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , 
-    .p_abuf0 ( p_abuf9 ) , .p_abuf1 ( p_abuf10 ) , .p4 ( p5 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf9 ) , 
+    .p_abuf1 ( p_abuf10 ) , .p4 ( p5 ) , .p6 ( p7 ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
     .fle_in ( { clb_I5[0] , clb_I5[1] , clb_I5i[0] , clb_I5i[1] } ) ,
     .fle_reg_in ( direct_interc_68_out ) , 
-    .fle_sc_in ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) ,
-    .fle_cin ( { SYNOPSYS_UNCONNECTED_11 } ) ,
-    .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , 
+    .fle_sc_in ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , 
+    .fle_cin ( direct_interc_70_out ) , .fle_reset ( clb_reset ) , 
+    .fle_clk ( clb_clk ) , 
     .ccff_head ( logical_tile_clb_mode_default__fle_4_ccff_tail ) ,
     .fle_out ( { clb_O[11] , clb_O[10] } ) ,
     .fle_reg_out ( direct_interc_77_out ) , 
-    .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) ,
-    .fle_cout ( { SYNOPSYS_UNCONNECTED_12 } ) ,
+    .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , 
+    .fle_cout ( direct_interc_79_out ) , 
     .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , 
-    .p_abuf0 ( p_abuf11 ) , .p_abuf1 ( p_abuf12 ) , .p6 ( p7 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf11 ) , 
+    .p_abuf1 ( p_abuf12 ) , .p3 ( p4 ) , .p6 ( p7 ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
     .fle_in ( { clb_I6[0] , clb_I6[1] , clb_I6i[0] , clb_I6i[1] } ) ,
     .fle_reg_in ( direct_interc_77_out ) , 
-    .fle_sc_in ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) ,
-    .fle_cin ( { SYNOPSYS_UNCONNECTED_13 } ) ,
-    .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , 
+    .fle_sc_in ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , 
+    .fle_cin ( direct_interc_79_out ) , .fle_reset ( clb_reset ) , 
+    .fle_clk ( clb_clk ) , 
     .ccff_head ( logical_tile_clb_mode_default__fle_5_ccff_tail ) ,
     .fle_out ( { clb_O[13] , clb_O[12] } ) ,
     .fle_reg_out ( direct_interc_86_out ) , 
-    .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) ,
-    .fle_cout ( { SYNOPSYS_UNCONNECTED_14 } ) ,
+    .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , 
+    .fle_cout ( direct_interc_88_out ) , 
     .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , 
-    .p_abuf0 ( p_abuf13 ) , .p3 ( p4 ) ) ;
+    .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf13 ) , .p0 ( p1 ) , 
+    .p3 ( p4 ) ) ;
 grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( 
     .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) ,
     .fle_in ( { clb_I7[0] , clb_I7[1] , clb_I7i[0] , clb_I7i[1] } ) ,
     .fle_reg_in ( direct_interc_86_out ) , 
-    .fle_sc_in ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) ,
-    .fle_cin ( { SYNOPSYS_UNCONNECTED_15 } ) ,
-    .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , 
+    .fle_sc_in ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , 
+    .fle_cin ( direct_interc_88_out ) , .fle_reset ( clb_reset ) , 
+    .fle_clk ( clb_clk ) , 
     .ccff_head ( logical_tile_clb_mode_default__fle_6_ccff_tail ) ,
     .fle_out ( { clb_O[15] , clb_O[14] } ) ,
     .fle_reg_out ( clb_reg_out ) , .fle_sc_out ( clb_sc_out ) , 
-    .fle_cout ( clb_cout ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , 
-    .p_abuf1 ( p_abuf14 ) , .p_abuf2 ( p_abuf15 ) , .p0 ( p1 ) , .p3 ( p4 ) ) ;
+    .fle_cout ( clb_cout ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf14 ) , 
+    .p_abuf2 ( p_abuf15 ) , .p0 ( p1 ) ) ;
 endmodule
 
 
@@ -79890,7 +106096,8 @@
     Test_en_E_in , Test_en_W_in , Test_en_W_out , Test_en_E_out , 
     pReset_N_in , Reset_E_in , Reset_W_in , Reset_W_out , Reset_E_out , 
     prog_clk_0_N_in , prog_clk_0_S_in , prog_clk_0_S_out , prog_clk_0_E_out , 
-    prog_clk_0_W_out , prog_clk_0_N_out , clk_0_N_in , clk_0_S_in ) ;
+    prog_clk_0_W_out , prog_clk_0_N_out , clk_0_N_in , clk_0_S_in , VDD , 
+    VSS ) ;
 input  [0:0] pReset ;
 input  [0:0] top_width_0_height_0__pin_0_ ;
 input  [0:0] top_width_0_height_0__pin_1_ ;
@@ -79986,16 +106193,18 @@
 output prog_clk_0_N_out ;
 input  clk_0_N_in ;
 input  clk_0_S_in ;
+input  VDD ;
+input  VSS ;
 
 wire p_abuf10 ;
-wire p_abuf13 ;
 wire p_abuf15 ;
-wire p_abuf0 ;
 wire prog_clk_0 ;
 wire [0:0] prog_clk ;
 wire [0:0] clk ;
 wire clk_0 ;
 wire [0:0] Test_en ;
+supply1 VDD ;
+supply0 VSS ;
 
 assign SC_IN_BOT = SC_IN_TOP ;
 assign Test_en_W_in = Test_en_E_in ;
@@ -80043,21 +106252,20 @@
         right_width_0_height_0__pin_31_[0] } ) ,
     .clb_reg_in ( top_width_0_height_0__pin_32_ ) ,
     .clb_sc_in ( { SC_IN_BOT } ) ,
-    .clb_cin ( { SYNOPSYS_UNCONNECTED_1 } ) ,
-    .clb_reset ( Reset ) , .clb_clk ( clk ) , .ccff_head ( ccff_head ) ,
+    .clb_cin ( top_width_0_height_0__pin_34_ ) , .clb_reset ( Reset ) , 
+    .clb_clk ( clk ) , .ccff_head ( ccff_head ) ,
     .clb_O ( { aps_rename_506_ , aps_rename_507_ , aps_rename_508_ , 
         aps_rename_509_ , aps_rename_510_ , aps_rename_511_ , 
         aps_rename_512_ , aps_rename_513_ , 
         right_width_0_height_0__pin_44_lower[0] , aps_rename_515_ , 
         aps_rename_516_ , aps_rename_517_ , 
-        right_width_0_height_0__pin_48_lower[0] , 
-        right_width_0_height_0__pin_49_lower[0] , 
+        right_width_0_height_0__pin_48_lower[0] , aps_rename_518_ , 
         right_width_0_height_0__pin_50_lower[0] , aps_rename_520_ } ) ,
     .clb_reg_out ( bottom_width_0_height_0__pin_52_ ) ,
-    .clb_sc_out ( { SC_OUT_BOT } ) ,
-    .clb_cout ( bottom_width_0_height_0__pin_54_ ) ,
-    .ccff_tail ( { ropt_net_245 } ) ,
-    .p_abuf0 ( p_abuf0 ) , 
+    .clb_sc_out ( { aps_rename_521_ } ) ,
+    .clb_cout ( bottom_width_0_height_0__pin_54_ ) , 
+    .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , 
+    .p_abuf0 ( SC_OUT_BOT ) , 
     .p_abuf1 ( top_width_0_height_0__pin_37_lower[0] ) , 
     .p_abuf2 ( top_width_0_height_0__pin_36_lower[0] ) , 
     .p_abuf3 ( top_width_0_height_0__pin_39_lower[0] ) , 
@@ -80070,490 +106278,513 @@
     .p_abuf10 ( p_abuf10 ) , 
     .p_abuf11 ( right_width_0_height_0__pin_47_lower[0] ) , 
     .p_abuf12 ( right_width_0_height_0__pin_46_lower[0] ) , 
-    .p_abuf13 ( p_abuf13 ) , 
+    .p_abuf13 ( right_width_0_height_0__pin_49_lower[0] ) , 
     .p_abuf14 ( right_width_0_height_0__pin_51_lower[0] ) , 
-    .p_abuf15 ( p_abuf15 ) , .p0 ( optlc_net_221 ) , .p1 ( optlc_net_222 ) , 
-    .p2 ( optlc_net_223 ) , .p3 ( optlc_net_224 ) , .p4 ( optlc_net_225 ) , 
-    .p5 ( optlc_net_226 ) , .p6 ( optlc_net_227 ) , .p7 ( optlc_net_228 ) ) ;
+    .p_abuf15 ( p_abuf15 ) , .p0 ( optlc_net_224 ) , .p1 ( optlc_net_225 ) , 
+    .p2 ( optlc_net_226 ) , .p3 ( optlc_net_227 ) , .p4 ( optlc_net_228 ) , 
+    .p5 ( optlc_net_229 ) , .p6 ( optlc_net_230 ) , .p7 ( optlc_net_231 ) ) ;
 sky130_fd_sc_hd__buf_2 Test_en_FTB00 ( .A ( Test_en_W_in ) , 
-    .X ( Test_en[0] ) ) ;
+    .X ( Test_en[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_W_in ) , 
-    .X ( net_net_178 ) ) ;
+    .X ( aps_rename_522_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_W_in ) , 
-    .X ( net_net_179 ) ) ;
-sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) ) ;
-sky130_fd_sc_hd__buf_4 Reset_FTB00 ( .A ( Reset_W_in ) , .X ( Reset[0] ) ) ;
+    .X ( aps_rename_523_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_4 Reset_FTB00 ( .A ( Reset_W_in ) , .X ( Reset[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__bufbuf_16 Reset_W_FTB01 ( .A ( Reset_W_in ) , 
-    .X ( Reset_W_out ) ) ;
-sky130_fd_sc_hd__bufbuf_16 Reset_E_FTB01 ( .A ( Reset_W_in ) , 
-    .X ( Reset_E_out ) ) ;
+    .X ( Reset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 Reset_E_FTB01 ( .A ( Reset_W_in ) , 
+    .X ( net_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , 
-    .X ( prog_clk_0 ) ) ;
+    .X ( prog_clk_0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_S_in ) , 
-    .X ( ctsbuf_net_1229 ) ) ;
-sky130_fd_sc_hd__clkbuf_1 prog_clk_0_E_FTB01 ( .A ( prog_clk_0_S_in ) , 
-    .X ( ctsbuf_net_2230 ) ) ;
+    .X ( ctsbuf_net_1232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_2 prog_clk_0_E_FTB01 ( .A ( prog_clk_0_S_in ) , 
+    .X ( ctsbuf_net_2233 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , 
-    .X ( ctsbuf_net_3231 ) ) ;
+    .X ( ctsbuf_net_3234 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_S_in ) , 
-    .X ( ctsbuf_net_4232 ) ) ;
-sky130_fd_sc_hd__buf_1 clk_0_FTB00 ( .A ( clk_0_S_in ) , .X ( clk[0] ) ) ;
+    .X ( ctsbuf_net_4235 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_1 clk_0_FTB00 ( .A ( clk_0_S_in ) , .X ( clk[0] ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_113__112 ( .A ( aps_rename_506_ ) , 
-    .X ( top_width_0_height_0__pin_36_upper[0] ) ) ;
+    .X ( top_width_0_height_0__pin_36_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_114__113 ( .A ( aps_rename_507_ ) , 
-    .X ( top_width_0_height_0__pin_37_upper[0] ) ) ;
+    .X ( top_width_0_height_0__pin_37_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_115__114 ( .A ( aps_rename_508_ ) , 
-    .X ( top_width_0_height_0__pin_38_upper[0] ) ) ;
+    .X ( top_width_0_height_0__pin_38_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_116__115 ( .A ( aps_rename_509_ ) , 
-    .X ( top_width_0_height_0__pin_39_upper[0] ) ) ;
+    .X ( top_width_0_height_0__pin_39_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_117__116 ( .A ( aps_rename_510_ ) , 
-    .X ( top_width_0_height_0__pin_40_upper[0] ) ) ;
+    .X ( top_width_0_height_0__pin_40_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_118__117 ( .A ( aps_rename_511_ ) , 
-    .X ( top_width_0_height_0__pin_41_upper[0] ) ) ;
+    .X ( top_width_0_height_0__pin_41_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_119__118 ( .A ( aps_rename_512_ ) , 
-    .X ( top_width_0_height_0__pin_42_upper[0] ) ) ;
+    .X ( top_width_0_height_0__pin_42_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_120__119 ( .A ( aps_rename_513_ ) , 
-    .X ( top_width_0_height_0__pin_43_upper[0] ) ) ;
+    .X ( top_width_0_height_0__pin_43_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_121__120 ( .A ( p_abuf10 ) , 
-    .X ( right_width_0_height_0__pin_44_upper[0] ) ) ;
+    .X ( right_width_0_height_0__pin_44_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_122__121 ( .A ( aps_rename_515_ ) , 
-    .X ( right_width_0_height_0__pin_45_upper[0] ) ) ;
+    .X ( right_width_0_height_0__pin_45_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_123__122 ( .A ( aps_rename_516_ ) , 
-    .X ( right_width_0_height_0__pin_46_upper[0] ) ) ;
+    .X ( right_width_0_height_0__pin_46_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_124__123 ( .A ( aps_rename_517_ ) , 
-    .X ( right_width_0_height_0__pin_47_upper[0] ) ) ;
-sky130_fd_sc_hd__buf_6 FTB_125__124 ( .A ( p_abuf13 ) , 
-    .X ( right_width_0_height_0__pin_48_upper[0] ) ) ;
-sky130_fd_sc_hd__buf_6 FTB_126__125 ( 
-    .A ( right_width_0_height_0__pin_49_lower[0] ) , 
-    .X ( right_width_0_height_0__pin_49_upper[0] ) ) ;
+    .X ( right_width_0_height_0__pin_47_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_125__124 ( 
+    .A ( right_width_0_height_0__pin_48_lower[0] ) , 
+    .X ( right_width_0_height_0__pin_48_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_126__125 ( .A ( aps_rename_518_ ) , 
+    .X ( right_width_0_height_0__pin_49_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_127__126 ( .A ( p_abuf15 ) , 
-    .X ( right_width_0_height_0__pin_50_upper[0] ) ) ;
+    .X ( right_width_0_height_0__pin_50_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__buf_6 FTB_128__127 ( .A ( aps_rename_520_ ) , 
-    .X ( right_width_0_height_0__pin_51_upper[0] ) ) ;
-sky130_fd_sc_hd__buf_6 FTB_129__128 ( .A ( p_abuf0 ) , .X ( SC_OUT_TOP ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_178 ( .A ( net_net_178 ) , 
-    .X ( Test_en_W_out ) ) ;
-sky130_fd_sc_hd__buf_6 BUFT_RR_179 ( .A ( net_net_179 ) , 
-    .X ( Test_en_E_out ) ) ;
-sky130_fd_sc_hd__conb_1 optlc_182 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , 
-    .HI ( optlc_net_221 ) ) ;
-sky130_fd_sc_hd__conb_1 optlc_184 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , 
-    .HI ( optlc_net_222 ) ) ;
-sky130_fd_sc_hd__conb_1 optlc_185 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , 
-    .HI ( optlc_net_223 ) ) ;
-sky130_fd_sc_hd__conb_1 optlc_187 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , 
-    .HI ( optlc_net_224 ) ) ;
-sky130_fd_sc_hd__conb_1 optlc_189 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , 
-    .HI ( optlc_net_225 ) ) ;
-sky130_fd_sc_hd__conb_1 optlc_191 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , 
-    .HI ( optlc_net_226 ) ) ;
-sky130_fd_sc_hd__conb_1 optlc_193 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) , 
-    .HI ( optlc_net_227 ) ) ;
-sky130_fd_sc_hd__conb_1 optlc_195 ( .LO ( SYNOPSYS_UNCONNECTED_9 ) , 
-    .HI ( optlc_net_228 ) ) ;
-sky130_fd_sc_hd__buf_8 ropt_mt_inst_1705 ( .A ( ropt_net_245 ) , 
-    .X ( ccff_tail[0] ) ) ;
-sky130_fd_sc_hd__buf_6 cts_buf_4181388 ( .A ( ctsbuf_net_1229 ) , 
-    .X ( prog_clk_0_S_out ) ) ;
-sky130_fd_sc_hd__clkbuf_8 cts_buf_4231393 ( .A ( ctsbuf_net_2230 ) , 
-    .X ( prog_clk_0_E_out ) ) ;
-sky130_fd_sc_hd__buf_6 cts_buf_4281398 ( .A ( ctsbuf_net_3231 ) , 
-    .X ( prog_clk_0_W_out ) ) ;
-sky130_fd_sc_hd__buf_6 cts_buf_4331403 ( .A ( ctsbuf_net_4232 ) , 
-    .X ( prog_clk_0_N_out ) ) ;
+    .X ( right_width_0_height_0__pin_51_upper[0] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 FTB_129__128 ( .A ( aps_rename_521_ ) , 
+    .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_8 BINV_R_180 ( .A ( BUF_net_181 ) , 
+    .Y ( Test_en_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__inv_1 BINV_R_181 ( .A ( aps_rename_522_ ) , 
+    .Y ( BUF_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 BUFT_RR_182 ( .A ( net_net_182 ) , .X ( Reset_E_out ) , 
+    .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_185 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , 
+    .HI ( optlc_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_187 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , 
+    .HI ( optlc_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_189 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , 
+    .HI ( optlc_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_191 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , 
+    .HI ( optlc_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_193 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , 
+    .HI ( optlc_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_195 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , 
+    .HI ( optlc_net_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_197 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , 
+    .HI ( optlc_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__conb_1 optlc_199 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) , 
+    .HI ( optlc_net_231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_200 ( .A ( aps_rename_523_ ) , 
+    .X ( Test_en_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_4181393 ( .A ( ctsbuf_net_1232 ) , 
+    .X ( prog_clk_0_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__clkbuf_8 cts_buf_4231398 ( .A ( ctsbuf_net_2233 ) , 
+    .X ( prog_clk_0_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_4281403 ( .A ( ctsbuf_net_3234 ) , 
+    .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
+sky130_fd_sc_hd__buf_6 cts_buf_4331408 ( .A ( ctsbuf_net_4235 ) , 
+    .X ( prog_clk_0_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 
 module fpga_core ( pReset , prog_clk , Test_en , IO_ISOL_N , clk , Reset , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , 
     gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , ccff_head , ccff_tail , sc_head , 
-    sc_tail , h_incr0 , p0 , p1 , p2 , p3 , p4 , p5 , p6 , p7 , p8 , p9 , 
-    p10 , p11 , p12 , p13 , p14 , p15 , p16 , p17 , p18 , p19 , p20 , p21 , 
-    p22 , p23 , p24 , p25 , p26 , p27 , p28 , p29 , p30 , p31 , p32 , p33 , 
-    p34 , p35 , p36 , p37 , p38 , p39 , p40 , p41 , p42 , p43 , p44 , p45 , 
-    p46 , p47 , p48 , p49 , p50 , p51 , p52 , p53 , p54 , p55 , p56 , p57 , 
-    p58 , p59 , p60 , p61 , p62 , p63 , p64 , p65 , p66 , p67 , p68 , p69 , 
-    p70 , p71 , p72 , p73 , p74 , p75 , p76 , p77 , p78 , p79 , p80 , p81 , 
-    p82 , p83 , p84 , p85 , p86 , p87 , p88 , p89 , p90 , p91 , p92 , p93 , 
-    p94 , p95 , p96 , p97 , p98 , p99 , p100 , p101 , p102 , p103 , p104 , 
-    p105 , p106 , p107 , p108 , p109 , p110 , p111 , p112 , p113 , p114 , 
-    p115 , p116 , p117 , p118 , p119 , p120 , p121 , p122 , p123 , p124 , 
-    p125 , p126 , p127 , p128 , p129 , p130 , p131 , p132 , p133 , p134 , 
-    p135 , p136 , p137 , p138 , p139 , p140 , p141 , p142 , p143 , p144 , 
-    p145 , p146 , p147 , p148 , p149 , p150 , p151 , p152 , p153 , p154 , 
-    p155 , p156 , p157 , p158 , p159 , p160 , p161 , p162 , p163 , p164 , 
-    p165 , p166 , p167 , p168 , p169 , p170 , p171 , p172 , p173 , p174 , 
-    p175 , p176 , p177 , p178 , p179 , p180 , p181 , p182 , p183 , p184 , 
-    p185 , p186 , p187 , p188 , p189 , p190 , p191 , p192 , p193 , p194 , 
-    p195 , p196 , p197 , p198 , p199 , p200 , p201 , p202 , p203 , p204 , 
-    p205 , p206 , p207 , p208 , p209 , p210 , p211 , p212 , p213 , p214 , 
-    p215 , p216 , p217 , p218 , p219 , p220 , p221 , p222 , p223 , p224 , 
-    p225 , p226 , p227 , p228 , p229 , p230 , p231 , p232 , p233 , p234 , 
-    p235 , p236 , p237 , p238 , p239 , p240 , p241 , p242 , p243 , p244 , 
-    p245 , p246 , p247 , p248 , p249 , p250 , p251 , p252 , p253 , p254 , 
-    p255 , p256 , p257 , p258 , p259 , p260 , p261 , p262 , p263 , p264 , 
-    p265 , p266 , p267 , p268 , p269 , p270 , p271 , p272 , p273 , p274 , 
-    p275 , p276 , p277 , p278 , p279 , p280 , p281 , p282 , p283 , p284 , 
-    p285 , p286 , p287 , p288 , p289 , p290 , p291 , p292 , p293 , p294 , 
-    p295 , p296 , p297 , p298 , p299 , p300 , p301 , p302 , p303 , p304 , 
-    p305 , p306 , p307 , p308 , p309 , p310 , p311 , p312 , p313 , p314 , 
-    p315 , p316 , p317 , p318 , p319 , p320 , p321 , p322 , p323 , p324 , 
-    p325 , p326 , p327 , p328 , p329 , p330 , p331 , p332 , p333 , p334 , 
-    p335 , p336 , p337 , p338 , p339 , p340 , p341 , p342 , p343 , p344 , 
-    p345 , p346 , p347 , p348 , p349 , p350 , p351 , p352 , p353 , p354 , 
-    p355 , p356 , p357 , p358 , p359 , p360 , p361 , p362 , p363 , p364 , 
-    p365 , p366 , p367 , p368 , p369 , p370 , p371 , p372 , p373 , p374 , 
-    p375 , p376 , p377 , p378 , p379 , p380 , p381 , p382 , p383 , p384 , 
-    p385 , p386 , p387 , p388 , p389 , p390 , p391 , p392 , p393 , p394 , 
-    p395 , p396 , p397 , p398 , p399 , p400 , p401 , p402 , p403 , p404 , 
-    p405 , p406 , p407 , p408 , p409 , p410 , p411 , p412 , p413 , p414 , 
-    p415 , p416 , p417 , p418 , p419 , p420 , p421 , p422 , p423 , p424 , 
-    p425 , p426 , p427 , p428 , p429 , p430 , p431 , p432 , p433 , p434 , 
-    p435 , p436 , p437 , p438 , p439 , p440 , p441 , p442 , p443 , p444 , 
-    p445 , p446 , p447 , p448 , p449 , p450 , p451 , p452 , p453 , p454 , 
-    p455 , p456 , p457 , p458 , p459 , p460 , p461 , p462 , p463 , p464 , 
-    p465 , p466 , p467 , p468 , p469 , p470 , p471 , p472 , p473 , p474 , 
-    p475 , p476 , p477 , p478 , p479 , p480 , p481 , p482 , p483 , p484 , 
-    p485 , p486 , p487 , p488 , p489 , p490 , p491 , p492 , p493 , p494 , 
-    p495 , p496 , p497 , p498 , p499 , p500 , p501 , p502 , p503 , p504 , 
-    p505 , p506 , p507 , p508 , p509 , p510 , p511 , p512 , p513 , p514 , 
-    p515 , p516 , p517 , p518 , p519 , p520 , p521 , p522 , p523 , p524 , 
-    p525 , p526 , p527 , p528 , p529 , p530 , p531 , p532 , p533 , p534 , 
-    p535 , p536 , p537 , p538 , p539 , p540 , p541 , p542 , p543 , p544 , 
-    p545 , p546 , p547 , p548 , p549 , p550 , p551 , p552 , p553 , p554 , 
-    p555 , p556 , p557 , p558 , p559 , p560 , p561 , p562 , p563 , p564 , 
-    p565 , p566 , p567 , p568 , p569 , p570 , p571 , p572 , p573 , p574 , 
-    p575 , p576 , p577 , p578 , p579 , p580 , p581 , p582 , p583 , p584 , 
-    p585 , p586 , p587 , p588 , p589 , p590 , p591 , p592 , p593 , p594 , 
-    p595 , p596 , p597 , p598 , p599 , p600 , p601 , p602 , p603 , p604 , 
-    p605 , p606 , p607 , p608 , p609 , p610 , p611 , p612 , p613 , p614 , 
-    p615 , p616 , p617 , p618 , p619 , p620 , p621 , p622 , p623 , p624 , 
-    p625 , p626 , p627 , p628 , p629 , p630 , p631 , p632 , p633 , p634 , 
-    p635 , p636 , p637 , p638 , p639 , p640 , p641 , p642 , p643 , p644 , 
-    p645 , p646 , p647 , p648 , p649 , p650 , p651 , p652 , p653 , p654 , 
-    p655 , p656 , p657 , p658 , p659 , p660 , p661 , p662 , p663 , p664 , 
-    p665 , p666 , p667 , p668 , p669 , p670 , p671 , p672 , p673 , p674 , 
-    p675 , p676 , p677 , p678 , p679 , p680 , p681 , p682 , p683 , p684 , 
-    p685 , p686 , p687 , p688 , p689 , p690 , p691 , p692 , p693 , p694 , 
-    p695 , p696 , p697 , p698 , p699 , p700 , p701 , p702 , p703 , p704 , 
-    p705 , p706 , p707 , p708 , p709 , p710 , p711 , p712 , p713 , p714 , 
-    p715 , p716 , p717 , p718 , p719 , p720 , p721 , p722 , p723 , p724 , 
-    p725 , p726 , p727 , p728 , p729 , p730 , p731 , p732 , p733 , p734 , 
-    p735 , p736 , p737 , p738 , p739 , p740 , p741 , p742 , p743 , p744 , 
-    p745 , p746 , p747 , p748 , p749 , p750 , p751 , p752 , p753 , p754 , 
-    p755 , p756 , p757 , p758 , p759 , p760 , p761 , p762 , p763 , p764 , 
-    p765 , p766 , p767 , p768 , p769 , p770 , p771 , p772 , p773 , p774 , 
-    p775 , p776 , p777 , p778 , p779 , p780 , p781 , p782 , p783 , p784 , 
-    p785 , p786 , p787 , p788 , p789 , p790 , p791 , p792 , p793 , p794 , 
-    p795 , p796 , p797 , p798 , p799 , p800 , p801 , p802 , p803 , p804 , 
-    p805 , p806 , p807 , p808 , p809 , p810 , p811 , p812 , p813 , p814 , 
-    p815 , p816 , p817 , p818 , p819 , p820 , p821 , p822 , p823 , p824 , 
-    p825 , p826 , p827 , p828 , p829 , p830 , p831 , p832 , p833 , p834 , 
-    p835 , p836 , p837 , p838 , p839 , p840 , p841 , p842 , p843 , p844 , 
-    p845 , p846 , p847 , p848 , p849 , p850 , p851 , p852 , p853 , p854 , 
-    p855 , p856 , p857 , p858 , p859 , p860 , p861 , p862 , p863 , p864 , 
-    p865 , p866 , p867 , p868 , p869 , p870 , p871 , p872 , p873 , p874 , 
-    p875 , p876 , p877 , p878 , p879 , p880 , p881 , p882 , p883 , p884 , 
-    p885 , p886 , p887 , p888 , p889 , p890 , p891 , p892 , p893 , p894 , 
-    p895 , p896 , p897 , p898 , p899 , p900 , p901 , p902 , p903 , p904 , 
-    p905 , p906 , p907 , p908 , p909 , p910 , p911 , p912 , p913 , p914 , 
-    p915 , p916 , p917 , p918 , p919 , p920 , p921 , p922 , p923 , p924 , 
-    p925 , p926 , p927 , p928 , p929 , p930 , p931 , p932 , p933 , p934 , 
-    p935 , p936 , p937 , p938 , p939 , p940 , p941 , p942 , p943 , p944 , 
-    p945 , p946 , p947 , p948 , p949 , p950 , p951 , p952 , p953 , p954 , 
-    p955 , p956 , p957 , p958 , p959 , p960 , p961 , p962 , p963 , p964 , 
-    p965 , p966 , p967 , p968 , p969 , p970 , p971 , p972 , p973 , p974 , 
-    p975 , p976 , p977 , p978 , p979 , p980 , p981 , p982 , p983 , p984 , 
-    p985 , p986 , p987 , p988 , p989 , p990 , p991 , p992 , p993 , p994 , 
-    p995 , p996 , p997 , p998 , p999 , p1000 , p1001 , p1002 , p1003 , p1004 , 
-    p1005 , p1006 , p1007 , p1008 , p1009 , p1010 , p1011 , p1012 , p1013 , 
-    p1014 , p1015 , p1016 , p1017 , p1018 , p1019 , p1020 , p1021 , p1022 , 
-    p1023 , p1024 , p1025 , p1026 , p1027 , p1028 , p1029 , p1030 , p1031 , 
-    p1032 , p1033 , p1034 , p1035 , p1036 , p1037 , p1038 , p1039 , p1040 , 
-    p1041 , p1042 , p1043 , p1044 , p1045 , p1046 , p1047 , p1048 , p1049 , 
-    p1050 , p1051 , p1052 , p1053 , p1054 , p1055 , p1056 , p1057 , p1058 , 
-    p1059 , p1060 , p1061 , p1062 , p1063 , p1064 , p1065 , p1066 , p1067 , 
-    p1068 , p1069 , p1070 , p1071 , p1072 , p1073 , p1074 , p1075 , p1076 , 
-    p1077 , p1078 , p1079 , p1080 , p1081 , p1082 , p1083 , p1084 , p1085 , 
-    p1086 , p1087 , p1088 , p1089 , p1090 , p1091 , p1092 , p1093 , p1094 , 
-    p1095 , p1096 , p1097 , p1098 , p1099 , p1100 , p1101 , p1102 , p1103 , 
-    p1104 , p1105 , p1106 , p1107 , p1108 , p1109 , p1110 , p1111 , p1112 , 
-    p1113 , p1114 , p1115 , p1116 , p1117 , p1118 , p1119 , p1120 , p1121 , 
-    p1122 , p1123 , p1124 , p1125 , p1126 , p1127 , p1128 , p1129 , p1130 , 
-    p1131 , p1132 , p1133 , p1134 , p1135 , p1136 , p1137 , p1138 , p1139 , 
-    p1140 , p1141 , p1142 , p1143 , p1144 , p1145 , p1146 , p1147 , p1148 , 
-    p1149 , p1150 , p1151 , p1152 , p1153 , p1154 , p1155 , p1156 , p1157 , 
-    p1158 , p1159 , p1160 , p1161 , p1162 , p1163 , p1164 , p1165 , p1166 , 
-    p1167 , p1168 , p1169 , p1170 , p1171 , p1172 , p1173 , p1174 , p1175 , 
-    p1176 , p1177 , p1178 , p1179 , p1180 , p1181 , p1182 , p1183 , p1184 , 
-    p1185 , p1186 , p1187 , p1188 , p1189 , p1190 , p1191 , p1192 , p1193 , 
-    p1194 , p1195 , p1196 , p1197 , p1198 , p1199 , p1200 , p1201 , p1202 , 
-    p1203 , p1204 , p1205 , p1206 , p1207 , p1208 , p1209 , p1210 , p1211 , 
-    p1212 , p1213 , p1214 , p1215 , p1216 , p1217 , p1218 , p1219 , p1220 , 
-    p1221 , p1222 , p1223 , p1224 , p1225 , p1226 , p1227 , p1228 , p1229 , 
-    p1230 , p1231 , p1232 , p1233 , p1234 , p1235 , p1236 , p1237 , p1238 , 
-    p1239 , p1240 , p1241 , p1242 , p1243 , p1244 , p1245 , p1246 , p1247 , 
-    p1248 , p1249 , p1250 , p1251 , p1252 , p1253 , p1254 , p1255 , p1256 , 
-    p1257 , p1258 , p1259 , p1260 , p1261 , p1262 , p1263 , p1264 , p1265 , 
-    p1266 , p1267 , p1268 , p1269 , p1270 , p1271 , p1272 , p1273 , p1274 , 
-    p1275 , p1276 , p1277 , p1278 , p1279 , p1280 , p1281 , p1282 , p1283 , 
-    p1284 , p1285 , p1286 , p1287 , p1288 , p1289 , p1290 , p1291 , p1292 , 
-    p1293 , p1294 , p1295 , p1296 , p1297 , p1298 , p1299 , p1300 , p1301 , 
-    p1302 , p1303 , p1304 , p1305 , p1306 , p1307 , p1308 , p1309 , p1310 , 
-    p1311 , p1312 , p1313 , p1314 , p1315 , p1316 , p1317 , p1318 , p1319 , 
-    p1320 , p1321 , p1322 , p1323 , p1324 , p1325 , p1326 , p1327 , p1328 , 
-    p1329 , p1330 , p1331 , p1332 , p1333 , p1334 , p1335 , p1336 , p1337 , 
-    p1338 , p1339 , p1340 , p1341 , p1342 , p1343 , p1344 , p1345 , p1346 , 
-    p1347 , p1348 , p1349 , p1350 , p1351 , p1352 , p1353 , p1354 , p1355 , 
-    p1356 , p1357 , p1358 , p1359 , p1360 , p1361 , p1362 , p1363 , p1364 , 
-    p1365 , p1366 , p1367 , p1368 , p1369 , p1370 , p1371 , p1372 , p1373 , 
-    p1374 , p1375 , p1376 , p1377 , p1378 , p1379 , p1380 , p1381 , p1382 , 
-    p1383 , p1384 , p1385 , p1386 , p1387 , p1388 , p1389 , p1390 , p1391 , 
-    p1392 , p1393 , p1394 , p1395 , p1396 , p1397 , p1398 , p1399 , p1400 , 
-    p1401 , p1402 , p1403 , p1404 , p1405 , p1406 , p1407 , p1408 , p1409 , 
-    p1410 , p1411 , p1412 , p1413 , p1414 , p1415 , p1416 , p1417 , p1418 , 
-    p1419 , p1420 , p1421 , p1422 , p1423 , p1424 , p1425 , p1426 , p1427 , 
-    p1428 , p1429 , p1430 , p1431 , p1432 , p1433 , p1434 , p1435 , p1436 , 
-    p1437 , p1438 , p1439 , p1440 , p1441 , p1442 , p1443 , p1444 , p1445 , 
-    p1446 , p1447 , p1448 , p1449 , p1450 , p1451 , p1452 , p1453 , p1454 , 
-    p1455 , p1456 , p1457 , p1458 , p1459 , p1460 , p1461 , p1462 , p1463 , 
-    p1464 , p1465 , p1466 , p1467 , p1468 , p1469 , p1470 , p1471 , p1472 , 
-    p1473 , p1474 , p1475 , p1476 , p1477 , p1478 , p1479 , p1480 , p1481 , 
-    p1482 , p1483 , p1484 , p1485 , p1486 , p1487 , p1488 , p1489 , p1490 , 
-    p1491 , p1492 , p1493 , p1494 , p1495 , p1496 , p1497 , p1498 , p1499 , 
-    p1500 , p1501 , p1502 , p1503 , p1504 , p1505 , p1506 , p1507 , p1508 , 
-    p1509 , p1510 , p1511 , p1512 , p1513 , p1514 , p1515 , p1516 , p1517 , 
-    p1518 , p1519 , p1520 , p1521 , p1522 , p1523 , p1524 , p1525 , p1526 , 
-    p1527 , p1528 , p1529 , p1530 , p1531 , p1532 , p1533 , p1534 , p1535 , 
-    p1536 , p1537 , p1538 , p1539 , p1540 , p1541 , p1542 , p1543 , p1544 , 
-    p1545 , p1546 , p1547 , p1548 , p1549 , p1550 , p1551 , p1552 , p1553 , 
-    p1554 , p1555 , p1556 , p1557 , p1558 , p1559 , p1560 , p1561 , p1562 , 
-    p1563 , p1564 , p1565 , p1566 , p1567 , p1568 , p1569 , p1570 , p1571 , 
-    p1572 , p1573 , p1574 , p1575 , p1576 , p1577 , p1578 , p1579 , p1580 , 
-    p1581 , p1582 , p1583 , p1584 , p1585 , p1586 , p1587 , p1588 , p1589 , 
-    p1590 , p1591 , p1592 , p1593 , p1594 , p1595 , p1596 , p1597 , p1598 , 
-    p1599 , p1600 , p1601 , p1602 , p1603 , p1604 , p1605 , p1606 , p1607 , 
-    p1608 , p1609 , p1610 , p1611 , p1612 , p1613 , p1614 , p1615 , p1616 , 
-    p1617 , p1618 , p1619 , p1620 , p1621 , p1622 , p1623 , p1624 , p1625 , 
-    p1626 , p1627 , p1628 , p1629 , p1630 , p1631 , p1632 , p1633 , p1634 , 
-    p1635 , p1636 , p1637 , p1638 , p1639 , p1640 , p1641 , p1642 , p1643 , 
-    p1644 , p1645 , p1646 , p1647 , p1648 , p1649 , p1650 , p1651 , p1652 , 
-    p1653 , p1654 , p1655 , p1656 , p1657 , p1658 , p1659 , p1660 , p1661 , 
-    p1662 , p1663 , p1664 , p1665 , p1666 , p1667 , p1668 , p1669 , p1670 , 
-    p1671 , p1672 , p1673 , p1674 , p1675 , p1676 , p1677 , p1678 , p1679 , 
-    p1680 , p1681 , p1682 , p1683 , p1684 , p1685 , p1686 , p1687 , p1688 , 
-    p1689 , p1690 , p1691 , p1692 , p1693 , p1694 , p1695 , p1696 , p1697 , 
-    p1698 , p1699 , p1700 , p1701 , p1702 , p1703 , p1704 , p1705 , p1706 , 
-    p1707 , p1708 , p1709 , p1710 , p1711 , p1712 , p1713 , p1714 , p1715 , 
-    p1716 , p1717 , p1718 , p1719 , p1720 , p1721 , p1722 , p1723 , p1724 , 
-    p1725 , p1726 , p1727 , p1728 , p1729 , p1730 , p1731 , p1732 , p1733 , 
-    p1734 , p1735 , p1736 , p1737 , p1738 , p1739 , p1740 , p1741 , p1742 , 
-    p1743 , p1744 , p1745 , p1746 , p1747 , p1748 , p1749 , p1750 , p1751 , 
-    p1752 , p1753 , p1754 , p1755 , p1756 , p1757 , p1758 , p1759 , p1760 , 
-    p1761 , p1762 , p1763 , p1764 , p1765 , p1766 , p1767 , p1768 , p1769 , 
-    p1770 , p1771 , p1772 , p1773 , p1774 , p1775 , p1776 , p1777 , p1778 , 
-    p1779 , p1780 , p1781 , p1782 , p1783 , p1784 , p1785 , p1786 , p1787 , 
-    p1788 , p1789 , p1790 , p1791 , p1792 , p1793 , p1794 , p1795 , p1796 , 
-    p1797 , p1798 , p1799 , p1800 , p1801 , p1802 , p1803 , p1804 , p1805 , 
-    p1806 , p1807 , p1808 , p1809 , p1810 , p1811 , p1812 , p1813 , p1814 , 
-    p1815 , p1816 , p1817 , p1818 , p1819 , p1820 , p1821 , p1822 , p1823 , 
-    p1824 , p1825 , p1826 , p1827 , p1828 , p1829 , p1830 , p1831 , p1832 , 
-    p1833 , p1834 , p1835 , p1836 , p1837 , p1838 , p1839 , p1840 , p1841 , 
-    p1842 , p1843 , p1844 , p1845 , p1846 , p1847 , p1848 , p1849 , p1850 , 
-    p1851 , p1852 , p1853 , p1854 , p1855 , p1856 , p1857 , p1858 , p1859 , 
-    p1860 , p1861 , p1862 , p1863 , p1864 , p1865 , p1866 , p1867 , p1868 , 
-    p1869 , p1870 , p1871 , p1872 , p1873 , p1874 , p1875 , p1876 , p1877 , 
-    p1878 , p1879 , p1880 , p1881 , p1882 , p1883 , p1884 , p1885 , p1886 , 
-    p1887 , p1888 , p1889 , p1890 , p1891 , p1892 , p1893 , p1894 , p1895 , 
-    p1896 , p1897 , p1898 , p1899 , p1900 , p1901 , p1902 , p1903 , p1904 , 
-    p1905 , p1906 , p1907 , p1908 , p1909 , p1910 , p1911 , p1912 , p1913 , 
-    p1914 , p1915 , p1916 , p1917 , p1918 , p1919 , p1920 , p1921 , p1922 , 
-    p1923 , p1924 , p1925 , p1926 , p1927 , p1928 , p1929 , p1930 , p1931 , 
-    p1932 , p1933 , p1934 , p1935 , p1936 , p1937 , p1938 , p1939 , p1940 , 
-    p1941 , p1942 , p1943 , p1944 , p1945 , p1946 , p1947 , p1948 , p1949 , 
-    p1950 , p1951 , p1952 , p1953 , p1954 , p1955 , p1956 , p1957 , p1958 , 
-    p1959 , p1960 , p1961 , p1962 , p1963 , p1964 , p1965 , p1966 , p1967 , 
-    p1968 , p1969 , p1970 , p1971 , p1972 , p1973 , p1974 , p1975 , p1976 , 
-    p1977 , p1978 , p1979 , p1980 , p1981 , p1982 , p1983 , p1984 , p1985 , 
-    p1986 , p1987 , p1988 , p1989 , p1990 , p1991 , p1992 , p1993 , p1994 , 
-    p1995 , p1996 , p1997 , p1998 , p1999 , p2000 , p2001 , p2002 , p2003 , 
-    p2004 , p2005 , p2006 , p2007 , p2008 , p2009 , p2010 , p2011 , p2012 , 
-    p2013 , p2014 , p2015 , p2016 , p2017 , p2018 , p2019 , p2020 , p2021 , 
-    p2022 , p2023 , p2024 , p2025 , p2026 , p2027 , p2028 , p2029 , p2030 , 
-    p2031 , p2032 , p2033 , p2034 , p2035 , p2036 , p2037 , p2038 , p2039 , 
-    p2040 , p2041 , p2042 , p2043 , p2044 , p2045 , p2046 , p2047 , p2048 , 
-    p2049 , p2050 , p2051 , p2052 , p2053 , p2054 , p2055 , p2056 , p2057 , 
-    p2058 , p2059 , p2060 , p2061 , p2062 , p2063 , p2064 , p2065 , p2066 , 
-    p2067 , p2068 , p2069 , p2070 , p2071 , p2072 , p2073 , p2074 , p2075 , 
-    p2076 , p2077 , p2078 , p2079 , p2080 , p2081 , p2082 , p2083 , p2084 , 
-    p2085 , p2086 , p2087 , p2088 , p2089 , p2090 , p2091 , p2092 , p2093 , 
-    p2094 , p2095 , p2096 , p2097 , p2098 , p2099 , p2100 , p2101 , p2102 , 
-    p2103 , p2104 , p2105 , p2106 , p2107 , p2108 , p2109 , p2110 , p2111 , 
-    p2112 , p2113 , p2114 , p2115 , p2116 , p2117 , p2118 , p2119 , p2120 , 
-    p2121 , p2122 , p2123 , p2124 , p2125 , p2126 , p2127 , p2128 , p2129 , 
-    p2130 , p2131 , p2132 , p2133 , p2134 , p2135 , p2136 , p2137 , p2138 , 
-    p2139 , p2140 , p2141 , p2142 , p2143 , p2144 , p2145 , p2146 , p2147 , 
-    p2148 , p2149 , p2150 , p2151 , p2152 , p2153 , p2154 , p2155 , p2156 , 
-    p2157 , p2158 , p2159 , p2160 , p2161 , p2162 , p2163 , p2164 , p2165 , 
-    p2166 , p2167 , p2168 , p2169 , p2170 , p2171 , p2172 , p2173 , p2174 , 
-    p2175 , p2176 , p2177 , p2178 , p2179 , p2180 , p2181 , p2182 , p2183 , 
-    p2184 , p2185 , p2186 , p2187 , p2188 , p2189 , p2190 , p2191 , p2192 , 
-    p2193 , p2194 , p2195 , p2196 , p2197 , p2198 , p2199 , p2200 , p2201 , 
-    p2202 , p2203 , p2204 , p2205 , p2206 , p2207 , p2208 , p2209 , p2210 , 
-    p2211 , p2212 , p2213 , p2214 , p2215 , p2216 , p2217 , p2218 , p2219 , 
-    p2220 , p2221 , p2222 , p2223 , p2224 , p2225 , p2226 , p2227 , p2228 , 
-    p2229 , p2230 , p2231 , p2232 , p2233 , p2234 , p2235 , p2236 , p2237 , 
-    p2238 , p2239 , p2240 , p2241 , p2242 , p2243 , p2244 , p2245 , p2246 , 
-    p2247 , p2248 , p2249 , p2250 , p2251 , p2252 , p2253 , p2254 , p2255 , 
-    p2256 , p2257 , p2258 , p2259 , p2260 , p2261 , p2262 , p2263 , p2264 , 
-    p2265 , p2266 , p2267 , p2268 , p2269 , p2270 , p2271 , p2272 , p2273 , 
-    p2274 , p2275 , p2276 , p2277 , p2278 , p2279 , p2280 , p2281 , p2282 , 
-    p2283 , p2284 , p2285 , p2286 , p2287 , p2288 , p2289 , p2290 , p2291 , 
-    p2292 , p2293 , p2294 , p2295 , p2296 , p2297 , p2298 , p2299 , p2300 , 
-    p2301 , p2302 , p2303 , p2304 , p2305 , p2306 , p2307 , p2308 , p2309 , 
-    p2310 , p2311 , p2312 , p2313 , p2314 , p2315 , p2316 , p2317 , p2318 , 
-    p2319 , p2320 , p2321 , p2322 , p2323 , p2324 , p2325 , p2326 , p2327 , 
-    p2328 , p2329 , p2330 , p2331 , p2332 , p2333 , p2334 , p2335 , p2336 , 
-    p2337 , p2338 , p2339 , p2340 , p2341 , p2342 , p2343 , p2344 , p2345 , 
-    p2346 , p2347 , p2348 , p2349 , p2350 , p2351 , p2352 , p2353 , p2354 , 
-    p2355 , p2356 , p2357 , p2358 , p2359 , p2360 , p2361 , p2362 , p2363 , 
-    p2364 , p2365 , p2366 , p2367 , p2368 , p2369 , p2370 , p2371 , p2372 , 
-    p2373 , p2374 , p2375 , p2376 , p2377 , p2378 , p2379 , p2380 , p2381 , 
-    p2382 , p2383 , p2384 , p2385 , p2386 , p2387 , p2388 , p2389 , p2390 , 
-    p2391 , p2392 , p2393 , p2394 , p2395 , p2396 , p2397 , p2398 , p2399 , 
-    p2400 , p2401 , p2402 , p2403 , p2404 , p2405 , p2406 , p2407 , p2408 , 
-    p2409 , p2410 , p2411 , p2412 , p2413 , p2414 , p2415 , p2416 , p2417 , 
-    p2418 , p2419 , p2420 , p2421 , p2422 , p2423 , p2424 , p2425 , p2426 , 
-    p2427 , p2428 , p2429 , p2430 , p2431 , p2432 , p2433 , p2434 , p2435 , 
-    p2436 , p2437 , p2438 , p2439 , p2440 , p2441 , p2442 , p2443 , p2444 , 
-    p2445 , p2446 , p2447 , p2448 , p2449 , p2450 , p2451 , p2452 , p2453 , 
-    p2454 , p2455 , p2456 , p2457 , p2458 , p2459 , p2460 , p2461 , p2462 , 
-    p2463 , p2464 , p2465 , p2466 , p2467 , p2468 , p2469 , p2470 , p2471 , 
-    p2472 , p2473 , p2474 , p2475 , p2476 , p2477 , p2478 , p2479 , p2480 , 
-    p2481 , p2482 , p2483 , p2484 , p2485 , p2486 , p2487 , p2488 , p2489 , 
-    p2490 , p2491 , p2492 , p2493 , p2494 , p2495 , p2496 , p2497 , p2498 , 
-    p2499 , p2500 , p2501 , p2502 , p2503 , p2504 , p2505 , p2506 , p2507 , 
-    p2508 , p2509 , p2510 , p2511 , p2512 , p2513 , p2514 , p2515 , p2516 , 
-    p2517 , p2518 , p2519 , p2520 , p2521 , p2522 , p2523 , p2524 , p2525 , 
-    p2526 , p2527 , p2528 , p2529 , p2530 , p2531 , p2532 , p2533 , p2534 , 
-    p2535 , p2536 , p2537 , p2538 , p2539 , p2540 , p2541 , p2542 , p2543 , 
-    p2544 , p2545 , p2546 , p2547 , p2548 , p2549 , p2550 , p2551 , p2552 , 
-    p2553 , p2554 , p2555 , p2556 , p2557 , p2558 , p2559 , p2560 , p2561 , 
-    p2562 , p2563 , p2564 , p2565 , p2566 , p2567 , p2568 , p2569 , p2570 , 
-    p2571 , p2572 , p2573 , p2574 , p2575 , p2576 , p2577 , p2578 , p2579 , 
-    p2580 , p2581 , p2582 , p2583 , p2584 , p2585 , p2586 , p2587 , p2588 , 
-    p2589 , p2590 , p2591 , p2592 , p2593 , p2594 , p2595 , p2596 , p2597 , 
-    p2598 , p2599 , p2600 , p2601 , p2602 , p2603 , p2604 , p2605 , p2606 , 
-    p2607 , p2608 , p2609 , p2610 , p2611 , p2612 , p2613 , p2614 , p2615 , 
-    p2616 , p2617 , p2618 , p2619 , p2620 , p2621 , p2622 , p2623 , p2624 , 
-    p2625 , p2626 , p2627 , p2628 , p2629 , p2630 , p2631 , p2632 , p2633 , 
-    p2634 , p2635 , p2636 , p2637 , p2638 , p2639 , p2640 , p2641 , p2642 , 
-    p2643 , p2644 , p2645 , p2646 , p2647 , p2648 , p2649 , p2650 , p2651 , 
-    p2652 , p2653 , p2654 , p2655 , p2656 , p2657 , p2658 , p2659 , p2660 , 
-    p2661 , p2662 , p2663 , p2664 , p2665 , p2666 , p2667 , p2668 , p2669 , 
-    p2670 , p2671 , p2672 , p2673 , p2674 , p2675 , p2676 , p2677 , p2678 , 
-    p2679 , p2680 , p2681 , p2682 , p2683 , p2684 , p2685 , p2686 , p2687 , 
-    p2688 , p2689 , p2690 , p2691 , p2692 , p2693 , p2694 , p2695 , p2696 , 
-    p2697 , p2698 , p2699 , p2700 , p2701 , p2702 , p2703 , p2704 , p2705 , 
-    p2706 , p2707 , p2708 , p2709 , p2710 , p2711 , p2712 , p2713 , p2714 , 
-    p2715 , p2716 , p2717 , p2718 , p2719 , p2720 , p2721 , p2722 , p2723 , 
-    p2724 , p2725 , p2726 , p2727 , p2728 , p2729 , p2730 , p2731 , p2732 , 
-    p2733 , p2734 , p2735 , p2736 , p2737 , p2738 , p2739 , p2740 , p2741 , 
-    p2742 , p2743 , p2744 , p2745 , p2746 , p2747 , p2748 , p2749 , p2750 , 
-    p2751 , p2752 , p2753 , p2754 , p2755 , p2756 , p2757 , p2758 , p2759 , 
-    p2760 , p2761 , p2762 , p2763 , p2764 , p2765 , p2766 , p2767 , p2768 , 
-    p2769 , p2770 , p2771 , p2772 , p2773 , p2774 , p2775 , p2776 , p2777 , 
-    p2778 , p2779 , p2780 , p2781 , p2782 , p2783 , p2784 , p2785 , p2786 , 
-    p2787 , p2788 , p2789 , p2790 , p2791 , p2792 , p2793 , p2794 , p2795 , 
-    p2796 , p2797 , p2798 , p2799 , p2800 , p2801 , p2802 , p2803 , p2804 , 
-    p2805 , p2806 , p2807 , p2808 , p2809 , p2810 , p2811 , p2812 , p2813 , 
-    p2814 , p2815 , p2816 , p2817 , p2818 , p2819 , p2820 , p2821 , p2822 , 
-    p2823 , p2824 , p2825 , p2826 , p2827 , p2828 , p2829 , p2830 , p2831 , 
-    p2832 , p2833 , p2834 , p2835 , p2836 , p2837 , p2838 , p2839 , p2840 , 
-    p2841 , p2842 , p2843 , p2844 , p2845 , p2846 , p2847 , p2848 , p2849 , 
-    p2850 , p2851 , p2852 , p2853 , p2854 , p2855 , p2856 , p2857 , p2858 , 
-    p2859 , p2860 , p2861 , p2862 , p2863 , p2864 , p2865 , p2866 , p2867 , 
-    p2868 , p2869 , p2870 , p2871 , p2872 , p2873 , p2874 , p2875 , p2876 , 
-    p2877 , p2878 , p2879 , p2880 , p2881 , p2882 , p2883 , p2884 , p2885 , 
-    p2886 , p2887 , p2888 , p2889 , p2890 , p2891 , p2892 , p2893 , p2894 , 
-    p2895 , p2896 , p2897 , p2898 , p2899 , p2900 , p2901 , p2902 , p2903 , 
-    p2904 , p2905 , p2906 , p2907 , p2908 , p2909 , p2910 , p2911 , p2912 , 
-    p2913 , p2914 , p2915 , p2916 , p2917 , p2918 , p2919 , p2920 , p2921 , 
-    p2922 , p2923 , p2924 , p2925 , p2926 , p2927 , p2928 , p2929 , p2930 , 
-    p2931 , p2932 , p2933 , p2934 , p2935 , p2936 , p2937 , p2938 , p2939 , 
-    p2940 , p2941 , p2942 , p2943 , p2944 , p2945 , p2946 , p2947 , p2948 , 
-    p2949 , p2950 , p2951 , p2952 , p2953 , p2954 , p2955 , p2956 , p2957 , 
-    p2958 , p2959 , p2960 , p2961 , p2962 , p2963 , p2964 , p2965 , p2966 , 
-    p2967 , p2968 , p2969 , p2970 , p2971 , p2972 , p2973 , p2974 , p2975 , 
-    p2976 , p2977 , p2978 , p2979 , p2980 , p2981 , p2982 , p2983 , p2984 , 
-    p2985 , p2986 , p2987 , p2988 , p2989 , p2990 , p2991 , p2992 , p2993 , 
-    p2994 , p2995 , p2996 , p2997 , p2998 , p2999 , p3000 , p3001 , p3002 , 
-    p3003 , p3004 , p3005 , p3006 , p3007 , p3008 , p3009 , p3010 , p3011 , 
-    p3012 , p3013 , p3014 , p3015 , p3016 , p3017 , p3018 , p3019 , p3020 , 
-    p3021 , p3022 , p3023 , p3024 , p3025 , p3026 , p3027 , p3028 , p3029 , 
-    p3030 , p3031 , p3032 , p3033 , p3034 , p3035 , p3036 , p3037 , p3038 , 
-    p3039 , p3040 , p3041 , p3042 , p3043 , p3044 , p3045 , p3046 , p3047 , 
-    p3048 , p3049 , p3050 , p3051 , p3052 , p3053 , p3054 , p3055 , p3056 , 
-    p3057 , p3058 , p3059 , p3060 , p3061 , p3062 , p3063 , p3064 , p3065 , 
-    p3066 , p3067 , p3068 , p3069 , p3070 , p3071 , p3072 , p3073 , p3074 , 
-    p3075 , p3076 , p3077 , p3078 , p3079 , p3080 , p3081 , p3082 , p3083 , 
-    p3084 , p3085 , p3086 , p3087 , p3088 , p3089 , p3090 , p3091 , p3092 , 
-    p3093 , p3094 , p3095 , p3096 , p3097 , p3098 , p3099 , p3100 , p3101 , 
-    p3102 , p3103 , p3104 , p3105 , p3106 , p3107 , p3108 , p3109 , p3110 , 
-    p3111 , p3112 , p3113 , p3114 , p3115 , p3116 , p3117 , p3118 , p3119 , 
-    p3120 , p3121 , p3122 , p3123 , p3124 , p3125 , p3126 , p3127 , p3128 , 
-    p3129 , p3130 , p3131 , p3132 , p3133 , p3134 , p3135 , p3136 , p3137 , 
-    p3138 , p3139 , p3140 , p3141 , p3142 , p3143 , p3144 , p3145 , p3146 , 
-    p3147 , p3148 , p3149 , p3150 , p3151 , p3152 , p3153 , p3154 , p3155 , 
-    p3156 , p3157 , p3158 , p3159 , p3160 , p3161 , p3162 , p3163 , p3164 , 
-    p3165 , p3166 , p3167 , p3168 , p3169 , p3170 , p3171 , p3172 , p3173 , 
-    p3174 , p3175 , p3176 , p3177 , p3178 , p3179 , p3180 , p3181 , p3182 , 
-    p3183 , p3184 , p3185 , p3186 , p3187 , p3188 , p3189 , p3190 , p3191 , 
-    p3192 , p3193 , p3194 , p3195 , p3196 , p3197 , p3198 , p3199 , p3200 , 
-    p3201 , p3202 , p3203 , p3204 , p3205 , p3206 , p3207 , p3208 , p3209 , 
-    p3210 , p3211 , p3212 , p3213 , p3214 , p3215 , p3216 , p3217 , p3218 , 
-    p3219 , p3220 , p3221 , p3222 , p3223 , p3224 , p3225 , p3226 , p3227 , 
-    p3228 , p3229 , p3230 , p3231 , p3232 , p3233 , p3234 , p3235 , p3236 , 
-    p3237 , p3238 , p3239 , p3240 , p3241 , p3242 , p3243 , p3244 , p3245 , 
-    p3246 , p3247 , p3248 , p3249 , p3250 , p3251 , p3252 , p3253 , p3254 , 
-    p3255 , p3256 , p3257 , p3258 , p3259 , p3260 , p3261 , p3262 , p3263 , 
-    p3264 , p3265 , p3266 , p3267 , p3268 , p3269 , p3270 , p3271 , p3272 , 
-    p3273 , p3274 , p3275 , p3276 , p3277 , p3278 , p3279 , p3280 , p3281 , 
-    p3282 , p3283 , p3284 , p3285 , p3286 , p3287 , p3288 , p3289 , p3290 , 
-    p3291 , p3292 , p3293 , p3294 , p3295 , p3296 , p3297 , p3298 , p3299 , 
-    p3300 , p3301 , p3302 , p3303 , p3304 , p3305 , p3306 , p3307 , p3308 , 
-    p3309 , p3310 , p3311 , p3312 , p3313 , p3314 , p3315 , p3316 , p3317 , 
-    p3318 , p3319 , p3320 , p3321 , p3322 , p3323 , p3324 , p3325 , p3326 , 
-    p3327 , p3328 , p3329 , p3330 , p3331 , p3332 , p3333 , p3334 , p3335 , 
-    p3336 , p3337 , p3338 , p3339 , p3340 , p3341 , p3342 , p3343 , p3344 , 
-    p3345 , p3346 , p3347 , p3348 , p3349 , p3350 , p3351 , p3352 , p3353 , 
-    p3354 , p3355 , p3356 , p3357 , p3358 , p3359 , p3360 , p3361 , p3362 , 
-    p3363 , p3364 , p3365 , p3366 , p3367 , p3368 , p3369 , p3370 , p3371 , 
-    p3372 , p3373 , p3374 , p3375 , p3376 , p3377 , p3378 , p3379 , p3380 , 
-    p3381 , p3382 , p3383 , p3384 , p3385 , p3386 , p3387 , p3388 , p3389 , 
-    p3390 , p3391 , p3392 , p3393 , p3394 , p3395 , p3396 , p3397 , p3398 , 
-    p3399 , p3400 , p3401 , p3402 , p3403 , p3404 , p3405 , p3406 , p3407 , 
-    p3408 , p3409 , p3410 , p3411 , p3412 , p3413 , p3414 , p3415 , p3416 , 
-    p3417 , p3418 , p3419 , p3420 , p3421 , p3422 , p3423 , p3424 , p3425 , 
-    p3426 , p3427 , p3428 , p3429 , p3430 , p3431 , p3432 , p3433 , p3434 , 
-    p3435 , p3436 , p3437 , p3438 , p3439 , p3440 , p3441 , p3442 , p3443 , 
-    p3444 , p3445 , p3446 , p3447 , p3448 , p3449 , p3450 , p3451 , p3452 , 
-    p3453 , p3454 , p3455 , p3456 , p3457 , p3458 , p3459 , p3460 , p3461 , 
-    p3462 , p3463 , p3464 , p3465 , p3466 , p3467 , p3468 , p3469 , p3470 , 
-    p3471 , p3472 , p3473 , p3474 , p3475 , p3476 , p3477 , p3478 , p3479 , 
-    p3480 , p3481 , p3482 , p3483 , p3484 , p3485 , p3486 , p3487 , p3488 , 
-    p3489 , p3490 , p3491 , p3492 , p3493 , p3494 , p3495 , p3496 , p3497 , 
-    p3498 , p3499 , p3500 , p3501 , p3502 , p3503 , p3504 , p3505 , p3506 , 
-    p3507 , p3508 , p3509 , p3510 , p3511 , p3512 , p3513 , p3514 , p3515 , 
-    p3516 , p3517 , p3518 , p3519 , p3520 , p3521 , p3522 , p3523 , p3524 , 
-    p3525 , p3526 , p3527 , p3528 , p3529 , p3530 , p3531 , p3532 , p3533 , 
-    p3534 , p3535 , p3536 , p3537 , p3538 , p3539 , p3540 , p3541 , p3542 , 
-    p3543 , p3544 , p3545 , p3546 , p3547 , p3548 , p3549 , p3550 , p3551 , 
-    p3552 , p3553 , p3554 , p3555 , p3556 , p3557 , p3558 , p3559 , p3560 , 
-    p3561 , p3562 , p3563 , p3564 , p3565 , p3566 , p3567 , p3568 , p3569 , 
-    p3570 , p3571 , p3572 , p3573 , p3574 , p3575 , p3576 , p3577 , p3578 , 
-    p3579 , p3580 , p3581 , p3582 , p3583 , p3584 , p3585 , p3586 , p3587 ) ;
+    sc_tail , VDD , VSS , h_incr0 , p0 , p1 , p2 , p3 , p4 , p5 , p6 , p7 , 
+    p8 , p9 , p10 , p11 , p12 , p13 , p14 , p15 , p16 , p17 , p18 , p19 , 
+    p20 , p21 , p22 , p23 , p24 , p25 , p26 , p27 , p28 , p29 , p30 , p31 , 
+    p32 , p33 , p34 , p35 , p36 , p37 , p38 , p39 , p40 , p41 , p42 , p43 , 
+    p44 , p45 , p46 , p47 , p48 , p49 , p50 , p51 , p52 , p53 , p54 , p55 , 
+    p56 , p57 , p58 , p59 , p60 , p61 , p62 , p63 , p64 , p65 , p66 , p67 , 
+    p68 , p69 , p70 , p71 , p72 , p73 , p74 , p75 , p76 , p77 , p78 , p79 , 
+    p80 , p81 , p82 , p83 , p84 , p85 , p86 , p87 , p88 , p89 , p90 , p91 , 
+    p92 , p93 , p94 , p95 , p96 , p97 , p98 , p99 , p100 , p101 , p102 , 
+    p103 , p104 , p105 , p106 , p107 , p108 , p109 , p110 , p111 , p112 , 
+    p113 , p114 , p115 , p116 , p117 , p118 , p119 , p120 , p121 , p122 , 
+    p123 , p124 , p125 , p126 , p127 , p128 , p129 , p130 , p131 , p132 , 
+    p133 , p134 , p135 , p136 , p137 , p138 , p139 , p140 , p141 , p142 , 
+    p143 , p144 , p145 , p146 , p147 , p148 , p149 , p150 , p151 , p152 , 
+    p153 , p154 , p155 , p156 , p157 , p158 , p159 , p160 , p161 , p162 , 
+    p163 , p164 , p165 , p166 , p167 , p168 , p169 , p170 , p171 , p172 , 
+    p173 , p174 , p175 , p176 , p177 , p178 , p179 , p180 , p181 , p182 , 
+    p183 , p184 , p185 , p186 , p187 , p188 , p189 , p190 , p191 , p192 , 
+    p193 , p194 , p195 , p196 , p197 , p198 , p199 , p200 , p201 , p202 , 
+    p203 , p204 , p205 , p206 , p207 , p208 , p209 , p210 , p211 , p212 , 
+    p213 , p214 , p215 , p216 , p217 , p218 , p219 , p220 , p221 , p222 , 
+    p223 , p224 , p225 , p226 , p227 , p228 , p229 , p230 , p231 , p232 , 
+    p233 , p234 , p235 , p236 , p237 , p238 , p239 , p240 , p241 , p242 , 
+    p243 , p244 , p245 , p246 , p247 , p248 , p249 , p250 , p251 , p252 , 
+    p253 , p254 , p255 , p256 , p257 , p258 , p259 , p260 , p261 , p262 , 
+    p263 , p264 , p265 , p266 , p267 , p268 , p269 , p270 , p271 , p272 , 
+    p273 , p274 , p275 , p276 , p277 , p278 , p279 , p280 , p281 , p282 , 
+    p283 , p284 , p285 , p286 , p287 , p288 , p289 , p290 , p291 , p292 , 
+    p293 , p294 , p295 , p296 , p297 , p298 , p299 , p300 , p301 , p302 , 
+    p303 , p304 , p305 , p306 , p307 , p308 , p309 , p310 , p311 , p312 , 
+    p313 , p314 , p315 , p316 , p317 , p318 , p319 , p320 , p321 , p322 , 
+    p323 , p324 , p325 , p326 , p327 , p328 , p329 , p330 , p331 , p332 , 
+    p333 , p334 , p335 , p336 , p337 , p338 , p339 , p340 , p341 , p342 , 
+    p343 , p344 , p345 , p346 , p347 , p348 , p349 , p350 , p351 , p352 , 
+    p353 , p354 , p355 , p356 , p357 , p358 , p359 , p360 , p361 , p362 , 
+    p363 , p364 , p365 , p366 , p367 , p368 , p369 , p370 , p371 , p372 , 
+    p373 , p374 , p375 , p376 , p377 , p378 , p379 , p380 , p381 , p382 , 
+    p383 , p384 , p385 , p386 , p387 , p388 , p389 , p390 , p391 , p392 , 
+    p393 , p394 , p395 , p396 , p397 , p398 , p399 , p400 , p401 , p402 , 
+    p403 , p404 , p405 , p406 , p407 , p408 , p409 , p410 , p411 , p412 , 
+    p413 , p414 , p415 , p416 , p417 , p418 , p419 , p420 , p421 , p422 , 
+    p423 , p424 , p425 , p426 , p427 , p428 , p429 , p430 , p431 , p432 , 
+    p433 , p434 , p435 , p436 , p437 , p438 , p439 , p440 , p441 , p442 , 
+    p443 , p444 , p445 , p446 , p447 , p448 , p449 , p450 , p451 , p452 , 
+    p453 , p454 , p455 , p456 , p457 , p458 , p459 , p460 , p461 , p462 , 
+    p463 , p464 , p465 , p466 , p467 , p468 , p469 , p470 , p471 , p472 , 
+    p473 , p474 , p475 , p476 , p477 , p478 , p479 , p480 , p481 , p482 , 
+    p483 , p484 , p485 , p486 , p487 , p488 , p489 , p490 , p491 , p492 , 
+    p493 , p494 , p495 , p496 , p497 , p498 , p499 , p500 , p501 , p502 , 
+    p503 , p504 , p505 , p506 , p507 , p508 , p509 , p510 , p511 , p512 , 
+    p513 , p514 , p515 , p516 , p517 , p518 , p519 , p520 , p521 , p522 , 
+    p523 , p524 , p525 , p526 , p527 , p528 , p529 , p530 , p531 , p532 , 
+    p533 , p534 , p535 , p536 , p537 , p538 , p539 , p540 , p541 , p542 , 
+    p543 , p544 , p545 , p546 , p547 , p548 , p549 , p550 , p551 , p552 , 
+    p553 , p554 , p555 , p556 , p557 , p558 , p559 , p560 , p561 , p562 , 
+    p563 , p564 , p565 , p566 , p567 , p568 , p569 , p570 , p571 , p572 , 
+    p573 , p574 , p575 , p576 , p577 , p578 , p579 , p580 , p581 , p582 , 
+    p583 , p584 , p585 , p586 , p587 , p588 , p589 , p590 , p591 , p592 , 
+    p593 , p594 , p595 , p596 , p597 , p598 , p599 , p600 , p601 , p602 , 
+    p603 , p604 , p605 , p606 , p607 , p608 , p609 , p610 , p611 , p612 , 
+    p613 , p614 , p615 , p616 , p617 , p618 , p619 , p620 , p621 , p622 , 
+    p623 , p624 , p625 , p626 , p627 , p628 , p629 , p630 , p631 , p632 , 
+    p633 , p634 , p635 , p636 , p637 , p638 , p639 , p640 , p641 , p642 , 
+    p643 , p644 , p645 , p646 , p647 , p648 , p649 , p650 , p651 , p652 , 
+    p653 , p654 , p655 , p656 , p657 , p658 , p659 , p660 , p661 , p662 , 
+    p663 , p664 , p665 , p666 , p667 , p668 , p669 , p670 , p671 , p672 , 
+    p673 , p674 , p675 , p676 , p677 , p678 , p679 , p680 , p681 , p682 , 
+    p683 , p684 , p685 , p686 , p687 , p688 , p689 , p690 , p691 , p692 , 
+    p693 , p694 , p695 , p696 , p697 , p698 , p699 , p700 , p701 , p702 , 
+    p703 , p704 , p705 , p706 , p707 , p708 , p709 , p710 , p711 , p712 , 
+    p713 , p714 , p715 , p716 , p717 , p718 , p719 , p720 , p721 , p722 , 
+    p723 , p724 , p725 , p726 , p727 , p728 , p729 , p730 , p731 , p732 , 
+    p733 , p734 , p735 , p736 , p737 , p738 , p739 , p740 , p741 , p742 , 
+    p743 , p744 , p745 , p746 , p747 , p748 , p749 , p750 , p751 , p752 , 
+    p753 , p754 , p755 , p756 , p757 , p758 , p759 , p760 , p761 , p762 , 
+    p763 , p764 , p765 , p766 , p767 , p768 , p769 , p770 , p771 , p772 , 
+    p773 , p774 , p775 , p776 , p777 , p778 , p779 , p780 , p781 , p782 , 
+    p783 , p784 , p785 , p786 , p787 , p788 , p789 , p790 , p791 , p792 , 
+    p793 , p794 , p795 , p796 , p797 , p798 , p799 , p800 , p801 , p802 , 
+    p803 , p804 , p805 , p806 , p807 , p808 , p809 , p810 , p811 , p812 , 
+    p813 , p814 , p815 , p816 , p817 , p818 , p819 , p820 , p821 , p822 , 
+    p823 , p824 , p825 , p826 , p827 , p828 , p829 , p830 , p831 , p832 , 
+    p833 , p834 , p835 , p836 , p837 , p838 , p839 , p840 , p841 , p842 , 
+    p843 , p844 , p845 , p846 , p847 , p848 , p849 , p850 , p851 , p852 , 
+    p853 , p854 , p855 , p856 , p857 , p858 , p859 , p860 , p861 , p862 , 
+    p863 , p864 , p865 , p866 , p867 , p868 , p869 , p870 , p871 , p872 , 
+    p873 , p874 , p875 , p876 , p877 , p878 , p879 , p880 , p881 , p882 , 
+    p883 , p884 , p885 , p886 , p887 , p888 , p889 , p890 , p891 , p892 , 
+    p893 , p894 , p895 , p896 , p897 , p898 , p899 , p900 , p901 , p902 , 
+    p903 , p904 , p905 , p906 , p907 , p908 , p909 , p910 , p911 , p912 , 
+    p913 , p914 , p915 , p916 , p917 , p918 , p919 , p920 , p921 , p922 , 
+    p923 , p924 , p925 , p926 , p927 , p928 , p929 , p930 , p931 , p932 , 
+    p933 , p934 , p935 , p936 , p937 , p938 , p939 , p940 , p941 , p942 , 
+    p943 , p944 , p945 , p946 , p947 , p948 , p949 , p950 , p951 , p952 , 
+    p953 , p954 , p955 , p956 , p957 , p958 , p959 , p960 , p961 , p962 , 
+    p963 , p964 , p965 , p966 , p967 , p968 , p969 , p970 , p971 , p972 , 
+    p973 , p974 , p975 , p976 , p977 , p978 , p979 , p980 , p981 , p982 , 
+    p983 , p984 , p985 , p986 , p987 , p988 , p989 , p990 , p991 , p992 , 
+    p993 , p994 , p995 , p996 , p997 , p998 , p999 , p1000 , p1001 , p1002 , 
+    p1003 , p1004 , p1005 , p1006 , p1007 , p1008 , p1009 , p1010 , p1011 , 
+    p1012 , p1013 , p1014 , p1015 , p1016 , p1017 , p1018 , p1019 , p1020 , 
+    p1021 , p1022 , p1023 , p1024 , p1025 , p1026 , p1027 , p1028 , p1029 , 
+    p1030 , p1031 , p1032 , p1033 , p1034 , p1035 , p1036 , p1037 , p1038 , 
+    p1039 , p1040 , p1041 , p1042 , p1043 , p1044 , p1045 , p1046 , p1047 , 
+    p1048 , p1049 , p1050 , p1051 , p1052 , p1053 , p1054 , p1055 , p1056 , 
+    p1057 , p1058 , p1059 , p1060 , p1061 , p1062 , p1063 , p1064 , p1065 , 
+    p1066 , p1067 , p1068 , p1069 , p1070 , p1071 , p1072 , p1073 , p1074 , 
+    p1075 , p1076 , p1077 , p1078 , p1079 , p1080 , p1081 , p1082 , p1083 , 
+    p1084 , p1085 , p1086 , p1087 , p1088 , p1089 , p1090 , p1091 , p1092 , 
+    p1093 , p1094 , p1095 , p1096 , p1097 , p1098 , p1099 , p1100 , p1101 , 
+    p1102 , p1103 , p1104 , p1105 , p1106 , p1107 , p1108 , p1109 , p1110 , 
+    p1111 , p1112 , p1113 , p1114 , p1115 , p1116 , p1117 , p1118 , p1119 , 
+    p1120 , p1121 , p1122 , p1123 , p1124 , p1125 , p1126 , p1127 , p1128 , 
+    p1129 , p1130 , p1131 , p1132 , p1133 , p1134 , p1135 , p1136 , p1137 , 
+    p1138 , p1139 , p1140 , p1141 , p1142 , p1143 , p1144 , p1145 , p1146 , 
+    p1147 , p1148 , p1149 , p1150 , p1151 , p1152 , p1153 , p1154 , p1155 , 
+    p1156 , p1157 , p1158 , p1159 , p1160 , p1161 , p1162 , p1163 , p1164 , 
+    p1165 , p1166 , p1167 , p1168 , p1169 , p1170 , p1171 , p1172 , p1173 , 
+    p1174 , p1175 , p1176 , p1177 , p1178 , p1179 , p1180 , p1181 , p1182 , 
+    p1183 , p1184 , p1185 , p1186 , p1187 , p1188 , p1189 , p1190 , p1191 , 
+    p1192 , p1193 , p1194 , p1195 , p1196 , p1197 , p1198 , p1199 , p1200 , 
+    p1201 , p1202 , p1203 , p1204 , p1205 , p1206 , p1207 , p1208 , p1209 , 
+    p1210 , p1211 , p1212 , p1213 , p1214 , p1215 , p1216 , p1217 , p1218 , 
+    p1219 , p1220 , p1221 , p1222 , p1223 , p1224 , p1225 , p1226 , p1227 , 
+    p1228 , p1229 , p1230 , p1231 , p1232 , p1233 , p1234 , p1235 , p1236 , 
+    p1237 , p1238 , p1239 , p1240 , p1241 , p1242 , p1243 , p1244 , p1245 , 
+    p1246 , p1247 , p1248 , p1249 , p1250 , p1251 , p1252 , p1253 , p1254 , 
+    p1255 , p1256 , p1257 , p1258 , p1259 , p1260 , p1261 , p1262 , p1263 , 
+    p1264 , p1265 , p1266 , p1267 , p1268 , p1269 , p1270 , p1271 , p1272 , 
+    p1273 , p1274 , p1275 , p1276 , p1277 , p1278 , p1279 , p1280 , p1281 , 
+    p1282 , p1283 , p1284 , p1285 , p1286 , p1287 , p1288 , p1289 , p1290 , 
+    p1291 , p1292 , p1293 , p1294 , p1295 , p1296 , p1297 , p1298 , p1299 , 
+    p1300 , p1301 , p1302 , p1303 , p1304 , p1305 , p1306 , p1307 , p1308 , 
+    p1309 , p1310 , p1311 , p1312 , p1313 , p1314 , p1315 , p1316 , p1317 , 
+    p1318 , p1319 , p1320 , p1321 , p1322 , p1323 , p1324 , p1325 , p1326 , 
+    p1327 , p1328 , p1329 , p1330 , p1331 , p1332 , p1333 , p1334 , p1335 , 
+    p1336 , p1337 , p1338 , p1339 , p1340 , p1341 , p1342 , p1343 , p1344 , 
+    p1345 , p1346 , p1347 , p1348 , p1349 , p1350 , p1351 , p1352 , p1353 , 
+    p1354 , p1355 , p1356 , p1357 , p1358 , p1359 , p1360 , p1361 , p1362 , 
+    p1363 , p1364 , p1365 , p1366 , p1367 , p1368 , p1369 , p1370 , p1371 , 
+    p1372 , p1373 , p1374 , p1375 , p1376 , p1377 , p1378 , p1379 , p1380 , 
+    p1381 , p1382 , p1383 , p1384 , p1385 , p1386 , p1387 , p1388 , p1389 , 
+    p1390 , p1391 , p1392 , p1393 , p1394 , p1395 , p1396 , p1397 , p1398 , 
+    p1399 , p1400 , p1401 , p1402 , p1403 , p1404 , p1405 , p1406 , p1407 , 
+    p1408 , p1409 , p1410 , p1411 , p1412 , p1413 , p1414 , p1415 , p1416 , 
+    p1417 , p1418 , p1419 , p1420 , p1421 , p1422 , p1423 , p1424 , p1425 , 
+    p1426 , p1427 , p1428 , p1429 , p1430 , p1431 , p1432 , p1433 , p1434 , 
+    p1435 , p1436 , p1437 , p1438 , p1439 , p1440 , p1441 , p1442 , p1443 , 
+    p1444 , p1445 , p1446 , p1447 , p1448 , p1449 , p1450 , p1451 , p1452 , 
+    p1453 , p1454 , p1455 , p1456 , p1457 , p1458 , p1459 , p1460 , p1461 , 
+    p1462 , p1463 , p1464 , p1465 , p1466 , p1467 , p1468 , p1469 , p1470 , 
+    p1471 , p1472 , p1473 , p1474 , p1475 , p1476 , p1477 , p1478 , p1479 , 
+    p1480 , p1481 , p1482 , p1483 , p1484 , p1485 , p1486 , p1487 , p1488 , 
+    p1489 , p1490 , p1491 , p1492 , p1493 , p1494 , p1495 , p1496 , p1497 , 
+    p1498 , p1499 , p1500 , p1501 , p1502 , p1503 , p1504 , p1505 , p1506 , 
+    p1507 , p1508 , p1509 , p1510 , p1511 , p1512 , p1513 , p1514 , p1515 , 
+    p1516 , p1517 , p1518 , p1519 , p1520 , p1521 , p1522 , p1523 , p1524 , 
+    p1525 , p1526 , p1527 , p1528 , p1529 , p1530 , p1531 , p1532 , p1533 , 
+    p1534 , p1535 , p1536 , p1537 , p1538 , p1539 , p1540 , p1541 , p1542 , 
+    p1543 , p1544 , p1545 , p1546 , p1547 , p1548 , p1549 , p1550 , p1551 , 
+    p1552 , p1553 , p1554 , p1555 , p1556 , p1557 , p1558 , p1559 , p1560 , 
+    p1561 , p1562 , p1563 , p1564 , p1565 , p1566 , p1567 , p1568 , p1569 , 
+    p1570 , p1571 , p1572 , p1573 , p1574 , p1575 , p1576 , p1577 , p1578 , 
+    p1579 , p1580 , p1581 , p1582 , p1583 , p1584 , p1585 , p1586 , p1587 , 
+    p1588 , p1589 , p1590 , p1591 , p1592 , p1593 , p1594 , p1595 , p1596 , 
+    p1597 , p1598 , p1599 , p1600 , p1601 , p1602 , p1603 , p1604 , p1605 , 
+    p1606 , p1607 , p1608 , p1609 , p1610 , p1611 , p1612 , p1613 , p1614 , 
+    p1615 , p1616 , p1617 , p1618 , p1619 , p1620 , p1621 , p1622 , p1623 , 
+    p1624 , p1625 , p1626 , p1627 , p1628 , p1629 , p1630 , p1631 , p1632 , 
+    p1633 , p1634 , p1635 , p1636 , p1637 , p1638 , p1639 , p1640 , p1641 , 
+    p1642 , p1643 , p1644 , p1645 , p1646 , p1647 , p1648 , p1649 , p1650 , 
+    p1651 , p1652 , p1653 , p1654 , p1655 , p1656 , p1657 , p1658 , p1659 , 
+    p1660 , p1661 , p1662 , p1663 , p1664 , p1665 , p1666 , p1667 , p1668 , 
+    p1669 , p1670 , p1671 , p1672 , p1673 , p1674 , p1675 , p1676 , p1677 , 
+    p1678 , p1679 , p1680 , p1681 , p1682 , p1683 , p1684 , p1685 , p1686 , 
+    p1687 , p1688 , p1689 , p1690 , p1691 , p1692 , p1693 , p1694 , p1695 , 
+    p1696 , p1697 , p1698 , p1699 , p1700 , p1701 , p1702 , p1703 , p1704 , 
+    p1705 , p1706 , p1707 , p1708 , p1709 , p1710 , p1711 , p1712 , p1713 , 
+    p1714 , p1715 , p1716 , p1717 , p1718 , p1719 , p1720 , p1721 , p1722 , 
+    p1723 , p1724 , p1725 , p1726 , p1727 , p1728 , p1729 , p1730 , p1731 , 
+    p1732 , p1733 , p1734 , p1735 , p1736 , p1737 , p1738 , p1739 , p1740 , 
+    p1741 , p1742 , p1743 , p1744 , p1745 , p1746 , p1747 , p1748 , p1749 , 
+    p1750 , p1751 , p1752 , p1753 , p1754 , p1755 , p1756 , p1757 , p1758 , 
+    p1759 , p1760 , p1761 , p1762 , p1763 , p1764 , p1765 , p1766 , p1767 , 
+    p1768 , p1769 , p1770 , p1771 , p1772 , p1773 , p1774 , p1775 , p1776 , 
+    p1777 , p1778 , p1779 , p1780 , p1781 , p1782 , p1783 , p1784 , p1785 , 
+    p1786 , p1787 , p1788 , p1789 , p1790 , p1791 , p1792 , p1793 , p1794 , 
+    p1795 , p1796 , p1797 , p1798 , p1799 , p1800 , p1801 , p1802 , p1803 , 
+    p1804 , p1805 , p1806 , p1807 , p1808 , p1809 , p1810 , p1811 , p1812 , 
+    p1813 , p1814 , p1815 , p1816 , p1817 , p1818 , p1819 , p1820 , p1821 , 
+    p1822 , p1823 , p1824 , p1825 , p1826 , p1827 , p1828 , p1829 , p1830 , 
+    p1831 , p1832 , p1833 , p1834 , p1835 , p1836 , p1837 , p1838 , p1839 , 
+    p1840 , p1841 , p1842 , p1843 , p1844 , p1845 , p1846 , p1847 , p1848 , 
+    p1849 , p1850 , p1851 , p1852 , p1853 , p1854 , p1855 , p1856 , p1857 , 
+    p1858 , p1859 , p1860 , p1861 , p1862 , p1863 , p1864 , p1865 , p1866 , 
+    p1867 , p1868 , p1869 , p1870 , p1871 , p1872 , p1873 , p1874 , p1875 , 
+    p1876 , p1877 , p1878 , p1879 , p1880 , p1881 , p1882 , p1883 , p1884 , 
+    p1885 , p1886 , p1887 , p1888 , p1889 , p1890 , p1891 , p1892 , p1893 , 
+    p1894 , p1895 , p1896 , p1897 , p1898 , p1899 , p1900 , p1901 , p1902 , 
+    p1903 , p1904 , p1905 , p1906 , p1907 , p1908 , p1909 , p1910 , p1911 , 
+    p1912 , p1913 , p1914 , p1915 , p1916 , p1917 , p1918 , p1919 , p1920 , 
+    p1921 , p1922 , p1923 , p1924 , p1925 , p1926 , p1927 , p1928 , p1929 , 
+    p1930 , p1931 , p1932 , p1933 , p1934 , p1935 , p1936 , p1937 , p1938 , 
+    p1939 , p1940 , p1941 , p1942 , p1943 , p1944 , p1945 , p1946 , p1947 , 
+    p1948 , p1949 , p1950 , p1951 , p1952 , p1953 , p1954 , p1955 , p1956 , 
+    p1957 , p1958 , p1959 , p1960 , p1961 , p1962 , p1963 , p1964 , p1965 , 
+    p1966 , p1967 , p1968 , p1969 , p1970 , p1971 , p1972 , p1973 , p1974 , 
+    p1975 , p1976 , p1977 , p1978 , p1979 , p1980 , p1981 , p1982 , p1983 , 
+    p1984 , p1985 , p1986 , p1987 , p1988 , p1989 , p1990 , p1991 , p1992 , 
+    p1993 , p1994 , p1995 , p1996 , p1997 , p1998 , p1999 , p2000 , p2001 , 
+    p2002 , p2003 , p2004 , p2005 , p2006 , p2007 , p2008 , p2009 , p2010 , 
+    p2011 , p2012 , p2013 , p2014 , p2015 , p2016 , p2017 , p2018 , p2019 , 
+    p2020 , p2021 , p2022 , p2023 , p2024 , p2025 , p2026 , p2027 , p2028 , 
+    p2029 , p2030 , p2031 , p2032 , p2033 , p2034 , p2035 , p2036 , p2037 , 
+    p2038 , p2039 , p2040 , p2041 , p2042 , p2043 , p2044 , p2045 , p2046 , 
+    p2047 , p2048 , p2049 , p2050 , p2051 , p2052 , p2053 , p2054 , p2055 , 
+    p2056 , p2057 , p2058 , p2059 , p2060 , p2061 , p2062 , p2063 , p2064 , 
+    p2065 , p2066 , p2067 , p2068 , p2069 , p2070 , p2071 , p2072 , p2073 , 
+    p2074 , p2075 , p2076 , p2077 , p2078 , p2079 , p2080 , p2081 , p2082 , 
+    p2083 , p2084 , p2085 , p2086 , p2087 , p2088 , p2089 , p2090 , p2091 , 
+    p2092 , p2093 , p2094 , p2095 , p2096 , p2097 , p2098 , p2099 , p2100 , 
+    p2101 , p2102 , p2103 , p2104 , p2105 , p2106 , p2107 , p2108 , p2109 , 
+    p2110 , p2111 , p2112 , p2113 , p2114 , p2115 , p2116 , p2117 , p2118 , 
+    p2119 , p2120 , p2121 , p2122 , p2123 , p2124 , p2125 , p2126 , p2127 , 
+    p2128 , p2129 , p2130 , p2131 , p2132 , p2133 , p2134 , p2135 , p2136 , 
+    p2137 , p2138 , p2139 , p2140 , p2141 , p2142 , p2143 , p2144 , p2145 , 
+    p2146 , p2147 , p2148 , p2149 , p2150 , p2151 , p2152 , p2153 , p2154 , 
+    p2155 , p2156 , p2157 , p2158 , p2159 , p2160 , p2161 , p2162 , p2163 , 
+    p2164 , p2165 , p2166 , p2167 , p2168 , p2169 , p2170 , p2171 , p2172 , 
+    p2173 , p2174 , p2175 , p2176 , p2177 , p2178 , p2179 , p2180 , p2181 , 
+    p2182 , p2183 , p2184 , p2185 , p2186 , p2187 , p2188 , p2189 , p2190 , 
+    p2191 , p2192 , p2193 , p2194 , p2195 , p2196 , p2197 , p2198 , p2199 , 
+    p2200 , p2201 , p2202 , p2203 , p2204 , p2205 , p2206 , p2207 , p2208 , 
+    p2209 , p2210 , p2211 , p2212 , p2213 , p2214 , p2215 , p2216 , p2217 , 
+    p2218 , p2219 , p2220 , p2221 , p2222 , p2223 , p2224 , p2225 , p2226 , 
+    p2227 , p2228 , p2229 , p2230 , p2231 , p2232 , p2233 , p2234 , p2235 , 
+    p2236 , p2237 , p2238 , p2239 , p2240 , p2241 , p2242 , p2243 , p2244 , 
+    p2245 , p2246 , p2247 , p2248 , p2249 , p2250 , p2251 , p2252 , p2253 , 
+    p2254 , p2255 , p2256 , p2257 , p2258 , p2259 , p2260 , p2261 , p2262 , 
+    p2263 , p2264 , p2265 , p2266 , p2267 , p2268 , p2269 , p2270 , p2271 , 
+    p2272 , p2273 , p2274 , p2275 , p2276 , p2277 , p2278 , p2279 , p2280 , 
+    p2281 , p2282 , p2283 , p2284 , p2285 , p2286 , p2287 , p2288 , p2289 , 
+    p2290 , p2291 , p2292 , p2293 , p2294 , p2295 , p2296 , p2297 , p2298 , 
+    p2299 , p2300 , p2301 , p2302 , p2303 , p2304 , p2305 , p2306 , p2307 , 
+    p2308 , p2309 , p2310 , p2311 , p2312 , p2313 , p2314 , p2315 , p2316 , 
+    p2317 , p2318 , p2319 , p2320 , p2321 , p2322 , p2323 , p2324 , p2325 , 
+    p2326 , p2327 , p2328 , p2329 , p2330 , p2331 , p2332 , p2333 , p2334 , 
+    p2335 , p2336 , p2337 , p2338 , p2339 , p2340 , p2341 , p2342 , p2343 , 
+    p2344 , p2345 , p2346 , p2347 , p2348 , p2349 , p2350 , p2351 , p2352 , 
+    p2353 , p2354 , p2355 , p2356 , p2357 , p2358 , p2359 , p2360 , p2361 , 
+    p2362 , p2363 , p2364 , p2365 , p2366 , p2367 , p2368 , p2369 , p2370 , 
+    p2371 , p2372 , p2373 , p2374 , p2375 , p2376 , p2377 , p2378 , p2379 , 
+    p2380 , p2381 , p2382 , p2383 , p2384 , p2385 , p2386 , p2387 , p2388 , 
+    p2389 , p2390 , p2391 , p2392 , p2393 , p2394 , p2395 , p2396 , p2397 , 
+    p2398 , p2399 , p2400 , p2401 , p2402 , p2403 , p2404 , p2405 , p2406 , 
+    p2407 , p2408 , p2409 , p2410 , p2411 , p2412 , p2413 , p2414 , p2415 , 
+    p2416 , p2417 , p2418 , p2419 , p2420 , p2421 , p2422 , p2423 , p2424 , 
+    p2425 , p2426 , p2427 , p2428 , p2429 , p2430 , p2431 , p2432 , p2433 , 
+    p2434 , p2435 , p2436 , p2437 , p2438 , p2439 , p2440 , p2441 , p2442 , 
+    p2443 , p2444 , p2445 , p2446 , p2447 , p2448 , p2449 , p2450 , p2451 , 
+    p2452 , p2453 , p2454 , p2455 , p2456 , p2457 , p2458 , p2459 , p2460 , 
+    p2461 , p2462 , p2463 , p2464 , p2465 , p2466 , p2467 , p2468 , p2469 , 
+    p2470 , p2471 , p2472 , p2473 , p2474 , p2475 , p2476 , p2477 , p2478 , 
+    p2479 , p2480 , p2481 , p2482 , p2483 , p2484 , p2485 , p2486 , p2487 , 
+    p2488 , p2489 , p2490 , p2491 , p2492 , p2493 , p2494 , p2495 , p2496 , 
+    p2497 , p2498 , p2499 , p2500 , p2501 , p2502 , p2503 , p2504 , p2505 , 
+    p2506 , p2507 , p2508 , p2509 , p2510 , p2511 , p2512 , p2513 , p2514 , 
+    p2515 , p2516 , p2517 , p2518 , p2519 , p2520 , p2521 , p2522 , p2523 , 
+    p2524 , p2525 , p2526 , p2527 , p2528 , p2529 , p2530 , p2531 , p2532 , 
+    p2533 , p2534 , p2535 , p2536 , p2537 , p2538 , p2539 , p2540 , p2541 , 
+    p2542 , p2543 , p2544 , p2545 , p2546 , p2547 , p2548 , p2549 , p2550 , 
+    p2551 , p2552 , p2553 , p2554 , p2555 , p2556 , p2557 , p2558 , p2559 , 
+    p2560 , p2561 , p2562 , p2563 , p2564 , p2565 , p2566 , p2567 , p2568 , 
+    p2569 , p2570 , p2571 , p2572 , p2573 , p2574 , p2575 , p2576 , p2577 , 
+    p2578 , p2579 , p2580 , p2581 , p2582 , p2583 , p2584 , p2585 , p2586 , 
+    p2587 , p2588 , p2589 , p2590 , p2591 , p2592 , p2593 , p2594 , p2595 , 
+    p2596 , p2597 , p2598 , p2599 , p2600 , p2601 , p2602 , p2603 , p2604 , 
+    p2605 , p2606 , p2607 , p2608 , p2609 , p2610 , p2611 , p2612 , p2613 , 
+    p2614 , p2615 , p2616 , p2617 , p2618 , p2619 , p2620 , p2621 , p2622 , 
+    p2623 , p2624 , p2625 , p2626 , p2627 , p2628 , p2629 , p2630 , p2631 , 
+    p2632 , p2633 , p2634 , p2635 , p2636 , p2637 , p2638 , p2639 , p2640 , 
+    p2641 , p2642 , p2643 , p2644 , p2645 , p2646 , p2647 , p2648 , p2649 , 
+    p2650 , p2651 , p2652 , p2653 , p2654 , p2655 , p2656 , p2657 , p2658 , 
+    p2659 , p2660 , p2661 , p2662 , p2663 , p2664 , p2665 , p2666 , p2667 , 
+    p2668 , p2669 , p2670 , p2671 , p2672 , p2673 , p2674 , p2675 , p2676 , 
+    p2677 , p2678 , p2679 , p2680 , p2681 , p2682 , p2683 , p2684 , p2685 , 
+    p2686 , p2687 , p2688 , p2689 , p2690 , p2691 , p2692 , p2693 , p2694 , 
+    p2695 , p2696 , p2697 , p2698 , p2699 , p2700 , p2701 , p2702 , p2703 , 
+    p2704 , p2705 , p2706 , p2707 , p2708 , p2709 , p2710 , p2711 , p2712 , 
+    p2713 , p2714 , p2715 , p2716 , p2717 , p2718 , p2719 , p2720 , p2721 , 
+    p2722 , p2723 , p2724 , p2725 , p2726 , p2727 , p2728 , p2729 , p2730 , 
+    p2731 , p2732 , p2733 , p2734 , p2735 , p2736 , p2737 , p2738 , p2739 , 
+    p2740 , p2741 , p2742 , p2743 , p2744 , p2745 , p2746 , p2747 , p2748 , 
+    p2749 , p2750 , p2751 , p2752 , p2753 , p2754 , p2755 , p2756 , p2757 , 
+    p2758 , p2759 , p2760 , p2761 , p2762 , p2763 , p2764 , p2765 , p2766 , 
+    p2767 , p2768 , p2769 , p2770 , p2771 , p2772 , p2773 , p2774 , p2775 , 
+    p2776 , p2777 , p2778 , p2779 , p2780 , p2781 , p2782 , p2783 , p2784 , 
+    p2785 , p2786 , p2787 , p2788 , p2789 , p2790 , p2791 , p2792 , p2793 , 
+    p2794 , p2795 , p2796 , p2797 , p2798 , p2799 , p2800 , p2801 , p2802 , 
+    p2803 , p2804 , p2805 , p2806 , p2807 , p2808 , p2809 , p2810 , p2811 , 
+    p2812 , p2813 , p2814 , p2815 , p2816 , p2817 , p2818 , p2819 , p2820 , 
+    p2821 , p2822 , p2823 , p2824 , p2825 , p2826 , p2827 , p2828 , p2829 , 
+    p2830 , p2831 , p2832 , p2833 , p2834 , p2835 , p2836 , p2837 , p2838 , 
+    p2839 , p2840 , p2841 , p2842 , p2843 , p2844 , p2845 , p2846 , p2847 , 
+    p2848 , p2849 , p2850 , p2851 , p2852 , p2853 , p2854 , p2855 , p2856 , 
+    p2857 , p2858 , p2859 , p2860 , p2861 , p2862 , p2863 , p2864 , p2865 , 
+    p2866 , p2867 , p2868 , p2869 , p2870 , p2871 , p2872 , p2873 , p2874 , 
+    p2875 , p2876 , p2877 , p2878 , p2879 , p2880 , p2881 , p2882 , p2883 , 
+    p2884 , p2885 , p2886 , p2887 , p2888 , p2889 , p2890 , p2891 , p2892 , 
+    p2893 , p2894 , p2895 , p2896 , p2897 , p2898 , p2899 , p2900 , p2901 , 
+    p2902 , p2903 , p2904 , p2905 , p2906 , p2907 , p2908 , p2909 , p2910 , 
+    p2911 , p2912 , p2913 , p2914 , p2915 , p2916 , p2917 , p2918 , p2919 , 
+    p2920 , p2921 , p2922 , p2923 , p2924 , p2925 , p2926 , p2927 , p2928 , 
+    p2929 , p2930 , p2931 , p2932 , p2933 , p2934 , p2935 , p2936 , p2937 , 
+    p2938 , p2939 , p2940 , p2941 , p2942 , p2943 , p2944 , p2945 , p2946 , 
+    p2947 , p2948 , p2949 , p2950 , p2951 , p2952 , p2953 , p2954 , p2955 , 
+    p2956 , p2957 , p2958 , p2959 , p2960 , p2961 , p2962 , p2963 , p2964 , 
+    p2965 , p2966 , p2967 , p2968 , p2969 , p2970 , p2971 , p2972 , p2973 , 
+    p2974 , p2975 , p2976 , p2977 , p2978 , p2979 , p2980 , p2981 , p2982 , 
+    p2983 , p2984 , p2985 , p2986 , p2987 , p2988 , p2989 , p2990 , p2991 , 
+    p2992 , p2993 , p2994 , p2995 , p2996 , p2997 , p2998 , p2999 , p3000 , 
+    p3001 , p3002 , p3003 , p3004 , p3005 , p3006 , p3007 , p3008 , p3009 , 
+    p3010 , p3011 , p3012 , p3013 , p3014 , p3015 , p3016 , p3017 , p3018 , 
+    p3019 , p3020 , p3021 , p3022 , p3023 , p3024 , p3025 , p3026 , p3027 , 
+    p3028 , p3029 , p3030 , p3031 , p3032 , p3033 , p3034 , p3035 , p3036 , 
+    p3037 , p3038 , p3039 , p3040 , p3041 , p3042 , p3043 , p3044 , p3045 , 
+    p3046 , p3047 , p3048 , p3049 , p3050 , p3051 , p3052 , p3053 , p3054 , 
+    p3055 , p3056 , p3057 , p3058 , p3059 , p3060 , p3061 , p3062 , p3063 , 
+    p3064 , p3065 , p3066 , p3067 , p3068 , p3069 , p3070 , p3071 , p3072 , 
+    p3073 , p3074 , p3075 , p3076 , p3077 , p3078 , p3079 , p3080 , p3081 , 
+    p3082 , p3083 , p3084 , p3085 , p3086 , p3087 , p3088 , p3089 , p3090 , 
+    p3091 , p3092 , p3093 , p3094 , p3095 , p3096 , p3097 , p3098 , p3099 , 
+    p3100 , p3101 , p3102 , p3103 , p3104 , p3105 , p3106 , p3107 , p3108 , 
+    p3109 , p3110 , p3111 , p3112 , p3113 , p3114 , p3115 , p3116 , p3117 , 
+    p3118 , p3119 , p3120 , p3121 , p3122 , p3123 , p3124 , p3125 , p3126 , 
+    p3127 , p3128 , p3129 , p3130 , p3131 , p3132 , p3133 , p3134 , p3135 , 
+    p3136 , p3137 , p3138 , p3139 , p3140 , p3141 , p3142 , p3143 , p3144 , 
+    p3145 , p3146 , p3147 , p3148 , p3149 , p3150 , p3151 , p3152 , p3153 , 
+    p3154 , p3155 , p3156 , p3157 , p3158 , p3159 , p3160 , p3161 , p3162 , 
+    p3163 , p3164 , p3165 , p3166 , p3167 , p3168 , p3169 , p3170 , p3171 , 
+    p3172 , p3173 , p3174 , p3175 , p3176 , p3177 , p3178 , p3179 , p3180 , 
+    p3181 , p3182 , p3183 , p3184 , p3185 , p3186 , p3187 , p3188 , p3189 , 
+    p3190 , p3191 , p3192 , p3193 , p3194 , p3195 , p3196 , p3197 , p3198 , 
+    p3199 , p3200 , p3201 , p3202 , p3203 , p3204 , p3205 , p3206 , p3207 , 
+    p3208 , p3209 , p3210 , p3211 , p3212 , p3213 , p3214 , p3215 , p3216 , 
+    p3217 , p3218 , p3219 , p3220 , p3221 , p3222 , p3223 , p3224 , p3225 , 
+    p3226 , p3227 , p3228 , p3229 , p3230 , p3231 , p3232 , p3233 , p3234 , 
+    p3235 , p3236 , p3237 , p3238 , p3239 , p3240 , p3241 , p3242 , p3243 , 
+    p3244 , p3245 , p3246 , p3247 , p3248 , p3249 , p3250 , p3251 , p3252 , 
+    p3253 , p3254 , p3255 , p3256 , p3257 , p3258 , p3259 , p3260 , p3261 , 
+    p3262 , p3263 , p3264 , p3265 , p3266 , p3267 , p3268 , p3269 , p3270 , 
+    p3271 , p3272 , p3273 , p3274 , p3275 , p3276 , p3277 , p3278 , p3279 , 
+    p3280 , p3281 , p3282 , p3283 , p3284 , p3285 , p3286 , p3287 , p3288 , 
+    p3289 , p3290 , p3291 , p3292 , p3293 , p3294 , p3295 , p3296 , p3297 , 
+    p3298 , p3299 , p3300 , p3301 , p3302 , p3303 , p3304 , p3305 , p3306 , 
+    p3307 , p3308 , p3309 , p3310 , p3311 , p3312 , p3313 , p3314 , p3315 , 
+    p3316 , p3317 , p3318 , p3319 , p3320 , p3321 , p3322 , p3323 , p3324 , 
+    p3325 , p3326 , p3327 , p3328 , p3329 , p3330 , p3331 , p3332 , p3333 , 
+    p3334 , p3335 , p3336 , p3337 , p3338 , p3339 , p3340 , p3341 , p3342 , 
+    p3343 , p3344 , p3345 , p3346 , p3347 , p3348 , p3349 , p3350 , p3351 , 
+    p3352 , p3353 , p3354 , p3355 , p3356 , p3357 , p3358 , p3359 , p3360 , 
+    p3361 , p3362 , p3363 , p3364 , p3365 , p3366 , p3367 , p3368 , p3369 , 
+    p3370 , p3371 , p3372 , p3373 , p3374 , p3375 , p3376 , p3377 , p3378 , 
+    p3379 , p3380 , p3381 , p3382 , p3383 , p3384 , p3385 , p3386 , p3387 , 
+    p3388 , p3389 , p3390 , p3391 , p3392 , p3393 , p3394 , p3395 , p3396 , 
+    p3397 , p3398 , p3399 , p3400 , p3401 , p3402 , p3403 , p3404 , p3405 , 
+    p3406 , p3407 , p3408 , p3409 , p3410 , p3411 , p3412 , p3413 , p3414 , 
+    p3415 , p3416 , p3417 , p3418 , p3419 , p3420 , p3421 , p3422 , p3423 , 
+    p3424 , p3425 , p3426 , p3427 , p3428 , p3429 , p3430 , p3431 , p3432 , 
+    p3433 , p3434 , p3435 , p3436 , p3437 , p3438 , p3439 , p3440 , p3441 , 
+    p3442 , p3443 , p3444 , p3445 , p3446 , p3447 , p3448 , p3449 , p3450 , 
+    p3451 , p3452 , p3453 , p3454 , p3455 , p3456 , p3457 , p3458 , p3459 , 
+    p3460 , p3461 , p3462 , p3463 , p3464 , p3465 , p3466 , p3467 , p3468 , 
+    p3469 , p3470 , p3471 , p3472 , p3473 , p3474 , p3475 , p3476 , p3477 , 
+    p3478 , p3479 , p3480 , p3481 , p3482 , p3483 , p3484 , p3485 , p3486 , 
+    p3487 , p3488 , p3489 , p3490 , p3491 , p3492 , p3493 , p3494 , p3495 , 
+    p3496 , p3497 , p3498 , p3499 , p3500 , p3501 , p3502 , p3503 , p3504 , 
+    p3505 , p3506 , p3507 , p3508 , p3509 , p3510 , p3511 , p3512 , p3513 , 
+    p3514 , p3515 , p3516 , p3517 , p3518 , p3519 , p3520 , p3521 , p3522 , 
+    p3523 , p3524 , p3525 , p3526 , p3527 , p3528 , p3529 , p3530 , p3531 , 
+    p3532 , p3533 , p3534 , p3535 , p3536 , p3537 , p3538 , p3539 , p3540 , 
+    p3541 , p3542 , p3543 , p3544 , p3545 , p3546 , p3547 , p3548 , p3549 , 
+    p3550 , p3551 , p3552 , p3553 , p3554 , p3555 , p3556 , p3557 , p3558 , 
+    p3559 , p3560 , p3561 , p3562 , p3563 , p3564 , p3565 , p3566 , p3567 , 
+    p3568 , p3569 , p3570 , p3571 , p3572 , p3573 , p3574 , p3575 , p3576 , 
+    p3577 , p3578 , p3579 , p3580 , p3581 , p3582 , p3583 , p3584 , p3585 , 
+    p3586 , p3587 ) ;
 input  [0:0] pReset ;
 input  [0:0] prog_clk ;
 input  [0:0] Test_en ;
@@ -80567,6 +106798,8 @@
 output [0:0] ccff_tail ;
 input  sc_head ;
 output sc_tail ;
+input  VDD ;
+input  VSS ;
 input  h_incr0 ;
 input  p0 ;
 input  p1 ;
@@ -96198,6 +122431,8 @@
 wire [251:0] clk_1_wires ;
 wire [135:0] clk_2_wires ;
 wire [100:0] clk_3_wires ;
+supply1 VDD ;
+supply0 VSS ;
 
 grid_clb grid_clb_1__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1 } ) ,
@@ -96291,7 +122526,8 @@
     .prog_clk_0_E_out ( prog_clk_0_wires[1] ) , 
     .prog_clk_0_W_out ( prog_clk_0_wires[3] ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_14 ) , 
-    .clk_0_N_in ( clk_1_wires[4] ) , .clk_0_S_in ( SYNOPSYS_UNCONNECTED_15 ) ) ;
+    .clk_0_N_in ( clk_1_wires[4] ) , .clk_0_S_in ( SYNOPSYS_UNCONNECTED_15 ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_1__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_16 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) , 
@@ -96383,7 +122619,8 @@
     .prog_clk_0_E_out ( prog_clk_0_wires[7] ) , 
     .prog_clk_0_W_out ( prog_clk_0_wires[9] ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_29 ) , 
-    .clk_0_N_in ( SYNOPSYS_UNCONNECTED_30 ) , .clk_0_S_in ( clk_1_wires[3] ) ) ;
+    .clk_0_N_in ( SYNOPSYS_UNCONNECTED_30 ) , .clk_0_S_in ( clk_1_wires[3] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_1__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_31 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__2_bottom_grid_pin_0_ ) , 
@@ -96476,7 +122713,7 @@
     .prog_clk_0_W_out ( prog_clk_0_wires[14] ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_44 ) , 
     .clk_0_N_in ( clk_1_wires[11] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_45 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_45 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_1__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_46 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__3_bottom_grid_pin_0_ ) , 
@@ -96569,7 +122806,7 @@
     .prog_clk_0_W_out ( prog_clk_0_wires[19] ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_59 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_60 ) , 
-    .clk_0_S_in ( clk_1_wires[10] ) ) ;
+    .clk_0_S_in ( clk_1_wires[10] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_1__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_61 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__4_bottom_grid_pin_0_ ) , 
@@ -96662,7 +122899,7 @@
     .prog_clk_0_W_out ( prog_clk_0_wires[24] ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_74 ) , 
     .clk_0_N_in ( clk_1_wires[18] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_75 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_75 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_1__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_76 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__5_bottom_grid_pin_0_ ) , 
@@ -96755,7 +122992,7 @@
     .prog_clk_0_W_out ( prog_clk_0_wires[29] ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_89 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_90 ) , 
-    .clk_0_S_in ( clk_1_wires[17] ) ) ;
+    .clk_0_S_in ( clk_1_wires[17] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_1__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_91 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__6_bottom_grid_pin_0_ ) , 
@@ -96848,7 +123085,7 @@
     .prog_clk_0_W_out ( prog_clk_0_wires[34] ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_104 ) , 
     .clk_0_N_in ( clk_1_wires[25] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_105 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_105 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_1__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_106 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__7_bottom_grid_pin_0_ ) , 
@@ -96941,7 +123178,7 @@
     .prog_clk_0_W_out ( prog_clk_0_wires[39] ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_119 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_120 ) , 
-    .clk_0_S_in ( clk_1_wires[24] ) ) ;
+    .clk_0_S_in ( clk_1_wires[24] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_1__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_121 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__8_bottom_grid_pin_0_ ) , 
@@ -97034,7 +123271,7 @@
     .prog_clk_0_W_out ( prog_clk_0_wires[44] ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_134 ) , 
     .clk_0_N_in ( clk_1_wires[32] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_135 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_135 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_1__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_136 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__9_bottom_grid_pin_0_ ) , 
@@ -97127,7 +123364,7 @@
     .prog_clk_0_W_out ( prog_clk_0_wires[49] ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_149 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_150 ) , 
-    .clk_0_S_in ( clk_1_wires[31] ) ) ;
+    .clk_0_S_in ( clk_1_wires[31] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_1__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_151 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__10_bottom_grid_pin_0_ ) , 
@@ -97220,7 +123457,7 @@
     .prog_clk_0_W_out ( prog_clk_0_wires[54] ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_164 ) , 
     .clk_0_N_in ( clk_1_wires[39] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_165 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_165 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_1__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_166 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__12__0_bottom_grid_pin_0_ ) , 
@@ -97314,7 +123551,7 @@
     .prog_clk_0_W_out ( prog_clk_0_wires[61] ) , 
     .prog_clk_0_N_out ( prog_clk_0_wires[59] ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_179 ) , 
-    .clk_0_S_in ( clk_1_wires[38] ) ) ;
+    .clk_0_S_in ( clk_1_wires[38] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_2__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_180 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__11_bottom_grid_pin_0_ ) , 
@@ -97409,7 +123646,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_191 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_192 ) , 
     .clk_0_N_in ( clk_1_wires[6] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_193 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_193 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_2__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_194 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__12_bottom_grid_pin_0_ ) , 
@@ -97503,7 +123740,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_205 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_206 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_207 ) , 
-    .clk_0_S_in ( clk_1_wires[5] ) ) ;
+    .clk_0_S_in ( clk_1_wires[5] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_2__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_208 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__13_bottom_grid_pin_0_ ) , 
@@ -97597,7 +123834,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_219 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_220 ) , 
     .clk_0_N_in ( clk_1_wires[13] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_221 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_221 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_2__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_222 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__14_bottom_grid_pin_0_ ) , 
@@ -97691,7 +123928,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_233 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_234 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_235 ) , 
-    .clk_0_S_in ( clk_1_wires[12] ) ) ;
+    .clk_0_S_in ( clk_1_wires[12] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_2__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_236 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__15_bottom_grid_pin_0_ ) , 
@@ -97785,7 +124022,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_247 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_248 ) , 
     .clk_0_N_in ( clk_1_wires[20] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_249 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_249 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_2__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_250 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__16_bottom_grid_pin_0_ ) , 
@@ -97879,7 +124116,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_261 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_262 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_263 ) , 
-    .clk_0_S_in ( clk_1_wires[19] ) ) ;
+    .clk_0_S_in ( clk_1_wires[19] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_2__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_264 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__17_bottom_grid_pin_0_ ) , 
@@ -97973,7 +124210,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_275 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_276 ) , 
     .clk_0_N_in ( clk_1_wires[27] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_277 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_277 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_2__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_278 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__18_bottom_grid_pin_0_ ) , 
@@ -98067,7 +124304,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_289 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_290 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_291 ) , 
-    .clk_0_S_in ( clk_1_wires[26] ) ) ;
+    .clk_0_S_in ( clk_1_wires[26] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_2__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_292 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__19_bottom_grid_pin_0_ ) , 
@@ -98161,7 +124398,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_303 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_304 ) , 
     .clk_0_N_in ( clk_1_wires[34] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_305 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_305 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_2__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_306 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__20_bottom_grid_pin_0_ ) , 
@@ -98255,7 +124492,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_317 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_318 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_319 ) , 
-    .clk_0_S_in ( clk_1_wires[33] ) ) ;
+    .clk_0_S_in ( clk_1_wires[33] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_2__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_320 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__21_bottom_grid_pin_0_ ) , 
@@ -98349,7 +124586,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_331 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_332 ) , 
     .clk_0_N_in ( clk_1_wires[41] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_333 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_333 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_2__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_334 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__12__1_bottom_grid_pin_0_ ) , 
@@ -98444,7 +124681,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_345 ) , 
     .prog_clk_0_N_out ( prog_clk_0_wires[99] ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_346 ) , 
-    .clk_0_S_in ( clk_1_wires[40] ) ) ;
+    .clk_0_S_in ( clk_1_wires[40] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_3__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_347 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__22_bottom_grid_pin_0_ ) , 
@@ -98538,7 +124775,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_358 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_359 ) , 
     .clk_0_N_in ( clk_1_wires[46] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_360 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_360 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_3__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_361 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__23_bottom_grid_pin_0_ ) , 
@@ -98631,7 +124868,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_372 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_373 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_374 ) , 
-    .clk_0_S_in ( clk_1_wires[45] ) ) ;
+    .clk_0_S_in ( clk_1_wires[45] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_3__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_375 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__24_bottom_grid_pin_0_ ) , 
@@ -98724,7 +124961,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_386 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_387 ) , 
     .clk_0_N_in ( clk_1_wires[53] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_388 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_388 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_3__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_389 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__25_bottom_grid_pin_0_ ) , 
@@ -98817,7 +125054,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_400 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_401 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_402 ) , 
-    .clk_0_S_in ( clk_1_wires[52] ) ) ;
+    .clk_0_S_in ( clk_1_wires[52] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_3__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_403 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__26_bottom_grid_pin_0_ ) , 
@@ -98910,7 +125147,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_414 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_415 ) , 
     .clk_0_N_in ( clk_1_wires[60] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_416 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_416 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_3__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_417 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__27_bottom_grid_pin_0_ ) , 
@@ -99003,7 +125240,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_428 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_429 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_430 ) , 
-    .clk_0_S_in ( clk_1_wires[59] ) ) ;
+    .clk_0_S_in ( clk_1_wires[59] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_3__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_431 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__28_bottom_grid_pin_0_ ) , 
@@ -99096,7 +125333,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_442 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_443 ) , 
     .clk_0_N_in ( clk_1_wires[67] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_444 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_444 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_3__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_445 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__29_bottom_grid_pin_0_ ) , 
@@ -99189,7 +125426,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_456 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_457 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_458 ) , 
-    .clk_0_S_in ( clk_1_wires[66] ) ) ;
+    .clk_0_S_in ( clk_1_wires[66] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_3__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_459 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__30_bottom_grid_pin_0_ ) , 
@@ -99282,7 +125519,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_470 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_471 ) , 
     .clk_0_N_in ( clk_1_wires[74] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_472 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_472 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_3__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_473 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__31_bottom_grid_pin_0_ ) , 
@@ -99375,7 +125612,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_484 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_485 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_486 ) , 
-    .clk_0_S_in ( clk_1_wires[73] ) ) ;
+    .clk_0_S_in ( clk_1_wires[73] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_3__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_487 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__32_bottom_grid_pin_0_ ) , 
@@ -99468,7 +125705,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_498 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_499 ) , 
     .clk_0_N_in ( clk_1_wires[81] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_500 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_500 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_3__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_501 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__12__2_bottom_grid_pin_0_ ) , 
@@ -99562,7 +125799,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_512 ) , 
     .prog_clk_0_N_out ( prog_clk_0_wires[137] ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_513 ) , 
-    .clk_0_S_in ( clk_1_wires[80] ) ) ;
+    .clk_0_S_in ( clk_1_wires[80] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_4__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_514 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__33_bottom_grid_pin_0_ ) , 
@@ -99657,7 +125894,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_525 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_526 ) , 
     .clk_0_N_in ( clk_1_wires[48] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_527 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_527 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_4__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_528 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__34_bottom_grid_pin_0_ ) , 
@@ -99751,7 +125988,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_539 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_540 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_541 ) , 
-    .clk_0_S_in ( clk_1_wires[47] ) ) ;
+    .clk_0_S_in ( clk_1_wires[47] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_4__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_542 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__35_bottom_grid_pin_0_ ) , 
@@ -99845,7 +126082,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_553 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_554 ) , 
     .clk_0_N_in ( clk_1_wires[55] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_555 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_555 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_4__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_556 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__36_bottom_grid_pin_0_ ) , 
@@ -99939,7 +126176,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_567 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_568 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_569 ) , 
-    .clk_0_S_in ( clk_1_wires[54] ) ) ;
+    .clk_0_S_in ( clk_1_wires[54] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_4__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_570 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__37_bottom_grid_pin_0_ ) , 
@@ -100033,7 +126270,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_581 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_582 ) , 
     .clk_0_N_in ( clk_1_wires[62] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_583 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_583 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_4__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_584 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__38_bottom_grid_pin_0_ ) , 
@@ -100127,7 +126364,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_595 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_596 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_597 ) , 
-    .clk_0_S_in ( clk_1_wires[61] ) ) ;
+    .clk_0_S_in ( clk_1_wires[61] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_4__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_598 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__39_bottom_grid_pin_0_ ) , 
@@ -100221,7 +126458,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_609 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_610 ) , 
     .clk_0_N_in ( clk_1_wires[69] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_611 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_611 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_4__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_612 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__40_bottom_grid_pin_0_ ) , 
@@ -100315,7 +126552,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_623 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_624 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_625 ) , 
-    .clk_0_S_in ( clk_1_wires[68] ) ) ;
+    .clk_0_S_in ( clk_1_wires[68] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_4__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_626 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__41_bottom_grid_pin_0_ ) , 
@@ -100409,7 +126646,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_637 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_638 ) , 
     .clk_0_N_in ( clk_1_wires[76] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_639 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_639 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_4__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_640 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__42_bottom_grid_pin_0_ ) , 
@@ -100503,7 +126740,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_651 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_652 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_653 ) , 
-    .clk_0_S_in ( clk_1_wires[75] ) ) ;
+    .clk_0_S_in ( clk_1_wires[75] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_4__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_654 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__43_bottom_grid_pin_0_ ) , 
@@ -100597,7 +126834,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_665 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_666 ) , 
     .clk_0_N_in ( clk_1_wires[83] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_667 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_667 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_4__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_668 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__12__3_bottom_grid_pin_0_ ) , 
@@ -100692,7 +126929,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_679 ) , 
     .prog_clk_0_N_out ( prog_clk_0_wires[175] ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_680 ) , 
-    .clk_0_S_in ( clk_1_wires[82] ) ) ;
+    .clk_0_S_in ( clk_1_wires[82] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_5__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_681 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__44_bottom_grid_pin_0_ ) , 
@@ -100786,7 +127023,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_692 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_693 ) , 
     .clk_0_N_in ( clk_1_wires[88] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_694 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_694 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_5__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_695 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__45_bottom_grid_pin_0_ ) , 
@@ -100879,7 +127116,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_706 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_707 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_708 ) , 
-    .clk_0_S_in ( clk_1_wires[87] ) ) ;
+    .clk_0_S_in ( clk_1_wires[87] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_5__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_709 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__46_bottom_grid_pin_0_ ) , 
@@ -100972,7 +127209,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_720 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_721 ) , 
     .clk_0_N_in ( clk_1_wires[95] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_722 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_722 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_5__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_723 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__47_bottom_grid_pin_0_ ) , 
@@ -101065,7 +127302,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_734 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_735 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_736 ) , 
-    .clk_0_S_in ( clk_1_wires[94] ) ) ;
+    .clk_0_S_in ( clk_1_wires[94] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_5__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_737 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__48_bottom_grid_pin_0_ ) , 
@@ -101158,7 +127395,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_748 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_749 ) , 
     .clk_0_N_in ( clk_1_wires[102] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_750 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_750 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_5__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_751 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__49_bottom_grid_pin_0_ ) , 
@@ -101251,7 +127488,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_762 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_763 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_764 ) , 
-    .clk_0_S_in ( clk_1_wires[101] ) ) ;
+    .clk_0_S_in ( clk_1_wires[101] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_5__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_765 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__50_bottom_grid_pin_0_ ) , 
@@ -101344,7 +127581,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_776 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_777 ) , 
     .clk_0_N_in ( clk_1_wires[109] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_778 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_778 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_5__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_779 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__51_bottom_grid_pin_0_ ) , 
@@ -101437,7 +127674,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_790 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_791 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_792 ) , 
-    .clk_0_S_in ( clk_1_wires[108] ) ) ;
+    .clk_0_S_in ( clk_1_wires[108] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_5__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_793 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__52_bottom_grid_pin_0_ ) , 
@@ -101530,7 +127767,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_804 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_805 ) , 
     .clk_0_N_in ( clk_1_wires[116] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_806 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_806 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_5__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_807 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__53_bottom_grid_pin_0_ ) , 
@@ -101623,7 +127860,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_818 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_819 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_820 ) , 
-    .clk_0_S_in ( clk_1_wires[115] ) ) ;
+    .clk_0_S_in ( clk_1_wires[115] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_5__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_821 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__54_bottom_grid_pin_0_ ) , 
@@ -101716,7 +127953,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_832 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_833 ) , 
     .clk_0_N_in ( clk_1_wires[123] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_834 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_834 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_5__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_835 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__12__4_bottom_grid_pin_0_ ) , 
@@ -101810,7 +128047,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_846 ) , 
     .prog_clk_0_N_out ( prog_clk_0_wires[213] ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_847 ) , 
-    .clk_0_S_in ( clk_1_wires[122] ) ) ;
+    .clk_0_S_in ( clk_1_wires[122] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_6__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_848 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__55_bottom_grid_pin_0_ ) , 
@@ -101905,7 +128142,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_859 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_860 ) , 
     .clk_0_N_in ( clk_1_wires[90] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_861 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_861 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_6__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_862 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__56_bottom_grid_pin_0_ ) , 
@@ -101999,7 +128236,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_873 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_874 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_875 ) , 
-    .clk_0_S_in ( clk_1_wires[89] ) ) ;
+    .clk_0_S_in ( clk_1_wires[89] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_6__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_876 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__57_bottom_grid_pin_0_ ) , 
@@ -102093,7 +128330,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_887 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_888 ) , 
     .clk_0_N_in ( clk_1_wires[97] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_889 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_889 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_6__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_890 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__58_bottom_grid_pin_0_ ) , 
@@ -102187,7 +128424,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_901 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_902 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_903 ) , 
-    .clk_0_S_in ( clk_1_wires[96] ) ) ;
+    .clk_0_S_in ( clk_1_wires[96] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_6__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_904 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__59_bottom_grid_pin_0_ ) , 
@@ -102281,7 +128518,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_915 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_916 ) , 
     .clk_0_N_in ( clk_1_wires[104] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_917 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_917 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_6__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_918 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__60_bottom_grid_pin_0_ ) , 
@@ -102375,7 +128612,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_929 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_930 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_931 ) , 
-    .clk_0_S_in ( clk_1_wires[103] ) ) ;
+    .clk_0_S_in ( clk_1_wires[103] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_6__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_932 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__61_bottom_grid_pin_0_ ) , 
@@ -102469,7 +128706,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_943 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_944 ) , 
     .clk_0_N_in ( clk_1_wires[111] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_945 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_945 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_6__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_946 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__62_bottom_grid_pin_0_ ) , 
@@ -102563,7 +128800,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_957 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_958 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_959 ) , 
-    .clk_0_S_in ( clk_1_wires[110] ) ) ;
+    .clk_0_S_in ( clk_1_wires[110] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_6__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_960 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__63_bottom_grid_pin_0_ ) , 
@@ -102657,7 +128894,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_971 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_972 ) , 
     .clk_0_N_in ( clk_1_wires[118] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_973 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_973 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_6__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_974 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__64_bottom_grid_pin_0_ ) , 
@@ -102751,7 +128988,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_985 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_986 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_987 ) , 
-    .clk_0_S_in ( clk_1_wires[117] ) ) ;
+    .clk_0_S_in ( clk_1_wires[117] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_6__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_988 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__65_bottom_grid_pin_0_ ) , 
@@ -102845,7 +129082,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_999 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1000 ) , 
     .clk_0_N_in ( clk_1_wires[125] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1001 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1001 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_6__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1002 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__12__5_bottom_grid_pin_0_ ) , 
@@ -102940,7 +129177,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1013 ) , 
     .prog_clk_0_N_out ( prog_clk_0_wires[251] ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1014 ) , 
-    .clk_0_S_in ( clk_1_wires[124] ) ) ;
+    .clk_0_S_in ( clk_1_wires[124] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_7__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1015 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__66_bottom_grid_pin_0_ ) , 
@@ -103035,7 +129272,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1026 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1027 ) , 
     .clk_0_N_in ( clk_1_wires[130] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1028 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1028 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_7__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1029 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__67_bottom_grid_pin_0_ ) , 
@@ -103129,7 +129366,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1040 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1041 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1042 ) , 
-    .clk_0_S_in ( clk_1_wires[129] ) ) ;
+    .clk_0_S_in ( clk_1_wires[129] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_7__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1043 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__68_bottom_grid_pin_0_ ) , 
@@ -103223,7 +129460,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1054 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1055 ) , 
     .clk_0_N_in ( clk_1_wires[137] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1056 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1056 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_7__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1057 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__69_bottom_grid_pin_0_ ) , 
@@ -103317,7 +129554,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1068 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1069 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1070 ) , 
-    .clk_0_S_in ( clk_1_wires[136] ) ) ;
+    .clk_0_S_in ( clk_1_wires[136] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_7__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1071 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__70_bottom_grid_pin_0_ ) , 
@@ -103411,7 +129648,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1082 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1083 ) , 
     .clk_0_N_in ( clk_1_wires[144] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1084 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1084 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_7__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1085 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__71_bottom_grid_pin_0_ ) , 
@@ -103505,7 +129742,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1096 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1097 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1098 ) , 
-    .clk_0_S_in ( clk_1_wires[143] ) ) ;
+    .clk_0_S_in ( clk_1_wires[143] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_7__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1099 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__72_bottom_grid_pin_0_ ) , 
@@ -103599,7 +129836,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1110 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1111 ) , 
     .clk_0_N_in ( clk_1_wires[151] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1112 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1112 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_7__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1113 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__73_bottom_grid_pin_0_ ) , 
@@ -103693,7 +129930,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1124 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1125 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1126 ) , 
-    .clk_0_S_in ( clk_1_wires[150] ) ) ;
+    .clk_0_S_in ( clk_1_wires[150] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_7__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1127 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__74_bottom_grid_pin_0_ ) , 
@@ -103787,7 +130024,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1138 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1139 ) , 
     .clk_0_N_in ( clk_1_wires[158] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1140 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1140 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_7__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1141 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__75_bottom_grid_pin_0_ ) , 
@@ -103881,7 +130118,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1152 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1153 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1154 ) , 
-    .clk_0_S_in ( clk_1_wires[157] ) ) ;
+    .clk_0_S_in ( clk_1_wires[157] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_7__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1155 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__76_bottom_grid_pin_0_ ) , 
@@ -103975,7 +130212,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1166 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1167 ) , 
     .clk_0_N_in ( clk_1_wires[165] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1168 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1168 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_7__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1169 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__12__6_bottom_grid_pin_0_ ) , 
@@ -104070,7 +130307,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1180 ) , 
     .prog_clk_0_N_out ( prog_clk_0_wires[289] ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1181 ) , 
-    .clk_0_S_in ( clk_1_wires[164] ) ) ;
+    .clk_0_S_in ( clk_1_wires[164] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_8__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1182 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__77_bottom_grid_pin_0_ ) , 
@@ -104165,7 +130402,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1193 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1194 ) , 
     .clk_0_N_in ( clk_1_wires[132] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1195 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1195 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_8__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1196 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__78_bottom_grid_pin_0_ ) , 
@@ -104259,7 +130496,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1207 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1208 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1209 ) , 
-    .clk_0_S_in ( clk_1_wires[131] ) ) ;
+    .clk_0_S_in ( clk_1_wires[131] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_8__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1210 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__79_bottom_grid_pin_0_ ) , 
@@ -104353,7 +130590,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1221 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1222 ) , 
     .clk_0_N_in ( clk_1_wires[139] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1223 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1223 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_8__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1224 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__80_bottom_grid_pin_0_ ) , 
@@ -104447,7 +130684,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1235 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1236 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1237 ) , 
-    .clk_0_S_in ( clk_1_wires[138] ) ) ;
+    .clk_0_S_in ( clk_1_wires[138] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_8__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1238 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__81_bottom_grid_pin_0_ ) , 
@@ -104541,7 +130778,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1249 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1250 ) , 
     .clk_0_N_in ( clk_1_wires[146] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1251 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1251 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_8__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1252 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__82_bottom_grid_pin_0_ ) , 
@@ -104635,7 +130872,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1263 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1264 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1265 ) , 
-    .clk_0_S_in ( clk_1_wires[145] ) ) ;
+    .clk_0_S_in ( clk_1_wires[145] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_8__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1266 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__83_bottom_grid_pin_0_ ) , 
@@ -104729,7 +130966,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1277 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1278 ) , 
     .clk_0_N_in ( clk_1_wires[153] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1279 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1279 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_8__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1280 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__84_bottom_grid_pin_0_ ) , 
@@ -104823,7 +131060,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1291 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1292 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1293 ) , 
-    .clk_0_S_in ( clk_1_wires[152] ) ) ;
+    .clk_0_S_in ( clk_1_wires[152] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_8__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1294 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__85_bottom_grid_pin_0_ ) , 
@@ -104917,7 +131154,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1305 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1306 ) , 
     .clk_0_N_in ( clk_1_wires[160] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1307 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1307 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_8__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1308 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__86_bottom_grid_pin_0_ ) , 
@@ -105011,7 +131248,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1319 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1320 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1321 ) , 
-    .clk_0_S_in ( clk_1_wires[159] ) ) ;
+    .clk_0_S_in ( clk_1_wires[159] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_8__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1322 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__87_bottom_grid_pin_0_ ) , 
@@ -105105,7 +131342,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1333 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1334 ) , 
     .clk_0_N_in ( clk_1_wires[167] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1335 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1335 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_8__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1336 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__12__7_bottom_grid_pin_0_ ) , 
@@ -105200,7 +131437,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1347 ) , 
     .prog_clk_0_N_out ( prog_clk_0_wires[327] ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1348 ) , 
-    .clk_0_S_in ( clk_1_wires[166] ) ) ;
+    .clk_0_S_in ( clk_1_wires[166] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_9__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1349 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__88_bottom_grid_pin_0_ ) , 
@@ -105295,7 +131532,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1360 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1361 ) , 
     .clk_0_N_in ( clk_1_wires[172] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1362 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1362 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_9__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1363 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__89_bottom_grid_pin_0_ ) , 
@@ -105389,7 +131626,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1374 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1375 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1376 ) , 
-    .clk_0_S_in ( clk_1_wires[171] ) ) ;
+    .clk_0_S_in ( clk_1_wires[171] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_9__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1377 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__90_bottom_grid_pin_0_ ) , 
@@ -105483,7 +131720,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1388 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1389 ) , 
     .clk_0_N_in ( clk_1_wires[179] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1390 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1390 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_9__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1391 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__91_bottom_grid_pin_0_ ) , 
@@ -105577,7 +131814,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1402 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1403 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1404 ) , 
-    .clk_0_S_in ( clk_1_wires[178] ) ) ;
+    .clk_0_S_in ( clk_1_wires[178] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_9__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1405 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__92_bottom_grid_pin_0_ ) , 
@@ -105671,7 +131908,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1416 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1417 ) , 
     .clk_0_N_in ( clk_1_wires[186] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1418 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1418 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_9__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1419 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__93_bottom_grid_pin_0_ ) , 
@@ -105765,7 +132002,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1430 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1431 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1432 ) , 
-    .clk_0_S_in ( clk_1_wires[185] ) ) ;
+    .clk_0_S_in ( clk_1_wires[185] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_9__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1433 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__94_bottom_grid_pin_0_ ) , 
@@ -105859,7 +132096,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1444 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1445 ) , 
     .clk_0_N_in ( clk_1_wires[193] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1446 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1446 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_9__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1447 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__95_bottom_grid_pin_0_ ) , 
@@ -105953,7 +132190,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1458 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1459 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1460 ) , 
-    .clk_0_S_in ( clk_1_wires[192] ) ) ;
+    .clk_0_S_in ( clk_1_wires[192] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_9__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1461 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__96_bottom_grid_pin_0_ ) , 
@@ -106047,7 +132284,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1472 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1473 ) , 
     .clk_0_N_in ( clk_1_wires[200] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1474 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1474 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_9__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1475 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__97_bottom_grid_pin_0_ ) , 
@@ -106141,7 +132378,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1486 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1487 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1488 ) , 
-    .clk_0_S_in ( clk_1_wires[199] ) ) ;
+    .clk_0_S_in ( clk_1_wires[199] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_9__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1489 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__98_bottom_grid_pin_0_ ) , 
@@ -106235,7 +132472,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1500 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1501 ) , 
     .clk_0_N_in ( clk_1_wires[207] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1502 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1502 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_9__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1503 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__12__8_bottom_grid_pin_0_ ) , 
@@ -106330,7 +132567,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1514 ) , 
     .prog_clk_0_N_out ( prog_clk_0_wires[365] ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1515 ) , 
-    .clk_0_S_in ( clk_1_wires[206] ) ) ;
+    .clk_0_S_in ( clk_1_wires[206] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_10__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1516 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__99_bottom_grid_pin_0_ ) , 
@@ -106425,7 +132662,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1527 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1528 ) , 
     .clk_0_N_in ( clk_1_wires[174] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1529 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1529 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_10__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1530 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__100_bottom_grid_pin_0_ ) , 
@@ -106519,7 +132756,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1541 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1542 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1543 ) , 
-    .clk_0_S_in ( clk_1_wires[173] ) ) ;
+    .clk_0_S_in ( clk_1_wires[173] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_10__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1544 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__101_bottom_grid_pin_0_ ) , 
@@ -106613,7 +132850,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1555 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1556 ) , 
     .clk_0_N_in ( clk_1_wires[181] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1557 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1557 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_10__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1558 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__102_bottom_grid_pin_0_ ) , 
@@ -106707,7 +132944,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1569 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1570 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1571 ) , 
-    .clk_0_S_in ( clk_1_wires[180] ) ) ;
+    .clk_0_S_in ( clk_1_wires[180] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_10__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1572 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__103_bottom_grid_pin_0_ ) , 
@@ -106801,7 +133038,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1583 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1584 ) , 
     .clk_0_N_in ( clk_1_wires[188] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1585 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1585 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_10__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1586 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__104_bottom_grid_pin_0_ ) , 
@@ -106895,7 +133132,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1597 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1598 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1599 ) , 
-    .clk_0_S_in ( clk_1_wires[187] ) ) ;
+    .clk_0_S_in ( clk_1_wires[187] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_10__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1600 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__105_bottom_grid_pin_0_ ) , 
@@ -106989,7 +133226,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1611 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1612 ) , 
     .clk_0_N_in ( clk_1_wires[195] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1613 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1613 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_10__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1614 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__106_bottom_grid_pin_0_ ) , 
@@ -107083,7 +133320,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1625 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1626 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1627 ) , 
-    .clk_0_S_in ( clk_1_wires[194] ) ) ;
+    .clk_0_S_in ( clk_1_wires[194] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_10__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1628 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__107_bottom_grid_pin_0_ ) , 
@@ -107177,7 +133414,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1639 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1640 ) , 
     .clk_0_N_in ( clk_1_wires[202] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1641 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1641 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_10__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1642 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__108_bottom_grid_pin_0_ ) , 
@@ -107271,7 +133508,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1653 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1654 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1655 ) , 
-    .clk_0_S_in ( clk_1_wires[201] ) ) ;
+    .clk_0_S_in ( clk_1_wires[201] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_10__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1656 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__109_bottom_grid_pin_0_ ) , 
@@ -107365,7 +133602,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1667 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1668 ) , 
     .clk_0_N_in ( clk_1_wires[209] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1669 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1669 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_10__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1670 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__12__9_bottom_grid_pin_0_ ) , 
@@ -107460,7 +133697,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1681 ) , 
     .prog_clk_0_N_out ( prog_clk_0_wires[403] ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1682 ) , 
-    .clk_0_S_in ( clk_1_wires[208] ) ) ;
+    .clk_0_S_in ( clk_1_wires[208] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_11__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1683 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__110_bottom_grid_pin_0_ ) , 
@@ -107555,7 +133792,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1694 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1695 ) , 
     .clk_0_N_in ( clk_1_wires[214] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1696 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1696 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_11__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1697 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__111_bottom_grid_pin_0_ ) , 
@@ -107649,7 +133886,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1708 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1709 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1710 ) , 
-    .clk_0_S_in ( clk_1_wires[213] ) ) ;
+    .clk_0_S_in ( clk_1_wires[213] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_11__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1711 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__112_bottom_grid_pin_0_ ) , 
@@ -107743,7 +133980,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1722 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1723 ) , 
     .clk_0_N_in ( clk_1_wires[221] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1724 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1724 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_11__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1725 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__113_bottom_grid_pin_0_ ) , 
@@ -107837,7 +134074,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1736 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1737 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1738 ) , 
-    .clk_0_S_in ( clk_1_wires[220] ) ) ;
+    .clk_0_S_in ( clk_1_wires[220] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_11__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1739 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__114_bottom_grid_pin_0_ ) , 
@@ -107931,7 +134168,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1750 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1751 ) , 
     .clk_0_N_in ( clk_1_wires[228] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1752 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1752 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_11__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1753 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__115_bottom_grid_pin_0_ ) , 
@@ -108025,7 +134262,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1764 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1765 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1766 ) , 
-    .clk_0_S_in ( clk_1_wires[227] ) ) ;
+    .clk_0_S_in ( clk_1_wires[227] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_11__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1767 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__116_bottom_grid_pin_0_ ) , 
@@ -108119,7 +134356,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1778 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1779 ) , 
     .clk_0_N_in ( clk_1_wires[235] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1780 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1780 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_11__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1781 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__117_bottom_grid_pin_0_ ) , 
@@ -108213,7 +134450,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1792 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1793 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1794 ) , 
-    .clk_0_S_in ( clk_1_wires[234] ) ) ;
+    .clk_0_S_in ( clk_1_wires[234] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_11__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1795 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__118_bottom_grid_pin_0_ ) , 
@@ -108307,7 +134544,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1806 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1807 ) , 
     .clk_0_N_in ( clk_1_wires[242] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1808 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1808 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_11__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1809 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__119_bottom_grid_pin_0_ ) , 
@@ -108401,7 +134638,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1820 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1821 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1822 ) , 
-    .clk_0_S_in ( clk_1_wires[241] ) ) ;
+    .clk_0_S_in ( clk_1_wires[241] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_11__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1823 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__120_bottom_grid_pin_0_ ) , 
@@ -108495,7 +134732,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1834 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1835 ) , 
     .clk_0_N_in ( clk_1_wires[249] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1836 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1836 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_11__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1837 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__12__10_bottom_grid_pin_0_ ) , 
@@ -108590,7 +134827,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1848 ) , 
     .prog_clk_0_N_out ( prog_clk_0_wires[441] ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1849 ) , 
-    .clk_0_S_in ( clk_1_wires[248] ) ) ;
+    .clk_0_S_in ( clk_1_wires[248] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_12__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1850 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__121_bottom_grid_pin_0_ ) , 
@@ -108686,7 +134923,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1863 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1864 ) , 
     .clk_0_N_in ( clk_1_wires[216] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1865 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1865 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_12__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1866 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__122_bottom_grid_pin_0_ ) , 
@@ -108781,7 +135018,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1879 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1880 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1881 ) , 
-    .clk_0_S_in ( clk_1_wires[215] ) ) ;
+    .clk_0_S_in ( clk_1_wires[215] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_12__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1882 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__123_bottom_grid_pin_0_ ) , 
@@ -108876,7 +135113,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1895 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1896 ) , 
     .clk_0_N_in ( clk_1_wires[223] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1897 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1897 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_12__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1898 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__124_bottom_grid_pin_0_ ) , 
@@ -108971,7 +135208,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1911 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1912 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1913 ) , 
-    .clk_0_S_in ( clk_1_wires[222] ) ) ;
+    .clk_0_S_in ( clk_1_wires[222] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_12__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1914 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__125_bottom_grid_pin_0_ ) , 
@@ -109066,7 +135303,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1927 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1928 ) , 
     .clk_0_N_in ( clk_1_wires[230] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1929 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1929 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_12__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1930 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__126_bottom_grid_pin_0_ ) , 
@@ -109161,7 +135398,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1943 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1944 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1945 ) , 
-    .clk_0_S_in ( clk_1_wires[229] ) ) ;
+    .clk_0_S_in ( clk_1_wires[229] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_12__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1946 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__127_bottom_grid_pin_0_ ) , 
@@ -109256,7 +135493,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1959 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1960 ) , 
     .clk_0_N_in ( clk_1_wires[237] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1961 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1961 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_12__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1962 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__128_bottom_grid_pin_0_ ) , 
@@ -109351,7 +135588,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1975 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1976 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1977 ) , 
-    .clk_0_S_in ( clk_1_wires[236] ) ) ;
+    .clk_0_S_in ( clk_1_wires[236] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_12__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1978 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__129_bottom_grid_pin_0_ ) , 
@@ -109446,7 +135683,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1991 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1992 ) , 
     .clk_0_N_in ( clk_1_wires[244] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1993 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1993 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_12__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_1994 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__130_bottom_grid_pin_0_ ) , 
@@ -109541,7 +135778,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_2007 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_2008 ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_2009 ) , 
-    .clk_0_S_in ( clk_1_wires[243] ) ) ;
+    .clk_0_S_in ( clk_1_wires[243] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_12__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2010 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__1__131_bottom_grid_pin_0_ ) , 
@@ -109636,7 +135873,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_2023 ) , 
     .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_2024 ) , 
     .clk_0_N_in ( clk_1_wires[251] ) , 
-    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_2025 ) ) ;
+    .clk_0_S_in ( SYNOPSYS_UNCONNECTED_2025 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 grid_clb grid_clb_12__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2026 } ) ,
     .top_width_0_height_0__pin_0_ ( cbx_1__12__11_bottom_grid_pin_0_ ) , 
@@ -109732,7 +135969,7 @@
     .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_2039 ) , 
     .prog_clk_0_N_out ( prog_clk_0_wires[479] ) , 
     .clk_0_N_in ( SYNOPSYS_UNCONNECTED_2040 ) , 
-    .clk_0_S_in ( clk_1_wires[250] ) ) ;
+    .clk_0_S_in ( clk_1_wires[250] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__0_ sb_0__0_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2041 } ) ,
     .chany_top_in ( cby_0__1__0_chany_bottom_out ) , 
@@ -109751,7 +135988,7 @@
     .chany_top_out ( sb_0__0__0_chany_top_out ) , 
     .chanx_right_out ( sb_0__0__0_chanx_right_out ) , 
     .ccff_tail ( ccff_tail ) , .pReset_E_in ( pResetWires[25] ) , 
-    .prog_clk_0_E_in ( prog_clk_0_wires[5] ) ) ;
+    .prog_clk_0_E_in ( prog_clk_0_wires[5] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1_ sb_0__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2042 } ) ,
     .chany_top_in ( cby_0__1__1_chany_bottom_out ) , 
@@ -109773,7 +136010,7 @@
     .chany_bottom_out ( sb_0__1__0_chany_bottom_out ) , 
     .ccff_tail ( sb_0__1__0_ccff_tail ) , .pReset_E_in ( pResetWires[61] ) , 
     .pReset_S_out ( pResetWires[64] ) , 
-    .prog_clk_0_E_in ( prog_clk_0_wires[4] ) ) ;
+    .prog_clk_0_E_in ( prog_clk_0_wires[4] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1_ sb_0__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2043 } ) ,
     .chany_top_in ( cby_0__1__2_chany_bottom_out ) , 
@@ -109795,7 +136032,7 @@
     .chany_bottom_out ( sb_0__1__1_chany_bottom_out ) , 
     .ccff_tail ( sb_0__1__1_ccff_tail ) , .pReset_E_in ( pResetWires[110] ) , 
     .pReset_S_out ( pResetWires[113] ) , 
-    .prog_clk_0_E_in ( prog_clk_0_wires[10] ) ) ;
+    .prog_clk_0_E_in ( prog_clk_0_wires[10] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1_ sb_0__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2044 } ) ,
     .chany_top_in ( cby_0__1__3_chany_bottom_out ) , 
@@ -109817,7 +136054,7 @@
     .chany_bottom_out ( sb_0__1__2_chany_bottom_out ) , 
     .ccff_tail ( sb_0__1__2_ccff_tail ) , .pReset_E_in ( pResetWires[159] ) , 
     .pReset_S_out ( pResetWires[162] ) , 
-    .prog_clk_0_E_in ( prog_clk_0_wires[15] ) ) ;
+    .prog_clk_0_E_in ( prog_clk_0_wires[15] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1_ sb_0__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2045 } ) ,
     .chany_top_in ( cby_0__1__4_chany_bottom_out ) , 
@@ -109839,7 +136076,7 @@
     .chany_bottom_out ( sb_0__1__3_chany_bottom_out ) , 
     .ccff_tail ( sb_0__1__3_ccff_tail ) , .pReset_E_in ( pResetWires[208] ) , 
     .pReset_S_out ( pResetWires[211] ) , 
-    .prog_clk_0_E_in ( prog_clk_0_wires[20] ) ) ;
+    .prog_clk_0_E_in ( prog_clk_0_wires[20] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1_ sb_0__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2046 } ) ,
     .chany_top_in ( cby_0__1__5_chany_bottom_out ) , 
@@ -109861,7 +136098,7 @@
     .chany_bottom_out ( sb_0__1__4_chany_bottom_out ) , 
     .ccff_tail ( sb_0__1__4_ccff_tail ) , .pReset_E_in ( pResetWires[257] ) , 
     .pReset_S_out ( pResetWires[260] ) , 
-    .prog_clk_0_E_in ( prog_clk_0_wires[25] ) ) ;
+    .prog_clk_0_E_in ( prog_clk_0_wires[25] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1_ sb_0__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2047 } ) ,
     .chany_top_in ( cby_0__1__6_chany_bottom_out ) , 
@@ -109883,7 +136120,7 @@
     .chany_bottom_out ( sb_0__1__5_chany_bottom_out ) , 
     .ccff_tail ( sb_0__1__5_ccff_tail ) , .pReset_E_in ( pResetWires[306] ) , 
     .pReset_S_out ( pResetWires[309] ) , 
-    .prog_clk_0_E_in ( prog_clk_0_wires[30] ) ) ;
+    .prog_clk_0_E_in ( prog_clk_0_wires[30] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1_ sb_0__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2048 } ) ,
     .chany_top_in ( cby_0__1__7_chany_bottom_out ) , 
@@ -109905,7 +136142,7 @@
     .chany_bottom_out ( sb_0__1__6_chany_bottom_out ) , 
     .ccff_tail ( sb_0__1__6_ccff_tail ) , .pReset_E_in ( pResetWires[355] ) , 
     .pReset_S_out ( pResetWires[358] ) , 
-    .prog_clk_0_E_in ( prog_clk_0_wires[35] ) ) ;
+    .prog_clk_0_E_in ( prog_clk_0_wires[35] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1_ sb_0__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2049 } ) ,
     .chany_top_in ( cby_0__1__8_chany_bottom_out ) , 
@@ -109927,7 +136164,7 @@
     .chany_bottom_out ( sb_0__1__7_chany_bottom_out ) , 
     .ccff_tail ( sb_0__1__7_ccff_tail ) , .pReset_E_in ( pResetWires[404] ) , 
     .pReset_S_out ( pResetWires[407] ) , 
-    .prog_clk_0_E_in ( prog_clk_0_wires[40] ) ) ;
+    .prog_clk_0_E_in ( prog_clk_0_wires[40] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1_ sb_0__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2050 } ) ,
     .chany_top_in ( cby_0__1__9_chany_bottom_out ) , 
@@ -109949,7 +136186,7 @@
     .chany_bottom_out ( sb_0__1__8_chany_bottom_out ) , 
     .ccff_tail ( sb_0__1__8_ccff_tail ) , .pReset_E_in ( pResetWires[453] ) , 
     .pReset_S_out ( pResetWires[456] ) , 
-    .prog_clk_0_E_in ( prog_clk_0_wires[45] ) ) ;
+    .prog_clk_0_E_in ( prog_clk_0_wires[45] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1_ sb_0__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2051 } ) ,
     .chany_top_in ( cby_0__1__10_chany_bottom_out ) , 
@@ -109971,7 +136208,7 @@
     .chany_bottom_out ( sb_0__1__9_chany_bottom_out ) , 
     .ccff_tail ( sb_0__1__9_ccff_tail ) , .pReset_E_in ( pResetWires[502] ) , 
     .pReset_S_out ( pResetWires[505] ) , 
-    .prog_clk_0_E_in ( prog_clk_0_wires[50] ) ) ;
+    .prog_clk_0_E_in ( prog_clk_0_wires[50] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__1_ sb_0__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2052 } ) ,
     .chany_top_in ( cby_0__1__11_chany_bottom_out ) , 
@@ -109993,7 +136230,7 @@
     .chany_bottom_out ( sb_0__1__10_chany_bottom_out ) , 
     .ccff_tail ( sb_0__1__10_ccff_tail ) , .pReset_E_in ( pResetWires[551] ) , 
     .pReset_S_out ( pResetWires[554] ) , 
-    .prog_clk_0_E_in ( prog_clk_0_wires[55] ) ) ;
+    .prog_clk_0_E_in ( prog_clk_0_wires[55] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_0__2_ sb_0__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2053 } ) ,
     .chanx_right_in ( cbx_1__12__0_chanx_left_out ) , 
@@ -110014,7 +136251,7 @@
     .ccff_tail ( sb_0__12__0_ccff_tail ) , .SC_IN_TOP ( sc_head ) , 
     .SC_OUT_BOT ( scff_Wires[0] ) , .pReset_E_in ( pResetWires[600] ) , 
     .pReset_S_out ( pResetWires[603] ) , 
-    .prog_clk_0_E_in ( prog_clk_0_wires[62] ) ) ;
+    .prog_clk_0_E_in ( prog_clk_0_wires[62] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0_ sb_1__0_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2054 } ) ,
     .chany_top_in ( cby_1__1__0_chany_bottom_out ) , 
@@ -110061,7 +136298,7 @@
     .Reset_N_out ( SYNOPSYS_UNCONNECTED_2059 ) , 
     .prog_clk_0_N_in ( prog_clk_0_wires[2] ) , .prog_clk_3_S_in ( p913 ) , 
     .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2060 ) , .clk_3_S_in ( p913 ) , 
-    .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2061 ) ) ;
+    .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2061 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0_ sb_2__0_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2062 } ) ,
     .chany_top_in ( cby_1__1__12_chany_bottom_out ) , 
@@ -110108,7 +136345,7 @@
     .Reset_N_out ( SYNOPSYS_UNCONNECTED_2068 ) , 
     .prog_clk_0_N_in ( prog_clk_0_wires[65] ) , .prog_clk_3_S_in ( p945 ) , 
     .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2069 ) , .clk_3_S_in ( p945 ) , 
-    .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2070 ) ) ;
+    .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2070 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0_ sb_3__0_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2071 } ) ,
     .chany_top_in ( cby_1__1__24_chany_bottom_out ) , 
@@ -110155,7 +136392,7 @@
     .Reset_N_out ( SYNOPSYS_UNCONNECTED_2076 ) , 
     .prog_clk_0_N_in ( prog_clk_0_wires[103] ) , .prog_clk_3_S_in ( p1461 ) , 
     .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2077 ) , .clk_3_S_in ( p1498 ) , 
-    .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2078 ) ) ;
+    .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2078 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0_ sb_4__0_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2079 } ) ,
     .chany_top_in ( cby_1__1__36_chany_bottom_out ) , 
@@ -110202,7 +136439,7 @@
     .Reset_N_out ( SYNOPSYS_UNCONNECTED_2085 ) , 
     .prog_clk_0_N_in ( prog_clk_0_wires[141] ) , .prog_clk_3_S_in ( p1473 ) , 
     .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2086 ) , .clk_3_S_in ( p1473 ) , 
-    .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2087 ) ) ;
+    .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2087 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0_ sb_5__0_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2088 } ) ,
     .chany_top_in ( cby_1__1__48_chany_bottom_out ) , 
@@ -110249,7 +136486,7 @@
     .Reset_N_out ( SYNOPSYS_UNCONNECTED_2093 ) , 
     .prog_clk_0_N_in ( prog_clk_0_wires[179] ) , .prog_clk_3_S_in ( p1205 ) , 
     .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2094 ) , .clk_3_S_in ( p1205 ) , 
-    .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2095 ) ) ;
+    .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2095 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0_ sb_6__0_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2096 } ) ,
     .chany_top_in ( cby_1__1__60_chany_bottom_out ) , 
@@ -110296,7 +136533,7 @@
     .prog_clk_0_N_in ( prog_clk_0_wires[217] ) , 
     .prog_clk_3_S_in ( prog_clk[0] ) , 
     .prog_clk_3_N_out ( prog_clk_3_wires[90] ) , .clk_3_S_in ( clk[0] ) , 
-    .clk_3_N_out ( clk_3_wires[90] ) ) ;
+    .clk_3_N_out ( clk_3_wires[90] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0_ sb_7__0_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2100 } ) ,
     .chany_top_in ( cby_1__1__72_chany_bottom_out ) , 
@@ -110343,7 +136580,7 @@
     .Reset_N_out ( SYNOPSYS_UNCONNECTED_2105 ) , 
     .prog_clk_0_N_in ( prog_clk_0_wires[255] ) , .prog_clk_3_S_in ( p340 ) , 
     .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2106 ) , .clk_3_S_in ( p340 ) , 
-    .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2107 ) ) ;
+    .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2107 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0_ sb_8__0_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2108 } ) ,
     .chany_top_in ( cby_1__1__84_chany_bottom_out ) , 
@@ -110390,7 +136627,7 @@
     .Reset_N_out ( SYNOPSYS_UNCONNECTED_2114 ) , 
     .prog_clk_0_N_in ( prog_clk_0_wires[293] ) , .prog_clk_3_S_in ( p956 ) , 
     .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2115 ) , .clk_3_S_in ( p956 ) , 
-    .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2116 ) ) ;
+    .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2116 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0_ sb_9__0_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2117 } ) ,
     .chany_top_in ( cby_1__1__96_chany_bottom_out ) , 
@@ -110437,7 +136674,7 @@
     .Reset_N_out ( SYNOPSYS_UNCONNECTED_2122 ) , 
     .prog_clk_0_N_in ( prog_clk_0_wires[331] ) , .prog_clk_3_S_in ( p1216 ) , 
     .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2123 ) , .clk_3_S_in ( p1216 ) , 
-    .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2124 ) ) ;
+    .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2124 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0_ sb_10__0_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2125 } ) ,
     .chany_top_in ( cby_1__1__108_chany_bottom_out ) , 
@@ -110484,7 +136721,7 @@
     .Reset_N_out ( SYNOPSYS_UNCONNECTED_2131 ) , 
     .prog_clk_0_N_in ( prog_clk_0_wires[369] ) , .prog_clk_3_S_in ( p657 ) , 
     .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2132 ) , .clk_3_S_in ( p657 ) , 
-    .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2133 ) ) ;
+    .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2133 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__0_ sb_11__0_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2134 } ) ,
     .chany_top_in ( cby_1__1__120_chany_bottom_out ) , 
@@ -110531,7 +136768,7 @@
     .Reset_N_out ( SYNOPSYS_UNCONNECTED_2139 ) , 
     .prog_clk_0_N_in ( prog_clk_0_wires[407] ) , .prog_clk_3_S_in ( p1151 ) , 
     .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2140 ) , .clk_3_S_in ( p1253 ) , 
-    .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2141 ) ) ;
+    .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2141 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_1__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2142 } ) ,
     .chany_top_in ( cby_1__1__1_chany_bottom_out ) , 
@@ -110612,7 +136849,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2162 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2163 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2164 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2165 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2165 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_1__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2166 } ) ,
     .chany_top_in ( cby_1__1__2_chany_bottom_out ) , 
@@ -110696,7 +136933,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2192 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2193 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2194 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2195 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2195 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_1__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2196 } ) ,
     .chany_top_in ( cby_1__1__3_chany_bottom_out ) , 
@@ -110777,7 +137014,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2216 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2217 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2218 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2219 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2219 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_1__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2220 } ) ,
     .chany_top_in ( cby_1__1__4_chany_bottom_out ) , 
@@ -110860,7 +137097,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2244 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2245 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2246 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2247 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2247 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_1__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2248 } ) ,
     .chany_top_in ( cby_1__1__5_chany_bottom_out ) , 
@@ -110941,7 +137178,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2268 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2269 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2270 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2271 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2271 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_1__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2272 } ) ,
     .chany_top_in ( cby_1__1__6_chany_bottom_out ) , 
@@ -111020,7 +137257,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2294 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2295 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2296 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2297 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2297 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_1__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2298 } ) ,
     .chany_top_in ( cby_1__1__7_chany_bottom_out ) , 
@@ -111101,7 +137338,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2318 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2319 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2320 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2321 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2321 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_1__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2322 } ) ,
     .chany_top_in ( cby_1__1__8_chany_bottom_out ) , 
@@ -111184,7 +137421,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2346 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2347 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2348 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2349 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2349 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_1__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2350 } ) ,
     .chany_top_in ( cby_1__1__9_chany_bottom_out ) , 
@@ -111265,7 +137502,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2370 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2371 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2372 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2373 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2373 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_1__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2374 } ) ,
     .chany_top_in ( cby_1__1__10_chany_bottom_out ) , 
@@ -111349,7 +137586,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2400 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2401 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2402 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2403 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2403 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_1__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2404 } ) ,
     .chany_top_in ( cby_1__1__11_chany_bottom_out ) , 
@@ -111430,7 +137667,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2424 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2425 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2426 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2427 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2427 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_2__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2428 } ) ,
     .chany_top_in ( cby_1__1__13_chany_bottom_out ) , 
@@ -111509,7 +137746,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2450 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2451 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2452 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2453 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2453 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_2__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2454 } ) ,
     .chany_top_in ( cby_1__1__14_chany_bottom_out ) , 
@@ -111593,7 +137830,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2480 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2481 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2482 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2483 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2483 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_2__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2484 } ) ,
     .chany_top_in ( cby_1__1__15_chany_bottom_out ) , 
@@ -111677,7 +137914,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2511 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2512 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2513 ) , 
-    .clk_3_S_out ( clk_3_wires[68] ) ) ;
+    .clk_3_S_out ( clk_3_wires[68] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_2__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2514 } ) ,
     .chany_top_in ( cby_1__1__16_chany_bottom_out ) , 
@@ -111766,7 +138003,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2545 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2546 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2547 ) , 
-    .clk_3_S_out ( clk_3_wires[64] ) ) ;
+    .clk_3_S_out ( clk_3_wires[64] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_2__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2548 } ) ,
     .chany_top_in ( cby_1__1__17_chany_bottom_out ) , 
@@ -111850,7 +138087,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2575 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2576 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2577 ) , 
-    .clk_3_S_out ( clk_3_wires[58] ) ) ;
+    .clk_3_S_out ( clk_3_wires[58] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_2__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2578 } ) ,
     .chany_top_in ( cby_1__1__18_chany_bottom_out ) , 
@@ -111933,7 +138170,8 @@
     .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2603 ) , 
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2604 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2605 ) , 
-    .clk_3_N_out ( clk_3_wires[52] ) , .clk_3_S_out ( clk_3_wires[54] ) ) ;
+    .clk_3_N_out ( clk_3_wires[52] ) , .clk_3_S_out ( clk_3_wires[54] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_2__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2606 } ) ,
     .chany_top_in ( cby_1__1__19_chany_bottom_out ) , 
@@ -112017,7 +138255,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2633 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2634 ) , 
     .clk_3_N_out ( clk_3_wires[56] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2635 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2635 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_2__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2636 } ) ,
     .chany_top_in ( cby_1__1__20_chany_bottom_out ) , 
@@ -112106,7 +138344,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2667 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2668 ) , 
     .clk_3_N_out ( clk_3_wires[62] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2669 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2669 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_2__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2670 } ) ,
     .chany_top_in ( cby_1__1__21_chany_bottom_out ) , 
@@ -112190,7 +138428,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2697 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2698 ) , 
     .clk_3_N_out ( clk_3_wires[66] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2699 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2699 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_2__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2700 } ) ,
     .chany_top_in ( cby_1__1__22_chany_bottom_out ) , 
@@ -112274,7 +138512,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2726 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2727 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2728 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2729 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2729 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_2__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2730 } ) ,
     .chany_top_in ( cby_1__1__23_chany_bottom_out ) , 
@@ -112353,7 +138591,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2752 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2753 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2754 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2755 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2755 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_3__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2756 } ) ,
     .chany_top_in ( cby_1__1__25_chany_bottom_out ) , 
@@ -112434,7 +138672,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2776 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2777 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2778 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2779 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2779 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_3__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2780 } ) ,
     .chany_top_in ( cby_1__1__26_chany_bottom_out ) , 
@@ -112518,7 +138756,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2806 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2807 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2808 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2809 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2809 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_3__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2810 } ) ,
     .chany_top_in ( cby_1__1__27_chany_bottom_out ) , 
@@ -112599,7 +138837,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2830 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2831 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2832 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2833 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2833 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_3__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2834 } ) ,
     .chany_top_in ( cby_1__1__28_chany_bottom_out ) , 
@@ -112682,7 +138920,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2858 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2859 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2860 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2861 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2861 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_3__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2862 } ) ,
     .chany_top_in ( cby_1__1__29_chany_bottom_out ) , 
@@ -112763,7 +139001,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2882 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2883 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2884 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2885 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2885 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_3__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2886 } ) ,
     .chany_top_in ( cby_1__1__30_chany_bottom_out ) , 
@@ -112847,7 +139085,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2913 ) , 
     .clk_3_W_out ( clk_3_wires[50] ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2914 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2915 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2915 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_3__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2916 } ) ,
     .chany_top_in ( cby_1__1__31_chany_bottom_out ) , 
@@ -112928,7 +139166,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2936 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2937 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2938 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2939 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2939 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_3__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2940 } ) ,
     .chany_top_in ( cby_1__1__32_chany_bottom_out ) , 
@@ -113011,7 +139249,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2964 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2965 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2966 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2967 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2967 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_3__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2968 } ) ,
     .chany_top_in ( cby_1__1__33_chany_bottom_out ) , 
@@ -113092,7 +139330,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2988 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2989 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2990 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2991 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2991 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_3__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_2992 } ) ,
     .chany_top_in ( cby_1__1__34_chany_bottom_out ) , 
@@ -113176,7 +139414,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3018 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3019 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3020 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3021 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3021 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_3__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3022 } ) ,
     .chany_top_in ( cby_1__1__35_chany_bottom_out ) , 
@@ -113257,7 +139495,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3042 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3043 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3044 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3045 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3045 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_4__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3046 } ) ,
     .chany_top_in ( cby_1__1__37_chany_bottom_out ) , 
@@ -113336,7 +139574,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3068 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3069 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3070 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3071 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3071 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_4__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3072 } ) ,
     .chany_top_in ( cby_1__1__38_chany_bottom_out ) , 
@@ -113420,7 +139658,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3096 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3097 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3098 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3099 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3099 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_4__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3100 } ) ,
     .chany_top_in ( cby_1__1__39_chany_bottom_out ) , 
@@ -113504,7 +139742,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3127 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3128 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3129 ) , 
-    .clk_3_S_out ( clk_3_wires[24] ) ) ;
+    .clk_3_S_out ( clk_3_wires[24] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_4__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3130 } ) ,
     .chany_top_in ( cby_1__1__40_chany_bottom_out ) , 
@@ -113593,7 +139831,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3159 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3160 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3161 ) , 
-    .clk_3_S_out ( clk_3_wires[20] ) ) ;
+    .clk_3_S_out ( clk_3_wires[20] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_4__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3162 } ) ,
     .chany_top_in ( cby_1__1__41_chany_bottom_out ) , 
@@ -113677,7 +139915,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3189 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3190 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3191 ) , 
-    .clk_3_S_out ( clk_3_wires[14] ) ) ;
+    .clk_3_S_out ( clk_3_wires[14] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_4__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3192 } ) ,
     .chany_top_in ( cby_1__1__42_chany_bottom_out ) , 
@@ -113760,7 +139998,7 @@
     .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3216 ) , 
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3217 ) , 
     .clk_3_W_out ( clk_3_wires[46] ) , .clk_3_N_out ( clk_3_wires[8] ) , 
-    .clk_3_S_out ( clk_3_wires[10] ) ) ;
+    .clk_3_S_out ( clk_3_wires[10] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_4__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3218 } ) ,
     .chany_top_in ( cby_1__1__43_chany_bottom_out ) , 
@@ -113844,7 +140082,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3245 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3246 ) , 
     .clk_3_N_out ( clk_3_wires[12] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3247 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3247 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_4__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3248 } ) ,
     .chany_top_in ( cby_1__1__44_chany_bottom_out ) , 
@@ -113933,7 +140171,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3277 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3278 ) , 
     .clk_3_N_out ( clk_3_wires[18] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3279 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3279 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_4__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3280 } ) ,
     .chany_top_in ( cby_1__1__45_chany_bottom_out ) , 
@@ -114017,7 +140255,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3307 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3308 ) , 
     .clk_3_N_out ( clk_3_wires[22] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3309 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3309 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_4__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3310 } ) ,
     .chany_top_in ( cby_1__1__46_chany_bottom_out ) , 
@@ -114101,7 +140339,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3334 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3335 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3336 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3337 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3337 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_4__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3338 } ) ,
     .chany_top_in ( cby_1__1__47_chany_bottom_out ) , 
@@ -114180,7 +140418,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3360 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3361 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3362 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3363 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3363 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_5__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3364 } ) ,
     .chany_top_in ( cby_1__1__49_chany_bottom_out ) , 
@@ -114261,7 +140499,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3384 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3385 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3386 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3387 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3387 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_5__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3388 } ) ,
     .chany_top_in ( cby_1__1__50_chany_bottom_out ) , 
@@ -114345,7 +140583,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3414 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3415 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3416 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3417 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3417 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_5__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3418 } ) ,
     .chany_top_in ( cby_1__1__51_chany_bottom_out ) , 
@@ -114426,7 +140664,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3438 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3439 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3440 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3441 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3441 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_5__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3442 } ) ,
     .chany_top_in ( cby_1__1__52_chany_bottom_out ) , 
@@ -114509,7 +140747,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3466 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3467 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3468 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3469 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3469 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_5__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3470 } ) ,
     .chany_top_in ( cby_1__1__53_chany_bottom_out ) , 
@@ -114590,7 +140828,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3490 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3491 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3492 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3493 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3493 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_5__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3494 } ) ,
     .chany_top_in ( cby_1__1__54_chany_bottom_out ) , 
@@ -114674,7 +140912,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3521 ) , 
     .clk_3_W_out ( clk_3_wires[6] ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3522 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3523 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3523 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_5__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3524 } ) ,
     .chany_top_in ( cby_1__1__55_chany_bottom_out ) , 
@@ -114755,7 +140993,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3544 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3545 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3546 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3547 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3547 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_5__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3548 } ) ,
     .chany_top_in ( cby_1__1__56_chany_bottom_out ) , 
@@ -114838,7 +141076,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3572 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3573 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3574 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3575 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3575 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_5__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3576 } ) ,
     .chany_top_in ( cby_1__1__57_chany_bottom_out ) , 
@@ -114919,7 +141157,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3596 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3597 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3598 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3599 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3599 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_5__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3600 } ) ,
     .chany_top_in ( cby_1__1__58_chany_bottom_out ) , 
@@ -115003,7 +141241,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3626 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3627 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3628 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3629 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3629 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_5__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3630 } ) ,
     .chany_top_in ( cby_1__1__59_chany_bottom_out ) , 
@@ -115084,7 +141322,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3650 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3651 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3652 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3653 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3653 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_6__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3654 } ) ,
     .chany_top_in ( cby_1__1__61_chany_bottom_out ) , 
@@ -115167,7 +141405,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3678 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3679 ) , 
     .clk_3_N_out ( clk_3_wires[92] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3680 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3680 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_6__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3681 } ) ,
     .chany_top_in ( cby_1__1__62_chany_bottom_out ) , 
@@ -115250,7 +141488,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3705 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3706 ) , 
     .clk_3_N_out ( clk_3_wires[94] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3707 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3707 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_6__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3708 } ) ,
     .chany_top_in ( cby_1__1__63_chany_bottom_out ) , 
@@ -115333,7 +141571,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3732 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3733 ) , 
     .clk_3_N_out ( clk_3_wires[96] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3734 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3734 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_6__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3735 } ) ,
     .chany_top_in ( cby_1__1__64_chany_bottom_out ) , 
@@ -115416,7 +141654,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3759 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3760 ) , 
     .clk_3_N_out ( clk_3_wires[98] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3761 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3761 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_6__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3762 } ) ,
     .chany_top_in ( cby_1__1__65_chany_bottom_out ) , 
@@ -115500,7 +141738,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3786 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3787 ) , 
     .clk_3_N_out ( clk_3_wires[100] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3788 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3788 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_6__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3789 } ) ,
     .chany_top_in ( cby_1__1__66_chany_bottom_out ) , 
@@ -115583,7 +141821,7 @@
     .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3811 ) , 
     .clk_3_E_out ( clk_3_wires[0] ) , .clk_3_W_out ( clk_3_wires[2] ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3812 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3813 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3813 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_6__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3814 } ) ,
     .chany_top_in ( cby_1__1__67_chany_bottom_out ) , 
@@ -115662,7 +141900,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3833 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3834 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3835 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3836 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3836 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_6__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3837 } ) ,
     .chany_top_in ( cby_1__1__68_chany_bottom_out ) , 
@@ -115741,7 +141979,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3856 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3857 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3858 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3859 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3859 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_6__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3860 } ) ,
     .chany_top_in ( cby_1__1__69_chany_bottom_out ) , 
@@ -115820,7 +142058,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3879 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3880 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3881 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3882 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3882 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_6__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3883 } ) ,
     .chany_top_in ( cby_1__1__70_chany_bottom_out ) , 
@@ -115899,7 +142137,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3902 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3903 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3904 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3905 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3905 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_6__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3906 } ) ,
     .chany_top_in ( cby_1__1__71_chany_bottom_out ) , 
@@ -115978,7 +142216,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3925 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3926 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3927 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3928 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3928 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_7__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3929 } ) ,
     .chany_top_in ( cby_1__1__73_chany_bottom_out ) , 
@@ -116059,7 +142297,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3949 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3950 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3951 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3952 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3952 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_7__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3953 } ) ,
     .chany_top_in ( cby_1__1__74_chany_bottom_out ) , 
@@ -116143,7 +142381,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3979 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3980 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3981 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3982 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3982 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_7__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_3983 } ) ,
     .chany_top_in ( cby_1__1__75_chany_bottom_out ) , 
@@ -116224,7 +142462,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4003 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4004 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4005 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4006 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4006 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_7__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4007 } ) ,
     .chany_top_in ( cby_1__1__76_chany_bottom_out ) , 
@@ -116307,7 +142545,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4031 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4032 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4033 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4034 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4034 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_7__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4035 } ) ,
     .chany_top_in ( cby_1__1__77_chany_bottom_out ) , 
@@ -116388,7 +142626,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4055 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4056 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4057 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4058 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4058 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_7__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4059 } ) ,
     .chany_top_in ( cby_1__1__78_chany_bottom_out ) , 
@@ -116472,7 +142710,7 @@
     .clk_3_E_out ( clk_3_wires[4] ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4086 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4087 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4088 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4088 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_7__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4089 } ) ,
     .chany_top_in ( cby_1__1__79_chany_bottom_out ) , 
@@ -116553,7 +142791,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4109 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4110 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4111 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4112 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4112 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_7__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4113 } ) ,
     .chany_top_in ( cby_1__1__80_chany_bottom_out ) , 
@@ -116636,7 +142874,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4137 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4138 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4139 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4140 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4140 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_7__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4141 } ) ,
     .chany_top_in ( cby_1__1__81_chany_bottom_out ) , 
@@ -116717,7 +142955,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4161 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4162 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4163 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4164 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4164 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_7__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4165 } ) ,
     .chany_top_in ( cby_1__1__82_chany_bottom_out ) , 
@@ -116801,7 +143039,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4191 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4192 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4193 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4194 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4194 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_7__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4195 } ) ,
     .chany_top_in ( cby_1__1__83_chany_bottom_out ) , 
@@ -116882,7 +143120,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4215 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4216 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4217 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4218 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4218 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_8__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4219 } ) ,
     .chany_top_in ( cby_1__1__85_chany_bottom_out ) , 
@@ -116961,7 +143199,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4241 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4242 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4243 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4244 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4244 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_8__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4245 } ) ,
     .chany_top_in ( cby_1__1__86_chany_bottom_out ) , 
@@ -117045,7 +143283,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4269 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4270 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4271 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4272 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4272 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_8__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4273 } ) ,
     .chany_top_in ( cby_1__1__87_chany_bottom_out ) , 
@@ -117129,7 +143367,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4300 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4301 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4302 ) , 
-    .clk_3_S_out ( clk_3_wires[42] ) ) ;
+    .clk_3_S_out ( clk_3_wires[42] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_8__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4303 } ) ,
     .chany_top_in ( cby_1__1__88_chany_bottom_out ) , 
@@ -117218,7 +143456,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4332 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4333 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4334 ) , 
-    .clk_3_S_out ( clk_3_wires[38] ) ) ;
+    .clk_3_S_out ( clk_3_wires[38] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_8__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4335 } ) ,
     .chany_top_in ( cby_1__1__89_chany_bottom_out ) , 
@@ -117302,7 +143540,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4362 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4363 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4364 ) , 
-    .clk_3_S_out ( clk_3_wires[32] ) ) ;
+    .clk_3_S_out ( clk_3_wires[32] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_8__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4365 } ) ,
     .chany_top_in ( cby_1__1__90_chany_bottom_out ) , 
@@ -117385,7 +143623,8 @@
     .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4389 ) , 
     .clk_3_E_out ( clk_3_wires[44] ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4390 ) , 
-    .clk_3_N_out ( clk_3_wires[26] ) , .clk_3_S_out ( clk_3_wires[28] ) ) ;
+    .clk_3_N_out ( clk_3_wires[26] ) , .clk_3_S_out ( clk_3_wires[28] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_8__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4391 } ) ,
     .chany_top_in ( cby_1__1__91_chany_bottom_out ) , 
@@ -117469,7 +143708,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4418 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4419 ) , 
     .clk_3_N_out ( clk_3_wires[30] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4420 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4420 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_8__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4421 } ) ,
     .chany_top_in ( cby_1__1__92_chany_bottom_out ) , 
@@ -117558,7 +143797,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4450 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4451 ) , 
     .clk_3_N_out ( clk_3_wires[36] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4452 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4452 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_8__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4453 } ) ,
     .chany_top_in ( cby_1__1__93_chany_bottom_out ) , 
@@ -117642,7 +143881,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4480 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4481 ) , 
     .clk_3_N_out ( clk_3_wires[40] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4482 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4482 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_8__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4483 } ) ,
     .chany_top_in ( cby_1__1__94_chany_bottom_out ) , 
@@ -117726,7 +143965,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4507 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4508 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4509 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4510 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4510 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_8__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4511 } ) ,
     .chany_top_in ( cby_1__1__95_chany_bottom_out ) , 
@@ -117805,7 +144044,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4533 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4534 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4535 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4536 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4536 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_9__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4537 } ) ,
     .chany_top_in ( cby_1__1__97_chany_bottom_out ) , 
@@ -117886,7 +144125,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4557 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4558 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4559 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4560 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4560 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_9__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4561 } ) ,
     .chany_top_in ( cby_1__1__98_chany_bottom_out ) , 
@@ -117970,7 +144209,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4587 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4588 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4589 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4590 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4590 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_9__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4591 } ) ,
     .chany_top_in ( cby_1__1__99_chany_bottom_out ) , 
@@ -118051,7 +144290,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4611 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4612 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4613 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4614 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4614 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_9__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4615 } ) ,
     .chany_top_in ( cby_1__1__100_chany_bottom_out ) , 
@@ -118134,7 +144373,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4639 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4640 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4641 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4642 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4642 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_9__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4643 } ) ,
     .chany_top_in ( cby_1__1__101_chany_bottom_out ) , 
@@ -118215,7 +144454,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4663 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4664 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4665 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4666 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4666 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_9__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4667 } ) ,
     .chany_top_in ( cby_1__1__102_chany_bottom_out ) , 
@@ -118299,7 +144538,7 @@
     .clk_3_E_out ( clk_3_wires[48] ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4694 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4695 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4696 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4696 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_9__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4697 } ) ,
     .chany_top_in ( cby_1__1__103_chany_bottom_out ) , 
@@ -118380,7 +144619,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4717 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4718 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4719 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4720 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4720 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_9__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4721 } ) ,
     .chany_top_in ( cby_1__1__104_chany_bottom_out ) , 
@@ -118463,7 +144702,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4745 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4746 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4747 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4748 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4748 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_9__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4749 } ) ,
     .chany_top_in ( cby_1__1__105_chany_bottom_out ) , 
@@ -118544,7 +144783,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4769 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4770 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4771 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4772 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4772 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_9__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4773 } ) ,
     .chany_top_in ( cby_1__1__106_chany_bottom_out ) , 
@@ -118628,7 +144867,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4799 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4800 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4801 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4802 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4802 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_9__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4803 } ) ,
     .chany_top_in ( cby_1__1__107_chany_bottom_out ) , 
@@ -118709,7 +144948,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4823 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4824 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4825 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4826 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4826 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_10__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4827 } ) ,
     .chany_top_in ( cby_1__1__109_chany_bottom_out ) , 
@@ -118788,7 +145027,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4849 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4850 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4851 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4852 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4852 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_10__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4853 } ) ,
     .chany_top_in ( cby_1__1__110_chany_bottom_out ) , 
@@ -118872,7 +145111,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4879 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4880 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4881 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4882 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4882 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_10__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4883 } ) ,
     .chany_top_in ( cby_1__1__111_chany_bottom_out ) , 
@@ -118956,7 +145195,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4910 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4911 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4912 ) , 
-    .clk_3_S_out ( clk_3_wires[86] ) ) ;
+    .clk_3_S_out ( clk_3_wires[86] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_10__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4913 } ) ,
     .chany_top_in ( cby_1__1__112_chany_bottom_out ) , 
@@ -119045,7 +145284,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4944 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4945 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4946 ) , 
-    .clk_3_S_out ( clk_3_wires[82] ) ) ;
+    .clk_3_S_out ( clk_3_wires[82] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_10__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4947 } ) ,
     .chany_top_in ( cby_1__1__113_chany_bottom_out ) , 
@@ -119129,7 +145368,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4974 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4975 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4976 ) , 
-    .clk_3_S_out ( clk_3_wires[76] ) ) ;
+    .clk_3_S_out ( clk_3_wires[76] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_10__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_4977 } ) ,
     .chany_top_in ( cby_1__1__114_chany_bottom_out ) , 
@@ -119212,7 +145451,8 @@
     .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5002 ) , 
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5003 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5004 ) , 
-    .clk_3_N_out ( clk_3_wires[70] ) , .clk_3_S_out ( clk_3_wires[72] ) ) ;
+    .clk_3_N_out ( clk_3_wires[70] ) , .clk_3_S_out ( clk_3_wires[72] ) , 
+    .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_10__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5005 } ) ,
     .chany_top_in ( cby_1__1__115_chany_bottom_out ) , 
@@ -119296,7 +145536,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5032 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5033 ) , 
     .clk_3_N_out ( clk_3_wires[74] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5034 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5034 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_10__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5035 } ) ,
     .chany_top_in ( cby_1__1__116_chany_bottom_out ) , 
@@ -119385,7 +145625,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5066 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5067 ) , 
     .clk_3_N_out ( clk_3_wires[80] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5068 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5068 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_10__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5069 } ) ,
     .chany_top_in ( cby_1__1__117_chany_bottom_out ) , 
@@ -119469,7 +145709,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5096 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5097 ) , 
     .clk_3_N_out ( clk_3_wires[84] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5098 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5098 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_10__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5099 } ) ,
     .chany_top_in ( cby_1__1__118_chany_bottom_out ) , 
@@ -119553,7 +145793,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5125 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5126 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5127 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5128 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5128 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_10__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5129 } ) ,
     .chany_top_in ( cby_1__1__119_chany_bottom_out ) , 
@@ -119632,7 +145872,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5151 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5152 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5153 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5154 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5154 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_11__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5155 } ) ,
     .chany_top_in ( cby_1__1__121_chany_bottom_out ) , 
@@ -119713,7 +145953,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5175 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5176 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5177 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5178 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5178 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_11__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5179 } ) ,
     .chany_top_in ( cby_1__1__122_chany_bottom_out ) , 
@@ -119797,7 +146037,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5205 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5206 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5207 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5208 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5208 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_11__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5209 } ) ,
     .chany_top_in ( cby_1__1__123_chany_bottom_out ) , 
@@ -119878,7 +146118,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5229 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5230 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5231 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5232 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5232 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_11__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5233 } ) ,
     .chany_top_in ( cby_1__1__124_chany_bottom_out ) , 
@@ -119961,7 +146201,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5257 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5258 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5259 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5260 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5260 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_11__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5261 } ) ,
     .chany_top_in ( cby_1__1__125_chany_bottom_out ) , 
@@ -120042,7 +146282,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5281 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5282 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5283 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5284 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5284 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_11__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5285 } ) ,
     .chany_top_in ( cby_1__1__126_chany_bottom_out ) , 
@@ -120121,7 +146361,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5307 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5308 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5309 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5310 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5310 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_11__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5311 } ) ,
     .chany_top_in ( cby_1__1__127_chany_bottom_out ) , 
@@ -120202,7 +146442,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5331 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5332 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5333 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5334 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5334 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_11__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5335 } ) ,
     .chany_top_in ( cby_1__1__128_chany_bottom_out ) , 
@@ -120285,7 +146525,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5359 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5360 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5361 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5362 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5362 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_11__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5363 } ) ,
     .chany_top_in ( cby_1__1__129_chany_bottom_out ) , 
@@ -120366,7 +146606,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5383 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5384 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5385 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5386 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5386 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_11__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5387 } ) ,
     .chany_top_in ( cby_1__1__130_chany_bottom_out ) , 
@@ -120450,7 +146690,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5413 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5414 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5415 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5416 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5416 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__1_ sb_11__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5417 } ) ,
     .chany_top_in ( cby_1__1__131_chany_bottom_out ) , 
@@ -120531,7 +146771,7 @@
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5437 ) , 
     .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5438 ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5439 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5440 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5440 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2_ sb_1__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5441 } ) ,
     .chanx_right_in ( cbx_1__12__1_chanx_left_out ) , 
@@ -120574,7 +146814,7 @@
     .pReset_W_in ( SYNOPSYS_UNCONNECTED_5444 ) , 
     .pReset_W_out ( pResetWires[601] ) , 
     .pReset_E_out ( SYNOPSYS_UNCONNECTED_5445 ) , 
-    .prog_clk_0_S_in ( prog_clk_0_wires[60] ) ) ;
+    .prog_clk_0_S_in ( prog_clk_0_wires[60] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2_ sb_2__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5446 } ) ,
     .chanx_right_in ( cbx_1__12__2_chanx_left_out ) , 
@@ -120617,7 +146857,7 @@
     .pReset_W_in ( SYNOPSYS_UNCONNECTED_5448 ) , 
     .pReset_W_out ( pResetWires[605] ) , 
     .pReset_E_out ( SYNOPSYS_UNCONNECTED_5449 ) , 
-    .prog_clk_0_S_in ( prog_clk_0_wires[100] ) ) ;
+    .prog_clk_0_S_in ( prog_clk_0_wires[100] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2_ sb_3__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5450 } ) ,
     .chanx_right_in ( cbx_1__12__3_chanx_left_out ) , 
@@ -120660,7 +146900,7 @@
     .pReset_W_in ( SYNOPSYS_UNCONNECTED_5453 ) , 
     .pReset_W_out ( pResetWires[608] ) , 
     .pReset_E_out ( SYNOPSYS_UNCONNECTED_5454 ) , 
-    .prog_clk_0_S_in ( prog_clk_0_wires[138] ) ) ;
+    .prog_clk_0_S_in ( prog_clk_0_wires[138] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2_ sb_4__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5455 } ) ,
     .chanx_right_in ( cbx_1__12__4_chanx_left_out ) , 
@@ -120703,7 +146943,7 @@
     .pReset_W_in ( SYNOPSYS_UNCONNECTED_5457 ) , 
     .pReset_W_out ( pResetWires[611] ) , 
     .pReset_E_out ( SYNOPSYS_UNCONNECTED_5458 ) , 
-    .prog_clk_0_S_in ( prog_clk_0_wires[176] ) ) ;
+    .prog_clk_0_S_in ( prog_clk_0_wires[176] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2_ sb_5__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5459 } ) ,
     .chanx_right_in ( cbx_1__12__5_chanx_left_out ) , 
@@ -120746,7 +146986,7 @@
     .pReset_W_in ( SYNOPSYS_UNCONNECTED_5462 ) , 
     .pReset_W_out ( pResetWires[614] ) , 
     .pReset_E_out ( SYNOPSYS_UNCONNECTED_5463 ) , 
-    .prog_clk_0_S_in ( prog_clk_0_wires[214] ) ) ;
+    .prog_clk_0_S_in ( prog_clk_0_wires[214] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2_ sb_6__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5464 } ) ,
     .chanx_right_in ( cbx_1__12__6_chanx_left_out ) , 
@@ -120787,7 +147027,7 @@
     .pReset_E_in ( SYNOPSYS_UNCONNECTED_5465 ) , 
     .pReset_W_in ( SYNOPSYS_UNCONNECTED_5466 ) , 
     .pReset_W_out ( pResetWires[617] ) , .pReset_E_out ( pResetWires[619] ) , 
-    .prog_clk_0_S_in ( prog_clk_0_wires[252] ) ) ;
+    .prog_clk_0_S_in ( prog_clk_0_wires[252] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2_ sb_7__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5467 } ) ,
     .chanx_right_in ( cbx_1__12__7_chanx_left_out ) , 
@@ -120830,7 +147070,7 @@
     .pReset_W_in ( pResetWires[620] ) , 
     .pReset_W_out ( SYNOPSYS_UNCONNECTED_5471 ) , 
     .pReset_E_out ( pResetWires[622] ) , 
-    .prog_clk_0_S_in ( prog_clk_0_wires[290] ) ) ;
+    .prog_clk_0_S_in ( prog_clk_0_wires[290] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2_ sb_8__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5472 } ) ,
     .chanx_right_in ( cbx_1__12__8_chanx_left_out ) , 
@@ -120873,7 +147113,7 @@
     .pReset_W_in ( pResetWires[623] ) , 
     .pReset_W_out ( SYNOPSYS_UNCONNECTED_5475 ) , 
     .pReset_E_out ( pResetWires[625] ) , 
-    .prog_clk_0_S_in ( prog_clk_0_wires[328] ) ) ;
+    .prog_clk_0_S_in ( prog_clk_0_wires[328] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2_ sb_9__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5476 } ) ,
     .chanx_right_in ( cbx_1__12__9_chanx_left_out ) , 
@@ -120916,7 +147156,7 @@
     .pReset_W_in ( pResetWires[626] ) , 
     .pReset_W_out ( SYNOPSYS_UNCONNECTED_5480 ) , 
     .pReset_E_out ( pResetWires[628] ) , 
-    .prog_clk_0_S_in ( prog_clk_0_wires[366] ) ) ;
+    .prog_clk_0_S_in ( prog_clk_0_wires[366] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2_ sb_10__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5481 } ) ,
     .chanx_right_in ( cbx_1__12__10_chanx_left_out ) , 
@@ -120959,7 +147199,7 @@
     .pReset_W_in ( pResetWires[629] ) , 
     .pReset_W_out ( SYNOPSYS_UNCONNECTED_5484 ) , 
     .pReset_E_out ( pResetWires[631] ) , 
-    .prog_clk_0_S_in ( prog_clk_0_wires[404] ) ) ;
+    .prog_clk_0_S_in ( prog_clk_0_wires[404] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_1__2_ sb_11__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5485 } ) ,
     .chanx_right_in ( cbx_1__12__11_chanx_left_out ) , 
@@ -121002,7 +147242,7 @@
     .pReset_W_in ( pResetWires[632] ) , 
     .pReset_W_out ( SYNOPSYS_UNCONNECTED_5489 ) , 
     .pReset_E_out ( pResetWires[634] ) , 
-    .prog_clk_0_S_in ( prog_clk_0_wires[442] ) ) ;
+    .prog_clk_0_S_in ( prog_clk_0_wires[442] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__0_ sb_12__0_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5490 } ) ,
     .chany_top_in ( cby_12__1__0_chany_bottom_out ) , 
@@ -121030,7 +147270,7 @@
     .chanx_left_out ( sb_12__0__0_chanx_left_out ) , 
     .ccff_tail ( sb_12__0__0_ccff_tail ) , .pReset_W_in ( pResetWires[59] ) , 
     .pReset_N_out ( pResetWires[60] ) , 
-    .prog_clk_0_N_in ( prog_clk_0_wires[445] ) ) ;
+    .prog_clk_0_N_in ( prog_clk_0_wires[445] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1_ sb_12__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5491 } ) ,
     .chany_top_in ( cby_12__1__1_chany_bottom_out ) , 
@@ -121068,7 +147308,7 @@
     .chanx_left_out ( sb_12__1__0_chanx_left_out ) , 
     .ccff_tail ( sb_12__1__0_ccff_tail ) , .pReset_W_in ( pResetWires[107] ) , 
     .pReset_N_out ( pResetWires[109] ) , 
-    .prog_clk_0_N_in ( prog_clk_0_wires[448] ) ) ;
+    .prog_clk_0_N_in ( prog_clk_0_wires[448] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1_ sb_12__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5492 } ) ,
     .chany_top_in ( cby_12__1__2_chany_bottom_out ) , 
@@ -121106,7 +147346,7 @@
     .chanx_left_out ( sb_12__1__1_chanx_left_out ) , 
     .ccff_tail ( sb_12__1__1_ccff_tail ) , .pReset_W_in ( pResetWires[156] ) , 
     .pReset_N_out ( pResetWires[158] ) , 
-    .prog_clk_0_N_in ( prog_clk_0_wires[451] ) ) ;
+    .prog_clk_0_N_in ( prog_clk_0_wires[451] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1_ sb_12__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5493 } ) ,
     .chany_top_in ( cby_12__1__3_chany_bottom_out ) , 
@@ -121144,7 +147384,7 @@
     .chanx_left_out ( sb_12__1__2_chanx_left_out ) , 
     .ccff_tail ( sb_12__1__2_ccff_tail ) , .pReset_W_in ( pResetWires[205] ) , 
     .pReset_N_out ( pResetWires[207] ) , 
-    .prog_clk_0_N_in ( prog_clk_0_wires[454] ) ) ;
+    .prog_clk_0_N_in ( prog_clk_0_wires[454] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1_ sb_12__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5494 } ) ,
     .chany_top_in ( cby_12__1__4_chany_bottom_out ) , 
@@ -121182,7 +147422,7 @@
     .chanx_left_out ( sb_12__1__3_chanx_left_out ) , 
     .ccff_tail ( sb_12__1__3_ccff_tail ) , .pReset_W_in ( pResetWires[254] ) , 
     .pReset_N_out ( pResetWires[256] ) , 
-    .prog_clk_0_N_in ( prog_clk_0_wires[457] ) ) ;
+    .prog_clk_0_N_in ( prog_clk_0_wires[457] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1_ sb_12__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5495 } ) ,
     .chany_top_in ( cby_12__1__5_chany_bottom_out ) , 
@@ -121220,7 +147460,7 @@
     .chanx_left_out ( sb_12__1__4_chanx_left_out ) , 
     .ccff_tail ( sb_12__1__4_ccff_tail ) , .pReset_W_in ( pResetWires[303] ) , 
     .pReset_N_out ( pResetWires[305] ) , 
-    .prog_clk_0_N_in ( prog_clk_0_wires[460] ) ) ;
+    .prog_clk_0_N_in ( prog_clk_0_wires[460] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1_ sb_12__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5496 } ) ,
     .chany_top_in ( cby_12__1__6_chany_bottom_out ) , 
@@ -121258,7 +147498,7 @@
     .chanx_left_out ( sb_12__1__5_chanx_left_out ) , 
     .ccff_tail ( sb_12__1__5_ccff_tail ) , .pReset_W_in ( pResetWires[352] ) , 
     .pReset_N_out ( pResetWires[354] ) , 
-    .prog_clk_0_N_in ( prog_clk_0_wires[463] ) ) ;
+    .prog_clk_0_N_in ( prog_clk_0_wires[463] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1_ sb_12__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5497 } ) ,
     .chany_top_in ( cby_12__1__7_chany_bottom_out ) , 
@@ -121296,7 +147536,7 @@
     .chanx_left_out ( sb_12__1__6_chanx_left_out ) , 
     .ccff_tail ( sb_12__1__6_ccff_tail ) , .pReset_W_in ( pResetWires[401] ) , 
     .pReset_N_out ( pResetWires[403] ) , 
-    .prog_clk_0_N_in ( prog_clk_0_wires[466] ) ) ;
+    .prog_clk_0_N_in ( prog_clk_0_wires[466] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1_ sb_12__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5498 } ) ,
     .chany_top_in ( cby_12__1__8_chany_bottom_out ) , 
@@ -121334,7 +147574,7 @@
     .chanx_left_out ( sb_12__1__7_chanx_left_out ) , 
     .ccff_tail ( sb_12__1__7_ccff_tail ) , .pReset_W_in ( pResetWires[450] ) , 
     .pReset_N_out ( pResetWires[452] ) , 
-    .prog_clk_0_N_in ( prog_clk_0_wires[469] ) ) ;
+    .prog_clk_0_N_in ( prog_clk_0_wires[469] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1_ sb_12__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5499 } ) ,
     .chany_top_in ( cby_12__1__9_chany_bottom_out ) , 
@@ -121372,7 +147612,7 @@
     .chanx_left_out ( sb_12__1__8_chanx_left_out ) , 
     .ccff_tail ( sb_12__1__8_ccff_tail ) , .pReset_W_in ( pResetWires[499] ) , 
     .pReset_N_out ( pResetWires[501] ) , 
-    .prog_clk_0_N_in ( prog_clk_0_wires[472] ) ) ;
+    .prog_clk_0_N_in ( prog_clk_0_wires[472] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1_ sb_12__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5500 } ) ,
     .chany_top_in ( cby_12__1__10_chany_bottom_out ) , 
@@ -121410,7 +147650,7 @@
     .chanx_left_out ( sb_12__1__9_chanx_left_out ) , 
     .ccff_tail ( sb_12__1__9_ccff_tail ) , .pReset_W_in ( pResetWires[548] ) , 
     .pReset_N_out ( pResetWires[550] ) , 
-    .prog_clk_0_N_in ( prog_clk_0_wires[475] ) ) ;
+    .prog_clk_0_N_in ( prog_clk_0_wires[475] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__1_ sb_12__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5501 } ) ,
     .chany_top_in ( cby_12__1__11_chany_bottom_out ) , 
@@ -121448,7 +147688,7 @@
     .chanx_left_out ( sb_12__1__10_chanx_left_out ) , 
     .ccff_tail ( sb_12__1__10_ccff_tail ) , 
     .pReset_W_in ( pResetWires[597] ) , .pReset_N_out ( pResetWires[599] ) , 
-    .prog_clk_0_N_in ( prog_clk_0_wires[478] ) ) ;
+    .prog_clk_0_N_in ( prog_clk_0_wires[478] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 sb_2__2_ sb_12__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5502 } ) ,
     .chany_bottom_in ( cby_12__1__11_chany_top_out ) , 
@@ -121476,7 +147716,7 @@
     .chanx_left_out ( sb_12__12__0_chanx_left_out ) , 
     .ccff_tail ( sb_12__12__0_ccff_tail ) , .SC_IN_BOT ( scff_Wires[317] ) , 
     .SC_OUT_BOT ( sc_tail ) , .pReset_W_in ( pResetWires[635] ) , 
-    .prog_clk_0_S_in ( prog_clk_0_wires[480] ) ) ;
+    .prog_clk_0_S_in ( prog_clk_0_wires[480] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0_ cbx_1__0_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5503 } ) ,
     .chanx_left_in ( sb_0__0__0_chanx_right_out ) , 
@@ -121531,7 +147771,7 @@
     .pReset_W_out ( pResetWires[25] ) , 
     .pReset_E_out ( SYNOPSYS_UNCONNECTED_5506 ) , 
     .prog_clk_0_N_in ( prog_clk_0_wires[0] ) , 
-    .prog_clk_0_W_out ( prog_clk_0_wires[5] ) ) ;
+    .prog_clk_0_W_out ( prog_clk_0_wires[5] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__0_ cbx_2__0_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5507 } ) ,
     .chanx_left_in ( sb_1__0__0_chanx_right_out ) , 
@@ -121586,7 +147826,8 @@
     .pReset_W_out ( pResetWires[28] ) , 
     .pReset_E_out ( SYNOPSYS_UNCONNECTED_5510 ) , 
     .prog_clk_0_N_in ( prog_clk_0_wires[63] ) , 
-    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5511 ) ) ;
+    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5511 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0_ cbx_3__0_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5512 } ) ,
     .chanx_left_in ( sb_1__0__1_chanx_right_out ) , 
@@ -121641,7 +147882,8 @@
     .pReset_W_out ( pResetWires[31] ) , 
     .pReset_E_out ( SYNOPSYS_UNCONNECTED_5515 ) , 
     .prog_clk_0_N_in ( prog_clk_0_wires[101] ) , 
-    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5516 ) ) ;
+    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5516 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0_ cbx_4__0_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5517 } ) ,
     .chanx_left_in ( sb_1__0__2_chanx_right_out ) , 
@@ -121696,7 +147938,8 @@
     .pReset_W_out ( pResetWires[34] ) , 
     .pReset_E_out ( SYNOPSYS_UNCONNECTED_5520 ) , 
     .prog_clk_0_N_in ( prog_clk_0_wires[139] ) , 
-    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5521 ) ) ;
+    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5521 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0_ cbx_5__0_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5522 } ) ,
     .chanx_left_in ( sb_1__0__3_chanx_right_out ) , 
@@ -121751,7 +147994,8 @@
     .pReset_W_out ( pResetWires[37] ) , 
     .pReset_E_out ( SYNOPSYS_UNCONNECTED_5525 ) , 
     .prog_clk_0_N_in ( prog_clk_0_wires[177] ) , 
-    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5526 ) ) ;
+    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5526 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0_ cbx_6__0_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5527 } ) ,
     .chanx_left_in ( sb_1__0__4_chanx_right_out ) , 
@@ -121806,7 +148050,8 @@
     .pReset_W_out ( pResetWires[40] ) , 
     .pReset_E_out ( SYNOPSYS_UNCONNECTED_5530 ) , 
     .prog_clk_0_N_in ( prog_clk_0_wires[215] ) , 
-    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5531 ) ) ;
+    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5531 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0_ cbx_7__0_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5532 } ) ,
     .chanx_left_in ( sb_1__0__5_chanx_right_out ) , 
@@ -121861,7 +148106,8 @@
     .pReset_W_out ( SYNOPSYS_UNCONNECTED_5535 ) , 
     .pReset_E_out ( pResetWires[44] ) , 
     .prog_clk_0_N_in ( prog_clk_0_wires[253] ) , 
-    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5536 ) ) ;
+    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5536 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0_ cbx_8__0_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5537 } ) ,
     .chanx_left_in ( sb_1__0__6_chanx_right_out ) , 
@@ -121916,7 +148162,8 @@
     .pReset_W_out ( SYNOPSYS_UNCONNECTED_5540 ) , 
     .pReset_E_out ( pResetWires[47] ) , 
     .prog_clk_0_N_in ( prog_clk_0_wires[291] ) , 
-    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5541 ) ) ;
+    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5541 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0_ cbx_9__0_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5542 } ) ,
     .chanx_left_in ( sb_1__0__7_chanx_right_out ) , 
@@ -121971,7 +148218,8 @@
     .pReset_W_out ( SYNOPSYS_UNCONNECTED_5545 ) , 
     .pReset_E_out ( pResetWires[50] ) , 
     .prog_clk_0_N_in ( prog_clk_0_wires[329] ) , 
-    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5546 ) ) ;
+    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5546 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0_ cbx_10__0_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5547 } ) ,
     .chanx_left_in ( sb_1__0__8_chanx_right_out ) , 
@@ -122026,7 +148274,8 @@
     .pReset_W_out ( SYNOPSYS_UNCONNECTED_5550 ) , 
     .pReset_E_out ( pResetWires[53] ) , 
     .prog_clk_0_N_in ( prog_clk_0_wires[367] ) , 
-    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5551 ) ) ;
+    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5551 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0_ cbx_11__0_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5552 } ) ,
     .chanx_left_in ( sb_1__0__9_chanx_right_out ) , 
@@ -122081,7 +148330,8 @@
     .pReset_W_out ( SYNOPSYS_UNCONNECTED_5555 ) , 
     .pReset_E_out ( pResetWires[56] ) , 
     .prog_clk_0_N_in ( prog_clk_0_wires[405] ) , 
-    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5556 ) ) ;
+    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5556 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__0_ cbx_12__0_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5557 } ) ,
     .chanx_left_in ( sb_1__0__10_chanx_right_out ) , 
@@ -122136,7 +148386,8 @@
     .pReset_W_out ( SYNOPSYS_UNCONNECTED_5560 ) , 
     .pReset_E_out ( pResetWires[59] ) , 
     .prog_clk_0_N_in ( prog_clk_0_wires[443] ) , 
-    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5561 ) ) ;
+    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5561 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_1__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5562 } ) ,
     .chanx_left_in ( sb_0__1__0_chanx_right_out ) , 
@@ -122189,7 +148440,7 @@
     .clk_2_W_in ( p2552 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5572 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5573 ) , .clk_3_W_in ( p2663 ) , 
     .clk_3_E_in ( p2583 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5574 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5575 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5575 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_1__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5576 } ) ,
     .chanx_left_in ( sb_0__1__1_chanx_right_out ) , 
@@ -122240,7 +148491,7 @@
     .clk_2_W_in ( p1210 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5588 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5589 ) , .clk_3_W_in ( p1149 ) , 
     .clk_3_E_in ( p3325 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5590 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5591 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5591 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_1__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5592 } ) ,
     .chanx_left_in ( sb_0__1__2_chanx_right_out ) , 
@@ -122293,7 +148544,7 @@
     .clk_2_W_in ( p2321 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5602 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5603 ) , .clk_3_W_in ( p2351 ) , 
     .clk_3_E_in ( p3232 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5604 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5605 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5605 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_1__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5606 } ) ,
     .chanx_left_in ( sb_0__1__3_chanx_right_out ) , 
@@ -122344,7 +148595,7 @@
     .clk_2_W_in ( p2759 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5618 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5619 ) , .clk_3_W_in ( p2828 ) , 
     .clk_3_E_in ( p2897 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5620 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5621 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5621 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_1__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5622 } ) ,
     .chanx_left_in ( sb_0__1__4_chanx_right_out ) , 
@@ -122397,7 +148648,7 @@
     .clk_2_W_in ( p2563 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5632 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5633 ) , .clk_3_W_in ( p2648 ) , 
     .clk_3_E_in ( p2345 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5634 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5635 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5635 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_1__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5636 } ) ,
     .chanx_left_in ( sb_0__1__5_chanx_right_out ) , 
@@ -122448,7 +148699,7 @@
     .clk_2_W_in ( p2314 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5648 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5649 ) , .clk_3_W_in ( p2401 ) , 
     .clk_3_E_in ( p2570 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5650 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5651 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5651 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_1__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5652 } ) ,
     .chanx_left_in ( sb_0__1__6_chanx_right_out ) , 
@@ -122501,7 +148752,7 @@
     .clk_2_W_in ( p1317 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5662 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5663 ) , .clk_3_W_in ( p1578 ) , 
     .clk_3_E_in ( p3258 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5664 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5665 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5665 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_1__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5666 } ) ,
     .chanx_left_in ( sb_0__1__7_chanx_right_out ) , 
@@ -122552,7 +148803,7 @@
     .clk_2_W_in ( p1667 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5678 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5679 ) , .clk_3_W_in ( p1913 ) , 
     .clk_3_E_in ( p509 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5680 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5681 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5681 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_1__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5682 } ) ,
     .chanx_left_in ( sb_0__1__8_chanx_right_out ) , 
@@ -122605,7 +148856,7 @@
     .clk_2_W_in ( p1354 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5692 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5693 ) , .clk_3_W_in ( p1393 ) , 
     .clk_3_E_in ( p2900 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5694 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5695 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5695 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_1__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5696 } ) ,
     .chanx_left_in ( sb_0__1__9_chanx_right_out ) , 
@@ -122656,7 +148907,7 @@
     .clk_2_W_in ( p1332 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5708 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5709 ) , .clk_3_W_in ( p1577 ) , 
     .clk_3_E_in ( p2539 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5710 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5711 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5711 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_1__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5712 } ) ,
     .chanx_left_in ( sb_0__1__10_chanx_right_out ) , 
@@ -122709,7 +148960,7 @@
     .clk_2_W_in ( p2541 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5722 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5723 ) , .clk_3_W_in ( p2633 ) , 
     .clk_3_E_in ( p2074 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5724 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5725 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5725 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_2__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5726 } ) ,
     .chanx_left_in ( sb_1__1__0_chanx_right_out ) , 
@@ -122763,7 +149014,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5737 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5738 ) , .clk_3_W_in ( p1758 ) , 
     .clk_3_E_in ( p2929 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5739 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5740 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5740 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_2__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5741 } ) ,
     .chanx_left_in ( sb_1__1__1_chanx_right_out ) , 
@@ -122817,7 +149068,7 @@
     .clk_2_W_out ( clk_2_wires[1] ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5755 ) , .clk_3_W_in ( p1487 ) , 
     .clk_3_E_in ( p1726 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5756 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5757 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5757 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_2__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5758 } ) ,
     .chanx_left_in ( sb_1__1__2_chanx_right_out ) , 
@@ -122871,7 +149122,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5769 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5770 ) , .clk_3_W_in ( p1944 ) , 
     .clk_3_E_in ( p2342 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5771 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5772 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5772 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_2__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5773 } ) ,
     .chanx_left_in ( sb_1__1__3_chanx_right_out ) , 
@@ -122925,7 +149176,7 @@
     .clk_2_W_out ( clk_2_wires[6] ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5787 ) , .clk_3_W_in ( p1429 ) , 
     .clk_3_E_in ( p2009 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5788 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5789 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5789 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_2__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5790 } ) ,
     .chanx_left_in ( sb_1__1__4_chanx_right_out ) , 
@@ -122979,7 +149230,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5801 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5802 ) , .clk_3_W_in ( p2476 ) , 
     .clk_3_E_in ( p3145 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5803 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5804 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5804 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_2__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5805 } ) ,
     .chanx_left_in ( sb_1__1__5_chanx_right_out ) , 
@@ -123030,7 +149281,7 @@
     .clk_2_W_in ( p2755 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5818 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5819 ) , .clk_3_W_in ( p2811 ) , 
     .clk_3_E_in ( p2317 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5820 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5821 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5821 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_2__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5822 } ) ,
     .chanx_left_in ( sb_1__1__6_chanx_right_out ) , 
@@ -123084,7 +149335,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5833 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5834 ) , .clk_3_W_in ( p2815 ) , 
     .clk_3_E_in ( p2731 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5835 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5836 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5836 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_2__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5837 } ) ,
     .chanx_left_in ( sb_1__1__7_chanx_right_out ) , 
@@ -123138,7 +149389,7 @@
     .clk_2_W_out ( clk_2_wires[13] ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5851 ) , .clk_3_W_in ( p1176 ) , 
     .clk_3_E_in ( p1689 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5852 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5853 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5853 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_2__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5854 } ) ,
     .chanx_left_in ( sb_1__1__8_chanx_right_out ) , 
@@ -123192,7 +149443,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5865 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5866 ) , .clk_3_W_in ( p1901 ) , 
     .clk_3_E_in ( p2746 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5867 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5868 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5868 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_2__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5869 } ) ,
     .chanx_left_in ( sb_1__1__9_chanx_right_out ) , 
@@ -123246,7 +149497,7 @@
     .clk_2_W_out ( clk_2_wires[20] ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5883 ) , .clk_3_W_in ( p1544 ) , 
     .clk_3_E_in ( p1983 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5884 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5885 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5885 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_2__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5886 } ) ,
     .chanx_left_in ( sb_1__1__10_chanx_right_out ) , 
@@ -123300,7 +149551,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5897 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5898 ) , .clk_3_W_in ( p1850 ) , 
     .clk_3_E_in ( p2329 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5899 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5900 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5900 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_3__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5901 } ) ,
     .chanx_left_in ( sb_1__1__11_chanx_right_out ) , 
@@ -123353,7 +149604,7 @@
     .clk_2_W_in ( p652 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5912 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5913 ) , .clk_3_W_in ( p1228 ) , 
     .clk_3_E_in ( p3054 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5914 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5915 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5915 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_3__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5916 } ) ,
     .chanx_left_in ( sb_1__1__12_chanx_right_out ) , 
@@ -123404,7 +149655,7 @@
     .clk_2_W_in ( p1628 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5929 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5930 ) , .clk_3_W_in ( p1938 ) , 
     .clk_3_E_in ( p2528 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5931 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5932 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5932 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_3__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5933 } ) ,
     .chanx_left_in ( sb_1__1__13_chanx_right_out ) , 
@@ -123457,7 +149708,7 @@
     .clk_2_W_in ( p2308 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5944 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5945 ) , .clk_3_W_in ( p2355 ) , 
     .clk_3_E_in ( p2523 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5946 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5947 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5947 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_3__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5948 } ) ,
     .chanx_left_in ( sb_1__1__14_chanx_right_out ) , 
@@ -123508,7 +149759,7 @@
     .clk_2_W_in ( p1307 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5961 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5962 ) , .clk_3_W_in ( p1507 ) , 
     .clk_3_E_in ( p2915 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5963 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5964 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5964 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_3__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5965 } ) ,
     .chanx_left_in ( sb_1__1__15_chanx_right_out ) , 
@@ -123561,7 +149812,7 @@
     .clk_2_W_in ( p1348 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5976 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5977 ) , .clk_3_W_in ( p1441 ) , 
     .clk_3_E_in ( p3167 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5978 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5979 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5979 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_3__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5980 } ) ,
     .chanx_left_in ( sb_1__1__16_chanx_right_out ) , 
@@ -123615,7 +149866,7 @@
     .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5995 ) , 
     .clk_3_E_in ( clk_3_wires[50] ) , 
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5996 ) , 
-    .clk_3_W_out ( clk_3_wires[51] ) ) ;
+    .clk_3_W_out ( clk_3_wires[51] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_3__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_5997 } ) ,
     .chanx_left_in ( sb_1__1__17_chanx_right_out ) , 
@@ -123668,7 +149919,7 @@
     .clk_2_W_in ( p1366 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6008 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6009 ) , .clk_3_W_in ( p1595 ) , 
     .clk_3_E_in ( p2547 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6010 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6011 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6011 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_3__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6012 } ) ,
     .chanx_left_in ( sb_1__1__18_chanx_right_out ) , 
@@ -123719,7 +149970,7 @@
     .clk_2_W_in ( p2030 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6025 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6026 ) , .clk_3_W_in ( p2111 ) , 
     .clk_3_E_in ( p2740 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6027 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6028 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6028 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_3__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6029 } ) ,
     .chanx_left_in ( sb_1__1__19_chanx_right_out ) , 
@@ -123772,7 +150023,7 @@
     .clk_2_W_in ( p580 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6040 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6041 ) , .clk_3_W_in ( p1222 ) , 
     .clk_3_E_in ( p3062 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6042 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6043 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6043 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_3__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6044 } ) ,
     .chanx_left_in ( sb_1__1__20_chanx_right_out ) , 
@@ -123823,7 +150074,7 @@
     .clk_2_W_in ( p2069 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6057 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6058 ) , .clk_3_W_in ( p2021 ) , 
     .clk_3_E_in ( p2914 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6059 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6060 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6060 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_3__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6061 } ) ,
     .chanx_left_in ( sb_1__1__21_chanx_right_out ) , 
@@ -123876,7 +150127,7 @@
     .clk_2_W_in ( p1359 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6072 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6073 ) , .clk_3_W_in ( p1572 ) , 
     .clk_3_E_in ( p1684 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6074 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6075 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6075 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_4__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6076 } ) ,
     .chanx_left_in ( sb_1__1__22_chanx_right_out ) , 
@@ -123930,7 +150181,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6087 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6088 ) , .clk_3_W_in ( p1547 ) , 
     .clk_3_E_in ( p3066 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6089 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6090 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6090 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_4__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6091 } ) ,
     .chanx_left_in ( sb_1__1__23_chanx_right_out ) , 
@@ -123984,7 +150235,7 @@
     .clk_2_W_out ( clk_2_wires[28] ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6105 ) , .clk_3_W_in ( p1812 ) , 
     .clk_3_E_in ( p532 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6106 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6107 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6107 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_4__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6108 } ) ,
     .chanx_left_in ( sb_1__1__24_chanx_right_out ) , 
@@ -124038,7 +150289,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6119 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6120 ) , .clk_3_W_in ( p2784 ) , 
     .clk_3_E_in ( p2296 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6121 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6122 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6122 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_4__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6123 } ) ,
     .chanx_left_in ( sb_1__1__25_chanx_right_out ) , 
@@ -124092,7 +150343,7 @@
     .clk_2_W_out ( clk_2_wires[37] ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6137 ) , .clk_3_W_in ( p1563 ) , 
     .clk_3_E_in ( p1342 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6138 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6139 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6139 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_4__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6140 } ) ,
     .chanx_left_in ( sb_1__1__26_chanx_right_out ) , 
@@ -124146,7 +150397,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6151 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6152 ) , .clk_3_W_in ( p2369 ) , 
     .clk_3_E_in ( p3311 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6153 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6154 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6154 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_4__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6155 } ) ,
     .chanx_left_in ( sb_1__1__27_chanx_right_out ) , 
@@ -124200,7 +150451,7 @@
     .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6170 ) , 
     .clk_3_E_in ( clk_3_wires[46] ) , 
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6171 ) , 
-    .clk_3_W_out ( clk_3_wires[47] ) ) ;
+    .clk_3_W_out ( clk_3_wires[47] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_4__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6172 } ) ,
     .chanx_left_in ( sb_1__1__28_chanx_right_out ) , 
@@ -124254,7 +150505,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6183 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6184 ) , .clk_3_W_in ( p2623 ) , 
     .clk_3_E_in ( p2878 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6185 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6186 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6186 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_4__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6187 } ) ,
     .chanx_left_in ( sb_1__1__29_chanx_right_out ) , 
@@ -124308,7 +150559,7 @@
     .clk_2_W_out ( clk_2_wires[50] ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6201 ) , .clk_3_W_in ( p1597 ) , 
     .clk_3_E_in ( p1992 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6202 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6203 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6203 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_4__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6204 } ) ,
     .chanx_left_in ( sb_1__1__30_chanx_right_out ) , 
@@ -124362,7 +150613,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6215 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6216 ) , .clk_3_W_in ( p1249 ) , 
     .clk_3_E_in ( p3239 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6217 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6218 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6218 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_4__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6219 } ) ,
     .chanx_left_in ( sb_1__1__31_chanx_right_out ) , 
@@ -124416,7 +150667,7 @@
     .clk_2_W_out ( clk_2_wires[63] ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6233 ) , .clk_3_W_in ( p1211 ) , 
     .clk_3_E_in ( p1685 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6234 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6235 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6235 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_4__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6236 } ) ,
     .chanx_left_in ( sb_1__1__32_chanx_right_out ) , 
@@ -124470,7 +150721,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6247 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6248 ) , .clk_3_W_in ( p1846 ) , 
     .clk_3_E_in ( p2739 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6249 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6250 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6250 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_5__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6251 } ) ,
     .chanx_left_in ( sb_1__1__33_chanx_right_out ) , 
@@ -124523,7 +150774,7 @@
     .clk_2_W_in ( p2315 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6262 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6263 ) , .clk_3_W_in ( p2383 ) , 
     .clk_3_E_in ( p1386 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6264 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6265 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6265 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_5__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6266 } ) ,
     .chanx_left_in ( sb_1__1__34_chanx_right_out ) , 
@@ -124577,7 +150828,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6280 ) , 
     .clk_2_E_out ( clk_2_wires[26] ) , .clk_3_W_in ( p1841 ) , 
     .clk_3_E_in ( p416 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6281 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6282 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6282 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_5__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6283 } ) ,
     .chanx_left_in ( sb_1__1__35_chanx_right_out ) , 
@@ -124630,7 +150881,7 @@
     .clk_2_W_in ( p2004 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6294 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6295 ) , .clk_3_W_in ( p2171 ) , 
     .clk_3_E_in ( p2535 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6296 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6297 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6297 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_5__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6298 } ) ,
     .chanx_left_in ( sb_1__1__36_chanx_right_out ) , 
@@ -124684,7 +150935,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6312 ) , 
     .clk_2_E_out ( clk_2_wires[35] ) , .clk_3_W_in ( p726 ) , 
     .clk_3_E_in ( p524 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6313 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6314 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6314 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_5__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6315 } ) ,
     .chanx_left_in ( sb_1__1__37_chanx_right_out ) , 
@@ -124737,7 +150988,7 @@
     .clk_2_W_in ( p1981 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6326 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6327 ) , .clk_3_W_in ( p2136 ) , 
     .clk_3_E_in ( p3035 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6328 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6329 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6329 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_5__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6330 } ) ,
     .chanx_left_in ( sb_1__1__38_chanx_right_out ) , 
@@ -124791,7 +151042,7 @@
     .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6345 ) , 
     .clk_3_E_in ( clk_3_wires[6] ) , 
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6346 ) , 
-    .clk_3_W_out ( clk_3_wires[7] ) ) ;
+    .clk_3_W_out ( clk_3_wires[7] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_5__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6347 } ) ,
     .chanx_left_in ( sb_1__1__39_chanx_right_out ) , 
@@ -124844,7 +151095,7 @@
     .clk_2_W_in ( p1656 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6358 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6359 ) , .clk_3_W_in ( p1852 ) , 
     .clk_3_E_in ( p3021 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6360 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6361 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6361 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_5__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6362 } ) ,
     .chanx_left_in ( sb_1__1__40_chanx_right_out ) , 
@@ -124898,7 +151149,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6376 ) , 
     .clk_2_E_out ( clk_2_wires[48] ) , .clk_3_W_in ( p909 ) , 
     .clk_3_E_in ( p385 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6377 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6378 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6378 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_5__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6379 } ) ,
     .chanx_left_in ( sb_1__1__41_chanx_right_out ) , 
@@ -124951,7 +151202,7 @@
     .clk_2_W_in ( p1993 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6390 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6391 ) , .clk_3_W_in ( p2231 ) , 
     .clk_3_E_in ( p3055 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6392 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6393 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6393 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_5__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6394 } ) ,
     .chanx_left_in ( sb_1__1__42_chanx_right_out ) , 
@@ -125005,7 +151256,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6408 ) , 
     .clk_2_E_out ( clk_2_wires[61] ) , .clk_3_W_in ( p1524 ) , 
     .clk_3_E_in ( p284 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6409 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6410 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6410 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_5__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6411 } ) ,
     .chanx_left_in ( sb_1__1__43_chanx_right_out ) , 
@@ -125058,7 +151309,7 @@
     .clk_2_W_in ( p1315 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6422 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6423 ) , .clk_3_W_in ( p1602 ) , 
     .clk_3_E_in ( p3069 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6424 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6425 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6425 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_6__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6426 } ) ,
     .chanx_left_in ( sb_1__1__44_chanx_right_out ) , 
@@ -125112,7 +151363,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6437 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6438 ) , .clk_3_W_in ( p2115 ) , 
     .clk_3_E_in ( p3309 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6439 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6440 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6440 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_6__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6441 } ) ,
     .chanx_left_in ( sb_1__1__45_chanx_right_out ) , 
@@ -125163,7 +151414,7 @@
     .clk_2_W_in ( p2293 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6454 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6455 ) , .clk_3_W_in ( p2384 ) , 
     .clk_3_E_in ( p1391 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6456 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6457 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6457 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_6__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6458 } ) ,
     .chanx_left_in ( sb_1__1__46_chanx_right_out ) , 
@@ -125217,7 +151468,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6469 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6470 ) , .clk_3_W_in ( p1874 ) , 
     .clk_3_E_in ( p2508 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6471 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6472 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6472 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_6__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6473 } ) ,
     .chanx_left_in ( sb_1__1__47_chanx_right_out ) , 
@@ -125268,7 +151519,7 @@
     .clk_2_W_in ( p2027 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6486 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6487 ) , .clk_3_W_in ( p2240 ) , 
     .clk_3_E_in ( p2522 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6488 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6489 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6489 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_6__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6490 } ) ,
     .chanx_left_in ( sb_1__1__48_chanx_right_out ) , 
@@ -125322,7 +151573,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6501 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6502 ) , .clk_3_W_in ( p2666 ) , 
     .clk_3_E_in ( p3040 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6503 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6504 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6504 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_6__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6505 } ) ,
     .chanx_left_in ( sb_1__1__49_chanx_right_out ) , 
@@ -125376,7 +151627,7 @@
     .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6520 ) , 
     .clk_3_E_in ( clk_3_wires[2] ) , 
     .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6521 ) , 
-    .clk_3_W_out ( clk_3_wires[3] ) ) ;
+    .clk_3_W_out ( clk_3_wires[3] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_6__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6522 } ) ,
     .chanx_left_in ( sb_1__1__50_chanx_right_out ) , 
@@ -125430,7 +151681,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6533 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6534 ) , .clk_3_W_in ( p2484 ) , 
     .clk_3_E_in ( p2767 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6535 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6536 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6536 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_6__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6537 } ) ,
     .chanx_left_in ( sb_1__1__51_chanx_right_out ) , 
@@ -125481,7 +151732,7 @@
     .clk_2_W_in ( p1990 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6550 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6551 ) , .clk_3_W_in ( p2172 ) , 
     .clk_3_E_in ( p2305 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6552 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6553 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6553 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_6__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6554 } ) ,
     .chanx_left_in ( sb_1__1__52_chanx_right_out ) , 
@@ -125535,7 +151786,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6565 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6566 ) , .clk_3_W_in ( p2376 ) , 
     .clk_3_E_in ( p2506 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6567 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6568 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6568 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_6__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6569 } ) ,
     .chanx_left_in ( sb_1__1__53_chanx_right_out ) , 
@@ -125586,7 +151837,7 @@
     .clk_2_W_in ( p1704 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6582 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6583 ) , .clk_3_W_in ( p1799 ) , 
     .clk_3_E_in ( p3156 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6584 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6585 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6585 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_6__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6586 } ) ,
     .chanx_left_in ( sb_1__1__54_chanx_right_out ) , 
@@ -125640,7 +151891,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6597 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6598 ) , .clk_3_W_in ( p2192 ) , 
     .clk_3_E_in ( p2250 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6599 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6600 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6600 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_7__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6601 } ) ,
     .chanx_left_in ( sb_1__1__55_chanx_right_out ) , 
@@ -125693,7 +151944,7 @@
     .clk_2_W_in ( p1632 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6612 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6613 ) , .clk_3_W_in ( p1733 ) , 
     .clk_3_E_in ( p2934 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6614 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6615 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6615 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_7__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6616 } ) ,
     .chanx_left_in ( sb_1__1__56_chanx_right_out ) , 
@@ -125744,7 +151995,7 @@
     .clk_2_W_in ( p2017 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6629 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6630 ) , .clk_3_W_in ( p2104 ) , 
     .clk_3_E_in ( p1986 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6631 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6632 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6632 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_7__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6633 } ) ,
     .chanx_left_in ( sb_1__1__57_chanx_right_out ) , 
@@ -125797,7 +152048,7 @@
     .clk_2_W_in ( p1679 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6644 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6645 ) , .clk_3_W_in ( p1926 ) , 
     .clk_3_E_in ( p2916 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6646 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6647 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6647 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_7__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6648 } ) ,
     .chanx_left_in ( sb_1__1__58_chanx_right_out ) , 
@@ -125848,7 +152099,7 @@
     .clk_2_W_in ( p2531 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6661 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6662 ) , .clk_3_W_in ( p2667 ) , 
     .clk_3_E_in ( p3374 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6663 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6664 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6664 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_7__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6665 } ) ,
     .chanx_left_in ( sb_1__1__59_chanx_right_out ) , 
@@ -125901,7 +152152,7 @@
     .clk_2_W_in ( p1700 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6676 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6677 ) , .clk_3_W_in ( p1773 ) , 
     .clk_3_E_in ( p2572 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6678 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6679 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6679 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_7__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6680 } ) ,
     .chanx_left_in ( sb_1__1__60_chanx_right_out ) , 
@@ -125955,7 +152206,7 @@
     .clk_3_W_in ( clk_3_wires[0] ) , 
     .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6695 ) , 
     .clk_3_E_out ( clk_3_wires[1] ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6696 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6696 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_7__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6697 } ) ,
     .chanx_left_in ( sb_1__1__61_chanx_right_out ) , 
@@ -126008,7 +152259,7 @@
     .clk_2_W_in ( p2304 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6708 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6709 ) , .clk_3_W_in ( p2393 ) , 
     .clk_3_E_in ( p2339 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6710 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6711 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6711 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_7__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6712 } ) ,
     .chanx_left_in ( sb_1__1__62_chanx_right_out ) , 
@@ -126059,7 +152310,7 @@
     .clk_2_W_in ( p1630 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6725 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6726 ) , .clk_3_W_in ( p1879 ) , 
     .clk_3_E_in ( p2537 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6727 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6728 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6728 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_7__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6729 } ) ,
     .chanx_left_in ( sb_1__1__63_chanx_right_out ) , 
@@ -126112,7 +152363,7 @@
     .clk_2_W_in ( p1978 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6740 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6741 ) , .clk_3_W_in ( p2228 ) , 
     .clk_3_E_in ( p2762 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6742 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6743 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6743 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_7__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6744 } ) ,
     .chanx_left_in ( sb_1__1__64_chanx_right_out ) , 
@@ -126163,7 +152414,7 @@
     .clk_2_W_in ( p1988 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6757 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6758 ) , .clk_3_W_in ( p2201 ) , 
     .clk_3_E_in ( p2877 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6759 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6760 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6760 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_7__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6761 } ) ,
     .chanx_left_in ( sb_1__1__65_chanx_right_out ) , 
@@ -126216,7 +152467,7 @@
     .clk_2_W_in ( p2016 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6772 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6773 ) , .clk_3_W_in ( p2199 ) , 
     .clk_3_E_in ( p2874 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6774 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6775 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6775 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_8__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6776 } ) ,
     .chanx_left_in ( sb_1__1__66_chanx_right_out ) , 
@@ -126270,7 +152521,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6787 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6788 ) , .clk_3_W_in ( p2612 ) , 
     .clk_3_E_in ( p2526 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6789 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6790 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6790 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_8__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6791 } ) ,
     .chanx_left_in ( sb_1__1__67_chanx_right_out ) , 
@@ -126324,7 +152575,7 @@
     .clk_2_W_out ( clk_2_wires[72] ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6805 ) , .clk_3_W_in ( p1223 ) , 
     .clk_3_E_in ( p1379 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6806 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6807 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6807 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_8__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6808 } ) ,
     .chanx_left_in ( sb_1__1__68_chanx_right_out ) , 
@@ -126378,7 +152629,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6819 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6820 ) , .clk_3_W_in ( p2173 ) , 
     .clk_3_E_in ( p2049 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6821 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6822 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6822 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_8__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6823 } ) ,
     .chanx_left_in ( sb_1__1__69_chanx_right_out ) , 
@@ -126432,7 +152683,7 @@
     .clk_2_W_out ( clk_2_wires[81] ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6837 ) , .clk_3_W_in ( p1445 ) , 
     .clk_3_E_in ( p2268 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6838 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6839 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6839 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_8__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6840 } ) ,
     .chanx_left_in ( sb_1__1__70_chanx_right_out ) , 
@@ -126486,7 +152737,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6851 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6852 ) , .clk_3_W_in ( p2177 ) , 
     .clk_3_E_in ( p2723 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6853 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6854 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6854 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_8__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6855 } ) ,
     .chanx_left_in ( sb_1__1__71_chanx_right_out ) , 
@@ -126540,7 +152791,7 @@
     .clk_3_W_in ( clk_3_wires[4] ) , 
     .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6870 ) , 
     .clk_3_E_out ( clk_3_wires[5] ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6871 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6871 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_8__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6872 } ) ,
     .chanx_left_in ( sb_1__1__72_chanx_right_out ) , 
@@ -126594,7 +152845,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6883 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6884 ) , .clk_3_W_in ( p2425 ) , 
     .clk_3_E_in ( p1985 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6885 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6886 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6886 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_8__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6887 } ) ,
     .chanx_left_in ( sb_1__1__73_chanx_right_out ) , 
@@ -126648,7 +152899,7 @@
     .clk_2_W_out ( clk_2_wires[94] ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6901 ) , .clk_3_W_in ( p1476 ) , 
     .clk_3_E_in ( p1662 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6902 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6903 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6903 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_8__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6904 } ) ,
     .chanx_left_in ( sb_1__1__74_chanx_right_out ) , 
@@ -126702,7 +152953,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6915 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6916 ) , .clk_3_W_in ( p2239 ) , 
     .clk_3_E_in ( p2893 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6917 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6918 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6918 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_8__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6919 } ) ,
     .chanx_left_in ( sb_1__1__75_chanx_right_out ) , 
@@ -126756,7 +153007,7 @@
     .clk_2_W_out ( clk_2_wires[107] ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6933 ) , .clk_3_W_in ( p1528 ) , 
     .clk_3_E_in ( p1675 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6934 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6935 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6935 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_8__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6936 } ) ,
     .chanx_left_in ( sb_1__1__76_chanx_right_out ) , 
@@ -126810,7 +153061,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6947 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6948 ) , .clk_3_W_in ( p2394 ) , 
     .clk_3_E_in ( p2752 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6949 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6950 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6950 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_9__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6951 } ) ,
     .chanx_left_in ( sb_1__1__77_chanx_right_out ) , 
@@ -126863,7 +153114,7 @@
     .clk_2_W_in ( p1987 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6962 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6963 ) , .clk_3_W_in ( p2072 ) , 
     .clk_3_E_in ( p2542 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6964 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6965 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6965 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_9__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6966 } ) ,
     .chanx_left_in ( sb_1__1__78_chanx_right_out ) , 
@@ -126917,7 +153168,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6980 ) , 
     .clk_2_E_out ( clk_2_wires[70] ) , .clk_3_W_in ( p1460 ) , 
     .clk_3_E_in ( p159 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6981 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6982 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6982 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_9__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6983 } ) ,
     .chanx_left_in ( sb_1__1__79_chanx_right_out ) , 
@@ -126970,7 +153221,7 @@
     .clk_2_W_in ( p2717 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6994 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6995 ) , .clk_3_W_in ( p2863 ) , 
     .clk_3_E_in ( p2876 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6996 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6997 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6997 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_9__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_6998 } ) ,
     .chanx_left_in ( sb_1__1__80_chanx_right_out ) , 
@@ -127024,7 +153275,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7012 ) , 
     .clk_2_E_out ( clk_2_wires[79] ) , .clk_3_W_in ( p1106 ) , 
     .clk_3_E_in ( p656 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7013 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7014 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7014 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_9__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7015 } ) ,
     .chanx_left_in ( sb_1__1__81_chanx_right_out ) , 
@@ -127077,7 +153328,7 @@
     .clk_2_W_in ( p1643 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7026 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7027 ) , .clk_3_W_in ( p1892 ) , 
     .clk_3_E_in ( p3020 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7028 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7029 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7029 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_9__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7030 } ) ,
     .chanx_left_in ( sb_1__1__82_chanx_right_out ) , 
@@ -127131,7 +153382,7 @@
     .clk_3_W_in ( clk_3_wires[44] ) , 
     .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7045 ) , 
     .clk_3_E_out ( clk_3_wires[45] ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7046 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7046 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_9__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7047 } ) ,
     .chanx_left_in ( sb_1__1__83_chanx_right_out ) , 
@@ -127184,7 +153435,7 @@
     .clk_2_W_in ( p2252 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7058 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7059 ) , .clk_3_W_in ( p2370 ) , 
     .clk_3_E_in ( p2307 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7060 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7061 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7061 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_9__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7062 } ) ,
     .chanx_left_in ( sb_1__1__84_chanx_right_out ) , 
@@ -127238,7 +153489,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7076 ) , 
     .clk_2_E_out ( clk_2_wires[92] ) , .clk_3_W_in ( p1119 ) , 
     .clk_3_E_in ( p645 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7077 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7078 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7078 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_9__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7079 } ) ,
     .chanx_left_in ( sb_1__1__85_chanx_right_out ) , 
@@ -127291,7 +153542,7 @@
     .clk_2_W_in ( p1311 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7090 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7091 ) , .clk_3_W_in ( p1569 ) , 
     .clk_3_E_in ( p2879 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7092 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7093 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7093 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_9__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7094 } ) ,
     .chanx_left_in ( sb_1__1__86_chanx_right_out ) , 
@@ -127345,7 +153596,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7108 ) , 
     .clk_2_E_out ( clk_2_wires[105] ) , .clk_3_W_in ( p1533 ) , 
     .clk_3_E_in ( p226 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7109 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7110 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7110 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_9__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7111 } ) ,
     .chanx_left_in ( sb_1__1__87_chanx_right_out ) , 
@@ -127398,7 +153649,7 @@
     .clk_2_W_in ( p2558 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7122 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7123 ) , .clk_3_W_in ( p2653 ) , 
     .clk_3_E_in ( p2766 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7124 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7125 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7125 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_10__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7126 } ) ,
     .chanx_left_in ( sb_1__1__88_chanx_right_out ) , 
@@ -127452,7 +153703,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7137 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7138 ) , .clk_3_W_in ( p1201 ) , 
     .clk_3_E_in ( p3174 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7139 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7140 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7140 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_10__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7141 } ) ,
     .chanx_left_in ( sb_1__1__89_chanx_right_out ) , 
@@ -127503,7 +153754,7 @@
     .clk_2_W_in ( p2576 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7154 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7155 ) , .clk_3_W_in ( p2592 ) , 
     .clk_3_E_in ( p2771 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7156 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7157 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7157 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_10__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7158 } ) ,
     .chanx_left_in ( sb_1__1__90_chanx_right_out ) , 
@@ -127557,7 +153808,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7169 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7170 ) , .clk_3_W_in ( p1754 ) , 
     .clk_3_E_in ( p2773 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7171 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7172 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7172 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_10__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7173 } ) ,
     .chanx_left_in ( sb_1__1__91_chanx_right_out ) , 
@@ -127608,7 +153859,7 @@
     .clk_2_W_in ( p2169 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7186 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7187 ) , .clk_3_W_in ( p2059 ) , 
     .clk_3_E_in ( p1426 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7188 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7189 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7189 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_10__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7190 } ) ,
     .chanx_left_in ( sb_1__1__92_chanx_right_out ) , 
@@ -127662,7 +153913,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7201 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7202 ) , .clk_3_W_in ( p969 ) , 
     .clk_3_E_in ( p3172 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7203 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7204 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7204 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_10__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7205 } ) ,
     .chanx_left_in ( sb_1__1__93_chanx_right_out ) , 
@@ -127716,7 +153967,7 @@
     .clk_3_W_in ( clk_3_wires[48] ) , 
     .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7220 ) , 
     .clk_3_E_out ( clk_3_wires[49] ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7221 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7221 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_10__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7222 } ) ,
     .chanx_left_in ( sb_1__1__94_chanx_right_out ) , 
@@ -127770,7 +154021,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7233 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7234 ) , .clk_3_W_in ( p2391 ) , 
     .clk_3_E_in ( p3060 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7235 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7236 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7236 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_10__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7237 } ) ,
     .chanx_left_in ( sb_1__1__95_chanx_right_out ) , 
@@ -127821,7 +154072,7 @@
     .clk_2_W_in ( p1719 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7250 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7251 ) , .clk_3_W_in ( p1924 ) , 
     .clk_3_E_in ( p3065 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7252 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7253 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7253 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_10__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7254 } ) ,
     .chanx_left_in ( sb_1__1__96_chanx_right_out ) , 
@@ -127875,7 +154126,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7265 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7266 ) , .clk_3_W_in ( p1940 ) , 
     .clk_3_E_in ( p2113 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7267 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7268 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7268 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_10__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7269 } ) ,
     .chanx_left_in ( sb_1__1__97_chanx_right_out ) , 
@@ -127926,7 +154177,7 @@
     .clk_2_W_in ( p1230 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7282 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7283 ) , .clk_3_W_in ( p1230 ) , 
     .clk_3_E_in ( p1939 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7284 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7285 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7285 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_10__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7286 } ) ,
     .chanx_left_in ( sb_1__1__98_chanx_right_out ) , 
@@ -127980,7 +154231,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7297 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7298 ) , .clk_3_W_in ( p1910 ) , 
     .clk_3_E_in ( p2360 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7299 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7300 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7300 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_11__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7301 } ) ,
     .chanx_left_in ( sb_1__1__99_chanx_right_out ) , 
@@ -128033,7 +154284,7 @@
     .clk_2_W_in ( p1370 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7312 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7313 ) , .clk_3_W_in ( p1417 ) , 
     .clk_3_E_in ( p2566 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7314 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7315 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7315 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_11__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7316 } ) ,
     .chanx_left_in ( sb_1__1__100_chanx_right_out ) , 
@@ -128087,7 +154338,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7330 ) , 
     .clk_2_E_out ( clk_2_wires[113] ) , .clk_3_W_in ( p1921 ) , 
     .clk_3_E_in ( p1233 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7331 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7332 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7332 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_11__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7333 } ) ,
     .chanx_left_in ( sb_1__1__101_chanx_right_out ) , 
@@ -128140,7 +154391,7 @@
     .clk_2_W_in ( p1390 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7344 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7345 ) , .clk_3_W_in ( p1371 ) , 
     .clk_3_E_in ( p2569 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7346 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7347 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7347 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_11__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7348 } ) ,
     .chanx_left_in ( sb_1__1__102_chanx_right_out ) , 
@@ -128194,7 +154445,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7362 ) , 
     .clk_2_E_out ( clk_2_wires[118] ) , .clk_3_W_in ( p1125 ) , 
     .clk_3_E_in ( p1103 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7363 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7364 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7364 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_11__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7365 } ) ,
     .chanx_left_in ( sb_1__1__103_chanx_right_out ) , 
@@ -128247,7 +154498,7 @@
     .clk_2_W_in ( p1256 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7376 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7377 ) , .clk_3_W_in ( p1575 ) , 
     .clk_3_E_in ( p2346 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7378 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7379 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7379 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_11__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7380 } ) ,
     .chanx_left_in ( sb_1__1__104_chanx_right_out ) , 
@@ -128298,7 +154549,7 @@
     .clk_2_W_in ( p2033 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7393 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7394 ) , .clk_3_W_in ( p2141 ) , 
     .clk_3_E_in ( p2772 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7395 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7396 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7396 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_11__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7397 } ) ,
     .chanx_left_in ( sb_1__1__105_chanx_right_out ) , 
@@ -128351,7 +154602,7 @@
     .clk_2_W_in ( p1343 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7408 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7409 ) , .clk_3_W_in ( p1554 ) , 
     .clk_3_E_in ( p3332 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7410 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7411 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7411 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_11__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7412 } ) ,
     .chanx_left_in ( sb_1__1__106_chanx_right_out ) , 
@@ -128405,7 +154656,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7426 ) , 
     .clk_2_E_out ( clk_2_wires[125] ) , .clk_3_W_in ( p1178 ) , 
     .clk_3_E_in ( p895 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7427 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7428 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7428 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_11__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7429 } ) ,
     .chanx_left_in ( sb_1__1__107_chanx_right_out ) , 
@@ -128458,7 +154709,7 @@
     .clk_2_W_in ( p2023 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7440 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7441 ) , .clk_3_W_in ( p2135 ) , 
     .clk_3_E_in ( p3164 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7442 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7443 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7443 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_11__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7444 } ) ,
     .chanx_left_in ( sb_1__1__108_chanx_right_out ) , 
@@ -128512,7 +154763,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7458 ) , 
     .clk_2_E_out ( clk_2_wires[132] ) , .clk_3_W_in ( p1513 ) , 
     .clk_3_E_in ( p1413 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7459 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7460 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7460 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_11__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7461 } ) ,
     .chanx_left_in ( sb_1__1__109_chanx_right_out ) , 
@@ -128565,7 +154816,7 @@
     .clk_2_W_in ( p2584 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7472 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7473 ) , .clk_3_W_in ( p2703 ) , 
     .clk_3_E_in ( p2029 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7474 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7475 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7475 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_12__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7476 } ) ,
     .chanx_left_in ( sb_1__1__110_chanx_right_out ) , 
@@ -128619,7 +154870,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7487 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7488 ) , .clk_3_W_in ( p2793 ) , 
     .clk_3_E_in ( p3169 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7489 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7490 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7490 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_12__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7491 } ) ,
     .chanx_left_in ( sb_1__1__111_chanx_right_out ) , 
@@ -128670,7 +154921,7 @@
     .clk_2_W_in ( p2323 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7504 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7505 ) , .clk_3_W_in ( p2449 ) , 
     .clk_3_E_in ( p2513 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7506 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7507 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7507 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_12__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7508 } ) ,
     .chanx_left_in ( sb_1__1__112_chanx_right_out ) , 
@@ -128724,7 +154975,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7519 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7520 ) , .clk_3_W_in ( p1470 ) , 
     .clk_3_E_in ( p2919 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7521 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7522 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7522 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_12__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7523 } ) ,
     .chanx_left_in ( sb_1__1__113_chanx_right_out ) , 
@@ -128775,7 +155026,7 @@
     .clk_2_W_in ( p2743 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7536 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7537 ) , .clk_3_W_in ( p2796 ) , 
     .clk_3_E_in ( p2918 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7538 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7539 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7539 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_12__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7540 } ) ,
     .chanx_left_in ( sb_1__1__114_chanx_right_out ) , 
@@ -128829,7 +155080,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7551 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7552 ) , .clk_3_W_in ( p2404 ) , 
     .clk_3_E_in ( p3049 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7553 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7554 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7554 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_12__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7555 } ) ,
     .chanx_left_in ( sb_1__1__115_chanx_right_out ) , 
@@ -128880,7 +155131,7 @@
     .clk_2_W_in ( p2525 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7568 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7569 ) , .clk_3_W_in ( p2632 ) , 
     .clk_3_E_in ( p2716 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7570 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7571 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7571 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_12__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7572 } ) ,
     .chanx_left_in ( sb_1__1__116_chanx_right_out ) , 
@@ -128934,7 +155185,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7583 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7584 ) , .clk_3_W_in ( p1827 ) , 
     .clk_3_E_in ( p2504 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7585 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7586 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7586 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_12__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7587 } ) ,
     .chanx_left_in ( sb_1__1__117_chanx_right_out ) , 
@@ -128985,7 +155236,7 @@
     .clk_2_W_in ( p1693 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7600 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7601 ) , .clk_3_W_in ( p1805 ) , 
     .clk_3_E_in ( p2344 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7602 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7603 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7603 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_12__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7604 } ) ,
     .chanx_left_in ( sb_1__1__118_chanx_right_out ) , 
@@ -129039,7 +155290,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7615 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7616 ) , .clk_3_W_in ( p2442 ) , 
     .clk_3_E_in ( p2928 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7617 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7618 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7618 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_12__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7619 } ) ,
     .chanx_left_in ( sb_1__1__119_chanx_right_out ) , 
@@ -129090,7 +155341,7 @@
     .clk_2_W_in ( p2034 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7632 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7633 ) , .clk_3_W_in ( p2226 ) , 
     .clk_3_E_in ( p3160 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7634 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7635 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7635 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__1_ cbx_12__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7636 } ) ,
     .chanx_left_in ( sb_1__1__120_chanx_right_out ) , 
@@ -129144,7 +155395,7 @@
     .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7647 ) , 
     .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7648 ) , .clk_3_W_in ( p2390 ) , 
     .clk_3_E_in ( p2281 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7649 ) , 
-    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7650 ) ) ;
+    .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7650 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2_ cbx_1__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7651 } ) ,
     .chanx_left_in ( sb_0__12__0_chanx_right_out ) , 
@@ -129183,7 +155434,7 @@
     .pReset_W_out ( pResetWires[600] ) , .pReset_S_out ( pResetWires[602] ) , 
     .pReset_E_out ( SYNOPSYS_UNCONNECTED_7654 ) , 
     .prog_clk_0_S_in ( prog_clk_0_wires[59] ) , 
-    .prog_clk_0_W_out ( prog_clk_0_wires[62] ) ) ;
+    .prog_clk_0_W_out ( prog_clk_0_wires[62] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cbx_1__2_ cbx_2__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7655 } ) ,
     .chanx_left_in ( sb_1__12__0_chanx_right_out ) , 
@@ -129222,7 +155473,8 @@
     .pReset_W_out ( pResetWires[604] ) , .pReset_S_out ( pResetWires[606] ) , 
     .pReset_E_out ( SYNOPSYS_UNCONNECTED_7658 ) , 
     .prog_clk_0_S_in ( prog_clk_0_wires[99] ) , 
-    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7659 ) ) ;
+    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7659 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2_ cbx_3__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7660 } ) ,
     .chanx_left_in ( sb_1__12__1_chanx_right_out ) , 
@@ -129261,7 +155513,8 @@
     .pReset_W_out ( pResetWires[607] ) , .pReset_S_out ( pResetWires[609] ) , 
     .pReset_E_out ( SYNOPSYS_UNCONNECTED_7663 ) , 
     .prog_clk_0_S_in ( prog_clk_0_wires[137] ) , 
-    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7664 ) ) ;
+    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7664 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2_ cbx_4__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7665 } ) ,
     .chanx_left_in ( sb_1__12__2_chanx_right_out ) , 
@@ -129300,7 +155553,8 @@
     .pReset_W_out ( pResetWires[610] ) , .pReset_S_out ( pResetWires[612] ) , 
     .pReset_E_out ( SYNOPSYS_UNCONNECTED_7668 ) , 
     .prog_clk_0_S_in ( prog_clk_0_wires[175] ) , 
-    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7669 ) ) ;
+    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7669 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2_ cbx_5__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7670 } ) ,
     .chanx_left_in ( sb_1__12__3_chanx_right_out ) , 
@@ -129339,7 +155593,8 @@
     .pReset_W_out ( pResetWires[613] ) , .pReset_S_out ( pResetWires[615] ) , 
     .pReset_E_out ( SYNOPSYS_UNCONNECTED_7673 ) , 
     .prog_clk_0_S_in ( prog_clk_0_wires[213] ) , 
-    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7674 ) ) ;
+    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7674 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2_ cbx_6__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7675 } ) ,
     .chanx_left_in ( sb_1__12__4_chanx_right_out ) , 
@@ -129378,7 +155633,8 @@
     .pReset_W_out ( pResetWires[616] ) , .pReset_S_out ( pResetWires[618] ) , 
     .pReset_E_out ( SYNOPSYS_UNCONNECTED_7678 ) , 
     .prog_clk_0_S_in ( prog_clk_0_wires[251] ) , 
-    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7679 ) ) ;
+    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7679 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2_ cbx_7__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7680 } ) ,
     .chanx_left_in ( sb_1__12__5_chanx_right_out ) , 
@@ -129417,7 +155673,8 @@
     .pReset_W_out ( SYNOPSYS_UNCONNECTED_7683 ) , 
     .pReset_S_out ( pResetWires[621] ) , .pReset_E_out ( pResetWires[620] ) , 
     .prog_clk_0_S_in ( prog_clk_0_wires[289] ) , 
-    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7684 ) ) ;
+    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7684 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2_ cbx_8__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7685 } ) ,
     .chanx_left_in ( sb_1__12__6_chanx_right_out ) , 
@@ -129456,7 +155713,8 @@
     .pReset_W_out ( SYNOPSYS_UNCONNECTED_7688 ) , 
     .pReset_S_out ( pResetWires[624] ) , .pReset_E_out ( pResetWires[623] ) , 
     .prog_clk_0_S_in ( prog_clk_0_wires[327] ) , 
-    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7689 ) ) ;
+    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7689 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2_ cbx_9__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7690 } ) ,
     .chanx_left_in ( sb_1__12__7_chanx_right_out ) , 
@@ -129495,7 +155753,8 @@
     .pReset_W_out ( SYNOPSYS_UNCONNECTED_7693 ) , 
     .pReset_S_out ( pResetWires[627] ) , .pReset_E_out ( pResetWires[626] ) , 
     .prog_clk_0_S_in ( prog_clk_0_wires[365] ) , 
-    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7694 ) ) ;
+    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7694 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2_ cbx_10__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7695 } ) ,
     .chanx_left_in ( sb_1__12__8_chanx_right_out ) , 
@@ -129534,7 +155793,8 @@
     .pReset_W_out ( SYNOPSYS_UNCONNECTED_7698 ) , 
     .pReset_S_out ( pResetWires[630] ) , .pReset_E_out ( pResetWires[629] ) , 
     .prog_clk_0_S_in ( prog_clk_0_wires[403] ) , 
-    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7699 ) ) ;
+    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7699 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2_ cbx_11__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7700 } ) ,
     .chanx_left_in ( sb_1__12__9_chanx_right_out ) , 
@@ -129573,7 +155833,8 @@
     .pReset_W_out ( SYNOPSYS_UNCONNECTED_7703 ) , 
     .pReset_S_out ( pResetWires[633] ) , .pReset_E_out ( pResetWires[632] ) , 
     .prog_clk_0_S_in ( prog_clk_0_wires[441] ) , 
-    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7704 ) ) ;
+    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7704 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cbx_1__2_ cbx_12__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7705 } ) ,
     .chanx_left_in ( sb_1__12__10_chanx_right_out ) , 
@@ -129612,7 +155873,8 @@
     .pReset_W_out ( SYNOPSYS_UNCONNECTED_7708 ) , 
     .pReset_S_out ( pResetWires[636] ) , .pReset_E_out ( pResetWires[635] ) , 
     .prog_clk_0_S_in ( prog_clk_0_wires[479] ) , 
-    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7709 ) ) ;
+    .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7709 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_0__1_ cby_0__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7710 } ) ,
     .chany_bottom_in ( sb_0__0__0_chany_top_out ) , 
@@ -129629,7 +155891,7 @@
     .right_width_0_height_0__pin_1_upper ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , 
     .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , 
     .pReset_N_in ( pResetWires[64] ) , 
-    .prog_clk_0_E_in ( prog_clk_0_wires[3] ) ) ;
+    .prog_clk_0_E_in ( prog_clk_0_wires[3] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_0__1_ cby_0__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7711 } ) ,
     .chany_bottom_in ( sb_0__1__0_chany_top_out ) , 
@@ -129646,7 +155908,7 @@
     .right_width_0_height_0__pin_1_upper ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , 
     .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , 
     .pReset_N_in ( pResetWires[113] ) , 
-    .prog_clk_0_E_in ( prog_clk_0_wires[9] ) ) ;
+    .prog_clk_0_E_in ( prog_clk_0_wires[9] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_0__1_ cby_0__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7712 } ) ,
     .chany_bottom_in ( sb_0__1__1_chany_top_out ) , 
@@ -129663,7 +155925,7 @@
     .right_width_0_height_0__pin_1_upper ( grid_io_left_2_right_width_0_height_0__pin_1_upper ) , 
     .right_width_0_height_0__pin_1_lower ( grid_io_left_2_right_width_0_height_0__pin_1_lower ) , 
     .pReset_N_in ( pResetWires[162] ) , 
-    .prog_clk_0_E_in ( prog_clk_0_wires[14] ) ) ;
+    .prog_clk_0_E_in ( prog_clk_0_wires[14] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_0__1_ cby_0__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7713 } ) ,
     .chany_bottom_in ( sb_0__1__2_chany_top_out ) , 
@@ -129680,7 +155942,7 @@
     .right_width_0_height_0__pin_1_upper ( grid_io_left_3_right_width_0_height_0__pin_1_upper ) , 
     .right_width_0_height_0__pin_1_lower ( grid_io_left_3_right_width_0_height_0__pin_1_lower ) , 
     .pReset_N_in ( pResetWires[211] ) , 
-    .prog_clk_0_E_in ( prog_clk_0_wires[19] ) ) ;
+    .prog_clk_0_E_in ( prog_clk_0_wires[19] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_0__1_ cby_0__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7714 } ) ,
     .chany_bottom_in ( sb_0__1__3_chany_top_out ) , 
@@ -129697,7 +155959,7 @@
     .right_width_0_height_0__pin_1_upper ( grid_io_left_4_right_width_0_height_0__pin_1_upper ) , 
     .right_width_0_height_0__pin_1_lower ( grid_io_left_4_right_width_0_height_0__pin_1_lower ) , 
     .pReset_N_in ( pResetWires[260] ) , 
-    .prog_clk_0_E_in ( prog_clk_0_wires[24] ) ) ;
+    .prog_clk_0_E_in ( prog_clk_0_wires[24] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_0__1_ cby_0__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7715 } ) ,
     .chany_bottom_in ( sb_0__1__4_chany_top_out ) , 
@@ -129714,7 +155976,7 @@
     .right_width_0_height_0__pin_1_upper ( grid_io_left_5_right_width_0_height_0__pin_1_upper ) , 
     .right_width_0_height_0__pin_1_lower ( grid_io_left_5_right_width_0_height_0__pin_1_lower ) , 
     .pReset_N_in ( pResetWires[309] ) , 
-    .prog_clk_0_E_in ( prog_clk_0_wires[29] ) ) ;
+    .prog_clk_0_E_in ( prog_clk_0_wires[29] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_0__1_ cby_0__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7716 } ) ,
     .chany_bottom_in ( sb_0__1__5_chany_top_out ) , 
@@ -129731,7 +155993,7 @@
     .right_width_0_height_0__pin_1_upper ( grid_io_left_6_right_width_0_height_0__pin_1_upper ) , 
     .right_width_0_height_0__pin_1_lower ( grid_io_left_6_right_width_0_height_0__pin_1_lower ) , 
     .pReset_N_in ( pResetWires[358] ) , 
-    .prog_clk_0_E_in ( prog_clk_0_wires[34] ) ) ;
+    .prog_clk_0_E_in ( prog_clk_0_wires[34] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_0__1_ cby_0__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7717 } ) ,
     .chany_bottom_in ( sb_0__1__6_chany_top_out ) , 
@@ -129748,7 +156010,7 @@
     .right_width_0_height_0__pin_1_upper ( grid_io_left_7_right_width_0_height_0__pin_1_upper ) , 
     .right_width_0_height_0__pin_1_lower ( grid_io_left_7_right_width_0_height_0__pin_1_lower ) , 
     .pReset_N_in ( pResetWires[407] ) , 
-    .prog_clk_0_E_in ( prog_clk_0_wires[39] ) ) ;
+    .prog_clk_0_E_in ( prog_clk_0_wires[39] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_0__1_ cby_0__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7718 } ) ,
     .chany_bottom_in ( sb_0__1__7_chany_top_out ) , 
@@ -129765,7 +156027,7 @@
     .right_width_0_height_0__pin_1_upper ( grid_io_left_8_right_width_0_height_0__pin_1_upper ) , 
     .right_width_0_height_0__pin_1_lower ( grid_io_left_8_right_width_0_height_0__pin_1_lower ) , 
     .pReset_N_in ( pResetWires[456] ) , 
-    .prog_clk_0_E_in ( prog_clk_0_wires[44] ) ) ;
+    .prog_clk_0_E_in ( prog_clk_0_wires[44] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_0__1_ cby_0__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7719 } ) ,
     .chany_bottom_in ( sb_0__1__8_chany_top_out ) , 
@@ -129782,7 +156044,7 @@
     .right_width_0_height_0__pin_1_upper ( grid_io_left_9_right_width_0_height_0__pin_1_upper ) , 
     .right_width_0_height_0__pin_1_lower ( grid_io_left_9_right_width_0_height_0__pin_1_lower ) , 
     .pReset_N_in ( pResetWires[505] ) , 
-    .prog_clk_0_E_in ( prog_clk_0_wires[49] ) ) ;
+    .prog_clk_0_E_in ( prog_clk_0_wires[49] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_0__1_ cby_0__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7720 } ) ,
     .chany_bottom_in ( sb_0__1__9_chany_top_out ) , 
@@ -129799,7 +156061,7 @@
     .right_width_0_height_0__pin_1_upper ( grid_io_left_10_right_width_0_height_0__pin_1_upper ) , 
     .right_width_0_height_0__pin_1_lower ( grid_io_left_10_right_width_0_height_0__pin_1_lower ) , 
     .pReset_N_in ( pResetWires[554] ) , 
-    .prog_clk_0_E_in ( prog_clk_0_wires[54] ) ) ;
+    .prog_clk_0_E_in ( prog_clk_0_wires[54] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_0__1_ cby_0__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7721 } ) ,
     .chany_bottom_in ( sb_0__1__10_chany_top_out ) , 
@@ -129816,7 +156078,7 @@
     .right_width_0_height_0__pin_1_upper ( grid_io_left_11_right_width_0_height_0__pin_1_upper ) , 
     .right_width_0_height_0__pin_1_lower ( grid_io_left_11_right_width_0_height_0__pin_1_lower ) , 
     .pReset_N_in ( pResetWires[603] ) , 
-    .prog_clk_0_E_in ( prog_clk_0_wires[61] ) ) ;
+    .prog_clk_0_E_in ( prog_clk_0_wires[61] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_1__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7722 } ) ,
     .chany_bottom_in ( sb_1__0__0_chany_top_out ) , 
@@ -129867,7 +156129,7 @@
     .clk_2_S_in ( p2347 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7737 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7738 ) , .clk_3_S_in ( p2466 ) , 
     .clk_3_N_in ( p935 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7739 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7740 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7740 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_1__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7741 } ) ,
     .chany_bottom_in ( sb_1__1__0_chany_top_out ) , 
@@ -129921,7 +156183,7 @@
     .clk_2_S_out ( clk_2_wires[4] ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7757 ) , .clk_3_S_in ( p2459 ) , 
     .clk_3_N_in ( p687 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7758 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7759 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7759 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_1__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7760 } ) ,
     .chany_bottom_in ( sb_1__1__1_chany_top_out ) , 
@@ -129972,7 +156234,7 @@
     .clk_2_S_in ( p3138 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7775 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7776 ) , .clk_3_S_in ( p3212 ) , 
     .clk_3_N_in ( p1158 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7777 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7778 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7778 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_1__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7779 } ) ,
     .chany_bottom_in ( sb_1__1__2_chany_top_out ) , 
@@ -130026,7 +156288,7 @@
     .clk_2_S_out ( clk_2_wires[11] ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7795 ) , .clk_3_S_in ( p1772 ) , 
     .clk_3_N_in ( p306 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7796 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7797 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7797 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_1__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7798 } ) ,
     .chany_bottom_in ( sb_1__1__3_chany_top_out ) , 
@@ -130080,7 +156342,7 @@
     .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7814 ) , 
     .clk_2_N_out ( clk_2_wires[9] ) , .clk_3_S_in ( p1869 ) , 
     .clk_3_N_in ( p478 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7815 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7816 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7816 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_1__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7817 } ) ,
     .chany_bottom_in ( sb_1__1__4_chany_top_out ) , 
@@ -130131,7 +156393,7 @@
     .clk_2_S_in ( p2775 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7832 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7833 ) , .clk_3_S_in ( p2859 ) , 
     .clk_3_N_in ( p571 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7834 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7835 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7835 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_1__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7836 } ) ,
     .chany_bottom_in ( sb_1__1__5_chany_top_out ) , 
@@ -130182,7 +156444,7 @@
     .clk_2_S_in ( p2559 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7851 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7852 ) , .clk_3_S_in ( p2619 ) , 
     .clk_3_N_in ( p624 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7853 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7854 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7854 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_1__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7855 } ) ,
     .chany_bottom_in ( sb_1__1__6_chany_top_out ) , 
@@ -130236,7 +156498,7 @@
     .clk_2_S_out ( clk_2_wires[18] ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7871 ) , .clk_3_S_in ( p2184 ) , 
     .clk_3_N_in ( p840 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7872 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7873 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7873 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_1__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7874 } ) ,
     .chany_bottom_in ( sb_1__1__7_chany_top_out ) , 
@@ -130290,7 +156552,7 @@
     .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7890 ) , 
     .clk_2_N_out ( clk_2_wires[16] ) , .clk_3_S_in ( p1588 ) , 
     .clk_3_N_in ( p844 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7891 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7892 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7892 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_1__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7893 } ) ,
     .chany_bottom_in ( sb_1__1__8_chany_top_out ) , 
@@ -130341,7 +156603,7 @@
     .clk_2_S_in ( p1732 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7908 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7909 ) , .clk_3_S_in ( p1880 ) , 
     .clk_3_N_in ( p386 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7910 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7911 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7911 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_1__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7912 } ) ,
     .chany_bottom_in ( sb_1__1__9_chany_top_out ) , 
@@ -130395,7 +156657,7 @@
     .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7928 ) , 
     .clk_2_N_out ( clk_2_wires[23] ) , .clk_3_S_in ( p1868 ) , 
     .clk_3_N_in ( p921 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7929 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7930 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7930 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_1__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7931 } ) ,
     .chany_bottom_in ( sb_1__1__10_chany_top_out ) , 
@@ -130446,7 +156708,7 @@
     .clk_2_S_in ( p2923 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7945 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7946 ) , .clk_3_S_in ( p2973 ) , 
     .clk_3_N_in ( p2008 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7947 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7948 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7948 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_2__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7949 } ) ,
     .chany_bottom_in ( sb_1__0__1_chany_top_out ) , 
@@ -130497,7 +156759,7 @@
     .clk_2_S_in ( p3143 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7964 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7965 ) , .clk_3_S_in ( p3181 ) , 
     .clk_3_N_in ( p1280 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7966 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7967 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7967 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_2__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7968 } ) ,
     .chany_bottom_in ( sb_1__1__11_chany_top_out ) , 
@@ -130548,7 +156810,7 @@
     .clk_2_S_in ( p2917 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7983 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7984 ) , .clk_3_S_in ( p2947 ) , 
     .clk_3_N_in ( p1 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7985 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7986 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7986 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_2__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_7987 } ) ,
     .chany_bottom_in ( sb_1__1__12_chany_top_out ) , 
@@ -130602,7 +156864,7 @@
     .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8004 ) , 
     .clk_3_N_in ( clk_3_wires[68] ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8005 ) , 
-    .clk_3_S_out ( clk_3_wires[69] ) ) ;
+    .clk_3_S_out ( clk_3_wires[69] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_2__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8006 } ) ,
     .chany_bottom_in ( sb_1__1__13_chany_top_out ) , 
@@ -130656,7 +156918,7 @@
     .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8023 ) , 
     .clk_3_N_in ( clk_3_wires[64] ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8024 ) , 
-    .clk_3_S_out ( clk_3_wires[65] ) ) ;
+    .clk_3_S_out ( clk_3_wires[65] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_2__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8025 } ) ,
     .chany_bottom_in ( sb_1__1__14_chany_top_out ) , 
@@ -130710,7 +156972,7 @@
     .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8042 ) , 
     .clk_3_N_in ( clk_3_wires[58] ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8043 ) , 
-    .clk_3_S_out ( clk_3_wires[59] ) ) ;
+    .clk_3_S_out ( clk_3_wires[59] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_2__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8044 } ) ,
     .chany_bottom_in ( sb_1__1__15_chany_top_out ) , 
@@ -130764,7 +157026,7 @@
     .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8061 ) , 
     .clk_3_N_in ( clk_3_wires[54] ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8062 ) , 
-    .clk_3_S_out ( clk_3_wires[55] ) ) ;
+    .clk_3_S_out ( clk_3_wires[55] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_2__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8063 } ) ,
     .chany_bottom_in ( sb_1__1__16_chany_top_out ) , 
@@ -130818,7 +157080,7 @@
     .clk_3_S_in ( clk_3_wires[52] ) , 
     .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8080 ) , 
     .clk_3_N_out ( clk_3_wires[53] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8081 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8081 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_2__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8082 } ) ,
     .chany_bottom_in ( sb_1__1__17_chany_top_out ) , 
@@ -130872,7 +157134,7 @@
     .clk_3_S_in ( clk_3_wires[56] ) , 
     .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8099 ) , 
     .clk_3_N_out ( clk_3_wires[57] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8100 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8100 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_2__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8101 } ) ,
     .chany_bottom_in ( sb_1__1__18_chany_top_out ) , 
@@ -130926,7 +157188,7 @@
     .clk_3_S_in ( clk_3_wires[62] ) , 
     .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8118 ) , 
     .clk_3_N_out ( clk_3_wires[63] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8119 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8119 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_2__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8120 } ) ,
     .chany_bottom_in ( sb_1__1__19_chany_top_out ) , 
@@ -130980,7 +157242,7 @@
     .clk_3_S_in ( clk_3_wires[66] ) , 
     .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8137 ) , 
     .clk_3_N_out ( clk_3_wires[67] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8138 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8138 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_2__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8139 } ) ,
     .chany_bottom_in ( sb_1__1__20_chany_top_out ) , 
@@ -131031,7 +157293,7 @@
     .clk_2_S_in ( p3166 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8154 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8155 ) , .clk_3_S_in ( p3210 ) , 
     .clk_3_N_in ( p859 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8156 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8157 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8157 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_2__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8158 } ) ,
     .chany_bottom_in ( sb_1__1__21_chany_top_out ) , 
@@ -131082,7 +157344,7 @@
     .clk_2_S_in ( p1971 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8172 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8173 ) , .clk_3_S_in ( p2218 ) , 
     .clk_3_N_in ( p1740 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8174 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8175 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8175 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_3__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8176 } ) ,
     .chany_bottom_in ( sb_1__0__2_chany_top_out ) , 
@@ -131133,7 +157395,7 @@
     .clk_2_S_in ( p2514 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8191 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8192 ) , .clk_3_S_in ( p2670 ) , 
     .clk_3_N_in ( p36 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8193 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8194 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8194 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_3__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8195 } ) ,
     .chany_bottom_in ( sb_1__1__22_chany_top_out ) , 
@@ -131187,7 +157449,7 @@
     .clk_2_S_out ( clk_2_wires[30] ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8211 ) , .clk_3_S_in ( p1762 ) , 
     .clk_3_N_in ( p84 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8212 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8213 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8213 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_3__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8214 } ) ,
     .chany_bottom_in ( sb_1__1__23_chany_top_out ) , 
@@ -131238,7 +157500,7 @@
     .clk_2_S_in ( p2042 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8229 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8230 ) , .clk_3_S_in ( p2196 ) , 
     .clk_3_N_in ( p436 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8231 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8232 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8232 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_3__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8233 } ) ,
     .chany_bottom_in ( sb_1__1__24_chany_top_out ) , 
@@ -131292,7 +157554,7 @@
     .clk_2_S_out ( clk_2_wires[41] ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8249 ) , .clk_3_S_in ( p1860 ) , 
     .clk_3_N_in ( p484 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8250 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8251 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8251 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_3__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8252 } ) ,
     .chany_bottom_in ( sb_1__1__25_chany_top_out ) , 
@@ -131346,7 +157608,7 @@
     .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8268 ) , 
     .clk_2_N_out ( clk_2_wires[39] ) , .clk_3_S_in ( p1839 ) , 
     .clk_3_N_in ( p988 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8269 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8270 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8270 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_3__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8271 } ) ,
     .chany_bottom_in ( sb_1__1__26_chany_top_out ) , 
@@ -131397,7 +157659,7 @@
     .clk_2_S_in ( p2722 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8286 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8287 ) , .clk_3_S_in ( p2833 ) , 
     .clk_3_N_in ( p439 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8288 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8289 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8289 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_3__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8290 } ) ,
     .chany_bottom_in ( sb_1__1__27_chany_top_out ) , 
@@ -131448,7 +157710,7 @@
     .clk_2_S_in ( p2519 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8305 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8306 ) , .clk_3_S_in ( p2499 ) , 
     .clk_3_N_in ( p612 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8307 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8308 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8308 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_3__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8309 } ) ,
     .chany_bottom_in ( sb_1__1__28_chany_top_out ) , 
@@ -131502,7 +157764,7 @@
     .clk_2_S_out ( clk_2_wires[54] ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8325 ) , .clk_3_S_in ( p2133 ) , 
     .clk_3_N_in ( p342 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8326 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8327 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8327 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_3__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8328 } ) ,
     .chany_bottom_in ( sb_1__1__29_chany_top_out ) , 
@@ -131556,7 +157818,7 @@
     .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8344 ) , 
     .clk_2_N_out ( clk_2_wires[52] ) , .clk_3_S_in ( p1909 ) , 
     .clk_3_N_in ( p510 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8345 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8346 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8346 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_3__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8347 } ) ,
     .chany_bottom_in ( sb_1__1__30_chany_top_out ) , 
@@ -131607,7 +157869,7 @@
     .clk_2_S_in ( p2503 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8362 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8363 ) , .clk_3_S_in ( p2609 ) , 
     .clk_3_N_in ( p336 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8364 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8365 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8365 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_3__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8366 } ) ,
     .chany_bottom_in ( sb_1__1__31_chany_top_out ) , 
@@ -131661,7 +157923,7 @@
     .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8382 ) , 
     .clk_2_N_out ( clk_2_wires[65] ) , .clk_3_S_in ( p1433 ) , 
     .clk_3_N_in ( p356 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8383 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8384 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8384 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_3__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8385 } ) ,
     .chany_bottom_in ( sb_1__1__32_chany_top_out ) , 
@@ -131712,7 +157974,7 @@
     .clk_2_S_in ( p2330 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8399 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8400 ) , .clk_3_S_in ( p2426 ) , 
     .clk_3_N_in ( p341 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8401 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8402 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8402 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_4__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8403 } ) ,
     .chany_bottom_in ( sb_1__0__3_chany_top_out ) , 
@@ -131763,7 +158025,7 @@
     .clk_2_S_in ( p2735 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8418 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8419 ) , .clk_3_S_in ( p2792 ) , 
     .clk_3_N_in ( p357 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8420 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8421 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8421 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_4__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8422 } ) ,
     .chany_bottom_in ( sb_1__1__33_chany_top_out ) , 
@@ -131814,7 +158076,7 @@
     .clk_2_S_in ( p2586 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8437 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8438 ) , .clk_3_S_in ( p2620 ) , 
     .clk_3_N_in ( p101 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8439 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8440 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8440 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_4__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8441 } ) ,
     .chany_bottom_in ( sb_1__1__34_chany_top_out ) , 
@@ -131868,7 +158130,7 @@
     .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8458 ) , 
     .clk_3_N_in ( clk_3_wires[24] ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8459 ) , 
-    .clk_3_S_out ( clk_3_wires[25] ) ) ;
+    .clk_3_S_out ( clk_3_wires[25] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_4__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8460 } ) ,
     .chany_bottom_in ( sb_1__1__35_chany_top_out ) , 
@@ -131922,7 +158184,7 @@
     .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8477 ) , 
     .clk_3_N_in ( clk_3_wires[20] ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8478 ) , 
-    .clk_3_S_out ( clk_3_wires[21] ) ) ;
+    .clk_3_S_out ( clk_3_wires[21] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_4__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8479 } ) ,
     .chany_bottom_in ( sb_1__1__36_chany_top_out ) , 
@@ -131976,7 +158238,7 @@
     .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8496 ) , 
     .clk_3_N_in ( clk_3_wires[14] ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8497 ) , 
-    .clk_3_S_out ( clk_3_wires[15] ) ) ;
+    .clk_3_S_out ( clk_3_wires[15] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_4__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8498 } ) ,
     .chany_bottom_in ( sb_1__1__37_chany_top_out ) , 
@@ -132030,7 +158292,7 @@
     .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8515 ) , 
     .clk_3_N_in ( clk_3_wires[10] ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8516 ) , 
-    .clk_3_S_out ( clk_3_wires[11] ) ) ;
+    .clk_3_S_out ( clk_3_wires[11] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_4__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8517 } ) ,
     .chany_bottom_in ( sb_1__1__38_chany_top_out ) , 
@@ -132084,7 +158346,7 @@
     .clk_3_S_in ( clk_3_wires[8] ) , 
     .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8534 ) , 
     .clk_3_N_out ( clk_3_wires[9] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8535 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8535 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_4__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8536 } ) ,
     .chany_bottom_in ( sb_1__1__39_chany_top_out ) , 
@@ -132138,7 +158400,7 @@
     .clk_3_S_in ( clk_3_wires[12] ) , 
     .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8553 ) , 
     .clk_3_N_out ( clk_3_wires[13] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8554 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8554 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_4__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8555 } ) ,
     .chany_bottom_in ( sb_1__1__40_chany_top_out ) , 
@@ -132192,7 +158454,7 @@
     .clk_3_S_in ( clk_3_wires[18] ) , 
     .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8572 ) , 
     .clk_3_N_out ( clk_3_wires[19] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8573 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8573 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_4__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8574 } ) ,
     .chany_bottom_in ( sb_1__1__41_chany_top_out ) , 
@@ -132246,7 +158508,7 @@
     .clk_3_S_in ( clk_3_wires[22] ) , 
     .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8591 ) , 
     .clk_3_N_out ( clk_3_wires[23] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8592 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8592 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_4__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8593 } ) ,
     .chany_bottom_in ( sb_1__1__42_chany_top_out ) , 
@@ -132297,7 +158559,7 @@
     .clk_2_S_in ( p2269 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8608 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8609 ) , .clk_3_S_in ( p2496 ) , 
     .clk_3_N_in ( p1652 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8610 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8611 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8611 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_4__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8612 } ) ,
     .chany_bottom_in ( sb_1__1__43_chany_top_out ) , 
@@ -132348,7 +158610,7 @@
     .clk_2_S_in ( p2719 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8626 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8627 ) , .clk_3_S_in ( p2800 ) , 
     .clk_3_N_in ( p412 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8628 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8629 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8629 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_5__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8630 } ) ,
     .chany_bottom_in ( sb_1__0__4_chany_top_out ) , 
@@ -132399,7 +158661,7 @@
     .clk_2_S_in ( p1999 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8645 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8646 ) , .clk_3_S_in ( p2217 ) , 
     .clk_3_N_in ( p902 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8647 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8648 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8648 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_5__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8649 } ) ,
     .chany_bottom_in ( sb_1__1__44_chany_top_out ) , 
@@ -132453,7 +158715,7 @@
     .clk_2_S_out ( clk_2_wires[32] ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8665 ) , .clk_3_S_in ( p1792 ) , 
     .clk_3_N_in ( p418 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8666 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8667 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8667 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_5__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8668 } ) ,
     .chany_bottom_in ( sb_1__1__45_chany_top_out ) , 
@@ -132504,7 +158766,7 @@
     .clk_2_S_in ( p2933 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8683 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8684 ) , .clk_3_S_in ( p2948 ) , 
     .clk_3_N_in ( p1019 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8685 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8686 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8686 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_5__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8687 } ) ,
     .chany_bottom_in ( sb_1__1__46_chany_top_out ) , 
@@ -132558,7 +158820,7 @@
     .clk_2_S_out ( clk_2_wires[45] ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8703 ) , .clk_3_S_in ( p1504 ) , 
     .clk_3_N_in ( p310 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8704 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8705 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8705 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_5__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8706 } ) ,
     .chany_bottom_in ( sb_1__1__47_chany_top_out ) , 
@@ -132612,7 +158874,7 @@
     .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8722 ) , 
     .clk_2_N_out ( clk_2_wires[43] ) , .clk_3_S_in ( p2396 ) , 
     .clk_3_N_in ( p683 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8723 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8724 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8724 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_5__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8725 } ) ,
     .chany_bottom_in ( sb_1__1__48_chany_top_out ) , 
@@ -132663,7 +158925,7 @@
     .clk_2_S_in ( p2579 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8740 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8741 ) , .clk_3_S_in ( p2625 ) , 
     .clk_3_N_in ( p534 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8742 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8743 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8743 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_5__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8744 } ) ,
     .chany_bottom_in ( sb_1__1__49_chany_top_out ) , 
@@ -132714,7 +158976,7 @@
     .clk_2_S_in ( p2587 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8759 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8760 ) , .clk_3_S_in ( p2593 ) , 
     .clk_3_N_in ( p96 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8761 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8762 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8762 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_5__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8763 } ) ,
     .chany_bottom_in ( sb_1__1__50_chany_top_out ) , 
@@ -132768,7 +159030,7 @@
     .clk_2_S_out ( clk_2_wires[58] ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8779 ) , .clk_3_S_in ( p1054 ) , 
     .clk_3_N_in ( p154 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8780 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8781 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8781 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_5__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8782 } ) ,
     .chany_bottom_in ( sb_1__1__51_chany_top_out ) , 
@@ -132822,7 +159084,7 @@
     .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8798 ) , 
     .clk_2_N_out ( clk_2_wires[56] ) , .clk_3_S_in ( p1808 ) , 
     .clk_3_N_in ( p279 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8799 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8800 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8800 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_5__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8801 } ) ,
     .chany_bottom_in ( sb_1__1__52_chany_top_out ) , 
@@ -132873,7 +159135,7 @@
     .clk_2_S_in ( p2913 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8816 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8817 ) , .clk_3_S_in ( p3012 ) , 
     .clk_3_N_in ( p894 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8818 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8819 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8819 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_5__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8820 } ) ,
     .chany_bottom_in ( sb_1__1__53_chany_top_out ) , 
@@ -132927,7 +159189,7 @@
     .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8836 ) , 
     .clk_2_N_out ( clk_2_wires[67] ) , .clk_3_S_in ( p2241 ) , 
     .clk_3_N_in ( p53 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8837 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8838 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8838 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_5__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8839 } ) ,
     .chany_bottom_in ( sb_1__1__54_chany_top_out ) , 
@@ -132978,7 +159240,7 @@
     .clk_2_S_in ( p2005 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8853 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8854 ) , .clk_3_S_in ( p2161 ) , 
     .clk_3_N_in ( p1717 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8855 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8856 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8856 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_6__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8857 } ) ,
     .chany_bottom_in ( sb_1__0__5_chany_top_out ) , 
@@ -133028,7 +159290,7 @@
     .clk_3_S_in ( clk_3_wires[90] ) , 
     .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8869 ) , 
     .clk_3_N_out ( clk_3_wires[89] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8870 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8870 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_6__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8871 } ) ,
     .chany_bottom_in ( sb_1__1__55_chany_top_out ) , 
@@ -133078,7 +159340,7 @@
     .clk_3_S_in ( clk_3_wires[92] ) , 
     .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8883 ) , 
     .clk_3_N_out ( clk_3_wires[91] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8884 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8884 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_6__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8885 } ) ,
     .chany_bottom_in ( sb_1__1__56_chany_top_out ) , 
@@ -133128,7 +159390,7 @@
     .clk_3_S_in ( clk_3_wires[94] ) , 
     .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8897 ) , 
     .clk_3_N_out ( clk_3_wires[93] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8898 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8898 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_6__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8899 } ) ,
     .chany_bottom_in ( sb_1__1__57_chany_top_out ) , 
@@ -133178,7 +159440,7 @@
     .clk_3_S_in ( clk_3_wires[96] ) , 
     .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8911 ) , 
     .clk_3_N_out ( clk_3_wires[95] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8912 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8912 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_6__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8913 } ) ,
     .chany_bottom_in ( sb_1__1__58_chany_top_out ) , 
@@ -133229,7 +159491,7 @@
     .clk_3_S_in ( clk_3_wires[98] ) , 
     .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8925 ) , 
     .clk_3_N_out ( clk_3_wires[97] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8926 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8926 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_6__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8927 } ) ,
     .chany_bottom_in ( sb_1__1__59_chany_top_out ) , 
@@ -133280,7 +159542,7 @@
     .clk_3_S_in ( clk_3_wires[100] ) , 
     .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8939 ) , 
     .clk_3_N_out ( clk_3_wires[99] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8940 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8940 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_6__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8941 } ) ,
     .chany_bottom_in ( sb_1__1__60_chany_top_out ) , 
@@ -133328,7 +159590,7 @@
     .clk_2_S_in ( p2060 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8951 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8952 ) , .clk_3_S_in ( p1475 ) , 
     .clk_3_N_in ( p481 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8953 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8954 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8954 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_6__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8955 } ) ,
     .chany_bottom_in ( sb_1__1__61_chany_top_out ) , 
@@ -133376,7 +159638,7 @@
     .clk_2_S_in ( p2257 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8965 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8966 ) , .clk_3_S_in ( p2457 ) , 
     .clk_3_N_in ( p768 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8967 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8968 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8968 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_6__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8969 } ) ,
     .chany_bottom_in ( sb_1__1__62_chany_top_out ) , 
@@ -133424,7 +159686,7 @@
     .clk_2_S_in ( p2765 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8979 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8980 ) , .clk_3_S_in ( p2810 ) , 
     .clk_3_N_in ( p1042 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8981 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8982 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8982 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_6__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8983 } ) ,
     .chany_bottom_in ( sb_1__1__63_chany_top_out ) , 
@@ -133472,7 +159734,7 @@
     .clk_2_S_in ( p2888 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8993 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8994 ) , .clk_3_S_in ( p2937 ) , 
     .clk_3_N_in ( p497 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8995 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8996 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8996 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_6__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_8997 } ) ,
     .chany_bottom_in ( sb_1__1__64_chany_top_out ) , 
@@ -133520,7 +159782,7 @@
     .clk_2_S_in ( p2266 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9007 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9008 ) , .clk_3_S_in ( p2397 ) , 
     .clk_3_N_in ( p1272 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9009 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9010 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9010 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_6__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9011 } ) ,
     .chany_bottom_in ( sb_1__1__65_chany_top_out ) , 
@@ -133568,7 +159830,7 @@
     .clk_2_S_in ( p2562 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9022 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9023 ) , .clk_3_S_in ( p2511 ) , 
     .clk_3_N_in ( p214 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9024 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9025 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9025 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_7__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9026 } ) ,
     .chany_bottom_in ( sb_1__0__6_chany_top_out ) , 
@@ -133618,7 +159880,7 @@
     .clk_2_S_in ( p3038 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9041 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9042 ) , .clk_3_S_in ( p3083 ) , 
     .clk_3_N_in ( p393 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9043 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9044 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9044 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_7__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9045 } ) ,
     .chany_bottom_in ( sb_1__1__66_chany_top_out ) , 
@@ -133671,7 +159933,7 @@
     .clk_2_S_out ( clk_2_wires[74] ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9061 ) , .clk_3_S_in ( p1890 ) , 
     .clk_3_N_in ( p379 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9062 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9063 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9063 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_7__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9064 } ) ,
     .chany_bottom_in ( sb_1__1__67_chany_top_out ) , 
@@ -133721,7 +159983,7 @@
     .clk_2_S_in ( p2302 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9079 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9080 ) , .clk_3_S_in ( p2399 ) , 
     .clk_3_N_in ( p1007 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9081 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9082 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9082 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_7__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9083 } ) ,
     .chany_bottom_in ( sb_1__1__68_chany_top_out ) , 
@@ -133774,7 +160036,7 @@
     .clk_2_S_out ( clk_2_wires[85] ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9099 ) , .clk_3_S_in ( p2216 ) , 
     .clk_3_N_in ( p765 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9100 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9101 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9101 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_7__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9102 } ) ,
     .chany_bottom_in ( sb_1__1__69_chany_top_out ) , 
@@ -133827,7 +160089,7 @@
     .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9118 ) , 
     .clk_2_N_out ( clk_2_wires[83] ) , .clk_3_S_in ( p1164 ) , 
     .clk_3_N_in ( p24 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9119 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9120 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9120 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_7__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9121 } ) ,
     .chany_bottom_in ( sb_1__1__70_chany_top_out ) , 
@@ -133877,7 +160139,7 @@
     .clk_2_S_in ( p1712 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9136 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9137 ) , .clk_3_S_in ( p1836 ) , 
     .clk_3_N_in ( p1094 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9138 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9139 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9139 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_7__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9140 } ) ,
     .chany_bottom_in ( sb_1__1__71_chany_top_out ) , 
@@ -133927,7 +160189,7 @@
     .clk_2_S_in ( p2932 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9155 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9156 ) , .clk_3_S_in ( p2817 ) , 
     .clk_3_N_in ( p794 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9157 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9158 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9158 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_7__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9159 } ) ,
     .chany_bottom_in ( sb_1__1__72_chany_top_out ) , 
@@ -133980,7 +160242,7 @@
     .clk_2_S_out ( clk_2_wires[98] ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9175 ) , .clk_3_S_in ( p1821 ) , 
     .clk_3_N_in ( p970 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9176 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9177 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9177 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_7__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9178 } ) ,
     .chany_bottom_in ( sb_1__1__73_chany_top_out ) , 
@@ -134033,7 +160295,7 @@
     .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9194 ) , 
     .clk_2_N_out ( clk_2_wires[96] ) , .clk_3_S_in ( p2352 ) , 
     .clk_3_N_in ( p122 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9195 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9196 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9196 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_7__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9197 } ) ,
     .chany_bottom_in ( sb_1__1__74_chany_top_out ) , 
@@ -134083,7 +160345,7 @@
     .clk_2_S_in ( p3260 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9212 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9213 ) , .clk_3_S_in ( p3261 ) , 
     .clk_3_N_in ( p382 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9214 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9215 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9215 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_7__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9216 } ) ,
     .chany_bottom_in ( sb_1__1__75_chany_top_out ) , 
@@ -134136,7 +160398,7 @@
     .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9232 ) , 
     .clk_2_N_out ( clk_2_wires[109] ) , .clk_3_S_in ( p1818 ) , 
     .clk_3_N_in ( p960 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9233 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9234 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9234 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_7__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9235 } ) ,
     .chany_bottom_in ( sb_1__1__76_chany_top_out ) , 
@@ -134186,7 +160448,7 @@
     .clk_2_S_in ( p2336 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9249 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9250 ) , .clk_3_S_in ( p2388 ) , 
     .clk_3_N_in ( p1956 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9251 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9252 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9252 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_8__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9253 } ) ,
     .chany_bottom_in ( sb_1__0__7_chany_top_out ) , 
@@ -134236,7 +160498,7 @@
     .clk_2_S_in ( p3034 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9268 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9269 ) , .clk_3_S_in ( p3088 ) , 
     .clk_3_N_in ( p1677 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9270 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9271 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9271 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_8__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9272 } ) ,
     .chany_bottom_in ( sb_1__1__77_chany_top_out ) , 
@@ -134286,7 +160548,7 @@
     .clk_2_S_in ( p1729 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9287 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9288 ) , .clk_3_S_in ( p1784 ) , 
     .clk_3_N_in ( p338 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9289 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9290 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9290 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_8__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9291 } ) ,
     .chany_bottom_in ( sb_1__1__78_chany_top_out ) , 
@@ -134339,7 +160601,7 @@
     .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9308 ) , 
     .clk_3_N_in ( clk_3_wires[42] ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9309 ) , 
-    .clk_3_S_out ( clk_3_wires[43] ) ) ;
+    .clk_3_S_out ( clk_3_wires[43] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_8__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9310 } ) ,
     .chany_bottom_in ( sb_1__1__79_chany_top_out ) , 
@@ -134392,7 +160654,7 @@
     .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9327 ) , 
     .clk_3_N_in ( clk_3_wires[38] ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9328 ) , 
-    .clk_3_S_out ( clk_3_wires[39] ) ) ;
+    .clk_3_S_out ( clk_3_wires[39] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_8__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9329 } ) ,
     .chany_bottom_in ( sb_1__1__80_chany_top_out ) , 
@@ -134445,7 +160707,7 @@
     .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9346 ) , 
     .clk_3_N_in ( clk_3_wires[32] ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9347 ) , 
-    .clk_3_S_out ( clk_3_wires[33] ) ) ;
+    .clk_3_S_out ( clk_3_wires[33] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_8__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9348 } ) ,
     .chany_bottom_in ( sb_1__1__81_chany_top_out ) , 
@@ -134498,7 +160760,7 @@
     .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9365 ) , 
     .clk_3_N_in ( clk_3_wires[28] ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9366 ) , 
-    .clk_3_S_out ( clk_3_wires[29] ) ) ;
+    .clk_3_S_out ( clk_3_wires[29] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_8__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9367 } ) ,
     .chany_bottom_in ( sb_1__1__82_chany_top_out ) , 
@@ -134551,7 +160813,7 @@
     .clk_3_S_in ( clk_3_wires[26] ) , 
     .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9384 ) , 
     .clk_3_N_out ( clk_3_wires[27] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9385 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9385 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_8__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9386 } ) ,
     .chany_bottom_in ( sb_1__1__83_chany_top_out ) , 
@@ -134604,7 +160866,7 @@
     .clk_3_S_in ( clk_3_wires[30] ) , 
     .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9403 ) , 
     .clk_3_N_out ( clk_3_wires[31] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9404 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9404 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_8__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9405 } ) ,
     .chany_bottom_in ( sb_1__1__84_chany_top_out ) , 
@@ -134657,7 +160919,7 @@
     .clk_3_S_in ( clk_3_wires[36] ) , 
     .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9422 ) , 
     .clk_3_N_out ( clk_3_wires[37] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9423 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9423 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_8__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9424 } ) ,
     .chany_bottom_in ( sb_1__1__85_chany_top_out ) , 
@@ -134710,7 +160972,7 @@
     .clk_3_S_in ( clk_3_wires[40] ) , 
     .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9441 ) , 
     .clk_3_N_out ( clk_3_wires[41] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9442 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9442 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_8__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9443 } ) ,
     .chany_bottom_in ( sb_1__1__86_chany_top_out ) , 
@@ -134760,7 +161022,7 @@
     .clk_2_S_in ( p2889 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9458 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9459 ) , .clk_3_S_in ( p2969 ) , 
     .clk_3_N_in ( p1283 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9460 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9461 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9461 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_8__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9462 } ) ,
     .chany_bottom_in ( sb_1__1__87_chany_top_out ) , 
@@ -134810,7 +161072,7 @@
     .clk_2_S_in ( p2924 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9476 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9477 ) , .clk_3_S_in ( p2936 ) , 
     .clk_3_N_in ( p137 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9478 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9479 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9479 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_9__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9480 } ) ,
     .chany_bottom_in ( sb_1__0__8_chany_top_out ) , 
@@ -134860,7 +161122,7 @@
     .clk_2_S_in ( p1285 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9495 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9496 ) , .clk_3_S_in ( p1410 ) , 
     .clk_3_N_in ( p303 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9497 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9498 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9498 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_9__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9499 } ) ,
     .chany_bottom_in ( sb_1__1__88_chany_top_out ) , 
@@ -134913,7 +161175,7 @@
     .clk_2_S_out ( clk_2_wires[76] ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9515 ) , .clk_3_S_in ( p2081 ) , 
     .clk_3_N_in ( p643 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9516 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9517 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9517 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_9__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9518 } ) ,
     .chany_bottom_in ( sb_1__1__89_chany_top_out ) , 
@@ -134963,7 +161225,7 @@
     .clk_2_S_in ( p1284 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9533 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9534 ) , .clk_3_S_in ( p1581 ) , 
     .clk_3_N_in ( p625 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9535 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9536 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9536 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_9__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9537 } ) ,
     .chany_bottom_in ( sb_1__1__90_chany_top_out ) , 
@@ -135016,7 +161278,7 @@
     .clk_2_S_out ( clk_2_wires[89] ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9553 ) , .clk_3_S_in ( p2188 ) , 
     .clk_3_N_in ( p59 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9554 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9555 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9555 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_9__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9556 } ) ,
     .chany_bottom_in ( sb_1__1__91_chany_top_out ) , 
@@ -135069,7 +161331,7 @@
     .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9572 ) , 
     .clk_2_N_out ( clk_2_wires[87] ) , .clk_3_S_in ( p2439 ) , 
     .clk_3_N_in ( p937 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9573 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9574 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9574 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_9__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9575 } ) ,
     .chany_bottom_in ( sb_1__1__92_chany_top_out ) , 
@@ -135119,7 +161381,7 @@
     .clk_2_S_in ( p2581 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9590 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9591 ) , .clk_3_S_in ( p2606 ) , 
     .clk_3_N_in ( p10 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9592 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9593 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9593 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_9__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9594 } ) ,
     .chany_bottom_in ( sb_1__1__93_chany_top_out ) , 
@@ -135169,7 +161431,7 @@
     .clk_2_S_in ( p2902 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9609 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9610 ) , .clk_3_S_in ( p2993 ) , 
     .clk_3_N_in ( p739 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9611 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9612 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9612 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_9__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9613 } ) ,
     .chany_bottom_in ( sb_1__1__94_chany_top_out ) , 
@@ -135222,7 +161484,7 @@
     .clk_2_S_out ( clk_2_wires[102] ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9629 ) , .clk_3_S_in ( p1925 ) , 
     .clk_3_N_in ( p406 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9630 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9631 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9631 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_9__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9632 } ) ,
     .chany_bottom_in ( sb_1__1__95_chany_top_out ) , 
@@ -135275,7 +161537,7 @@
     .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9648 ) , 
     .clk_2_N_out ( clk_2_wires[100] ) , .clk_3_S_in ( p1474 ) , 
     .clk_3_N_in ( p347 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9649 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9650 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9650 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_9__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9651 } ) ,
     .chany_bottom_in ( sb_1__1__96_chany_top_out ) , 
@@ -135325,7 +161587,7 @@
     .clk_2_S_in ( p2515 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9666 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9667 ) , .clk_3_S_in ( p2643 ) , 
     .clk_3_N_in ( p958 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9668 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9669 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9669 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_9__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9670 } ) ,
     .chany_bottom_in ( sb_1__1__97_chany_top_out ) , 
@@ -135378,7 +161640,7 @@
     .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9686 ) , 
     .clk_2_N_out ( clk_2_wires[111] ) , .clk_3_S_in ( p1822 ) , 
     .clk_3_N_in ( p371 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9687 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9688 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9688 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_9__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9689 } ) ,
     .chany_bottom_in ( sb_1__1__98_chany_top_out ) , 
@@ -135428,7 +161690,7 @@
     .clk_2_S_in ( p2036 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9703 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9704 ) , .clk_3_S_in ( p2164 ) , 
     .clk_3_N_in ( p1367 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9705 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9706 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9706 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_10__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9707 } ) ,
     .chany_bottom_in ( sb_1__0__9_chany_top_out ) , 
@@ -135478,7 +161740,7 @@
     .clk_2_S_in ( p1281 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9722 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9723 ) , .clk_3_S_in ( p1404 ) , 
     .clk_3_N_in ( p1745 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9724 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9725 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9725 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_10__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9726 } ) ,
     .chany_bottom_in ( sb_1__1__99_chany_top_out ) , 
@@ -135528,7 +161790,7 @@
     .clk_2_S_in ( p2571 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9741 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9742 ) , .clk_3_S_in ( p2683 ) , 
     .clk_3_N_in ( p66 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9743 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9744 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9744 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_10__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9745 } ) ,
     .chany_bottom_in ( sb_1__1__100_chany_top_out ) , 
@@ -135581,7 +161843,7 @@
     .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9762 ) , 
     .clk_3_N_in ( clk_3_wires[86] ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9763 ) , 
-    .clk_3_S_out ( clk_3_wires[87] ) ) ;
+    .clk_3_S_out ( clk_3_wires[87] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_10__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9764 } ) ,
     .chany_bottom_in ( sb_1__1__101_chany_top_out ) , 
@@ -135634,7 +161896,7 @@
     .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9781 ) , 
     .clk_3_N_in ( clk_3_wires[82] ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9782 ) , 
-    .clk_3_S_out ( clk_3_wires[83] ) ) ;
+    .clk_3_S_out ( clk_3_wires[83] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_10__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9783 } ) ,
     .chany_bottom_in ( sb_1__1__102_chany_top_out ) , 
@@ -135687,7 +161949,7 @@
     .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9800 ) , 
     .clk_3_N_in ( clk_3_wires[76] ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9801 ) , 
-    .clk_3_S_out ( clk_3_wires[77] ) ) ;
+    .clk_3_S_out ( clk_3_wires[77] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_10__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9802 } ) ,
     .chany_bottom_in ( sb_1__1__103_chany_top_out ) , 
@@ -135740,7 +162002,7 @@
     .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9819 ) , 
     .clk_3_N_in ( clk_3_wires[72] ) , 
     .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9820 ) , 
-    .clk_3_S_out ( clk_3_wires[73] ) ) ;
+    .clk_3_S_out ( clk_3_wires[73] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_10__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9821 } ) ,
     .chany_bottom_in ( sb_1__1__104_chany_top_out ) , 
@@ -135793,7 +162055,7 @@
     .clk_3_S_in ( clk_3_wires[70] ) , 
     .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9838 ) , 
     .clk_3_N_out ( clk_3_wires[71] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9839 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9839 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_10__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9840 } ) ,
     .chany_bottom_in ( sb_1__1__105_chany_top_out ) , 
@@ -135846,7 +162108,7 @@
     .clk_3_S_in ( clk_3_wires[74] ) , 
     .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9857 ) , 
     .clk_3_N_out ( clk_3_wires[75] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9858 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9858 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_10__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9859 } ) ,
     .chany_bottom_in ( sb_1__1__106_chany_top_out ) , 
@@ -135899,7 +162161,7 @@
     .clk_3_S_in ( clk_3_wires[80] ) , 
     .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9876 ) , 
     .clk_3_N_out ( clk_3_wires[81] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9877 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9877 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_10__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9878 } ) ,
     .chany_bottom_in ( sb_1__1__107_chany_top_out ) , 
@@ -135952,7 +162214,7 @@
     .clk_3_S_in ( clk_3_wires[84] ) , 
     .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9895 ) , 
     .clk_3_N_out ( clk_3_wires[85] ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9896 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9896 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_10__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9897 } ) ,
     .chany_bottom_in ( sb_1__1__108_chany_top_out ) , 
@@ -136002,7 +162264,7 @@
     .clk_2_S_in ( p2920 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9912 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9913 ) , .clk_3_S_in ( p2988 ) , 
     .clk_3_N_in ( p1274 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9914 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9915 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9915 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_10__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9916 } ) ,
     .chany_bottom_in ( sb_1__1__109_chany_top_out ) , 
@@ -136052,7 +162314,7 @@
     .clk_2_S_in ( p2926 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9930 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9931 ) , .clk_3_S_in ( p2994 ) , 
     .clk_3_N_in ( p1631 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9932 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9933 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9933 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_11__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9934 } ) ,
     .chany_bottom_in ( sb_1__0__10_chany_top_out ) , 
@@ -136102,7 +162364,7 @@
     .clk_2_S_in ( p608 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9949 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9950 ) , .clk_3_S_in ( p1002 ) , 
     .clk_3_N_in ( p218 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9951 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9952 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9952 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_11__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9953 } ) ,
     .chany_bottom_in ( sb_1__1__110_chany_top_out ) , 
@@ -136155,7 +162417,7 @@
     .clk_2_S_out ( clk_2_wires[116] ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9969 ) , .clk_3_S_in ( p1414 ) , 
     .clk_3_N_in ( p33 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9970 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9971 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9971 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_11__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9972 } ) ,
     .chany_bottom_in ( sb_1__1__111_chany_top_out ) , 
@@ -136205,7 +162467,7 @@
     .clk_2_S_in ( p3163 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9987 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9988 ) , .clk_3_S_in ( p3219 ) , 
     .clk_3_N_in ( p16 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9989 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9990 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9990 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
 cby_1__1_ cby_11__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_9991 } ) ,
     .chany_bottom_in ( sb_1__1__112_chany_top_out ) , 
@@ -136258,7 +162520,8 @@
     .clk_2_S_out ( clk_2_wires[123] ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10007 ) , .clk_3_S_in ( p1510 ) , 
     .clk_3_N_in ( p291 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10008 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10009 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10009 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1_ cby_11__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_10010 } ) ,
     .chany_bottom_in ( sb_1__1__113_chany_top_out ) , 
@@ -136311,7 +162574,8 @@
     .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10026 ) , 
     .clk_2_N_out ( clk_2_wires[121] ) , .clk_3_S_in ( p1661 ) , 
     .clk_3_N_in ( p1064 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10027 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10028 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10028 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1_ cby_11__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_10029 } ) ,
     .chany_bottom_in ( sb_1__1__114_chany_top_out ) , 
@@ -136361,7 +162625,8 @@
     .clk_2_S_in ( p2770 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10044 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10045 ) , .clk_3_S_in ( p2786 ) , 
     .clk_3_N_in ( p917 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10046 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10047 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10047 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1_ cby_11__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_10048 } ) ,
     .chany_bottom_in ( sb_1__1__115_chany_top_out ) , 
@@ -136411,7 +162676,8 @@
     .clk_2_S_in ( p2578 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10063 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10064 ) , .clk_3_S_in ( p2698 ) , 
     .clk_3_N_in ( p221 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10065 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10066 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10066 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1_ cby_11__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_10067 } ) ,
     .chany_bottom_in ( sb_1__1__116_chany_top_out ) , 
@@ -136464,7 +162730,8 @@
     .clk_2_S_out ( clk_2_wires[130] ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10083 ) , .clk_3_S_in ( p1927 ) , 
     .clk_3_N_in ( p273 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10084 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10085 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10085 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1_ cby_11__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_10086 } ) ,
     .chany_bottom_in ( sb_1__1__117_chany_top_out ) , 
@@ -136517,7 +162784,8 @@
     .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10102 ) , 
     .clk_2_N_out ( clk_2_wires[128] ) , .clk_3_S_in ( p1539 ) , 
     .clk_3_N_in ( p389 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10103 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10104 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10104 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1_ cby_11__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_10105 } ) ,
     .chany_bottom_in ( sb_1__1__118_chany_top_out ) , 
@@ -136567,7 +162835,8 @@
     .clk_2_S_in ( p2573 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10120 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10121 ) , .clk_3_S_in ( p2681 ) , 
     .clk_3_N_in ( p562 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10122 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10123 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10123 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1_ cby_11__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_10124 } ) ,
     .chany_bottom_in ( sb_1__1__119_chany_top_out ) , 
@@ -136620,7 +162889,8 @@
     .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10140 ) , 
     .clk_2_N_out ( clk_2_wires[135] ) , .clk_3_S_in ( p1923 ) , 
     .clk_3_N_in ( p449 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10141 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10142 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10142 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_1__1_ cby_11__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_10143 } ) ,
     .chany_bottom_in ( sb_1__1__120_chany_top_out ) , 
@@ -136670,7 +162940,8 @@
     .clk_2_S_in ( p1699 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10157 ) , 
     .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10158 ) , .clk_3_S_in ( p1931 ) , 
     .clk_3_N_in ( p1968 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10159 ) , 
-    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10160 ) ) ;
+    .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10160 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1_ cby_12__1_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_10161 } ) ,
     .chany_bottom_in ( sb_12__0__0_chany_top_out ) , 
@@ -136705,7 +162976,8 @@
     .pReset_S_in ( pResetWires[60] ) , 
     .prog_clk_0_W_in ( prog_clk_0_wires[444] ) , 
     .prog_clk_0_S_out ( prog_clk_0_wires[445] ) , 
-    .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10162 ) ) ;
+    .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10162 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1_ cby_12__2_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_10163 } ) ,
     .chany_bottom_in ( sb_12__1__0_chany_top_out ) , 
@@ -136740,7 +163012,8 @@
     .pReset_S_in ( pResetWires[109] ) , 
     .prog_clk_0_W_in ( prog_clk_0_wires[447] ) , 
     .prog_clk_0_S_out ( prog_clk_0_wires[448] ) , 
-    .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10164 ) ) ;
+    .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10164 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1_ cby_12__3_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_10165 } ) ,
     .chany_bottom_in ( sb_12__1__1_chany_top_out ) , 
@@ -136775,7 +163048,8 @@
     .pReset_S_in ( pResetWires[158] ) , 
     .prog_clk_0_W_in ( prog_clk_0_wires[450] ) , 
     .prog_clk_0_S_out ( prog_clk_0_wires[451] ) , 
-    .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10166 ) ) ;
+    .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10166 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1_ cby_12__4_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_10167 } ) ,
     .chany_bottom_in ( sb_12__1__2_chany_top_out ) , 
@@ -136810,7 +163084,8 @@
     .pReset_S_in ( pResetWires[207] ) , 
     .prog_clk_0_W_in ( prog_clk_0_wires[453] ) , 
     .prog_clk_0_S_out ( prog_clk_0_wires[454] ) , 
-    .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10168 ) ) ;
+    .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10168 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1_ cby_12__5_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_10169 } ) ,
     .chany_bottom_in ( sb_12__1__3_chany_top_out ) , 
@@ -136845,7 +163120,8 @@
     .pReset_S_in ( pResetWires[256] ) , 
     .prog_clk_0_W_in ( prog_clk_0_wires[456] ) , 
     .prog_clk_0_S_out ( prog_clk_0_wires[457] ) , 
-    .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10170 ) ) ;
+    .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10170 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1_ cby_12__6_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_10171 } ) ,
     .chany_bottom_in ( sb_12__1__4_chany_top_out ) , 
@@ -136880,7 +163156,8 @@
     .pReset_S_in ( pResetWires[305] ) , 
     .prog_clk_0_W_in ( prog_clk_0_wires[459] ) , 
     .prog_clk_0_S_out ( prog_clk_0_wires[460] ) , 
-    .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10172 ) ) ;
+    .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10172 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1_ cby_12__7_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_10173 } ) ,
     .chany_bottom_in ( sb_12__1__5_chany_top_out ) , 
@@ -136915,7 +163192,8 @@
     .pReset_S_in ( pResetWires[354] ) , 
     .prog_clk_0_W_in ( prog_clk_0_wires[462] ) , 
     .prog_clk_0_S_out ( prog_clk_0_wires[463] ) , 
-    .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10174 ) ) ;
+    .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10174 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1_ cby_12__8_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_10175 } ) ,
     .chany_bottom_in ( sb_12__1__6_chany_top_out ) , 
@@ -136950,7 +163228,8 @@
     .pReset_S_in ( pResetWires[403] ) , 
     .prog_clk_0_W_in ( prog_clk_0_wires[465] ) , 
     .prog_clk_0_S_out ( prog_clk_0_wires[466] ) , 
-    .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10176 ) ) ;
+    .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10176 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1_ cby_12__9_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_10177 } ) ,
     .chany_bottom_in ( sb_12__1__7_chany_top_out ) , 
@@ -136985,7 +163264,8 @@
     .pReset_S_in ( pResetWires[452] ) , 
     .prog_clk_0_W_in ( prog_clk_0_wires[468] ) , 
     .prog_clk_0_S_out ( prog_clk_0_wires[469] ) , 
-    .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10178 ) ) ;
+    .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10178 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1_ cby_12__10_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_10179 } ) ,
     .chany_bottom_in ( sb_12__1__8_chany_top_out ) , 
@@ -137020,7 +163300,8 @@
     .pReset_S_in ( pResetWires[501] ) , 
     .prog_clk_0_W_in ( prog_clk_0_wires[471] ) , 
     .prog_clk_0_S_out ( prog_clk_0_wires[472] ) , 
-    .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10180 ) ) ;
+    .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10180 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1_ cby_12__11_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_10181 } ) ,
     .chany_bottom_in ( sb_12__1__9_chany_top_out ) , 
@@ -137055,7 +163336,8 @@
     .pReset_S_in ( pResetWires[550] ) , 
     .prog_clk_0_W_in ( prog_clk_0_wires[474] ) , 
     .prog_clk_0_S_out ( prog_clk_0_wires[475] ) , 
-    .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10182 ) ) ;
+    .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10182 ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 cby_2__1_ cby_12__12_ (
     .pReset ( { SYNOPSYS_UNCONNECTED_10183 } ) ,
     .chany_bottom_in ( sb_12__1__10_chany_top_out ) , 
@@ -137090,7 +163372,8 @@
     .pReset_S_in ( pResetWires[599] ) , 
     .prog_clk_0_W_in ( prog_clk_0_wires[477] ) , 
     .prog_clk_0_S_out ( prog_clk_0_wires[478] ) , 
-    .prog_clk_0_N_out ( prog_clk_0_wires[480] ) ) ;
+    .prog_clk_0_N_out ( prog_clk_0_wires[480] ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) ) ;
 endmodule
 
 
@@ -137105,7 +163388,7 @@
     analog_io_25_ , analog_io_26_ , analog_io_27_ , analog_io_28_ , 
     analog_io_29_ , analog_io_2_ , analog_io_30_ , analog_io_3_ , 
     analog_io_4_ , analog_io_5_ , analog_io_6_ , analog_io_7_ , analog_io_8_ , 
-    analog_io_9_ , user_clock2 ) ;
+    analog_io_9_ , user_clock2 , VDD , VSS ) ;
 inout  vdda1 ;
 inout  vdda2 ;
 inout  vssa1 ;
@@ -137162,6 +163445,8 @@
 inout  analog_io_8_ ;
 inout  analog_io_9_ ;
 input  user_clock2 ;
+input  VDD ;
+input  VSS ;
 
 wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
 wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
@@ -137177,6 +163462,8 @@
 wire ccff_tail ;
 wire sc_head ;
 wire wb_la_switch ;
+supply1 VDD ;
+supply0 VSS ;
 
 assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = io_in[24] ;
 assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] = io_out[24] ;
@@ -137400,424 +163687,497 @@
 assign wb_la_switch = io_in[25] ;
 
 sky130_fd_sc_hd__inv_8 WB_LA_SWITCH_INV ( .A ( io_in[25] ) , 
-    .Y ( wb_la_switch_b ) ) ;
+    .Y ( wb_la_switch_b ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[0] ) ) ;
+    .Z ( wbs_dat_o[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[116] ) ) ;
+    .Z ( la_data_out[116] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[1] ) ) ;
+    .Z ( wbs_dat_o[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[115] ) ) ;
+    .Z ( la_data_out[115] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[2] ) ) ;
+    .Z ( wbs_dat_o[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[114] ) ) ;
+    .Z ( la_data_out[114] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[3] ) ) ;
+    .Z ( wbs_dat_o[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[113] ) ) ;
+    .Z ( la_data_out[113] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[4] ) ) ;
+    .Z ( wbs_dat_o[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[112] ) ) ;
+    .Z ( la_data_out[112] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[5] ) ) ;
+    .Z ( wbs_dat_o[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[111] ) ) ;
+    .Z ( la_data_out[111] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[6] ) ) ;
+    .Z ( wbs_dat_o[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[110] ) ) ;
+    .Z ( la_data_out[110] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[7] ) ) ;
+    .Z ( wbs_dat_o[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[109] ) ) ;
+    .Z ( la_data_out[109] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[8] ) ) ;
+    .Z ( wbs_dat_o[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[108] ) ) ;
+    .Z ( la_data_out[108] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[9] ) ) ;
+    .Z ( wbs_dat_o[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[107] ) ) ;
+    .Z ( la_data_out[107] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[10] ) ) ;
+    .Z ( wbs_dat_o[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[106] ) ) ;
+    .Z ( la_data_out[106] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[11] ) ) ;
+    .Z ( wbs_dat_o[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[105] ) ) ;
+    .Z ( la_data_out[105] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[12] ) ) ;
+    .Z ( wbs_dat_o[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[104] ) ) ;
+    .Z ( la_data_out[104] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[13] ) ) ;
+    .Z ( wbs_dat_o[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[103] ) ) ;
+    .Z ( la_data_out[103] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[14] ) ) ;
+    .Z ( wbs_dat_o[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[102] ) ) ;
+    .Z ( la_data_out[102] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[15] ) ) ;
+    .Z ( wbs_dat_o[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[101] ) ) ;
+    .Z ( la_data_out[101] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[16] ) ) ;
+    .Z ( wbs_dat_o[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[100] ) ) ;
+    .Z ( la_data_out[100] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[17] ) ) ;
+    .Z ( wbs_dat_o[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[99] ) ) ;
+    .Z ( la_data_out[99] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[18] ) ) ;
+    .Z ( wbs_dat_o[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[98] ) ) ;
+    .Z ( la_data_out[98] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[19] ) ) ;
+    .Z ( wbs_dat_o[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[97] ) ) ;
+    .Z ( la_data_out[97] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[20] ) ) ;
+    .Z ( wbs_dat_o[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[96] ) ) ;
+    .Z ( la_data_out[96] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[21] ) ) ;
+    .Z ( wbs_dat_o[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[95] ) ) ;
+    .Z ( la_data_out[95] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[22] ) ) ;
+    .Z ( wbs_dat_o[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[94] ) ) ;
+    .Z ( la_data_out[94] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[23] ) ) ;
+    .Z ( wbs_dat_o[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[93] ) ) ;
+    .Z ( la_data_out[93] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[24] ) ) ;
+    .Z ( wbs_dat_o[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[92] ) ) ;
+    .Z ( la_data_out[92] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[25] ) ) ;
+    .Z ( wbs_dat_o[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[91] ) ) ;
+    .Z ( la_data_out[91] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[26] ) ) ;
+    .Z ( wbs_dat_o[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[90] ) ) ;
+    .Z ( la_data_out[90] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[27] ) ) ;
+    .Z ( wbs_dat_o[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[89] ) ) ;
+    .Z ( la_data_out[89] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[28] ) ) ;
+    .Z ( wbs_dat_o[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[88] ) ) ;
+    .Z ( la_data_out[88] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[29] ) ) ;
+    .Z ( wbs_dat_o[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[87] ) ) ;
+    .Z ( la_data_out[87] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[30] ) ) ;
+    .Z ( wbs_dat_o[30] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[86] ) ) ;
+    .Z ( la_data_out[86] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_dat_o[31] ) ) ;
+    .Z ( wbs_dat_o[31] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[85] ) ) ;
+    .Z ( la_data_out[85] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_62_MUX ( .A0 ( la_data_in[84] ) , 
     .A1 ( wbs_dat_i[0] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_63_MUX ( .A0 ( la_data_in[83] ) , 
     .A1 ( wbs_dat_i[1] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_64_MUX ( .A0 ( la_data_in[82] ) , 
     .A1 ( wbs_dat_i[2] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_65_MUX ( .A0 ( la_data_in[81] ) , 
     .A1 ( wbs_dat_i[3] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_66_MUX ( .A0 ( la_data_in[80] ) , 
     .A1 ( wbs_dat_i[4] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_67_MUX ( .A0 ( la_data_in[79] ) , 
     .A1 ( wbs_dat_i[5] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_68_MUX ( .A0 ( la_data_in[78] ) , 
     .A1 ( wbs_dat_i[6] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_69_MUX ( .A0 ( la_data_in[77] ) , 
     .A1 ( wbs_dat_i[7] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_70_MUX ( .A0 ( la_data_in[76] ) , 
     .A1 ( wbs_dat_i[8] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_71_MUX ( .A0 ( la_data_in[75] ) , 
     .A1 ( wbs_dat_i[9] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_72_MUX ( .A0 ( la_data_in[74] ) , 
     .A1 ( wbs_dat_i[10] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_73_MUX ( .A0 ( la_data_in[73] ) , 
     .A1 ( wbs_dat_i[11] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_74_MUX ( .A0 ( la_data_in[72] ) , 
     .A1 ( wbs_dat_i[12] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_75_MUX ( .A0 ( la_data_in[71] ) , 
     .A1 ( wbs_dat_i[13] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_76_MUX ( .A0 ( la_data_in[70] ) , 
     .A1 ( wbs_dat_i[14] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_77_MUX ( .A0 ( la_data_in[69] ) , 
     .A1 ( wbs_dat_i[15] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_78_MUX ( .A0 ( la_data_in[68] ) , 
     .A1 ( wbs_dat_i[16] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_79_MUX ( .A0 ( la_data_in[67] ) , 
     .A1 ( wbs_dat_i[17] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_80_MUX ( .A0 ( la_data_in[66] ) , 
     .A1 ( wbs_dat_i[18] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_81_MUX ( .A0 ( la_data_in[65] ) , 
     .A1 ( wbs_dat_i[19] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_82_MUX ( .A0 ( la_data_in[64] ) , 
     .A1 ( wbs_dat_i[20] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_83_MUX ( .A0 ( la_data_in[63] ) , 
     .A1 ( wbs_dat_i[21] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_84_MUX ( .A0 ( la_data_in[62] ) , 
     .A1 ( wbs_dat_i[22] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_85_MUX ( .A0 ( la_data_in[61] ) , 
     .A1 ( wbs_dat_i[23] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_86_MUX ( .A0 ( la_data_in[60] ) , 
     .A1 ( wbs_dat_i[24] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_87_MUX ( .A0 ( la_data_in[59] ) , 
     .A1 ( wbs_dat_i[25] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_88_MUX ( .A0 ( la_data_in[58] ) , 
     .A1 ( wbs_dat_i[26] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_89_MUX ( .A0 ( la_data_in[57] ) , 
     .A1 ( wbs_dat_i[27] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_90_MUX ( .A0 ( la_data_in[56] ) , 
     .A1 ( wbs_dat_i[28] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_91_MUX ( .A0 ( la_data_in[55] ) , 
     .A1 ( wbs_dat_i[29] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_92_MUX ( .A0 ( la_data_in[54] ) , 
     .A1 ( wbs_dat_i[30] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_93_MUX ( .A0 ( la_data_in[53] ) , 
     .A1 ( wbs_dat_i[31] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_94_MUX ( .A0 ( la_data_in[52] ) , 
     .A1 ( wbs_adr_i[0] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_95_MUX ( .A0 ( la_data_in[51] ) , 
     .A1 ( wbs_adr_i[1] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_96_MUX ( .A0 ( la_data_in[50] ) , 
     .A1 ( wbs_adr_i[2] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_97_MUX ( .A0 ( la_data_in[49] ) , 
     .A1 ( wbs_adr_i[3] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_98_MUX ( .A0 ( la_data_in[48] ) , 
     .A1 ( wbs_adr_i[4] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_99_MUX ( .A0 ( la_data_in[47] ) , 
     .A1 ( wbs_adr_i[5] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_100_MUX ( .A0 ( la_data_in[46] ) , 
     .A1 ( wbs_adr_i[6] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_101_MUX ( .A0 ( la_data_in[45] ) , 
     .A1 ( wbs_adr_i[7] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_102_MUX ( .A0 ( la_data_in[44] ) , 
     .A1 ( wbs_adr_i[8] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_103_MUX ( .A0 ( la_data_in[43] ) , 
     .A1 ( wbs_adr_i[9] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_104_MUX ( .A0 ( la_data_in[42] ) , 
     .A1 ( wbs_adr_i[10] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_105_MUX ( .A0 ( la_data_in[41] ) , 
     .A1 ( wbs_adr_i[11] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_106_MUX ( .A0 ( la_data_in[40] ) , 
     .A1 ( wbs_adr_i[12] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_107_MUX ( .A0 ( la_data_in[39] ) , 
     .A1 ( wbs_adr_i[13] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_108_MUX ( .A0 ( la_data_in[38] ) , 
     .A1 ( wbs_adr_i[14] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_109_MUX ( .A0 ( la_data_in[37] ) , 
     .A1 ( wbs_adr_i[15] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_110_MUX ( .A0 ( la_data_in[36] ) , 
     .A1 ( wbs_adr_i[16] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_111_MUX ( .A0 ( la_data_in[35] ) , 
     .A1 ( wbs_adr_i[17] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_112_MUX ( .A0 ( la_data_in[34] ) , 
     .A1 ( wbs_adr_i[18] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_113_MUX ( .A0 ( la_data_in[33] ) , 
     .A1 ( wbs_adr_i[19] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_114_MUX ( .A0 ( la_data_in[32] ) , 
     .A1 ( wbs_adr_i[20] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_115_MUX ( .A0 ( la_data_in[31] ) , 
     .A1 ( wbs_adr_i[21] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_116_MUX ( .A0 ( la_data_in[30] ) , 
     .A1 ( wbs_adr_i[22] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_117_MUX ( .A0 ( la_data_in[29] ) , 
     .A1 ( wbs_adr_i[23] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_118_MUX ( .A0 ( la_data_in[28] ) , 
     .A1 ( wbs_adr_i[24] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_119_MUX ( .A0 ( la_data_in[27] ) , 
     .A1 ( wbs_adr_i[25] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_120_MUX ( .A0 ( la_data_in[26] ) , 
     .A1 ( wbs_adr_i[26] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_121_MUX ( .A0 ( la_data_in[25] ) , 
     .A1 ( wbs_adr_i[27] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_122_MUX ( .A0 ( la_data_in[24] ) , 
     .A1 ( wbs_adr_i[28] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_123_MUX ( .A0 ( la_data_in[23] ) , 
     .A1 ( wbs_adr_i[29] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_124_MUX ( .A0 ( la_data_in[22] ) , 
     .A1 ( wbs_adr_i[30] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_125_MUX ( .A0 ( la_data_in[21] ) , 
     .A1 ( wbs_adr_i[31] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_126_MUX ( .A0 ( la_data_in[20] ) , 
     .A1 ( wbs_sel_i[0] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_127_MUX ( .A0 ( la_data_in[19] ) , 
     .A1 ( wbs_sel_i[1] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_128_MUX ( .A0 ( la_data_in[18] ) , 
     .A1 ( wbs_sel_i[2] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_129_MUX ( .A0 ( la_data_in[17] ) , 
     .A1 ( wbs_sel_i[3] ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_130_MUX ( .A0 ( la_data_in[16] ) , 
     .A1 ( wbs_we_i ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_131_MUX ( .A0 ( la_data_in[15] ) , 
     .A1 ( wbs_stb_i ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_132_MUX ( .A0 ( la_data_in[14] ) , 
     .A1 ( wbs_cyc_i ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_WB ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ) , .TE_B ( wb_la_switch_b ) , 
-    .Z ( wbs_ack_o ) ) ;
+    .Z ( wbs_ack_o ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_LA ( 
     .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ) , .TE_B ( io_in[25] ) , 
-    .Z ( la_data_out[13] ) ) ;
+    .Z ( la_data_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_134_MUX ( .A0 ( la_data_in[12] ) , 
     .A1 ( wb_rst_i ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_135_MUX ( .A0 ( la_data_in[11] ) , 
     .A1 ( wb_clk_i ) , .S ( io_in[25] ) , 
-    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] ) ) ;
+    .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] ) , .VPWR ( VDD ) , 
+    .VGND ( VSS ) ) ;
 fpga_core fpga_core_uut ( .pReset ( io_in[3] ) , .prog_clk ( io_in[37] ) , 
     .Test_en ( io_in[0] ) , .IO_ISOL_N ( io_in[1] ) , .clk ( io_in[36] ) , 
     .Reset ( io_in[2] ) ,
@@ -138104,9001 +164464,9002 @@
         io_oeb[32] , io_oeb[31] , io_oeb[30] , io_oeb[29] , io_oeb[28] , 
         io_oeb[27] } ) ,
     .ccff_head ( io_in[12] ) , .ccff_tail ( io_out[35] ) , 
-    .sc_head ( io_in[26] ) , .sc_tail ( io_out[11] ) , 
-    .h_incr0 ( SYNOPSYS_UNCONNECTED_1 ) , .p0 ( optlc_net_20 ) , 
-    .p1 ( optlc_net_21 ) , .p2 ( optlc_net_22 ) , .p3 ( optlc_net_23 ) , 
-    .p4 ( optlc_net_24 ) , .p5 ( optlc_net_25 ) , .p6 ( optlc_net_26 ) , 
-    .p7 ( optlc_net_27 ) , .p8 ( optlc_net_28 ) , .p9 ( optlc_net_29 ) , 
-    .p10 ( optlc_net_30 ) , .p11 ( optlc_net_31 ) , .p12 ( optlc_net_32 ) , 
-    .p13 ( optlc_net_33 ) , .p14 ( optlc_net_34 ) , .p15 ( optlc_net_35 ) , 
-    .p16 ( optlc_net_36 ) , .p17 ( optlc_net_37 ) , .p18 ( optlc_net_38 ) , 
-    .p19 ( optlc_net_39 ) , .p20 ( optlc_net_40 ) , .p21 ( optlc_net_41 ) , 
-    .p22 ( optlc_net_42 ) , .p23 ( optlc_net_43 ) , .p24 ( optlc_net_44 ) , 
-    .p25 ( optlc_net_45 ) , .p26 ( optlc_net_46 ) , .p27 ( optlc_net_47 ) , 
-    .p28 ( optlc_net_48 ) , .p29 ( optlc_net_49 ) , .p30 ( optlc_net_50 ) , 
-    .p31 ( optlc_net_51 ) , .p32 ( optlc_net_52 ) , .p33 ( optlc_net_53 ) , 
-    .p34 ( optlc_net_54 ) , .p35 ( optlc_net_55 ) , .p36 ( optlc_net_56 ) , 
-    .p37 ( optlc_net_57 ) , .p38 ( optlc_net_58 ) , .p39 ( optlc_net_59 ) , 
-    .p40 ( optlc_net_60 ) , .p41 ( optlc_net_61 ) , .p42 ( optlc_net_62 ) , 
-    .p43 ( optlc_net_63 ) , .p44 ( optlc_net_64 ) , .p45 ( optlc_net_65 ) , 
-    .p46 ( optlc_net_66 ) , .p47 ( optlc_net_67 ) , .p48 ( optlc_net_68 ) , 
-    .p49 ( optlc_net_69 ) , .p50 ( optlc_net_70 ) , .p51 ( optlc_net_71 ) , 
-    .p52 ( optlc_net_72 ) , .p53 ( optlc_net_73 ) , .p54 ( optlc_net_74 ) , 
-    .p55 ( optlc_net_75 ) , .p56 ( optlc_net_76 ) , .p57 ( optlc_net_77 ) , 
-    .p58 ( optlc_net_78 ) , .p59 ( optlc_net_79 ) , .p60 ( optlc_net_80 ) , 
-    .p61 ( optlc_net_81 ) , .p62 ( optlc_net_82 ) , .p63 ( optlc_net_83 ) , 
-    .p64 ( optlc_net_84 ) , .p65 ( optlc_net_85 ) , .p66 ( optlc_net_86 ) , 
-    .p67 ( optlc_net_87 ) , .p68 ( optlc_net_88 ) , .p69 ( optlc_net_89 ) , 
-    .p70 ( optlc_net_90 ) , .p71 ( optlc_net_91 ) , .p72 ( optlc_net_92 ) , 
-    .p73 ( optlc_net_93 ) , .p74 ( optlc_net_94 ) , .p75 ( optlc_net_95 ) , 
-    .p76 ( optlc_net_96 ) , .p77 ( optlc_net_97 ) , .p78 ( optlc_net_98 ) , 
-    .p79 ( optlc_net_99 ) , .p80 ( optlc_net_100 ) , .p81 ( optlc_net_101 ) , 
-    .p82 ( optlc_net_102 ) , .p83 ( optlc_net_103 ) , .p84 ( optlc_net_104 ) , 
-    .p85 ( optlc_net_105 ) , .p86 ( optlc_net_106 ) , .p87 ( optlc_net_107 ) , 
-    .p88 ( optlc_net_108 ) , .p89 ( optlc_net_109 ) , .p90 ( optlc_net_110 ) , 
-    .p91 ( optlc_net_111 ) , .p92 ( optlc_net_112 ) , .p93 ( optlc_net_113 ) , 
-    .p94 ( optlc_net_114 ) , .p95 ( optlc_net_115 ) , .p96 ( optlc_net_116 ) , 
-    .p97 ( optlc_net_117 ) , .p98 ( optlc_net_118 ) , .p99 ( optlc_net_119 ) , 
-    .p100 ( optlc_net_120 ) , .p101 ( optlc_net_121 ) , 
-    .p102 ( optlc_net_122 ) , .p103 ( optlc_net_123 ) , 
-    .p104 ( optlc_net_124 ) , .p105 ( optlc_net_125 ) , 
-    .p106 ( optlc_net_126 ) , .p107 ( optlc_net_127 ) , 
-    .p108 ( optlc_net_128 ) , .p109 ( optlc_net_129 ) , 
-    .p110 ( optlc_net_130 ) , .p111 ( optlc_net_131 ) , 
-    .p112 ( optlc_net_132 ) , .p113 ( optlc_net_133 ) , 
-    .p114 ( optlc_net_134 ) , .p115 ( optlc_net_135 ) , 
-    .p116 ( optlc_net_136 ) , .p117 ( optlc_net_137 ) , 
-    .p118 ( optlc_net_138 ) , .p119 ( optlc_net_139 ) , 
-    .p120 ( optlc_net_140 ) , .p121 ( optlc_net_141 ) , 
-    .p122 ( optlc_net_142 ) , .p123 ( optlc_net_143 ) , 
-    .p124 ( optlc_net_144 ) , .p125 ( optlc_net_145 ) , 
-    .p126 ( optlc_net_146 ) , .p127 ( optlc_net_147 ) , 
-    .p128 ( optlc_net_148 ) , .p129 ( optlc_net_149 ) , 
-    .p130 ( optlc_net_150 ) , .p131 ( optlc_net_151 ) , 
-    .p132 ( optlc_net_152 ) , .p133 ( optlc_net_153 ) , 
-    .p134 ( optlc_net_154 ) , .p135 ( optlc_net_155 ) , 
-    .p136 ( optlc_net_156 ) , .p137 ( optlc_net_157 ) , 
-    .p138 ( optlc_net_158 ) , .p139 ( optlc_net_159 ) , 
-    .p140 ( optlc_net_160 ) , .p141 ( optlc_net_161 ) , 
-    .p142 ( optlc_net_162 ) , .p143 ( optlc_net_163 ) , 
-    .p144 ( optlc_net_164 ) , .p145 ( optlc_net_165 ) , 
-    .p146 ( optlc_net_166 ) , .p147 ( optlc_net_167 ) , 
-    .p148 ( optlc_net_168 ) , .p149 ( optlc_net_169 ) , 
-    .p150 ( optlc_net_170 ) , .p151 ( optlc_net_171 ) , 
-    .p152 ( optlc_net_172 ) , .p153 ( optlc_net_173 ) , 
-    .p154 ( optlc_net_174 ) , .p155 ( optlc_net_175 ) , 
-    .p156 ( optlc_net_176 ) , .p157 ( optlc_net_177 ) , 
-    .p158 ( optlc_net_178 ) , .p159 ( optlc_net_179 ) , 
-    .p160 ( optlc_net_180 ) , .p161 ( optlc_net_181 ) , 
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-    .p3308 ( optlc_net_3328 ) , .p3309 ( optlc_net_3329 ) , 
-    .p3310 ( optlc_net_3330 ) , .p3311 ( optlc_net_3331 ) , 
-    .p3312 ( optlc_net_3332 ) , .p3313 ( optlc_net_3333 ) , 
-    .p3314 ( optlc_net_3334 ) , .p3315 ( optlc_net_3335 ) , 
-    .p3316 ( optlc_net_3336 ) , .p3317 ( optlc_net_3337 ) , 
-    .p3318 ( optlc_net_3338 ) , .p3319 ( optlc_net_3339 ) , 
-    .p3320 ( optlc_net_3340 ) , .p3321 ( optlc_net_3341 ) , 
-    .p3322 ( optlc_net_3342 ) , .p3323 ( optlc_net_3343 ) , 
-    .p3324 ( optlc_net_3344 ) , .p3325 ( optlc_net_3345 ) , 
-    .p3326 ( optlc_net_3346 ) , .p3327 ( optlc_net_3347 ) , 
-    .p3328 ( optlc_net_3348 ) , .p3329 ( optlc_net_3349 ) , 
-    .p3330 ( optlc_net_3350 ) , .p3331 ( optlc_net_3351 ) , 
-    .p3332 ( optlc_net_3352 ) , .p3333 ( optlc_net_3353 ) , 
-    .p3334 ( optlc_net_3354 ) , .p3335 ( optlc_net_3355 ) , 
-    .p3336 ( optlc_net_3356 ) , .p3337 ( optlc_net_3357 ) , 
-    .p3338 ( optlc_net_3358 ) , .p3339 ( optlc_net_3359 ) , 
-    .p3340 ( optlc_net_3360 ) , .p3341 ( optlc_net_3361 ) , 
-    .p3342 ( optlc_net_3362 ) , .p3343 ( optlc_net_3363 ) , 
-    .p3344 ( optlc_net_3364 ) , .p3345 ( optlc_net_3365 ) , 
-    .p3346 ( optlc_net_3366 ) , .p3347 ( optlc_net_3367 ) , 
-    .p3348 ( optlc_net_3368 ) , .p3349 ( optlc_net_3369 ) , 
-    .p3350 ( optlc_net_3370 ) , .p3351 ( optlc_net_3371 ) , 
-    .p3352 ( optlc_net_3372 ) , .p3353 ( optlc_net_3373 ) , 
-    .p3354 ( optlc_net_3374 ) , .p3355 ( optlc_net_3375 ) , 
-    .p3356 ( optlc_net_3376 ) , .p3357 ( optlc_net_3377 ) , 
-    .p3358 ( optlc_net_3378 ) , .p3359 ( optlc_net_3379 ) , 
-    .p3360 ( optlc_net_3380 ) , .p3361 ( optlc_net_3381 ) , 
-    .p3362 ( optlc_net_3382 ) , .p3363 ( optlc_net_3383 ) , 
-    .p3364 ( optlc_net_3384 ) , .p3365 ( optlc_net_3385 ) , 
-    .p3366 ( optlc_net_3386 ) , .p3367 ( optlc_net_3387 ) , 
-    .p3368 ( optlc_net_3388 ) , .p3369 ( optlc_net_3389 ) , 
-    .p3370 ( optlc_net_3390 ) , .p3371 ( optlc_net_3391 ) , 
-    .p3372 ( optlc_net_3392 ) , .p3373 ( optlc_net_3393 ) , 
-    .p3374 ( optlc_net_3394 ) , .p3375 ( optlc_net_3395 ) , 
-    .p3376 ( optlc_net_3396 ) , .p3377 ( optlc_net_3397 ) , 
-    .p3378 ( optlc_net_3398 ) , .p3379 ( optlc_net_3399 ) , 
-    .p3380 ( optlc_net_3400 ) , .p3381 ( optlc_net_3401 ) , 
-    .p3382 ( optlc_net_3402 ) , .p3383 ( optlc_net_3403 ) , 
-    .p3384 ( optlc_net_3404 ) , .p3385 ( optlc_net_3405 ) , 
-    .p3386 ( optlc_net_3406 ) , .p3387 ( optlc_net_3407 ) , 
-    .p3388 ( optlc_net_3408 ) , .p3389 ( optlc_net_3409 ) , 
-    .p3390 ( optlc_net_3410 ) , .p3391 ( optlc_net_3411 ) , 
-    .p3392 ( optlc_net_3412 ) , .p3393 ( optlc_net_3413 ) , 
-    .p3394 ( optlc_net_3414 ) , .p3395 ( optlc_net_3415 ) , 
-    .p3396 ( optlc_net_3416 ) , .p3397 ( optlc_net_3417 ) , 
-    .p3398 ( optlc_net_3418 ) , .p3399 ( optlc_net_3419 ) , 
-    .p3400 ( optlc_net_3420 ) , .p3401 ( optlc_net_3421 ) , 
-    .p3402 ( optlc_net_3422 ) , .p3403 ( optlc_net_3423 ) , 
-    .p3404 ( optlc_net_3424 ) , .p3405 ( optlc_net_3425 ) , 
-    .p3406 ( optlc_net_3426 ) , .p3407 ( optlc_net_3427 ) , 
-    .p3408 ( optlc_net_3428 ) , .p3409 ( optlc_net_3429 ) , 
-    .p3410 ( optlc_net_3430 ) , .p3411 ( optlc_net_3431 ) , 
-    .p3412 ( optlc_net_3432 ) , .p3413 ( optlc_net_3433 ) , 
-    .p3414 ( optlc_net_3434 ) , .p3415 ( optlc_net_3435 ) , 
-    .p3416 ( optlc_net_3436 ) , .p3417 ( optlc_net_3437 ) , 
-    .p3418 ( optlc_net_3438 ) , .p3419 ( optlc_net_3439 ) , 
-    .p3420 ( optlc_net_3440 ) , .p3421 ( optlc_net_3441 ) , 
-    .p3422 ( optlc_net_3442 ) , .p3423 ( optlc_net_3443 ) , 
-    .p3424 ( optlc_net_3444 ) , .p3425 ( optlc_net_3445 ) , 
-    .p3426 ( optlc_net_3446 ) , .p3427 ( optlc_net_3447 ) , 
-    .p3428 ( optlc_net_3448 ) , .p3429 ( optlc_net_3449 ) , 
-    .p3430 ( optlc_net_3450 ) , .p3431 ( optlc_net_3451 ) , 
-    .p3432 ( optlc_net_3452 ) , .p3433 ( optlc_net_3453 ) , 
-    .p3434 ( optlc_net_3454 ) , .p3435 ( optlc_net_3455 ) , 
-    .p3436 ( optlc_net_3456 ) , .p3437 ( optlc_net_3457 ) , 
-    .p3438 ( optlc_net_3458 ) , .p3439 ( optlc_net_3459 ) , 
-    .p3440 ( optlc_net_3460 ) , .p3441 ( optlc_net_3461 ) , 
-    .p3442 ( optlc_net_3462 ) , .p3443 ( optlc_net_3463 ) , 
-    .p3444 ( optlc_net_3464 ) , .p3445 ( optlc_net_3465 ) , 
-    .p3446 ( optlc_net_3466 ) , .p3447 ( optlc_net_3467 ) , 
-    .p3448 ( optlc_net_3468 ) , .p3449 ( optlc_net_3469 ) , 
-    .p3450 ( optlc_net_3470 ) , .p3451 ( optlc_net_3471 ) , 
-    .p3452 ( optlc_net_3472 ) , .p3453 ( optlc_net_3473 ) , 
-    .p3454 ( optlc_net_3474 ) , .p3455 ( optlc_net_3475 ) , 
-    .p3456 ( optlc_net_3476 ) , .p3457 ( optlc_net_3477 ) , 
-    .p3458 ( optlc_net_3478 ) , .p3459 ( optlc_net_3479 ) , 
-    .p3460 ( optlc_net_3480 ) , .p3461 ( optlc_net_3481 ) , 
-    .p3462 ( optlc_net_3482 ) , .p3463 ( optlc_net_3483 ) , 
-    .p3464 ( optlc_net_3484 ) , .p3465 ( optlc_net_3485 ) , 
-    .p3466 ( optlc_net_3486 ) , .p3467 ( optlc_net_3487 ) , 
-    .p3468 ( optlc_net_3488 ) , .p3469 ( optlc_net_3489 ) , 
-    .p3470 ( optlc_net_3490 ) , .p3471 ( optlc_net_3491 ) , 
-    .p3472 ( optlc_net_3492 ) , .p3473 ( optlc_net_3493 ) , 
-    .p3474 ( optlc_net_3494 ) , .p3475 ( optlc_net_3495 ) , 
-    .p3476 ( optlc_net_3496 ) , .p3477 ( optlc_net_3497 ) , 
-    .p3478 ( optlc_net_3498 ) , .p3479 ( optlc_net_3499 ) , 
-    .p3480 ( optlc_net_3500 ) , .p3481 ( optlc_net_3501 ) , 
-    .p3482 ( optlc_net_3502 ) , .p3483 ( optlc_net_3503 ) , 
-    .p3484 ( optlc_net_3504 ) , .p3485 ( optlc_net_3505 ) , 
-    .p3486 ( optlc_net_3506 ) , .p3487 ( optlc_net_3507 ) , 
-    .p3488 ( optlc_net_3508 ) , .p3489 ( optlc_net_3509 ) , 
-    .p3490 ( optlc_net_3510 ) , .p3491 ( optlc_net_3511 ) , 
-    .p3492 ( optlc_net_3512 ) , .p3493 ( optlc_net_3513 ) , 
-    .p3494 ( optlc_net_3514 ) , .p3495 ( optlc_net_3515 ) , 
-    .p3496 ( optlc_net_3516 ) , .p3497 ( optlc_net_3517 ) , 
-    .p3498 ( optlc_net_3518 ) , .p3499 ( optlc_net_3519 ) , 
-    .p3500 ( optlc_net_3520 ) , .p3501 ( optlc_net_3521 ) , 
-    .p3502 ( optlc_net_3522 ) , .p3503 ( optlc_net_3523 ) , 
-    .p3504 ( optlc_net_3524 ) , .p3505 ( optlc_net_3525 ) , 
-    .p3506 ( optlc_net_3526 ) , .p3507 ( optlc_net_3527 ) , 
-    .p3508 ( optlc_net_3528 ) , .p3509 ( optlc_net_3529 ) , 
-    .p3510 ( optlc_net_3530 ) , .p3511 ( optlc_net_3531 ) , 
-    .p3512 ( optlc_net_3532 ) , .p3513 ( optlc_net_3533 ) , 
-    .p3514 ( optlc_net_3534 ) , .p3515 ( optlc_net_3535 ) , 
-    .p3516 ( optlc_net_3536 ) , .p3517 ( optlc_net_3537 ) , 
-    .p3518 ( optlc_net_3538 ) , .p3519 ( optlc_net_3539 ) , 
-    .p3520 ( optlc_net_3540 ) , .p3521 ( optlc_net_3541 ) , 
-    .p3522 ( optlc_net_3542 ) , .p3523 ( optlc_net_3543 ) , 
-    .p3524 ( optlc_net_3544 ) , .p3525 ( optlc_net_3545 ) , 
-    .p3526 ( optlc_net_3546 ) , .p3527 ( optlc_net_3547 ) , 
-    .p3528 ( optlc_net_3548 ) , .p3529 ( optlc_net_3549 ) , 
-    .p3530 ( optlc_net_3550 ) , .p3531 ( optlc_net_3551 ) , 
-    .p3532 ( optlc_net_3552 ) , .p3533 ( optlc_net_3553 ) , 
-    .p3534 ( optlc_net_3554 ) , .p3535 ( optlc_net_3555 ) , 
-    .p3536 ( optlc_net_3556 ) , .p3537 ( optlc_net_3557 ) , 
-    .p3538 ( optlc_net_3558 ) , .p3539 ( optlc_net_3559 ) , 
-    .p3540 ( optlc_net_3560 ) , .p3541 ( optlc_net_3561 ) , 
-    .p3542 ( optlc_net_3562 ) , .p3543 ( optlc_net_3563 ) , 
-    .p3544 ( optlc_net_3564 ) , .p3545 ( optlc_net_3565 ) , 
-    .p3546 ( optlc_net_3566 ) , .p3547 ( optlc_net_3567 ) , 
-    .p3548 ( optlc_net_3568 ) , .p3549 ( optlc_net_3569 ) , 
-    .p3550 ( optlc_net_3570 ) , .p3551 ( optlc_net_3571 ) , 
-    .p3552 ( optlc_net_3572 ) , .p3553 ( optlc_net_3573 ) , 
-    .p3554 ( optlc_net_3574 ) , .p3555 ( optlc_net_3575 ) , 
-    .p3556 ( optlc_net_3576 ) , .p3557 ( optlc_net_3577 ) , 
-    .p3558 ( optlc_net_3578 ) , .p3559 ( optlc_net_3579 ) , 
-    .p3560 ( optlc_net_3580 ) , .p3561 ( optlc_net_3581 ) , 
-    .p3562 ( optlc_net_3582 ) , .p3563 ( optlc_net_3583 ) , 
-    .p3564 ( optlc_net_3584 ) , .p3565 ( optlc_net_3585 ) , 
-    .p3566 ( optlc_net_3586 ) , .p3567 ( optlc_net_3587 ) , 
-    .p3568 ( optlc_net_3588 ) , .p3569 ( optlc_net_3589 ) , 
-    .p3570 ( optlc_net_3590 ) , .p3571 ( optlc_net_3591 ) , 
-    .p3572 ( optlc_net_3592 ) , .p3573 ( optlc_net_3593 ) , 
-    .p3574 ( optlc_net_3594 ) , .p3575 ( optlc_net_3595 ) , 
-    .p3576 ( optlc_net_3596 ) , .p3577 ( optlc_net_3597 ) , 
-    .p3578 ( optlc_net_3598 ) , .p3579 ( optlc_net_3599 ) , 
-    .p3580 ( optlc_net_3600 ) , .p3581 ( optlc_net_3601 ) , 
-    .p3582 ( optlc_net_3602 ) , .p3583 ( optlc_net_3603 ) , 
-    .p3584 ( optlc_net_3604 ) , .p3585 ( optlc_net_3605 ) , 
-    .p3586 ( optlc_net_3606 ) , .p3587 ( optlc_net_3607 ) ) ;
+    .sc_head ( io_in[26] ) , .sc_tail ( io_out[11] ) , .VDD ( VDD ) , 
+    .VSS ( VSS ) , .h_incr0 ( SYNOPSYS_UNCONNECTED_1 ) , 
+    .p0 ( optlc_net_20 ) , .p1 ( optlc_net_21 ) , .p2 ( optlc_net_22 ) , 
+    .p3 ( optlc_net_23 ) , .p4 ( optlc_net_24 ) , .p5 ( optlc_net_25 ) , 
+    .p6 ( optlc_net_26 ) , .p7 ( optlc_net_27 ) , .p8 ( optlc_net_28 ) , 
+    .p9 ( optlc_net_29 ) , .p10 ( optlc_net_30 ) , .p11 ( optlc_net_31 ) , 
+    .p12 ( optlc_net_32 ) , .p13 ( optlc_net_33 ) , .p14 ( optlc_net_34 ) , 
+    .p15 ( optlc_net_35 ) , .p16 ( optlc_net_36 ) , .p17 ( optlc_net_37 ) , 
+    .p18 ( optlc_net_38 ) , .p19 ( optlc_net_39 ) , .p20 ( optlc_net_40 ) , 
+    .p21 ( optlc_net_41 ) , .p22 ( optlc_net_42 ) , .p23 ( optlc_net_43 ) , 
+    .p24 ( optlc_net_44 ) , .p25 ( optlc_net_45 ) , .p26 ( optlc_net_46 ) , 
+    .p27 ( optlc_net_47 ) , .p28 ( optlc_net_48 ) , .p29 ( optlc_net_49 ) , 
+    .p30 ( optlc_net_50 ) , .p31 ( optlc_net_51 ) , .p32 ( optlc_net_52 ) , 
+    .p33 ( optlc_net_53 ) , .p34 ( optlc_net_54 ) , .p35 ( optlc_net_55 ) , 
+    .p36 ( optlc_net_56 ) , .p37 ( optlc_net_57 ) , .p38 ( optlc_net_58 ) , 
+    .p39 ( optlc_net_59 ) , .p40 ( optlc_net_60 ) , .p41 ( optlc_net_61 ) , 
+    .p42 ( optlc_net_62 ) , .p43 ( optlc_net_63 ) , .p44 ( optlc_net_64 ) , 
+    .p45 ( optlc_net_65 ) , .p46 ( optlc_net_66 ) , .p47 ( optlc_net_67 ) , 
+    .p48 ( optlc_net_68 ) , .p49 ( optlc_net_69 ) , .p50 ( optlc_net_70 ) , 
+    .p51 ( optlc_net_71 ) , .p52 ( optlc_net_72 ) , .p53 ( optlc_net_73 ) , 
+    .p54 ( optlc_net_74 ) , .p55 ( optlc_net_75 ) , .p56 ( optlc_net_76 ) , 
+    .p57 ( optlc_net_77 ) , .p58 ( optlc_net_78 ) , .p59 ( optlc_net_79 ) , 
+    .p60 ( optlc_net_80 ) , .p61 ( optlc_net_81 ) , .p62 ( optlc_net_82 ) , 
+    .p63 ( optlc_net_83 ) , .p64 ( optlc_net_84 ) , .p65 ( optlc_net_85 ) , 
+    .p66 ( optlc_net_86 ) , .p67 ( optlc_net_87 ) , .p68 ( optlc_net_88 ) , 
+    .p69 ( optlc_net_89 ) , .p70 ( optlc_net_90 ) , .p71 ( optlc_net_91 ) , 
+    .p72 ( optlc_net_92 ) , .p73 ( optlc_net_93 ) , .p74 ( optlc_net_94 ) , 
+    .p75 ( optlc_net_95 ) , .p76 ( optlc_net_96 ) , .p77 ( optlc_net_97 ) , 
+    .p78 ( optlc_net_98 ) , .p79 ( optlc_net_99 ) , .p80 ( optlc_net_100 ) , 
+    .p81 ( optlc_net_101 ) , .p82 ( optlc_net_102 ) , .p83 ( optlc_net_103 ) , 
+    .p84 ( optlc_net_104 ) , .p85 ( optlc_net_105 ) , .p86 ( optlc_net_106 ) , 
+    .p87 ( optlc_net_107 ) , .p88 ( optlc_net_108 ) , .p89 ( optlc_net_109 ) , 
+    .p90 ( optlc_net_110 ) , .p91 ( optlc_net_111 ) , .p92 ( optlc_net_112 ) , 
+    .p93 ( optlc_net_113 ) , .p94 ( optlc_net_114 ) , .p95 ( optlc_net_115 ) , 
+    .p96 ( optlc_net_116 ) , .p97 ( optlc_net_117 ) , .p98 ( optlc_net_118 ) , 
+    .p99 ( optlc_net_119 ) , .p100 ( optlc_net_120 ) , 
+    .p101 ( optlc_net_121 ) , .p102 ( optlc_net_122 ) , 
+    .p103 ( optlc_net_123 ) , .p104 ( optlc_net_124 ) , 
+    .p105 ( optlc_net_125 ) , .p106 ( optlc_net_126 ) , 
+    .p107 ( optlc_net_127 ) , .p108 ( optlc_net_128 ) , 
+    .p109 ( optlc_net_129 ) , .p110 ( optlc_net_130 ) , 
+    .p111 ( optlc_net_131 ) , .p112 ( optlc_net_132 ) , 
+    .p113 ( optlc_net_133 ) , .p114 ( optlc_net_134 ) , 
+    .p115 ( optlc_net_135 ) , .p116 ( optlc_net_136 ) , 
+    .p117 ( optlc_net_137 ) , .p118 ( optlc_net_138 ) , 
+    .p119 ( optlc_net_139 ) , .p120 ( optlc_net_140 ) , 
+    .p121 ( optlc_net_141 ) , .p122 ( optlc_net_142 ) , 
+    .p123 ( optlc_net_143 ) , .p124 ( optlc_net_144 ) , 
+    .p125 ( optlc_net_145 ) , .p126 ( optlc_net_146 ) , 
+    .p127 ( optlc_net_147 ) , .p128 ( optlc_net_148 ) , 
+    .p129 ( optlc_net_149 ) , .p130 ( optlc_net_150 ) , 
+    .p131 ( optlc_net_151 ) , .p132 ( optlc_net_152 ) , 
+    .p133 ( optlc_net_153 ) , .p134 ( optlc_net_154 ) , 
+    .p135 ( optlc_net_155 ) , .p136 ( optlc_net_156 ) , 
+    .p137 ( optlc_net_157 ) , .p138 ( optlc_net_158 ) , 
+    .p139 ( optlc_net_159 ) , .p140 ( optlc_net_160 ) , 
+    .p141 ( optlc_net_161 ) , .p142 ( optlc_net_162 ) , 
+    .p143 ( optlc_net_163 ) , .p144 ( optlc_net_164 ) , 
+    .p145 ( optlc_net_165 ) , .p146 ( optlc_net_166 ) , 
+    .p147 ( optlc_net_167 ) , .p148 ( optlc_net_168 ) , 
+    .p149 ( optlc_net_169 ) , .p150 ( optlc_net_170 ) , 
+    .p151 ( optlc_net_171 ) , .p152 ( optlc_net_172 ) , 
+    .p153 ( optlc_net_173 ) , .p154 ( optlc_net_174 ) , 
+    .p155 ( optlc_net_175 ) , .p156 ( optlc_net_176 ) , 
+    .p157 ( optlc_net_177 ) , .p158 ( optlc_net_178 ) , 
+    .p159 ( optlc_net_179 ) , .p160 ( optlc_net_180 ) , 
+    .p161 ( optlc_net_181 ) , .p162 ( optlc_net_182 ) , 
+    .p163 ( optlc_net_183 ) , .p164 ( optlc_net_184 ) , 
+    .p165 ( optlc_net_185 ) , .p166 ( optlc_net_186 ) , 
+    .p167 ( optlc_net_187 ) , .p168 ( optlc_net_188 ) , 
+    .p169 ( optlc_net_189 ) , .p170 ( optlc_net_190 ) , 
+    .p171 ( optlc_net_191 ) , .p172 ( optlc_net_192 ) , 
+    .p173 ( optlc_net_193 ) , .p174 ( optlc_net_194 ) , 
+    .p175 ( optlc_net_195 ) , .p176 ( optlc_net_196 ) , 
+    .p177 ( optlc_net_197 ) , .p178 ( optlc_net_198 ) , 
+    .p179 ( optlc_net_199 ) , .p180 ( optlc_net_200 ) , 
+    .p181 ( optlc_net_201 ) , .p182 ( optlc_net_202 ) , 
+    .p183 ( optlc_net_203 ) , .p184 ( optlc_net_204 ) , 
+    .p185 ( optlc_net_205 ) , .p186 ( optlc_net_206 ) , 
+    .p187 ( optlc_net_207 ) , .p188 ( optlc_net_208 ) , 
+    .p189 ( optlc_net_209 ) , .p190 ( optlc_net_210 ) , 
+    .p191 ( optlc_net_211 ) , .p192 ( optlc_net_212 ) , 
+    .p193 ( optlc_net_213 ) , .p194 ( optlc_net_214 ) , 
+    .p195 ( optlc_net_215 ) , .p196 ( optlc_net_216 ) , 
+    .p197 ( optlc_net_217 ) , .p198 ( optlc_net_218 ) , 
+    .p199 ( optlc_net_219 ) , .p200 ( optlc_net_220 ) , 
+    .p201 ( optlc_net_221 ) , .p202 ( optlc_net_222 ) , 
+    .p203 ( optlc_net_223 ) , .p204 ( optlc_net_224 ) , 
+    .p205 ( optlc_net_225 ) , .p206 ( optlc_net_226 ) , 
+    .p207 ( optlc_net_227 ) , .p208 ( optlc_net_228 ) , 
+    .p209 ( optlc_net_229 ) , .p210 ( optlc_net_230 ) , 
+    .p211 ( optlc_net_231 ) , .p212 ( optlc_net_232 ) , 
+    .p213 ( optlc_net_233 ) , .p214 ( optlc_net_234 ) , 
+    .p215 ( optlc_net_235 ) , .p216 ( optlc_net_236 ) , 
+    .p217 ( optlc_net_237 ) , .p218 ( optlc_net_238 ) , 
+    .p219 ( optlc_net_239 ) , .p220 ( optlc_net_240 ) , 
+    .p221 ( optlc_net_241 ) , .p222 ( optlc_net_242 ) , 
+    .p223 ( optlc_net_243 ) , .p224 ( optlc_net_244 ) , 
+    .p225 ( optlc_net_245 ) , .p226 ( optlc_net_246 ) , 
+    .p227 ( optlc_net_247 ) , .p228 ( optlc_net_248 ) , 
+    .p229 ( optlc_net_249 ) , .p230 ( optlc_net_250 ) , 
+    .p231 ( optlc_net_251 ) , .p232 ( optlc_net_252 ) , 
+    .p233 ( optlc_net_253 ) , .p234 ( optlc_net_254 ) , 
+    .p235 ( optlc_net_255 ) , .p236 ( optlc_net_256 ) , 
+    .p237 ( optlc_net_257 ) , .p238 ( optlc_net_258 ) , 
+    .p239 ( optlc_net_259 ) , .p240 ( optlc_net_260 ) , 
+    .p241 ( optlc_net_261 ) , .p242 ( optlc_net_262 ) , 
+    .p243 ( optlc_net_263 ) , .p244 ( optlc_net_264 ) , 
+    .p245 ( optlc_net_265 ) , .p246 ( optlc_net_266 ) , 
+    .p247 ( optlc_net_267 ) , .p248 ( optlc_net_268 ) , 
+    .p249 ( optlc_net_269 ) , .p250 ( optlc_net_270 ) , 
+    .p251 ( optlc_net_271 ) , .p252 ( optlc_net_272 ) , 
+    .p253 ( optlc_net_273 ) , .p254 ( optlc_net_274 ) , 
+    .p255 ( optlc_net_275 ) , .p256 ( optlc_net_276 ) , 
+    .p257 ( optlc_net_277 ) , .p258 ( optlc_net_278 ) , 
+    .p259 ( optlc_net_279 ) , .p260 ( optlc_net_280 ) , 
+    .p261 ( optlc_net_281 ) , .p262 ( optlc_net_282 ) , 
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+    .p1909 ( optlc_net_1929 ) , .p1910 ( optlc_net_1930 ) , 
+    .p1911 ( optlc_net_1931 ) , .p1912 ( optlc_net_1932 ) , 
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+    .p1919 ( optlc_net_1939 ) , .p1920 ( optlc_net_1940 ) , 
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+    .p1931 ( optlc_net_1951 ) , .p1932 ( optlc_net_1952 ) , 
+    .p1933 ( optlc_net_1953 ) , .p1934 ( optlc_net_1954 ) , 
+    .p1935 ( optlc_net_1955 ) , .p1936 ( optlc_net_1956 ) , 
+    .p1937 ( optlc_net_1957 ) , .p1938 ( optlc_net_1958 ) , 
+    .p1939 ( optlc_net_1959 ) , .p1940 ( optlc_net_1960 ) , 
+    .p1941 ( optlc_net_1961 ) , .p1942 ( optlc_net_1962 ) , 
+    .p1943 ( optlc_net_1963 ) , .p1944 ( optlc_net_1964 ) , 
+    .p1945 ( optlc_net_1965 ) , .p1946 ( optlc_net_1966 ) , 
+    .p1947 ( optlc_net_1967 ) , .p1948 ( optlc_net_1968 ) , 
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+    .p1951 ( optlc_net_1971 ) , .p1952 ( optlc_net_1972 ) , 
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+    .p1957 ( optlc_net_1977 ) , .p1958 ( optlc_net_1978 ) , 
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+    .p1961 ( optlc_net_1981 ) , .p1962 ( optlc_net_1982 ) , 
+    .p1963 ( optlc_net_1983 ) , .p1964 ( optlc_net_1984 ) , 
+    .p1965 ( optlc_net_1985 ) , .p1966 ( optlc_net_1986 ) , 
+    .p1967 ( optlc_net_1987 ) , .p1968 ( optlc_net_1988 ) , 
+    .p1969 ( optlc_net_1989 ) , .p1970 ( optlc_net_1990 ) , 
+    .p1971 ( optlc_net_1991 ) , .p1972 ( optlc_net_1992 ) , 
+    .p1973 ( optlc_net_1993 ) , .p1974 ( optlc_net_1994 ) , 
+    .p1975 ( optlc_net_1995 ) , .p1976 ( optlc_net_1996 ) , 
+    .p1977 ( optlc_net_1997 ) , .p1978 ( optlc_net_1998 ) , 
+    .p1979 ( optlc_net_1999 ) , .p1980 ( optlc_net_2000 ) , 
+    .p1981 ( optlc_net_2001 ) , .p1982 ( optlc_net_2002 ) , 
+    .p1983 ( optlc_net_2003 ) , .p1984 ( optlc_net_2004 ) , 
+    .p1985 ( optlc_net_2005 ) , .p1986 ( optlc_net_2006 ) , 
+    .p1987 ( optlc_net_2007 ) , .p1988 ( optlc_net_2008 ) , 
+    .p1989 ( optlc_net_2009 ) , .p1990 ( optlc_net_2010 ) , 
+    .p1991 ( optlc_net_2011 ) , .p1992 ( optlc_net_2012 ) , 
+    .p1993 ( optlc_net_2013 ) , .p1994 ( optlc_net_2014 ) , 
+    .p1995 ( optlc_net_2015 ) , .p1996 ( optlc_net_2016 ) , 
+    .p1997 ( optlc_net_2017 ) , .p1998 ( optlc_net_2018 ) , 
+    .p1999 ( optlc_net_2019 ) , .p2000 ( optlc_net_2020 ) , 
+    .p2001 ( optlc_net_2021 ) , .p2002 ( optlc_net_2022 ) , 
+    .p2003 ( optlc_net_2023 ) , .p2004 ( optlc_net_2024 ) , 
+    .p2005 ( optlc_net_2025 ) , .p2006 ( optlc_net_2026 ) , 
+    .p2007 ( optlc_net_2027 ) , .p2008 ( optlc_net_2028 ) , 
+    .p2009 ( optlc_net_2029 ) , .p2010 ( optlc_net_2030 ) , 
+    .p2011 ( optlc_net_2031 ) , .p2012 ( optlc_net_2032 ) , 
+    .p2013 ( optlc_net_2033 ) , .p2014 ( optlc_net_2034 ) , 
+    .p2015 ( optlc_net_2035 ) , .p2016 ( optlc_net_2036 ) , 
+    .p2017 ( optlc_net_2037 ) , .p2018 ( optlc_net_2038 ) , 
+    .p2019 ( optlc_net_2039 ) , .p2020 ( optlc_net_2040 ) , 
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+    .p2301 ( optlc_net_2321 ) , .p2302 ( optlc_net_2322 ) , 
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+    .p2315 ( optlc_net_2335 ) , .p2316 ( optlc_net_2336 ) , 
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+    .p2327 ( optlc_net_2347 ) , .p2328 ( optlc_net_2348 ) , 
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+    .p2331 ( optlc_net_2351 ) , .p2332 ( optlc_net_2352 ) , 
+    .p2333 ( optlc_net_2353 ) , .p2334 ( optlc_net_2354 ) , 
+    .p2335 ( optlc_net_2355 ) , .p2336 ( optlc_net_2356 ) , 
+    .p2337 ( optlc_net_2357 ) , .p2338 ( optlc_net_2358 ) , 
+    .p2339 ( optlc_net_2359 ) , .p2340 ( optlc_net_2360 ) , 
+    .p2341 ( optlc_net_2361 ) , .p2342 ( optlc_net_2362 ) , 
+    .p2343 ( optlc_net_2363 ) , .p2344 ( optlc_net_2364 ) , 
+    .p2345 ( optlc_net_2365 ) , .p2346 ( optlc_net_2366 ) , 
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+    .p2351 ( optlc_net_2371 ) , .p2352 ( optlc_net_2372 ) , 
+    .p2353 ( optlc_net_2373 ) , .p2354 ( optlc_net_2374 ) , 
+    .p2355 ( optlc_net_2375 ) , .p2356 ( optlc_net_2376 ) , 
+    .p2357 ( optlc_net_2377 ) , .p2358 ( optlc_net_2378 ) , 
+    .p2359 ( optlc_net_2379 ) , .p2360 ( optlc_net_2380 ) , 
+    .p2361 ( optlc_net_2381 ) , .p2362 ( optlc_net_2382 ) , 
+    .p2363 ( optlc_net_2383 ) , .p2364 ( optlc_net_2384 ) , 
+    .p2365 ( optlc_net_2385 ) , .p2366 ( optlc_net_2386 ) , 
+    .p2367 ( optlc_net_2387 ) , .p2368 ( optlc_net_2388 ) , 
+    .p2369 ( optlc_net_2389 ) , .p2370 ( optlc_net_2390 ) , 
+    .p2371 ( optlc_net_2391 ) , .p2372 ( optlc_net_2392 ) , 
+    .p2373 ( optlc_net_2393 ) , .p2374 ( optlc_net_2394 ) , 
+    .p2375 ( optlc_net_2395 ) , .p2376 ( optlc_net_2396 ) , 
+    .p2377 ( optlc_net_2397 ) , .p2378 ( optlc_net_2398 ) , 
+    .p2379 ( optlc_net_2399 ) , .p2380 ( optlc_net_2400 ) , 
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+    .p3397 ( optlc_net_3417 ) , .p3398 ( optlc_net_3418 ) , 
+    .p3399 ( optlc_net_3419 ) , .p3400 ( optlc_net_3420 ) , 
+    .p3401 ( optlc_net_3421 ) , .p3402 ( optlc_net_3422 ) , 
+    .p3403 ( optlc_net_3423 ) , .p3404 ( optlc_net_3424 ) , 
+    .p3405 ( optlc_net_3425 ) , .p3406 ( optlc_net_3426 ) , 
+    .p3407 ( optlc_net_3427 ) , .p3408 ( optlc_net_3428 ) , 
+    .p3409 ( optlc_net_3429 ) , .p3410 ( optlc_net_3430 ) , 
+    .p3411 ( optlc_net_3431 ) , .p3412 ( optlc_net_3432 ) , 
+    .p3413 ( optlc_net_3433 ) , .p3414 ( optlc_net_3434 ) , 
+    .p3415 ( optlc_net_3435 ) , .p3416 ( optlc_net_3436 ) , 
+    .p3417 ( optlc_net_3437 ) , .p3418 ( optlc_net_3438 ) , 
+    .p3419 ( optlc_net_3439 ) , .p3420 ( optlc_net_3440 ) , 
+    .p3421 ( optlc_net_3441 ) , .p3422 ( optlc_net_3442 ) , 
+    .p3423 ( optlc_net_3443 ) , .p3424 ( optlc_net_3444 ) , 
+    .p3425 ( optlc_net_3445 ) , .p3426 ( optlc_net_3446 ) , 
+    .p3427 ( optlc_net_3447 ) , .p3428 ( optlc_net_3448 ) , 
+    .p3429 ( optlc_net_3449 ) , .p3430 ( optlc_net_3450 ) , 
+    .p3431 ( optlc_net_3451 ) , .p3432 ( optlc_net_3452 ) , 
+    .p3433 ( optlc_net_3453 ) , .p3434 ( optlc_net_3454 ) , 
+    .p3435 ( optlc_net_3455 ) , .p3436 ( optlc_net_3456 ) , 
+    .p3437 ( optlc_net_3457 ) , .p3438 ( optlc_net_3458 ) , 
+    .p3439 ( optlc_net_3459 ) , .p3440 ( optlc_net_3460 ) , 
+    .p3441 ( optlc_net_3461 ) , .p3442 ( optlc_net_3462 ) , 
+    .p3443 ( optlc_net_3463 ) , .p3444 ( optlc_net_3464 ) , 
+    .p3445 ( optlc_net_3465 ) , .p3446 ( optlc_net_3466 ) , 
+    .p3447 ( optlc_net_3467 ) , .p3448 ( optlc_net_3468 ) , 
+    .p3449 ( optlc_net_3469 ) , .p3450 ( optlc_net_3470 ) , 
+    .p3451 ( optlc_net_3471 ) , .p3452 ( optlc_net_3472 ) , 
+    .p3453 ( optlc_net_3473 ) , .p3454 ( optlc_net_3474 ) , 
+    .p3455 ( optlc_net_3475 ) , .p3456 ( optlc_net_3476 ) , 
+    .p3457 ( optlc_net_3477 ) , .p3458 ( optlc_net_3478 ) , 
+    .p3459 ( optlc_net_3479 ) , .p3460 ( optlc_net_3480 ) , 
+    .p3461 ( optlc_net_3481 ) , .p3462 ( optlc_net_3482 ) , 
+    .p3463 ( optlc_net_3483 ) , .p3464 ( optlc_net_3484 ) , 
+    .p3465 ( optlc_net_3485 ) , .p3466 ( optlc_net_3486 ) , 
+    .p3467 ( optlc_net_3487 ) , .p3468 ( optlc_net_3488 ) , 
+    .p3469 ( optlc_net_3489 ) , .p3470 ( optlc_net_3490 ) , 
+    .p3471 ( optlc_net_3491 ) , .p3472 ( optlc_net_3492 ) , 
+    .p3473 ( optlc_net_3493 ) , .p3474 ( optlc_net_3494 ) , 
+    .p3475 ( optlc_net_3495 ) , .p3476 ( optlc_net_3496 ) , 
+    .p3477 ( optlc_net_3497 ) , .p3478 ( optlc_net_3498 ) , 
+    .p3479 ( optlc_net_3499 ) , .p3480 ( optlc_net_3500 ) , 
+    .p3481 ( optlc_net_3501 ) , .p3482 ( optlc_net_3502 ) , 
+    .p3483 ( optlc_net_3503 ) , .p3484 ( optlc_net_3504 ) , 
+    .p3485 ( optlc_net_3505 ) , .p3486 ( optlc_net_3506 ) , 
+    .p3487 ( optlc_net_3507 ) , .p3488 ( optlc_net_3508 ) , 
+    .p3489 ( optlc_net_3509 ) , .p3490 ( optlc_net_3510 ) , 
+    .p3491 ( optlc_net_3511 ) , .p3492 ( optlc_net_3512 ) , 
+    .p3493 ( optlc_net_3513 ) , .p3494 ( optlc_net_3514 ) , 
+    .p3495 ( optlc_net_3515 ) , .p3496 ( optlc_net_3516 ) , 
+    .p3497 ( optlc_net_3517 ) , .p3498 ( optlc_net_3518 ) , 
+    .p3499 ( optlc_net_3519 ) , .p3500 ( optlc_net_3520 ) , 
+    .p3501 ( optlc_net_3521 ) , .p3502 ( optlc_net_3522 ) , 
+    .p3503 ( optlc_net_3523 ) , .p3504 ( optlc_net_3524 ) , 
+    .p3505 ( optlc_net_3525 ) , .p3506 ( optlc_net_3526 ) , 
+    .p3507 ( optlc_net_3527 ) , .p3508 ( optlc_net_3528 ) , 
+    .p3509 ( optlc_net_3529 ) , .p3510 ( optlc_net_3530 ) , 
+    .p3511 ( optlc_net_3531 ) , .p3512 ( optlc_net_3532 ) , 
+    .p3513 ( optlc_net_3533 ) , .p3514 ( optlc_net_3534 ) , 
+    .p3515 ( optlc_net_3535 ) , .p3516 ( optlc_net_3536 ) , 
+    .p3517 ( optlc_net_3537 ) , .p3518 ( optlc_net_3538 ) , 
+    .p3519 ( optlc_net_3539 ) , .p3520 ( optlc_net_3540 ) , 
+    .p3521 ( optlc_net_3541 ) , .p3522 ( optlc_net_3542 ) , 
+    .p3523 ( optlc_net_3543 ) , .p3524 ( optlc_net_3544 ) , 
+    .p3525 ( optlc_net_3545 ) , .p3526 ( optlc_net_3546 ) , 
+    .p3527 ( optlc_net_3547 ) , .p3528 ( optlc_net_3548 ) , 
+    .p3529 ( optlc_net_3549 ) , .p3530 ( optlc_net_3550 ) , 
+    .p3531 ( optlc_net_3551 ) , .p3532 ( optlc_net_3552 ) , 
+    .p3533 ( optlc_net_3553 ) , .p3534 ( optlc_net_3554 ) , 
+    .p3535 ( optlc_net_3555 ) , .p3536 ( optlc_net_3556 ) , 
+    .p3537 ( optlc_net_3557 ) , .p3538 ( optlc_net_3558 ) , 
+    .p3539 ( optlc_net_3559 ) , .p3540 ( optlc_net_3560 ) , 
+    .p3541 ( optlc_net_3561 ) , .p3542 ( optlc_net_3562 ) , 
+    .p3543 ( optlc_net_3563 ) , .p3544 ( optlc_net_3564 ) , 
+    .p3545 ( optlc_net_3565 ) , .p3546 ( optlc_net_3566 ) , 
+    .p3547 ( optlc_net_3567 ) , .p3548 ( optlc_net_3568 ) , 
+    .p3549 ( optlc_net_3569 ) , .p3550 ( optlc_net_3570 ) , 
+    .p3551 ( optlc_net_3571 ) , .p3552 ( optlc_net_3572 ) , 
+    .p3553 ( optlc_net_3573 ) , .p3554 ( optlc_net_3574 ) , 
+    .p3555 ( optlc_net_3575 ) , .p3556 ( optlc_net_3576 ) , 
+    .p3557 ( optlc_net_3577 ) , .p3558 ( optlc_net_3578 ) , 
+    .p3559 ( optlc_net_3579 ) , .p3560 ( optlc_net_3580 ) , 
+    .p3561 ( optlc_net_3581 ) , .p3562 ( optlc_net_3582 ) , 
+    .p3563 ( optlc_net_3583 ) , .p3564 ( optlc_net_3584 ) , 
+    .p3565 ( optlc_net_3585 ) , .p3566 ( optlc_net_3586 ) , 
+    .p3567 ( optlc_net_3587 ) , .p3568 ( optlc_net_3588 ) , 
+    .p3569 ( optlc_net_3589 ) , .p3570 ( optlc_net_3590 ) , 
+    .p3571 ( optlc_net_3591 ) , .p3572 ( optlc_net_3592 ) , 
+    .p3573 ( optlc_net_3593 ) , .p3574 ( optlc_net_3594 ) , 
+    .p3575 ( optlc_net_3595 ) , .p3576 ( optlc_net_3596 ) , 
+    .p3577 ( optlc_net_3597 ) , .p3578 ( optlc_net_3598 ) , 
+    .p3579 ( optlc_net_3599 ) , .p3580 ( optlc_net_3600 ) , 
+    .p3581 ( optlc_net_3601 ) , .p3582 ( optlc_net_3602 ) , 
+    .p3583 ( optlc_net_3603 ) , .p3584 ( optlc_net_3604 ) , 
+    .p3585 ( optlc_net_3605 ) , .p3586 ( optlc_net_3606 ) , 
+    .p3587 ( optlc_net_3607 ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_0 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , 
-    .HI ( io_oeb[0] ) ) ;
+    .HI ( io_oeb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , 
-    .HI ( io_oeb[1] ) ) ;
+    .HI ( io_oeb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , 
-    .HI ( io_oeb[2] ) ) ;
+    .HI ( io_oeb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , 
-    .HI ( io_oeb[3] ) ) ;
+    .HI ( io_oeb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_4 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , 
-    .HI ( io_oeb[12] ) ) ;
+    .HI ( io_oeb[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_5 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , 
-    .HI ( io_oeb[25] ) ) ;
+    .HI ( io_oeb[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_6 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) , 
-    .HI ( io_oeb[26] ) ) ;
+    .HI ( io_oeb[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_7 ( .LO ( SYNOPSYS_UNCONNECTED_9 ) , 
-    .HI ( io_oeb[36] ) ) ;
+    .HI ( io_oeb[36] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_8 ( .LO ( SYNOPSYS_UNCONNECTED_10 ) , 
-    .HI ( io_oeb[37] ) ) ;
+    .HI ( io_oeb[37] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_9 ( .LO ( io_oeb[11] ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_11 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_11 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_10 ( .LO ( io_oeb[35] ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_12 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_12 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_11 ( .LO ( io_out[0] ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_13 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_13 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_12 ( .LO ( io_out[1] ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_14 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_14 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_13 ( .LO ( io_out[2] ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_15 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_15 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_14 ( .LO ( io_out[3] ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_16 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_16 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_15 ( .LO ( io_out[12] ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_17 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_17 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_16 ( .LO ( io_out[25] ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_18 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_18 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_17 ( .LO ( io_out[26] ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_19 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_19 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_18 ( .LO ( io_out[36] ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_20 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_20 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_19 ( .LO ( io_out[37] ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_21 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_21 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_21 ( .LO ( optlc_net_20 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_22 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_22 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_22 ( .LO ( optlc_net_21 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_23 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_23 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_23 ( .LO ( optlc_net_22 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_24 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_24 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_24 ( .LO ( optlc_net_23 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_25 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_25 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_25 ( .LO ( optlc_net_24 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_26 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_26 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_26 ( .LO ( optlc_net_25 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_27 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_27 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_27 ( .LO ( optlc_net_26 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_28 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_28 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_28 ( .LO ( optlc_net_27 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_29 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_29 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_29 ( .LO ( optlc_net_28 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_30 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_30 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_30 ( .LO ( optlc_net_29 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_31 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_31 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_31 ( .LO ( optlc_net_30 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_32 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_32 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_32 ( .LO ( optlc_net_31 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_33 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_33 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_33 ( .LO ( optlc_net_32 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_34 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_34 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_34 ( .LO ( optlc_net_33 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_35 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_35 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_35 ( .LO ( optlc_net_34 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_36 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_36 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_36 ( .LO ( optlc_net_35 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_37 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_37 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_37 ( .LO ( optlc_net_36 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_38 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_38 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_38 ( .LO ( optlc_net_37 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_39 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_39 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_39 ( .LO ( optlc_net_38 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_40 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_40 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_40 ( .LO ( optlc_net_39 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_41 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_41 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_41 ( .LO ( optlc_net_40 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_42 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_42 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_42 ( .LO ( optlc_net_41 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_43 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_43 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_43 ( .LO ( optlc_net_42 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_44 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_44 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_44 ( .LO ( optlc_net_43 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_45 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_45 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_45 ( .LO ( optlc_net_44 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_46 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_46 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_46 ( .LO ( optlc_net_45 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_47 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_47 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_47 ( .LO ( optlc_net_46 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_48 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_48 ( .LO ( optlc_net_47 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_49 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_49 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_49 ( .LO ( optlc_net_48 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_50 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_50 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_50 ( .LO ( optlc_net_49 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_51 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_51 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_51 ( .LO ( optlc_net_50 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_52 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_52 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_52 ( .LO ( optlc_net_51 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_53 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_53 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_53 ( .LO ( optlc_net_52 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_54 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_54 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_54 ( .LO ( optlc_net_53 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_55 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_55 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_55 ( .LO ( optlc_net_54 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_56 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_56 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_56 ( .LO ( optlc_net_55 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_57 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_57 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_57 ( .LO ( optlc_net_56 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_58 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_58 ( .LO ( optlc_net_57 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_59 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_59 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_59 ( .LO ( optlc_net_58 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_60 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_60 ( .LO ( optlc_net_59 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_61 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_61 ( .LO ( optlc_net_60 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_62 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_62 ( .LO ( optlc_net_61 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_63 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_63 ( .LO ( optlc_net_62 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_64 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_64 ( .LO ( optlc_net_63 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_65 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_65 ( .LO ( optlc_net_64 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_66 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_66 ( .LO ( optlc_net_65 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_67 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( optlc_net_66 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_68 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_68 ( .LO ( optlc_net_67 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_69 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_69 ( .LO ( optlc_net_68 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_70 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_70 ( .LO ( optlc_net_69 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_71 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( optlc_net_70 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_72 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_72 ( .LO ( optlc_net_71 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_73 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( optlc_net_72 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_74 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( optlc_net_73 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_75 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( optlc_net_74 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_76 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( optlc_net_75 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_77 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( optlc_net_76 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_78 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( optlc_net_77 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_79 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_79 ( .LO ( optlc_net_78 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_80 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( optlc_net_79 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_81 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_81 ( .LO ( optlc_net_80 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_82 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_82 ( .LO ( optlc_net_81 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_83 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_83 ( .LO ( optlc_net_82 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_84 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( optlc_net_83 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_85 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_85 ( .LO ( optlc_net_84 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_86 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( optlc_net_85 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_87 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_87 ( .LO ( optlc_net_86 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_88 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( optlc_net_87 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_89 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( optlc_net_88 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_90 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( optlc_net_89 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_91 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( optlc_net_90 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_92 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( optlc_net_91 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_93 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( optlc_net_92 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_94 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( optlc_net_93 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_95 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( optlc_net_94 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_96 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( optlc_net_95 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_97 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( optlc_net_96 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_98 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( optlc_net_97 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_99 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( optlc_net_98 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_100 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( optlc_net_99 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_101 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( optlc_net_100 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_102 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( optlc_net_101 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_103 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( optlc_net_102 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_104 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( optlc_net_103 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_105 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( optlc_net_104 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_106 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( optlc_net_105 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_107 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( optlc_net_106 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_108 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( optlc_net_107 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_109 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( optlc_net_108 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_110 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( optlc_net_109 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_111 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( optlc_net_110 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_112 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( optlc_net_111 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_113 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( optlc_net_112 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_114 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_114 ( .LO ( optlc_net_113 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_115 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( optlc_net_114 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_116 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( optlc_net_115 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_117 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( optlc_net_116 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_118 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( optlc_net_117 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_119 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( optlc_net_118 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_120 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( optlc_net_119 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_121 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( optlc_net_120 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_122 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( optlc_net_121 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_123 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( optlc_net_122 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_124 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( optlc_net_123 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_125 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( optlc_net_124 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_126 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( optlc_net_125 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_127 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( optlc_net_126 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_128 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_128 ( .LO ( optlc_net_127 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_129 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( optlc_net_128 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_130 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_130 ( .LO ( optlc_net_129 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_131 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( optlc_net_130 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_132 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( optlc_net_131 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_133 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_133 ( .LO ( optlc_net_132 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_134 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( optlc_net_133 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_135 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_135 ( .LO ( optlc_net_134 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_136 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( optlc_net_135 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_137 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( optlc_net_136 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_138 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( optlc_net_137 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_139 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_139 ( .LO ( optlc_net_138 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_140 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( optlc_net_139 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_141 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( optlc_net_140 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_142 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( optlc_net_141 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_143 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( optlc_net_142 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_144 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( optlc_net_143 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_145 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( optlc_net_144 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_146 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( optlc_net_145 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_147 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( optlc_net_146 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_148 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( optlc_net_147 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_149 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( optlc_net_148 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_150 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( optlc_net_149 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_151 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( optlc_net_150 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_152 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( optlc_net_151 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_153 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( optlc_net_152 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_154 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( optlc_net_153 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_155 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( optlc_net_154 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_156 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( optlc_net_155 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_157 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( optlc_net_156 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_158 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( optlc_net_157 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_159 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_159 ( .LO ( optlc_net_158 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_160 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( optlc_net_159 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_161 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( optlc_net_160 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_162 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( optlc_net_161 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_163 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_163 ( .LO ( optlc_net_162 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_164 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( optlc_net_163 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_165 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_165 ( .LO ( optlc_net_164 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_166 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( optlc_net_165 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_167 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_167 ( .LO ( optlc_net_166 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_168 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( optlc_net_167 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_169 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_169 ( .LO ( optlc_net_168 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_170 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_170 ( .LO ( optlc_net_169 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_171 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_171 ( .LO ( optlc_net_170 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_172 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_172 ( .LO ( optlc_net_171 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_173 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_173 ( .LO ( optlc_net_172 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_174 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_174 ( .LO ( optlc_net_173 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_175 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( optlc_net_174 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_176 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( optlc_net_175 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_177 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( optlc_net_176 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_178 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( optlc_net_177 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_179 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_179 ( .LO ( optlc_net_178 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_180 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_180 ( .LO ( optlc_net_179 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_181 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_181 ( .LO ( optlc_net_180 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_182 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_182 ( .LO ( optlc_net_181 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_183 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_183 ( .LO ( optlc_net_182 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_184 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_184 ( .LO ( optlc_net_183 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_185 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_185 ( .LO ( optlc_net_184 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_186 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_186 ( .LO ( optlc_net_185 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_187 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_187 ( .LO ( optlc_net_186 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_188 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_188 ( .LO ( optlc_net_187 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_189 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_189 ( .LO ( optlc_net_188 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_190 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_190 ( .LO ( optlc_net_189 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_191 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_191 ( .LO ( optlc_net_190 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_192 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_192 ( .LO ( optlc_net_191 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_193 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_193 ( .LO ( optlc_net_192 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_194 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_194 ( .LO ( optlc_net_193 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_195 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_195 ( .LO ( optlc_net_194 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_196 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_196 ( .LO ( optlc_net_195 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_197 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_197 ( .LO ( optlc_net_196 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_198 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_198 ( .LO ( optlc_net_197 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_199 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_199 ( .LO ( optlc_net_198 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_200 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_200 ( .LO ( optlc_net_199 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_201 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_201 ( .LO ( optlc_net_200 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_202 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_202 ( .LO ( optlc_net_201 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_203 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_203 ( .LO ( optlc_net_202 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_204 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_204 ( .LO ( optlc_net_203 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_205 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_205 ( .LO ( optlc_net_204 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_206 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_206 ( .LO ( optlc_net_205 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_207 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_207 ( .LO ( optlc_net_206 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_208 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_208 ( .LO ( optlc_net_207 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_209 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_209 ( .LO ( optlc_net_208 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_210 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_210 ( .LO ( optlc_net_209 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_211 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_211 ( .LO ( optlc_net_210 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_212 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_212 ( .LO ( optlc_net_211 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_213 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_213 ( .LO ( optlc_net_212 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_214 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_214 ( .LO ( optlc_net_213 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_215 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_215 ( .LO ( optlc_net_214 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_216 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_216 ( .LO ( optlc_net_215 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_217 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_217 ( .LO ( optlc_net_216 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_218 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_218 ( .LO ( optlc_net_217 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_219 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_219 ( .LO ( optlc_net_218 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_220 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_220 ( .LO ( optlc_net_219 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_221 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_221 ( .LO ( optlc_net_220 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_222 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_222 ( .LO ( optlc_net_221 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_223 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_223 ( .LO ( optlc_net_222 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_224 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_224 ( .LO ( optlc_net_223 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_225 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_225 ( .LO ( optlc_net_224 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_226 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_226 ( .LO ( optlc_net_225 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_227 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_227 ( .LO ( optlc_net_226 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_228 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_228 ( .LO ( optlc_net_227 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_229 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_229 ( .LO ( optlc_net_228 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_230 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_230 ( .LO ( optlc_net_229 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_231 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_231 ( .LO ( optlc_net_230 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_232 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_232 ( .LO ( optlc_net_231 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_233 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_233 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_233 ( .LO ( optlc_net_232 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_234 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_234 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_234 ( .LO ( optlc_net_233 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_235 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_235 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_235 ( .LO ( optlc_net_234 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_236 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_236 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_236 ( .LO ( optlc_net_235 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_237 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_237 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_237 ( .LO ( optlc_net_236 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_238 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_238 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_238 ( .LO ( optlc_net_237 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_239 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_239 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_239 ( .LO ( optlc_net_238 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_240 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_240 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_240 ( .LO ( optlc_net_239 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_241 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_241 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_241 ( .LO ( optlc_net_240 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_242 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_242 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_242 ( .LO ( optlc_net_241 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_243 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_243 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_243 ( .LO ( optlc_net_242 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_244 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_244 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_244 ( .LO ( optlc_net_243 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_245 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_245 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_245 ( .LO ( optlc_net_244 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_246 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_246 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_246 ( .LO ( optlc_net_245 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_247 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_247 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_247 ( .LO ( optlc_net_246 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_248 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_248 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_248 ( .LO ( optlc_net_247 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_249 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_249 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_249 ( .LO ( optlc_net_248 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_250 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_250 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_250 ( .LO ( optlc_net_249 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_251 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_251 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_251 ( .LO ( optlc_net_250 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_252 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_252 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_252 ( .LO ( optlc_net_251 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_253 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_253 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_253 ( .LO ( optlc_net_252 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_254 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_254 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_254 ( .LO ( optlc_net_253 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_255 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_255 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_255 ( .LO ( optlc_net_254 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_256 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_256 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_256 ( .LO ( optlc_net_255 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_257 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_257 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_257 ( .LO ( optlc_net_256 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_258 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_258 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_258 ( .LO ( optlc_net_257 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_259 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_259 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_259 ( .LO ( optlc_net_258 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_260 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_260 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_260 ( .LO ( optlc_net_259 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_261 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_261 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_261 ( .LO ( optlc_net_260 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_262 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_262 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_262 ( .LO ( optlc_net_261 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_263 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_263 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_263 ( .LO ( optlc_net_262 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_264 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_264 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_264 ( .LO ( optlc_net_263 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_265 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_265 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_265 ( .LO ( optlc_net_264 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_266 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_266 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_266 ( .LO ( optlc_net_265 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_267 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_267 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_267 ( .LO ( optlc_net_266 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_268 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_268 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_268 ( .LO ( optlc_net_267 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_269 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_269 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_269 ( .LO ( optlc_net_268 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_270 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_270 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_270 ( .LO ( optlc_net_269 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_271 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_271 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_271 ( .LO ( optlc_net_270 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_272 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_272 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_272 ( .LO ( optlc_net_271 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_273 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_273 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_273 ( .LO ( optlc_net_272 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_274 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_274 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_274 ( .LO ( optlc_net_273 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_275 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_275 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_275 ( .LO ( optlc_net_274 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_276 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_276 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_276 ( .LO ( optlc_net_275 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_277 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_277 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_277 ( .LO ( optlc_net_276 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_278 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_278 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_278 ( .LO ( optlc_net_277 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_279 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_279 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_279 ( .LO ( optlc_net_278 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_280 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_280 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_280 ( .LO ( optlc_net_279 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_281 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_281 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_281 ( .LO ( optlc_net_280 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_282 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_282 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_282 ( .LO ( optlc_net_281 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_283 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_283 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_283 ( .LO ( optlc_net_282 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_284 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_284 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_284 ( .LO ( optlc_net_283 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_285 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_285 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_285 ( .LO ( optlc_net_284 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_286 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_286 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_286 ( .LO ( optlc_net_285 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_287 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_287 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_287 ( .LO ( optlc_net_286 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_288 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_288 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_288 ( .LO ( optlc_net_287 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_289 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_289 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_289 ( .LO ( optlc_net_288 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_290 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_290 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_290 ( .LO ( optlc_net_289 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_291 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_291 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_291 ( .LO ( optlc_net_290 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_292 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_292 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_292 ( .LO ( optlc_net_291 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_293 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_293 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_293 ( .LO ( optlc_net_292 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_294 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_294 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_294 ( .LO ( optlc_net_293 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_295 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_295 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_295 ( .LO ( optlc_net_294 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_296 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_296 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_296 ( .LO ( optlc_net_295 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_297 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_297 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_297 ( .LO ( optlc_net_296 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_298 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_298 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_298 ( .LO ( optlc_net_297 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_299 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_299 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_299 ( .LO ( optlc_net_298 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_300 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_300 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_300 ( .LO ( optlc_net_299 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_301 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_301 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_301 ( .LO ( optlc_net_300 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_302 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_302 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_302 ( .LO ( optlc_net_301 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_303 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_303 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_303 ( .LO ( optlc_net_302 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_304 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_304 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_304 ( .LO ( optlc_net_303 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_305 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_305 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_305 ( .LO ( optlc_net_304 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_306 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_306 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_306 ( .LO ( optlc_net_305 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_307 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_307 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_307 ( .LO ( optlc_net_306 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_308 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_308 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_308 ( .LO ( optlc_net_307 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_309 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_309 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_309 ( .LO ( optlc_net_308 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_310 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_310 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_310 ( .LO ( optlc_net_309 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_311 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_311 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_311 ( .LO ( optlc_net_310 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_312 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_312 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_312 ( .LO ( optlc_net_311 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_313 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_313 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_313 ( .LO ( optlc_net_312 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_314 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_314 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_314 ( .LO ( optlc_net_313 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_315 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_315 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_315 ( .LO ( optlc_net_314 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_316 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_316 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_316 ( .LO ( optlc_net_315 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_317 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_317 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_317 ( .LO ( optlc_net_316 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_318 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_318 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_318 ( .LO ( optlc_net_317 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_319 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_319 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_319 ( .LO ( optlc_net_318 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_320 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_320 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_320 ( .LO ( optlc_net_319 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_321 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_321 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_321 ( .LO ( optlc_net_320 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_322 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_322 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_322 ( .LO ( optlc_net_321 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_323 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_323 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_323 ( .LO ( optlc_net_322 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_324 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_324 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_324 ( .LO ( optlc_net_323 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_325 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_325 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_325 ( .LO ( optlc_net_324 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_326 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_326 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_326 ( .LO ( optlc_net_325 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_327 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_327 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_327 ( .LO ( optlc_net_326 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_328 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_328 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_328 ( .LO ( optlc_net_327 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_329 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_329 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_329 ( .LO ( optlc_net_328 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_330 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_330 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_330 ( .LO ( optlc_net_329 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_331 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_331 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_331 ( .LO ( optlc_net_330 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_332 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_332 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_332 ( .LO ( optlc_net_331 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_333 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_333 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_333 ( .LO ( optlc_net_332 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_334 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_334 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_334 ( .LO ( optlc_net_333 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_335 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_335 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_335 ( .LO ( optlc_net_334 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_336 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_336 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_336 ( .LO ( optlc_net_335 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_337 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_337 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_337 ( .LO ( optlc_net_336 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_338 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_338 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_338 ( .LO ( optlc_net_337 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_339 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_339 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_339 ( .LO ( optlc_net_338 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_340 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_340 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_340 ( .LO ( optlc_net_339 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_341 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_341 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_341 ( .LO ( optlc_net_340 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_342 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_342 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_342 ( .LO ( optlc_net_341 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_343 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_343 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_343 ( .LO ( optlc_net_342 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_344 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_344 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_344 ( .LO ( optlc_net_343 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_345 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_345 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_345 ( .LO ( optlc_net_344 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_346 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_346 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_346 ( .LO ( optlc_net_345 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_347 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_347 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_347 ( .LO ( optlc_net_346 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_348 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_348 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_348 ( .LO ( optlc_net_347 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_349 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_349 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_349 ( .LO ( optlc_net_348 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_350 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_350 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_350 ( .LO ( optlc_net_349 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_351 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_351 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_351 ( .LO ( optlc_net_350 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_352 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_352 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_352 ( .LO ( optlc_net_351 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_353 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_353 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_353 ( .LO ( optlc_net_352 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_354 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_354 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_354 ( .LO ( optlc_net_353 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_355 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_355 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_355 ( .LO ( optlc_net_354 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_356 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_356 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_356 ( .LO ( optlc_net_355 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_357 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_357 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_357 ( .LO ( optlc_net_356 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_358 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_358 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_358 ( .LO ( optlc_net_357 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_359 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_359 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_359 ( .LO ( optlc_net_358 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_360 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_360 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_360 ( .LO ( optlc_net_359 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_361 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_361 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_362 ( .LO ( optlc_net_360 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_362 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_362 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_363 ( .LO ( optlc_net_361 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_363 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_363 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_364 ( .LO ( optlc_net_362 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_364 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_364 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_365 ( .LO ( optlc_net_363 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_365 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_365 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_366 ( .LO ( optlc_net_364 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_366 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_366 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_367 ( .LO ( optlc_net_365 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_367 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_367 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_368 ( .LO ( optlc_net_366 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_368 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_368 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_369 ( .LO ( optlc_net_367 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_369 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_369 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_370 ( .LO ( optlc_net_368 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_370 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_370 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_371 ( .LO ( optlc_net_369 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_371 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_371 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_372 ( .LO ( optlc_net_370 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_372 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_372 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_373 ( .LO ( optlc_net_371 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_373 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_373 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_374 ( .LO ( optlc_net_372 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_374 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_374 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_375 ( .LO ( optlc_net_373 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_375 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_375 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_376 ( .LO ( optlc_net_374 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_376 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_376 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_377 ( .LO ( optlc_net_375 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_377 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_377 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_378 ( .LO ( optlc_net_376 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_378 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_378 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_379 ( .LO ( optlc_net_377 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_379 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_379 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_380 ( .LO ( optlc_net_378 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_380 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_380 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_381 ( .LO ( optlc_net_379 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_381 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_381 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_382 ( .LO ( optlc_net_380 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_382 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_382 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_383 ( .LO ( optlc_net_381 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_383 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_383 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_384 ( .LO ( optlc_net_382 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_384 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_384 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_385 ( .LO ( optlc_net_383 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_385 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_385 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_386 ( .LO ( optlc_net_384 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_386 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_386 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_387 ( .LO ( optlc_net_385 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_387 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_387 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_388 ( .LO ( optlc_net_386 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_388 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_388 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_389 ( .LO ( optlc_net_387 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_389 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_389 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_390 ( .LO ( optlc_net_388 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_390 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_390 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_391 ( .LO ( optlc_net_389 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_391 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_391 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_392 ( .LO ( optlc_net_390 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_392 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_392 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_393 ( .LO ( optlc_net_391 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_393 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_393 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_394 ( .LO ( optlc_net_392 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_394 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_394 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_395 ( .LO ( optlc_net_393 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_395 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_395 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_396 ( .LO ( optlc_net_394 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_396 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_396 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_397 ( .LO ( optlc_net_395 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_397 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_397 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_398 ( .LO ( optlc_net_396 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_398 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_398 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_399 ( .LO ( optlc_net_397 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_399 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_399 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_400 ( .LO ( optlc_net_398 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_400 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_400 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_401 ( .LO ( optlc_net_399 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_401 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_401 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_402 ( .LO ( optlc_net_400 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_402 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_402 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_403 ( .LO ( optlc_net_401 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_403 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_403 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_404 ( .LO ( optlc_net_402 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_404 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_404 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_405 ( .LO ( optlc_net_403 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_405 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_405 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_406 ( .LO ( optlc_net_404 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_406 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_406 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_407 ( .LO ( optlc_net_405 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_407 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_407 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_408 ( .LO ( optlc_net_406 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_408 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_408 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_409 ( .LO ( optlc_net_407 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_409 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_409 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_410 ( .LO ( optlc_net_408 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_410 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_410 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_411 ( .LO ( optlc_net_409 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_411 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_411 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_412 ( .LO ( optlc_net_410 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_412 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_412 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_413 ( .LO ( optlc_net_411 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_413 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_413 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_414 ( .LO ( optlc_net_412 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_414 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_414 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_415 ( .LO ( optlc_net_413 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_415 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_415 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_416 ( .LO ( optlc_net_414 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_416 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_416 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_417 ( .LO ( optlc_net_415 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_417 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_417 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_418 ( .LO ( optlc_net_416 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_418 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_418 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_419 ( .LO ( optlc_net_417 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_419 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_419 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_420 ( .LO ( optlc_net_418 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_420 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_420 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_421 ( .LO ( optlc_net_419 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_421 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_421 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_422 ( .LO ( optlc_net_420 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_422 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_422 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_423 ( .LO ( optlc_net_421 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_423 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_423 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_424 ( .LO ( optlc_net_422 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_424 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_424 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_425 ( .LO ( optlc_net_423 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_425 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_425 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_426 ( .LO ( optlc_net_424 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_426 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_426 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_427 ( .LO ( optlc_net_425 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_427 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_427 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_428 ( .LO ( optlc_net_426 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_428 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_428 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_429 ( .LO ( optlc_net_427 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_429 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_429 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_430 ( .LO ( optlc_net_428 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_430 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_430 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_431 ( .LO ( optlc_net_429 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_431 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_431 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_432 ( .LO ( optlc_net_430 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_432 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_432 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_433 ( .LO ( optlc_net_431 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_433 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_433 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_434 ( .LO ( optlc_net_432 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_434 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_434 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_435 ( .LO ( optlc_net_433 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_435 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_435 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_436 ( .LO ( optlc_net_434 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_436 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_436 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_437 ( .LO ( optlc_net_435 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_437 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_437 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_438 ( .LO ( optlc_net_436 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_438 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_438 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_439 ( .LO ( optlc_net_437 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_439 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_439 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_440 ( .LO ( optlc_net_438 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_440 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_440 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_441 ( .LO ( optlc_net_439 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_441 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_441 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_442 ( .LO ( optlc_net_440 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_442 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_442 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_443 ( .LO ( optlc_net_441 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_443 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_443 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_444 ( .LO ( optlc_net_442 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_444 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_444 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_445 ( .LO ( optlc_net_443 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_445 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_445 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_446 ( .LO ( optlc_net_444 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_446 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_446 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_447 ( .LO ( optlc_net_445 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_447 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_447 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_448 ( .LO ( optlc_net_446 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_448 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_448 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_449 ( .LO ( optlc_net_447 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_449 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_449 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_450 ( .LO ( optlc_net_448 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_450 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_450 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_451 ( .LO ( optlc_net_449 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_451 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_451 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_452 ( .LO ( optlc_net_450 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_452 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_452 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_453 ( .LO ( optlc_net_451 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_453 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_453 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_454 ( .LO ( optlc_net_452 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_454 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_454 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_455 ( .LO ( optlc_net_453 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_455 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_455 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_456 ( .LO ( optlc_net_454 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_456 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_456 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_457 ( .LO ( optlc_net_455 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_457 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_457 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_458 ( .LO ( optlc_net_456 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_458 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_458 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_459 ( .LO ( optlc_net_457 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_459 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_459 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_460 ( .LO ( optlc_net_458 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_460 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_460 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_461 ( .LO ( optlc_net_459 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_461 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_461 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_462 ( .LO ( optlc_net_460 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_462 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_462 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_463 ( .LO ( optlc_net_461 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_463 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_463 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_464 ( .LO ( optlc_net_462 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_464 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_464 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_465 ( .LO ( optlc_net_463 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_465 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_465 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_466 ( .LO ( optlc_net_464 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_466 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_466 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_467 ( .LO ( optlc_net_465 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_467 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_467 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_468 ( .LO ( optlc_net_466 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_468 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_468 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_469 ( .LO ( optlc_net_467 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_469 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_469 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_470 ( .LO ( optlc_net_468 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_470 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_470 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_471 ( .LO ( optlc_net_469 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_471 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_471 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_472 ( .LO ( optlc_net_470 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_472 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_472 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_473 ( .LO ( optlc_net_471 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_473 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_473 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_474 ( .LO ( optlc_net_472 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_474 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_474 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_475 ( .LO ( optlc_net_473 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_475 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_475 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_476 ( .LO ( optlc_net_474 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_476 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_476 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_477 ( .LO ( optlc_net_475 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_477 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_477 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_478 ( .LO ( optlc_net_476 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_478 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_478 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_479 ( .LO ( optlc_net_477 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_479 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_479 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_480 ( .LO ( optlc_net_478 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_480 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_480 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_481 ( .LO ( optlc_net_479 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_481 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_481 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_482 ( .LO ( optlc_net_480 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_482 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_482 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_483 ( .LO ( optlc_net_481 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_483 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_483 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_484 ( .LO ( optlc_net_482 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_484 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_484 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_485 ( .LO ( optlc_net_483 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_485 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_485 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_486 ( .LO ( optlc_net_484 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_486 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_486 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_487 ( .LO ( optlc_net_485 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_487 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_487 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_488 ( .LO ( optlc_net_486 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_488 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_488 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_489 ( .LO ( optlc_net_487 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_489 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_489 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_490 ( .LO ( optlc_net_488 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_490 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_490 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_491 ( .LO ( optlc_net_489 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_491 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_491 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_492 ( .LO ( optlc_net_490 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_492 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_492 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_493 ( .LO ( optlc_net_491 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_493 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_493 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_494 ( .LO ( optlc_net_492 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_494 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_494 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_495 ( .LO ( optlc_net_493 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_495 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_495 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_496 ( .LO ( optlc_net_494 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_496 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_496 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_497 ( .LO ( optlc_net_495 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_497 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_497 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_498 ( .LO ( optlc_net_496 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_498 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_498 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_499 ( .LO ( optlc_net_497 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_499 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_499 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_500 ( .LO ( optlc_net_498 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_500 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_500 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_501 ( .LO ( optlc_net_499 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_501 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_501 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_502 ( .LO ( optlc_net_500 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_502 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_502 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_503 ( .LO ( optlc_net_501 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_503 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_503 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_504 ( .LO ( optlc_net_502 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_504 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_504 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_505 ( .LO ( optlc_net_503 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_505 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_505 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_506 ( .LO ( optlc_net_504 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_506 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_506 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_507 ( .LO ( optlc_net_505 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_507 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_507 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_508 ( .LO ( optlc_net_506 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_508 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_508 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_509 ( .LO ( optlc_net_507 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_509 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_509 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_510 ( .LO ( optlc_net_508 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_510 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_510 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_511 ( .LO ( optlc_net_509 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_511 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_511 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_512 ( .LO ( optlc_net_510 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_512 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_512 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_513 ( .LO ( optlc_net_511 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_513 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_513 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_514 ( .LO ( optlc_net_512 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_514 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_514 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_515 ( .LO ( optlc_net_513 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_515 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_515 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_516 ( .LO ( optlc_net_514 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_516 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_516 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_517 ( .LO ( optlc_net_515 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_517 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_517 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_518 ( .LO ( optlc_net_516 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_518 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_518 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_519 ( .LO ( optlc_net_517 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_519 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_519 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_520 ( .LO ( optlc_net_518 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_520 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_520 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_521 ( .LO ( optlc_net_519 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_521 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_521 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_522 ( .LO ( optlc_net_520 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_522 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_522 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_523 ( .LO ( optlc_net_521 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_523 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_523 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_524 ( .LO ( optlc_net_522 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_524 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_524 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_525 ( .LO ( optlc_net_523 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_525 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_525 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_526 ( .LO ( optlc_net_524 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_526 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_526 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_527 ( .LO ( optlc_net_525 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_527 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_527 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_528 ( .LO ( optlc_net_526 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_528 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_528 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_529 ( .LO ( optlc_net_527 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_529 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_529 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_530 ( .LO ( optlc_net_528 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_530 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_530 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_531 ( .LO ( optlc_net_529 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_531 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_531 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_532 ( .LO ( optlc_net_530 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_532 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_532 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_533 ( .LO ( optlc_net_531 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_533 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_533 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_534 ( .LO ( optlc_net_532 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_534 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_534 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_535 ( .LO ( optlc_net_533 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_535 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_535 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_536 ( .LO ( optlc_net_534 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_536 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_536 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_537 ( .LO ( optlc_net_535 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_537 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_537 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_538 ( .LO ( optlc_net_536 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_538 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_538 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_539 ( .LO ( optlc_net_537 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_539 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_539 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_540 ( .LO ( optlc_net_538 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_540 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_540 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_541 ( .LO ( optlc_net_539 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_541 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_541 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_542 ( .LO ( optlc_net_540 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_542 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_542 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_543 ( .LO ( optlc_net_541 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_543 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_543 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_544 ( .LO ( optlc_net_542 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_544 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_544 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_545 ( .LO ( optlc_net_543 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_545 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_545 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_546 ( .LO ( optlc_net_544 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_546 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_546 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_547 ( .LO ( optlc_net_545 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_547 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_547 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_548 ( .LO ( optlc_net_546 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_548 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_548 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_549 ( .LO ( optlc_net_547 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_549 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_549 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_550 ( .LO ( optlc_net_548 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_550 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_550 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_551 ( .LO ( optlc_net_549 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_551 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_551 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_552 ( .LO ( optlc_net_550 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_552 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_552 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_553 ( .LO ( optlc_net_551 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_553 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_553 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_554 ( .LO ( optlc_net_552 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_554 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_554 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_555 ( .LO ( optlc_net_553 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_555 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_555 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_556 ( .LO ( optlc_net_554 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_556 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_556 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_557 ( .LO ( optlc_net_555 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_557 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_557 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_558 ( .LO ( optlc_net_556 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_558 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_558 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_559 ( .LO ( optlc_net_557 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_559 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_559 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_560 ( .LO ( optlc_net_558 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_560 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_560 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_561 ( .LO ( optlc_net_559 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_561 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_561 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_562 ( .LO ( optlc_net_560 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_562 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_562 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_563 ( .LO ( optlc_net_561 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_563 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_563 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_564 ( .LO ( optlc_net_562 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_564 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_564 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_565 ( .LO ( optlc_net_563 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_565 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_565 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_566 ( .LO ( optlc_net_564 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_566 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_566 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_567 ( .LO ( optlc_net_565 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_567 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_567 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_568 ( .LO ( optlc_net_566 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_568 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_568 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_569 ( .LO ( optlc_net_567 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_569 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_569 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_570 ( .LO ( optlc_net_568 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_570 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_570 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_571 ( .LO ( optlc_net_569 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_571 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_571 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_572 ( .LO ( optlc_net_570 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_572 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_572 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_573 ( .LO ( optlc_net_571 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_573 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_573 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_574 ( .LO ( optlc_net_572 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_574 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_574 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_575 ( .LO ( optlc_net_573 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_575 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_575 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_576 ( .LO ( optlc_net_574 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_576 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_576 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_577 ( .LO ( optlc_net_575 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_577 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_577 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_578 ( .LO ( optlc_net_576 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_578 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_578 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_579 ( .LO ( optlc_net_577 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_579 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_579 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_580 ( .LO ( optlc_net_578 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_580 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_580 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_581 ( .LO ( optlc_net_579 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_581 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_581 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_582 ( .LO ( optlc_net_580 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_582 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_582 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_583 ( .LO ( optlc_net_581 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_583 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_583 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_584 ( .LO ( optlc_net_582 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_584 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_584 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_585 ( .LO ( optlc_net_583 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_585 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_585 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_586 ( .LO ( optlc_net_584 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_586 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_586 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_587 ( .LO ( optlc_net_585 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_587 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_587 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_588 ( .LO ( optlc_net_586 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_588 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_588 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_589 ( .LO ( optlc_net_587 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_589 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_589 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_590 ( .LO ( optlc_net_588 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_590 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_590 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_591 ( .LO ( optlc_net_589 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_591 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_591 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_592 ( .LO ( optlc_net_590 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_592 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_592 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_593 ( .LO ( optlc_net_591 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_593 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_593 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_594 ( .LO ( optlc_net_592 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_594 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_594 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_595 ( .LO ( optlc_net_593 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_595 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_595 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_596 ( .LO ( optlc_net_594 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_596 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_596 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_597 ( .LO ( optlc_net_595 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_597 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_597 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_598 ( .LO ( optlc_net_596 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_598 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_598 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_599 ( .LO ( optlc_net_597 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_599 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_599 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_600 ( .LO ( optlc_net_598 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_600 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_600 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_601 ( .LO ( optlc_net_599 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_601 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_601 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_602 ( .LO ( optlc_net_600 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_602 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_602 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_603 ( .LO ( optlc_net_601 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_603 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_603 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_604 ( .LO ( optlc_net_602 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_604 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_604 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_605 ( .LO ( optlc_net_603 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_605 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_605 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_606 ( .LO ( optlc_net_604 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_606 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_606 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_607 ( .LO ( optlc_net_605 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_607 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_607 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_608 ( .LO ( optlc_net_606 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_608 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_608 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_609 ( .LO ( optlc_net_607 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_609 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_609 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_610 ( .LO ( optlc_net_608 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_610 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_610 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_611 ( .LO ( optlc_net_609 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_611 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_611 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_612 ( .LO ( optlc_net_610 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_612 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_612 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_613 ( .LO ( optlc_net_611 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_613 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_613 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_614 ( .LO ( optlc_net_612 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_614 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_614 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_615 ( .LO ( optlc_net_613 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_615 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_615 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_616 ( .LO ( optlc_net_614 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_616 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_616 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_617 ( .LO ( optlc_net_615 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_617 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_617 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_618 ( .LO ( optlc_net_616 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_618 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_618 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_619 ( .LO ( optlc_net_617 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_619 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_619 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_620 ( .LO ( optlc_net_618 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_620 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_620 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_621 ( .LO ( optlc_net_619 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_621 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_621 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_622 ( .LO ( optlc_net_620 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_622 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_622 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_623 ( .LO ( optlc_net_621 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_623 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_623 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_624 ( .LO ( optlc_net_622 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_624 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_624 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_625 ( .LO ( optlc_net_623 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_625 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_625 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_626 ( .LO ( optlc_net_624 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_626 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_626 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_627 ( .LO ( optlc_net_625 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_627 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_627 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_628 ( .LO ( optlc_net_626 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_628 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_628 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_629 ( .LO ( optlc_net_627 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_629 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_629 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_630 ( .LO ( optlc_net_628 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_630 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_630 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_631 ( .LO ( optlc_net_629 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_631 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_631 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_632 ( .LO ( optlc_net_630 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_632 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_632 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_633 ( .LO ( optlc_net_631 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_633 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_633 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_634 ( .LO ( optlc_net_632 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_634 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_634 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_635 ( .LO ( optlc_net_633 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_635 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_635 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_636 ( .LO ( optlc_net_634 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_636 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_636 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_637 ( .LO ( optlc_net_635 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_637 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_637 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_638 ( .LO ( optlc_net_636 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_638 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_638 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_639 ( .LO ( optlc_net_637 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_639 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_639 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_640 ( .LO ( optlc_net_638 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_640 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_640 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_641 ( .LO ( optlc_net_639 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_641 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_641 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_643 ( .LO ( optlc_net_640 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_642 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_642 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_644 ( .LO ( optlc_net_641 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_643 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_643 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_645 ( .LO ( optlc_net_642 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_644 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_644 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_646 ( .LO ( optlc_net_643 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_645 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_645 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_647 ( .LO ( optlc_net_644 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_646 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_646 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_648 ( .LO ( optlc_net_645 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_647 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_647 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_649 ( .LO ( optlc_net_646 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_648 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_648 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_650 ( .LO ( optlc_net_647 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_649 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_649 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_651 ( .LO ( optlc_net_648 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_650 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_650 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_652 ( .LO ( optlc_net_649 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_651 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_651 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_653 ( .LO ( optlc_net_650 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_652 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_652 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_654 ( .LO ( optlc_net_651 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_653 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_653 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_655 ( .LO ( optlc_net_652 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_654 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_654 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_656 ( .LO ( optlc_net_653 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_655 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_655 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_657 ( .LO ( optlc_net_654 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_656 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_656 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_658 ( .LO ( optlc_net_655 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_657 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_657 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_659 ( .LO ( optlc_net_656 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_658 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_658 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_660 ( .LO ( optlc_net_657 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_659 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_659 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_661 ( .LO ( optlc_net_658 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_660 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_660 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_662 ( .LO ( optlc_net_659 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_661 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_661 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_663 ( .LO ( optlc_net_660 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_662 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_662 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_664 ( .LO ( optlc_net_661 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_663 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_663 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_665 ( .LO ( optlc_net_662 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_664 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_664 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_666 ( .LO ( optlc_net_663 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_665 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_665 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_668 ( .LO ( optlc_net_664 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_666 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_666 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_669 ( .LO ( optlc_net_665 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_667 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_667 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_670 ( .LO ( optlc_net_666 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_668 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_668 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_671 ( .LO ( optlc_net_667 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_669 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_669 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_672 ( .LO ( optlc_net_668 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_670 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_670 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_673 ( .LO ( optlc_net_669 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_671 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_671 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_674 ( .LO ( optlc_net_670 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_672 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_672 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_675 ( .LO ( optlc_net_671 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_673 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_673 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_676 ( .LO ( optlc_net_672 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_674 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_674 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_677 ( .LO ( optlc_net_673 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_675 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_675 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_678 ( .LO ( optlc_net_674 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_676 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_676 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_679 ( .LO ( optlc_net_675 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_677 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_677 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_680 ( .LO ( optlc_net_676 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_678 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_678 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_682 ( .LO ( optlc_net_677 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_679 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_679 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_683 ( .LO ( optlc_net_678 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_680 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_680 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_684 ( .LO ( optlc_net_679 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_681 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_681 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_685 ( .LO ( optlc_net_680 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_682 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_682 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_686 ( .LO ( optlc_net_681 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_683 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_683 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_687 ( .LO ( optlc_net_682 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_684 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_684 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_688 ( .LO ( optlc_net_683 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_685 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_685 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_689 ( .LO ( optlc_net_684 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_686 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_686 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_690 ( .LO ( optlc_net_685 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_687 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_687 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_691 ( .LO ( optlc_net_686 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_688 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_688 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_692 ( .LO ( optlc_net_687 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_689 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_689 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_693 ( .LO ( optlc_net_688 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_690 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_690 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_694 ( .LO ( optlc_net_689 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_691 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_691 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_695 ( .LO ( optlc_net_690 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_692 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_692 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_696 ( .LO ( optlc_net_691 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_693 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_693 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_697 ( .LO ( optlc_net_692 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_694 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_694 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_698 ( .LO ( optlc_net_693 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_695 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_695 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_699 ( .LO ( optlc_net_694 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_696 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_696 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_700 ( .LO ( optlc_net_695 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_697 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_697 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_701 ( .LO ( optlc_net_696 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_698 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_698 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_702 ( .LO ( optlc_net_697 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_699 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_699 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_703 ( .LO ( optlc_net_698 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_700 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_700 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_704 ( .LO ( optlc_net_699 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_701 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_701 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_705 ( .LO ( optlc_net_700 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_702 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_702 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_706 ( .LO ( optlc_net_701 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_703 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_703 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_707 ( .LO ( optlc_net_702 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_704 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_704 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_708 ( .LO ( optlc_net_703 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_705 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_705 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_709 ( .LO ( optlc_net_704 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_706 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_706 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_710 ( .LO ( optlc_net_705 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_707 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_707 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_711 ( .LO ( optlc_net_706 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_708 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_708 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_712 ( .LO ( optlc_net_707 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_709 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_709 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_713 ( .LO ( optlc_net_708 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_710 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_710 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_714 ( .LO ( optlc_net_709 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_711 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_711 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_715 ( .LO ( optlc_net_710 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_712 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_712 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_716 ( .LO ( optlc_net_711 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_713 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_713 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_717 ( .LO ( optlc_net_712 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_714 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_714 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_718 ( .LO ( optlc_net_713 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_715 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_715 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_719 ( .LO ( optlc_net_714 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_716 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_716 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_720 ( .LO ( optlc_net_715 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_717 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_717 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_721 ( .LO ( optlc_net_716 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_718 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_718 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_722 ( .LO ( optlc_net_717 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_719 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_719 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_723 ( .LO ( optlc_net_718 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_720 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_720 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_724 ( .LO ( optlc_net_719 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_721 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_721 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_725 ( .LO ( optlc_net_720 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_722 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_722 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_726 ( .LO ( optlc_net_721 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_723 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_723 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_727 ( .LO ( optlc_net_722 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_724 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_724 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_728 ( .LO ( optlc_net_723 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_725 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_725 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_729 ( .LO ( optlc_net_724 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_726 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_726 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_730 ( .LO ( optlc_net_725 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_727 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_727 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_731 ( .LO ( optlc_net_726 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_728 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_728 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_732 ( .LO ( optlc_net_727 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_729 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_729 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_733 ( .LO ( optlc_net_728 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_730 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_730 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_734 ( .LO ( optlc_net_729 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_731 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_731 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_735 ( .LO ( optlc_net_730 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_732 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_732 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_736 ( .LO ( optlc_net_731 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_733 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_733 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_737 ( .LO ( optlc_net_732 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_734 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_734 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_738 ( .LO ( optlc_net_733 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_735 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_735 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_739 ( .LO ( optlc_net_734 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_736 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_736 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_740 ( .LO ( optlc_net_735 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_737 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_737 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_741 ( .LO ( optlc_net_736 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_738 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_738 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_742 ( .LO ( optlc_net_737 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_739 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_739 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_743 ( .LO ( optlc_net_738 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_740 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_740 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_744 ( .LO ( optlc_net_739 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_741 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_741 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_745 ( .LO ( optlc_net_740 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_742 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_742 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_746 ( .LO ( optlc_net_741 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_743 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_743 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_747 ( .LO ( optlc_net_742 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_744 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_744 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_748 ( .LO ( optlc_net_743 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_745 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_745 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_749 ( .LO ( optlc_net_744 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_746 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_746 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_750 ( .LO ( optlc_net_745 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_747 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_747 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_752 ( .LO ( optlc_net_746 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_748 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_748 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_753 ( .LO ( optlc_net_747 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_749 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_749 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_754 ( .LO ( optlc_net_748 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_750 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_750 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_755 ( .LO ( optlc_net_749 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_751 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_751 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_756 ( .LO ( optlc_net_750 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_752 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_752 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_757 ( .LO ( optlc_net_751 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_753 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_753 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_758 ( .LO ( optlc_net_752 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_754 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_754 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_759 ( .LO ( optlc_net_753 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_755 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_755 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_760 ( .LO ( optlc_net_754 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_756 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_756 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_761 ( .LO ( optlc_net_755 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_757 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_757 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_762 ( .LO ( optlc_net_756 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_758 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_758 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_763 ( .LO ( optlc_net_757 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_759 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_759 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_764 ( .LO ( optlc_net_758 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_760 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_760 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_765 ( .LO ( optlc_net_759 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_761 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_761 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_766 ( .LO ( optlc_net_760 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_762 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_762 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_767 ( .LO ( optlc_net_761 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_763 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_763 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_768 ( .LO ( optlc_net_762 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_764 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_764 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_769 ( .LO ( optlc_net_763 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_765 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_765 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_770 ( .LO ( optlc_net_764 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_766 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_766 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_771 ( .LO ( optlc_net_765 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_767 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_767 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_772 ( .LO ( optlc_net_766 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_768 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_768 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_773 ( .LO ( optlc_net_767 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_769 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_769 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_774 ( .LO ( optlc_net_768 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_770 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_770 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_775 ( .LO ( optlc_net_769 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_771 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_771 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_776 ( .LO ( optlc_net_770 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_772 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_772 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_777 ( .LO ( optlc_net_771 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_773 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_773 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_778 ( .LO ( optlc_net_772 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_774 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_774 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_779 ( .LO ( optlc_net_773 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_775 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_775 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_780 ( .LO ( optlc_net_774 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_776 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_776 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_781 ( .LO ( optlc_net_775 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_777 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_777 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_782 ( .LO ( optlc_net_776 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_778 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_778 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_783 ( .LO ( optlc_net_777 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_779 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_779 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_784 ( .LO ( optlc_net_778 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_780 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_780 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_785 ( .LO ( optlc_net_779 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_781 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_781 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_786 ( .LO ( optlc_net_780 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_782 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_782 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_787 ( .LO ( optlc_net_781 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_783 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_783 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_788 ( .LO ( optlc_net_782 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_784 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_784 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_789 ( .LO ( optlc_net_783 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_785 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_785 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_790 ( .LO ( optlc_net_784 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_786 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_786 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_791 ( .LO ( optlc_net_785 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_787 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_787 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_792 ( .LO ( optlc_net_786 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_788 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_788 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_793 ( .LO ( optlc_net_787 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_789 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_789 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_794 ( .LO ( optlc_net_788 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_790 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_790 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_795 ( .LO ( optlc_net_789 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_791 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_791 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_796 ( .LO ( optlc_net_790 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_792 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_792 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_797 ( .LO ( optlc_net_791 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_793 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_793 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_798 ( .LO ( optlc_net_792 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_794 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_794 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_799 ( .LO ( optlc_net_793 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_795 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_795 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_800 ( .LO ( optlc_net_794 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_796 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_796 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_801 ( .LO ( optlc_net_795 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_797 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_797 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_802 ( .LO ( optlc_net_796 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_798 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_798 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_803 ( .LO ( optlc_net_797 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_799 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_799 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_804 ( .LO ( optlc_net_798 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_800 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_800 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_805 ( .LO ( optlc_net_799 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_801 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_801 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_806 ( .LO ( optlc_net_800 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_802 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_802 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_807 ( .LO ( optlc_net_801 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_803 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_803 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_808 ( .LO ( optlc_net_802 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_804 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_804 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_809 ( .LO ( optlc_net_803 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_805 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_805 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_810 ( .LO ( optlc_net_804 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_806 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_806 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_811 ( .LO ( optlc_net_805 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_807 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_807 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_812 ( .LO ( optlc_net_806 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_808 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_808 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_813 ( .LO ( optlc_net_807 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_809 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_809 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_814 ( .LO ( optlc_net_808 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_810 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_810 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_815 ( .LO ( optlc_net_809 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_811 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_811 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_816 ( .LO ( optlc_net_810 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_812 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_812 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_817 ( .LO ( optlc_net_811 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_813 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_813 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_818 ( .LO ( optlc_net_812 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_814 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_814 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_819 ( .LO ( optlc_net_813 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_815 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_815 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_820 ( .LO ( optlc_net_814 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_816 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_816 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_821 ( .LO ( optlc_net_815 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_817 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_817 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_822 ( .LO ( optlc_net_816 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_818 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_818 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_823 ( .LO ( optlc_net_817 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_819 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_819 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_824 ( .LO ( optlc_net_818 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_820 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_820 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_826 ( .LO ( optlc_net_819 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_821 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_821 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_827 ( .LO ( optlc_net_820 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_822 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_822 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_828 ( .LO ( optlc_net_821 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_823 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_823 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_829 ( .LO ( optlc_net_822 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_824 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_824 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_830 ( .LO ( optlc_net_823 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_825 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_825 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_831 ( .LO ( optlc_net_824 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_826 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_826 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_832 ( .LO ( optlc_net_825 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_827 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_827 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_833 ( .LO ( optlc_net_826 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_828 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_828 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_834 ( .LO ( optlc_net_827 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_829 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_829 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_835 ( .LO ( optlc_net_828 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_830 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_830 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_836 ( .LO ( optlc_net_829 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_831 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_831 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_837 ( .LO ( optlc_net_830 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_832 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_832 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_838 ( .LO ( optlc_net_831 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_833 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_833 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_839 ( .LO ( optlc_net_832 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_834 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_834 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_840 ( .LO ( optlc_net_833 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_835 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_835 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_841 ( .LO ( optlc_net_834 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_836 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_836 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_842 ( .LO ( optlc_net_835 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_837 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_837 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_843 ( .LO ( optlc_net_836 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_838 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_838 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_844 ( .LO ( optlc_net_837 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_839 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_839 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_845 ( .LO ( optlc_net_838 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_840 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_840 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_846 ( .LO ( optlc_net_839 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_841 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_841 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_847 ( .LO ( optlc_net_840 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_842 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_842 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_848 ( .LO ( optlc_net_841 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_843 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_843 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_849 ( .LO ( optlc_net_842 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_844 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_844 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_851 ( .LO ( optlc_net_843 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_845 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_845 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_852 ( .LO ( optlc_net_844 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_846 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_846 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_853 ( .LO ( optlc_net_845 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_847 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_847 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_854 ( .LO ( optlc_net_846 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_848 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_848 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_855 ( .LO ( optlc_net_847 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_849 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_849 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_856 ( .LO ( optlc_net_848 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_850 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_850 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_858 ( .LO ( optlc_net_849 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_851 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_851 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_859 ( .LO ( optlc_net_850 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_852 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_852 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_860 ( .LO ( optlc_net_851 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_853 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_853 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_861 ( .LO ( optlc_net_852 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_854 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_854 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_862 ( .LO ( optlc_net_853 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_855 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_855 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_863 ( .LO ( optlc_net_854 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_856 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_856 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_864 ( .LO ( optlc_net_855 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_857 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_857 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_865 ( .LO ( optlc_net_856 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_858 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_858 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_866 ( .LO ( optlc_net_857 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_859 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_859 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_867 ( .LO ( optlc_net_858 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_860 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_860 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_868 ( .LO ( optlc_net_859 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_861 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_861 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_869 ( .LO ( optlc_net_860 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_862 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_862 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_870 ( .LO ( optlc_net_861 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_863 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_863 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_871 ( .LO ( optlc_net_862 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_864 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_864 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_872 ( .LO ( optlc_net_863 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_865 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_865 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_873 ( .LO ( optlc_net_864 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_866 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_866 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_874 ( .LO ( optlc_net_865 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_867 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_867 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_875 ( .LO ( optlc_net_866 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_868 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_868 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_876 ( .LO ( optlc_net_867 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_869 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_869 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_877 ( .LO ( optlc_net_868 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_870 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_870 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_878 ( .LO ( optlc_net_869 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_871 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_871 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_879 ( .LO ( optlc_net_870 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_872 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_872 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_880 ( .LO ( optlc_net_871 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_873 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_873 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_881 ( .LO ( optlc_net_872 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_874 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_874 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_882 ( .LO ( optlc_net_873 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_875 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_875 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_883 ( .LO ( optlc_net_874 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_876 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_876 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_884 ( .LO ( optlc_net_875 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_877 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_877 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_885 ( .LO ( optlc_net_876 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_878 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_878 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_886 ( .LO ( optlc_net_877 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_879 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_879 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_887 ( .LO ( optlc_net_878 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_880 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_880 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_888 ( .LO ( optlc_net_879 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_881 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_881 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_889 ( .LO ( optlc_net_880 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_882 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_882 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_890 ( .LO ( optlc_net_881 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_883 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_883 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_891 ( .LO ( optlc_net_882 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_884 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_884 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_892 ( .LO ( optlc_net_883 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_885 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_885 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_893 ( .LO ( optlc_net_884 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_886 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_886 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_894 ( .LO ( optlc_net_885 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_887 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_887 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_895 ( .LO ( optlc_net_886 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_888 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_888 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_896 ( .LO ( optlc_net_887 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_889 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_889 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_897 ( .LO ( optlc_net_888 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_890 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_890 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_898 ( .LO ( optlc_net_889 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_891 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_891 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_899 ( .LO ( optlc_net_890 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_892 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_892 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_900 ( .LO ( optlc_net_891 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_893 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_893 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_901 ( .LO ( optlc_net_892 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_894 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_894 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_902 ( .LO ( optlc_net_893 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_895 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_895 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_903 ( .LO ( optlc_net_894 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_896 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_896 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_904 ( .LO ( optlc_net_895 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_897 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_897 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_905 ( .LO ( optlc_net_896 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_898 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_898 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_906 ( .LO ( optlc_net_897 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_899 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_899 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_907 ( .LO ( optlc_net_898 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_900 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_900 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_908 ( .LO ( optlc_net_899 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_901 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_901 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_909 ( .LO ( optlc_net_900 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_902 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_902 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_910 ( .LO ( optlc_net_901 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_903 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_903 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_911 ( .LO ( optlc_net_902 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_904 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_904 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_912 ( .LO ( optlc_net_903 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_905 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_905 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_913 ( .LO ( optlc_net_904 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_906 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_906 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_914 ( .LO ( optlc_net_905 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_907 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_907 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_915 ( .LO ( optlc_net_906 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_908 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_908 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_916 ( .LO ( optlc_net_907 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_909 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_909 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_917 ( .LO ( optlc_net_908 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_910 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_910 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_918 ( .LO ( optlc_net_909 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_911 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_911 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_919 ( .LO ( optlc_net_910 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_912 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_912 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_920 ( .LO ( optlc_net_911 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_913 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_913 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_921 ( .LO ( optlc_net_912 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_914 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_914 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_922 ( .LO ( optlc_net_913 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_915 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_915 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_923 ( .LO ( optlc_net_914 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_916 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_916 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_924 ( .LO ( optlc_net_915 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_917 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_917 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_925 ( .LO ( optlc_net_916 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_918 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_918 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_926 ( .LO ( optlc_net_917 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_919 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_919 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_927 ( .LO ( optlc_net_918 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_920 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_920 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_928 ( .LO ( optlc_net_919 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_921 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_921 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_929 ( .LO ( optlc_net_920 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_922 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_922 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_930 ( .LO ( optlc_net_921 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_923 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_923 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_931 ( .LO ( optlc_net_922 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_924 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_924 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_932 ( .LO ( optlc_net_923 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_925 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_925 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_933 ( .LO ( optlc_net_924 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_926 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_926 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_934 ( .LO ( optlc_net_925 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_927 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_927 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_935 ( .LO ( optlc_net_926 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_928 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_928 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_936 ( .LO ( optlc_net_927 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_929 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_929 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_938 ( .LO ( optlc_net_928 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_930 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_930 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_940 ( .LO ( optlc_net_929 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_931 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_931 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_941 ( .LO ( optlc_net_930 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_932 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_932 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_942 ( .LO ( optlc_net_931 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_933 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_933 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_943 ( .LO ( optlc_net_932 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_934 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_934 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_945 ( .LO ( optlc_net_933 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_935 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_935 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_946 ( .LO ( optlc_net_934 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_936 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_936 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_947 ( .LO ( optlc_net_935 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_937 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_937 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_948 ( .LO ( optlc_net_936 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_938 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_938 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_949 ( .LO ( optlc_net_937 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_939 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_939 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_950 ( .LO ( optlc_net_938 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_940 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_940 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_951 ( .LO ( optlc_net_939 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_941 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_941 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_952 ( .LO ( optlc_net_940 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_942 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_942 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_953 ( .LO ( optlc_net_941 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_943 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_943 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_954 ( .LO ( optlc_net_942 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_944 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_944 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_955 ( .LO ( optlc_net_943 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_945 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_945 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_956 ( .LO ( optlc_net_944 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_946 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_946 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_957 ( .LO ( optlc_net_945 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_947 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_947 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_958 ( .LO ( optlc_net_946 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_948 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_948 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_959 ( .LO ( optlc_net_947 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_949 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_949 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_960 ( .LO ( optlc_net_948 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_950 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_950 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_961 ( .LO ( optlc_net_949 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_951 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_951 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_962 ( .LO ( optlc_net_950 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_952 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_952 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_963 ( .LO ( optlc_net_951 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_953 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_953 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_964 ( .LO ( optlc_net_952 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_954 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_954 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_965 ( .LO ( optlc_net_953 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_955 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_955 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_966 ( .LO ( optlc_net_954 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_956 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_956 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_967 ( .LO ( optlc_net_955 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_957 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_957 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_968 ( .LO ( optlc_net_956 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_958 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_958 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_969 ( .LO ( optlc_net_957 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_959 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_959 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_970 ( .LO ( optlc_net_958 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_960 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_960 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_971 ( .LO ( optlc_net_959 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_961 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_961 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_972 ( .LO ( optlc_net_960 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_962 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_962 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_973 ( .LO ( optlc_net_961 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_963 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_963 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_974 ( .LO ( optlc_net_962 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_964 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_964 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_975 ( .LO ( optlc_net_963 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_965 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_965 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_976 ( .LO ( optlc_net_964 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_966 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_966 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_978 ( .LO ( optlc_net_965 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_967 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_967 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_979 ( .LO ( optlc_net_966 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_968 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_968 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_980 ( .LO ( optlc_net_967 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_969 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_969 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_981 ( .LO ( optlc_net_968 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_970 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_970 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_983 ( .LO ( optlc_net_969 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_971 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_971 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_984 ( .LO ( optlc_net_970 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_972 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_972 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_985 ( .LO ( optlc_net_971 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_973 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_973 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_986 ( .LO ( optlc_net_972 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_974 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_974 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_987 ( .LO ( optlc_net_973 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_975 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_975 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_988 ( .LO ( optlc_net_974 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_976 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_976 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_989 ( .LO ( optlc_net_975 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_977 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_977 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_991 ( .LO ( optlc_net_976 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_978 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_978 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_992 ( .LO ( optlc_net_977 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_979 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_979 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_993 ( .LO ( optlc_net_978 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_980 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_980 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_994 ( .LO ( optlc_net_979 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_981 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_981 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_995 ( .LO ( optlc_net_980 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_982 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_982 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_996 ( .LO ( optlc_net_981 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_983 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_983 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_997 ( .LO ( optlc_net_982 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_984 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_984 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_998 ( .LO ( optlc_net_983 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_985 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_985 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_999 ( .LO ( optlc_net_984 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_986 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_986 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1000 ( .LO ( optlc_net_985 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_987 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_987 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1001 ( .LO ( optlc_net_986 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_988 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_988 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1002 ( .LO ( optlc_net_987 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_989 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_989 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1004 ( .LO ( optlc_net_988 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_990 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_990 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1006 ( .LO ( optlc_net_989 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_991 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_991 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1007 ( .LO ( optlc_net_990 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_992 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_992 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1008 ( .LO ( optlc_net_991 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_993 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_993 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1009 ( .LO ( optlc_net_992 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_994 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_994 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1010 ( .LO ( optlc_net_993 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_995 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_995 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1011 ( .LO ( optlc_net_994 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_996 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_996 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1012 ( .LO ( optlc_net_995 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_997 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_997 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1013 ( .LO ( optlc_net_996 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_998 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_998 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1014 ( .LO ( optlc_net_997 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_999 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_999 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1015 ( .LO ( optlc_net_998 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1000 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1000 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1016 ( .LO ( optlc_net_999 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1001 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1001 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1017 ( .LO ( optlc_net_1000 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1002 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1002 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1018 ( .LO ( optlc_net_1001 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1003 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1003 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1019 ( .LO ( optlc_net_1002 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1004 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1004 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1020 ( .LO ( optlc_net_1003 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1005 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1005 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1021 ( .LO ( optlc_net_1004 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1006 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1006 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1022 ( .LO ( optlc_net_1005 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1007 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1007 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1023 ( .LO ( optlc_net_1006 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1008 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1008 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1024 ( .LO ( optlc_net_1007 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1009 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1009 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1025 ( .LO ( optlc_net_1008 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1010 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1010 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1026 ( .LO ( optlc_net_1009 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1011 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1011 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1027 ( .LO ( optlc_net_1010 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1012 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1012 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1028 ( .LO ( optlc_net_1011 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1013 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1013 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1029 ( .LO ( optlc_net_1012 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1014 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1014 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1030 ( .LO ( optlc_net_1013 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1015 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1015 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1031 ( .LO ( optlc_net_1014 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1016 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1016 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1032 ( .LO ( optlc_net_1015 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1017 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1017 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1033 ( .LO ( optlc_net_1016 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1018 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1018 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1034 ( .LO ( optlc_net_1017 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1019 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1019 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1035 ( .LO ( optlc_net_1018 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1020 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1020 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1036 ( .LO ( optlc_net_1019 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1021 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1021 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1037 ( .LO ( optlc_net_1020 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1022 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1022 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1038 ( .LO ( optlc_net_1021 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1023 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1023 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1039 ( .LO ( optlc_net_1022 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1024 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1024 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1040 ( .LO ( optlc_net_1023 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1025 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1025 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1041 ( .LO ( optlc_net_1024 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1026 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1026 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1042 ( .LO ( optlc_net_1025 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1027 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1027 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1043 ( .LO ( optlc_net_1026 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1028 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1028 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1044 ( .LO ( optlc_net_1027 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1029 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1029 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1045 ( .LO ( optlc_net_1028 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1030 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1030 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1046 ( .LO ( optlc_net_1029 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1031 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1031 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1047 ( .LO ( optlc_net_1030 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1032 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1032 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1048 ( .LO ( optlc_net_1031 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1033 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1033 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1049 ( .LO ( optlc_net_1032 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1034 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1034 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1050 ( .LO ( optlc_net_1033 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1035 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1035 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1051 ( .LO ( optlc_net_1034 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1036 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1036 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1052 ( .LO ( optlc_net_1035 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1037 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1037 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1053 ( .LO ( optlc_net_1036 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1038 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1038 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1054 ( .LO ( optlc_net_1037 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1039 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1039 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1055 ( .LO ( optlc_net_1038 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1040 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1040 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1056 ( .LO ( optlc_net_1039 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1041 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1041 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1057 ( .LO ( optlc_net_1040 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1042 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1042 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1058 ( .LO ( optlc_net_1041 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1043 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1043 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1059 ( .LO ( optlc_net_1042 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1044 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1044 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1060 ( .LO ( optlc_net_1043 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1045 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1045 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1061 ( .LO ( optlc_net_1044 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1046 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1046 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1062 ( .LO ( optlc_net_1045 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1047 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1047 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1063 ( .LO ( optlc_net_1046 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1048 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1048 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1065 ( .LO ( optlc_net_1047 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1049 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1049 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1066 ( .LO ( optlc_net_1048 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1050 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1050 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1067 ( .LO ( optlc_net_1049 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1051 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1051 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1068 ( .LO ( optlc_net_1050 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1052 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1052 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1069 ( .LO ( optlc_net_1051 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1053 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1053 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1070 ( .LO ( optlc_net_1052 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1054 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1054 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1071 ( .LO ( optlc_net_1053 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1055 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1055 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1072 ( .LO ( optlc_net_1054 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1056 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1056 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1073 ( .LO ( optlc_net_1055 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1057 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1057 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1074 ( .LO ( optlc_net_1056 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1058 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1058 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1075 ( .LO ( optlc_net_1057 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1059 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1059 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1076 ( .LO ( optlc_net_1058 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1060 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1060 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1077 ( .LO ( optlc_net_1059 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1061 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1061 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1078 ( .LO ( optlc_net_1060 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1062 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1062 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1079 ( .LO ( optlc_net_1061 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1063 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1063 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1080 ( .LO ( optlc_net_1062 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1064 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1064 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1081 ( .LO ( optlc_net_1063 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1065 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1065 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1082 ( .LO ( optlc_net_1064 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1066 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1066 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1083 ( .LO ( optlc_net_1065 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1067 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1067 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1084 ( .LO ( optlc_net_1066 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1068 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1068 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1085 ( .LO ( optlc_net_1067 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1069 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1069 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1086 ( .LO ( optlc_net_1068 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1070 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1070 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1087 ( .LO ( optlc_net_1069 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1071 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1071 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1088 ( .LO ( optlc_net_1070 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1072 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1072 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1089 ( .LO ( optlc_net_1071 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1073 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1073 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1090 ( .LO ( optlc_net_1072 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1074 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1074 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1091 ( .LO ( optlc_net_1073 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1075 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1075 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1093 ( .LO ( optlc_net_1074 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1076 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1076 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1094 ( .LO ( optlc_net_1075 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1077 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1077 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1095 ( .LO ( optlc_net_1076 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1078 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1078 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1096 ( .LO ( optlc_net_1077 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1079 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1079 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1097 ( .LO ( optlc_net_1078 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1080 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1080 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1098 ( .LO ( optlc_net_1079 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1081 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1081 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1100 ( .LO ( optlc_net_1080 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1082 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1082 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1101 ( .LO ( optlc_net_1081 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1083 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1083 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1102 ( .LO ( optlc_net_1082 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1084 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1084 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1103 ( .LO ( optlc_net_1083 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1085 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1085 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1104 ( .LO ( optlc_net_1084 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1086 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1086 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1105 ( .LO ( optlc_net_1085 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1087 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1087 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1106 ( .LO ( optlc_net_1086 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1088 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1088 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1108 ( .LO ( optlc_net_1087 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1089 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1089 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1109 ( .LO ( optlc_net_1088 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1090 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1090 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1110 ( .LO ( optlc_net_1089 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1091 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1091 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1111 ( .LO ( optlc_net_1090 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1092 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1092 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1112 ( .LO ( optlc_net_1091 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1093 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1093 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1113 ( .LO ( optlc_net_1092 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1094 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1094 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1114 ( .LO ( optlc_net_1093 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1095 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1095 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1115 ( .LO ( optlc_net_1094 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1096 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1096 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1116 ( .LO ( optlc_net_1095 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1097 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1097 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1117 ( .LO ( optlc_net_1096 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1098 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1098 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1118 ( .LO ( optlc_net_1097 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1099 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1099 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1119 ( .LO ( optlc_net_1098 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1100 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1120 ( .LO ( optlc_net_1099 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1101 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1121 ( .LO ( optlc_net_1100 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1102 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1122 ( .LO ( optlc_net_1101 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1103 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1123 ( .LO ( optlc_net_1102 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1104 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1124 ( .LO ( optlc_net_1103 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1105 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1125 ( .LO ( optlc_net_1104 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1106 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1126 ( .LO ( optlc_net_1105 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1107 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1127 ( .LO ( optlc_net_1106 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1108 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1128 ( .LO ( optlc_net_1107 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1109 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1129 ( .LO ( optlc_net_1108 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1110 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1130 ( .LO ( optlc_net_1109 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1111 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1131 ( .LO ( optlc_net_1110 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1112 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1132 ( .LO ( optlc_net_1111 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1113 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1133 ( .LO ( optlc_net_1112 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1114 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1134 ( .LO ( optlc_net_1113 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1115 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1135 ( .LO ( optlc_net_1114 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1116 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1137 ( .LO ( optlc_net_1115 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1117 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1138 ( .LO ( optlc_net_1116 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1118 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1139 ( .LO ( optlc_net_1117 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1119 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1140 ( .LO ( optlc_net_1118 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1120 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1141 ( .LO ( optlc_net_1119 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1121 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1142 ( .LO ( optlc_net_1120 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1122 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1143 ( .LO ( optlc_net_1121 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1123 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1144 ( .LO ( optlc_net_1122 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1124 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1145 ( .LO ( optlc_net_1123 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1125 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1146 ( .LO ( optlc_net_1124 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1126 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1147 ( .LO ( optlc_net_1125 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1127 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1149 ( .LO ( optlc_net_1126 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1128 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1150 ( .LO ( optlc_net_1127 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1129 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1151 ( .LO ( optlc_net_1128 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1130 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1152 ( .LO ( optlc_net_1129 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1131 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1153 ( .LO ( optlc_net_1130 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1132 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1154 ( .LO ( optlc_net_1131 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1133 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1155 ( .LO ( optlc_net_1132 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1134 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1156 ( .LO ( optlc_net_1133 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1135 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1157 ( .LO ( optlc_net_1134 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1136 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1158 ( .LO ( optlc_net_1135 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1137 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1160 ( .LO ( optlc_net_1136 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1138 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1161 ( .LO ( optlc_net_1137 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1139 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1162 ( .LO ( optlc_net_1138 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1140 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1164 ( .LO ( optlc_net_1139 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1141 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1165 ( .LO ( optlc_net_1140 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1142 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1166 ( .LO ( optlc_net_1141 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1143 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1167 ( .LO ( optlc_net_1142 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1144 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1168 ( .LO ( optlc_net_1143 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1145 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1169 ( .LO ( optlc_net_1144 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1146 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1171 ( .LO ( optlc_net_1145 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1147 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1173 ( .LO ( optlc_net_1146 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1148 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1174 ( .LO ( optlc_net_1147 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1149 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1175 ( .LO ( optlc_net_1148 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1150 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1176 ( .LO ( optlc_net_1149 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1151 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1177 ( .LO ( optlc_net_1150 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1152 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1178 ( .LO ( optlc_net_1151 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1153 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1179 ( .LO ( optlc_net_1152 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1154 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1180 ( .LO ( optlc_net_1153 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1155 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1181 ( .LO ( optlc_net_1154 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1156 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1182 ( .LO ( optlc_net_1155 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1157 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1183 ( .LO ( optlc_net_1156 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1158 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1184 ( .LO ( optlc_net_1157 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1159 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1185 ( .LO ( optlc_net_1158 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1160 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1186 ( .LO ( optlc_net_1159 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1161 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1188 ( .LO ( optlc_net_1160 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1162 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1190 ( .LO ( optlc_net_1161 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1163 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1191 ( .LO ( optlc_net_1162 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1164 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1193 ( .LO ( optlc_net_1163 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1165 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1194 ( .LO ( optlc_net_1164 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1166 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1195 ( .LO ( optlc_net_1165 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1167 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1196 ( .LO ( optlc_net_1166 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1168 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1197 ( .LO ( optlc_net_1167 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1169 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1198 ( .LO ( optlc_net_1168 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1170 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1200 ( .LO ( optlc_net_1169 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1171 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1201 ( .LO ( optlc_net_1170 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1172 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1202 ( .LO ( optlc_net_1171 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1173 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1203 ( .LO ( optlc_net_1172 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1174 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1204 ( .LO ( optlc_net_1173 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1175 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1205 ( .LO ( optlc_net_1174 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1176 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1206 ( .LO ( optlc_net_1175 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1177 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1207 ( .LO ( optlc_net_1176 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1178 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1208 ( .LO ( optlc_net_1177 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1179 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1210 ( .LO ( optlc_net_1178 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1180 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1211 ( .LO ( optlc_net_1179 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1181 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1213 ( .LO ( optlc_net_1180 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1182 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1214 ( .LO ( optlc_net_1181 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1183 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1215 ( .LO ( optlc_net_1182 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1184 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1216 ( .LO ( optlc_net_1183 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1185 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1218 ( .LO ( optlc_net_1184 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1186 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1219 ( .LO ( optlc_net_1185 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1187 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1220 ( .LO ( optlc_net_1186 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1188 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1221 ( .LO ( optlc_net_1187 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1189 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1222 ( .LO ( optlc_net_1188 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1190 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1224 ( .LO ( optlc_net_1189 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1191 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1225 ( .LO ( optlc_net_1190 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1192 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1226 ( .LO ( optlc_net_1191 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1193 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1227 ( .LO ( optlc_net_1192 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1194 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1228 ( .LO ( optlc_net_1193 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1195 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1229 ( .LO ( optlc_net_1194 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1196 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1230 ( .LO ( optlc_net_1195 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1197 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1232 ( .LO ( optlc_net_1196 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1198 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1233 ( .LO ( optlc_net_1197 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1199 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1235 ( .LO ( optlc_net_1198 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1200 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1236 ( .LO ( optlc_net_1199 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1201 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1238 ( .LO ( optlc_net_1200 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1202 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1240 ( .LO ( optlc_net_1201 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1203 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1241 ( .LO ( optlc_net_1202 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1204 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1242 ( .LO ( optlc_net_1203 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1205 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1244 ( .LO ( optlc_net_1204 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1206 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1245 ( .LO ( optlc_net_1205 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1207 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1246 ( .LO ( optlc_net_1206 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1208 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1247 ( .LO ( optlc_net_1207 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1209 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1248 ( .LO ( optlc_net_1208 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1210 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1249 ( .LO ( optlc_net_1209 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1211 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1250 ( .LO ( optlc_net_1210 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1212 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1252 ( .LO ( optlc_net_1211 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1213 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1253 ( .LO ( optlc_net_1212 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1214 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1254 ( .LO ( optlc_net_1213 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1215 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1256 ( .LO ( optlc_net_1214 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1216 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1257 ( .LO ( optlc_net_1215 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1217 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1258 ( .LO ( optlc_net_1216 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1218 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1259 ( .LO ( optlc_net_1217 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1219 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1260 ( .LO ( optlc_net_1218 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1220 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1261 ( .LO ( optlc_net_1219 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1221 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1263 ( .LO ( optlc_net_1220 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1222 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1265 ( .LO ( optlc_net_1221 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1223 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1266 ( .LO ( optlc_net_1222 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1224 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1267 ( .LO ( optlc_net_1223 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1225 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1269 ( .LO ( optlc_net_1224 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1226 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1271 ( .LO ( optlc_net_1225 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1227 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1272 ( .LO ( optlc_net_1226 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1228 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1274 ( .LO ( optlc_net_1227 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1229 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1275 ( .LO ( optlc_net_1228 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1230 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1276 ( .LO ( optlc_net_1229 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1231 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1277 ( .LO ( optlc_net_1230 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1232 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1279 ( .LO ( optlc_net_1231 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1233 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1233 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1280 ( .LO ( optlc_net_1232 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1234 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1234 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1282 ( .LO ( optlc_net_1233 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1235 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1235 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1284 ( .LO ( optlc_net_1234 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1236 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1236 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1286 ( .LO ( optlc_net_1235 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1237 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1237 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1288 ( .LO ( optlc_net_1236 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1238 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1238 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1289 ( .LO ( optlc_net_1237 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1239 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1239 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1290 ( .LO ( optlc_net_1238 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1240 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1240 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1291 ( .LO ( optlc_net_1239 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1241 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1241 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1292 ( .LO ( optlc_net_1240 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1242 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1242 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1293 ( .LO ( optlc_net_1241 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1243 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1243 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1295 ( .LO ( optlc_net_1242 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1244 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1244 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1297 ( .LO ( optlc_net_1243 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1245 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1245 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1298 ( .LO ( optlc_net_1244 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1246 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1246 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1300 ( .LO ( optlc_net_1245 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1247 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1247 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1301 ( .LO ( optlc_net_1246 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1248 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1248 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1302 ( .LO ( optlc_net_1247 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1249 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1249 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1304 ( .LO ( optlc_net_1248 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1250 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1250 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1305 ( .LO ( optlc_net_1249 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1251 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1251 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1307 ( .LO ( optlc_net_1250 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1252 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1252 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1308 ( .LO ( optlc_net_1251 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1253 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1253 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1309 ( .LO ( optlc_net_1252 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1254 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1254 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1310 ( .LO ( optlc_net_1253 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1255 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1255 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1311 ( .LO ( optlc_net_1254 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1256 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1256 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1313 ( .LO ( optlc_net_1255 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1257 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1257 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1315 ( .LO ( optlc_net_1256 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1258 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1258 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1316 ( .LO ( optlc_net_1257 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1259 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1259 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1317 ( .LO ( optlc_net_1258 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1260 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1260 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1319 ( .LO ( optlc_net_1259 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1261 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1261 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1321 ( .LO ( optlc_net_1260 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1262 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1262 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1323 ( .LO ( optlc_net_1261 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1263 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1263 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1324 ( .LO ( optlc_net_1262 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1264 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1264 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1326 ( .LO ( optlc_net_1263 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1265 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1265 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1327 ( .LO ( optlc_net_1264 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1266 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1266 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1329 ( .LO ( optlc_net_1265 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1267 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1267 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1330 ( .LO ( optlc_net_1266 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1268 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1268 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1331 ( .LO ( optlc_net_1267 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1269 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1269 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1333 ( .LO ( optlc_net_1268 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1270 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1270 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1335 ( .LO ( optlc_net_1269 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1271 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1271 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1337 ( .LO ( optlc_net_1270 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1272 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1272 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1338 ( .LO ( optlc_net_1271 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1273 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1273 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1339 ( .LO ( optlc_net_1272 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1274 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1274 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1341 ( .LO ( optlc_net_1273 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1275 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1275 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1342 ( .LO ( optlc_net_1274 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1276 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1276 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1343 ( .LO ( optlc_net_1275 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1277 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1277 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1344 ( .LO ( optlc_net_1276 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1278 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1278 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1345 ( .LO ( optlc_net_1277 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1279 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1279 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1346 ( .LO ( optlc_net_1278 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1280 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1280 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1347 ( .LO ( optlc_net_1279 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1281 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1281 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1348 ( .LO ( optlc_net_1280 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1282 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1282 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1349 ( .LO ( optlc_net_1281 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1283 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1283 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1350 ( .LO ( optlc_net_1282 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1284 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1284 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1351 ( .LO ( optlc_net_1283 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1285 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1285 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1352 ( .LO ( optlc_net_1284 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1286 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1286 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1353 ( .LO ( optlc_net_1285 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1287 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1287 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1354 ( .LO ( optlc_net_1286 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1288 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1288 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1355 ( .LO ( optlc_net_1287 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1289 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1289 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1356 ( .LO ( optlc_net_1288 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1290 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1290 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1357 ( .LO ( optlc_net_1289 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1291 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1291 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1358 ( .LO ( optlc_net_1290 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1292 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1292 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1359 ( .LO ( optlc_net_1291 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1293 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1293 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1360 ( .LO ( optlc_net_1292 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1294 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1294 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1361 ( .LO ( optlc_net_1293 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1295 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1295 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1362 ( .LO ( optlc_net_1294 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1296 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1296 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1363 ( .LO ( optlc_net_1295 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1297 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1297 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1364 ( .LO ( optlc_net_1296 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1298 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1298 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1365 ( .LO ( optlc_net_1297 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1299 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1299 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1366 ( .LO ( optlc_net_1298 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1300 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1300 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1367 ( .LO ( optlc_net_1299 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1301 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1301 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1368 ( .LO ( optlc_net_1300 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1302 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1302 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1369 ( .LO ( optlc_net_1301 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1303 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1303 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1370 ( .LO ( optlc_net_1302 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1304 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1304 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1371 ( .LO ( optlc_net_1303 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1305 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1305 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1372 ( .LO ( optlc_net_1304 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1306 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1306 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1373 ( .LO ( optlc_net_1305 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1307 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1307 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1374 ( .LO ( optlc_net_1306 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1308 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1308 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1375 ( .LO ( optlc_net_1307 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1309 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1309 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1376 ( .LO ( optlc_net_1308 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1310 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1310 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1377 ( .LO ( optlc_net_1309 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1311 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1311 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1378 ( .LO ( optlc_net_1310 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1312 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1312 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1379 ( .LO ( optlc_net_1311 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1313 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1313 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1380 ( .LO ( optlc_net_1312 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1314 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1314 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1381 ( .LO ( optlc_net_1313 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1315 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1315 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1382 ( .LO ( optlc_net_1314 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1316 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1316 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1383 ( .LO ( optlc_net_1315 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1317 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1317 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1384 ( .LO ( optlc_net_1316 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1318 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1318 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1385 ( .LO ( optlc_net_1317 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1319 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1319 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1386 ( .LO ( optlc_net_1318 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1320 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1320 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1387 ( .LO ( optlc_net_1319 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1321 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1321 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1388 ( .LO ( optlc_net_1320 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1322 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1322 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1389 ( .LO ( optlc_net_1321 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1323 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1323 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1390 ( .LO ( optlc_net_1322 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1324 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1324 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1391 ( .LO ( optlc_net_1323 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1325 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1325 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1392 ( .LO ( optlc_net_1324 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1326 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1326 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1393 ( .LO ( optlc_net_1325 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1327 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1327 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1394 ( .LO ( optlc_net_1326 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1328 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1328 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1395 ( .LO ( optlc_net_1327 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1329 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1329 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1396 ( .LO ( optlc_net_1328 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1330 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1330 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1397 ( .LO ( optlc_net_1329 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1331 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1331 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1398 ( .LO ( optlc_net_1330 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1332 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1332 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1399 ( .LO ( optlc_net_1331 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1333 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1333 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1400 ( .LO ( optlc_net_1332 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1334 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1334 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1401 ( .LO ( optlc_net_1333 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1335 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1335 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1402 ( .LO ( optlc_net_1334 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1336 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1336 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1403 ( .LO ( optlc_net_1335 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1337 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1337 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1404 ( .LO ( optlc_net_1336 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1338 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1338 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1405 ( .LO ( optlc_net_1337 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1339 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1339 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1406 ( .LO ( optlc_net_1338 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1340 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1340 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1407 ( .LO ( optlc_net_1339 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1341 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1341 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1408 ( .LO ( optlc_net_1340 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1342 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1342 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1409 ( .LO ( optlc_net_1341 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1343 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1343 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1410 ( .LO ( optlc_net_1342 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1344 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1344 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1411 ( .LO ( optlc_net_1343 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1345 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1345 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1412 ( .LO ( optlc_net_1344 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1346 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1346 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1413 ( .LO ( optlc_net_1345 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1347 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1347 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1414 ( .LO ( optlc_net_1346 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1348 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1348 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1415 ( .LO ( optlc_net_1347 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1349 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1349 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1416 ( .LO ( optlc_net_1348 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1350 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1350 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1417 ( .LO ( optlc_net_1349 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1351 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1351 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1418 ( .LO ( optlc_net_1350 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1352 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1352 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1419 ( .LO ( optlc_net_1351 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1353 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1353 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1420 ( .LO ( optlc_net_1352 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1354 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1354 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1421 ( .LO ( optlc_net_1353 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1355 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1355 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1422 ( .LO ( optlc_net_1354 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1356 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1356 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1423 ( .LO ( optlc_net_1355 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1357 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1357 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1424 ( .LO ( optlc_net_1356 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1358 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1358 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1426 ( .LO ( optlc_net_1357 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1359 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1359 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1427 ( .LO ( optlc_net_1358 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1360 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1360 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1428 ( .LO ( optlc_net_1359 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1361 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1361 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1429 ( .LO ( optlc_net_1360 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1362 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1362 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1430 ( .LO ( optlc_net_1361 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1363 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1363 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1431 ( .LO ( optlc_net_1362 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1364 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1364 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1432 ( .LO ( optlc_net_1363 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1365 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1365 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1433 ( .LO ( optlc_net_1364 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1366 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1366 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1434 ( .LO ( optlc_net_1365 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1367 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1367 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1435 ( .LO ( optlc_net_1366 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1368 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1368 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1436 ( .LO ( optlc_net_1367 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1369 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1369 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1437 ( .LO ( optlc_net_1368 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1370 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1370 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1438 ( .LO ( optlc_net_1369 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1371 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1371 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1439 ( .LO ( optlc_net_1370 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1372 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1372 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1440 ( .LO ( optlc_net_1371 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1373 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1373 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1441 ( .LO ( optlc_net_1372 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1374 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1374 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1442 ( .LO ( optlc_net_1373 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1375 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1375 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1443 ( .LO ( optlc_net_1374 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1376 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1376 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1444 ( .LO ( optlc_net_1375 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1377 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1377 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1445 ( .LO ( optlc_net_1376 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1378 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1378 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1446 ( .LO ( optlc_net_1377 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1379 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1379 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1447 ( .LO ( optlc_net_1378 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1380 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1380 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1448 ( .LO ( optlc_net_1379 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1381 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1381 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1449 ( .LO ( optlc_net_1380 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1382 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1382 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1450 ( .LO ( optlc_net_1381 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1383 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1383 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1451 ( .LO ( optlc_net_1382 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1384 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1384 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1452 ( .LO ( optlc_net_1383 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1385 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1385 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1453 ( .LO ( optlc_net_1384 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1386 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1386 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1454 ( .LO ( optlc_net_1385 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1387 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1387 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1455 ( .LO ( optlc_net_1386 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1388 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1388 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1456 ( .LO ( optlc_net_1387 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1389 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1389 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1457 ( .LO ( optlc_net_1388 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1390 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1390 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1458 ( .LO ( optlc_net_1389 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1391 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1391 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1459 ( .LO ( optlc_net_1390 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1392 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1392 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1461 ( .LO ( optlc_net_1391 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1393 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1393 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1462 ( .LO ( optlc_net_1392 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1394 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1394 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1464 ( .LO ( optlc_net_1393 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1395 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1395 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1465 ( .LO ( optlc_net_1394 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1396 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1396 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1466 ( .LO ( optlc_net_1395 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1397 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1397 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1467 ( .LO ( optlc_net_1396 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1398 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1398 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1469 ( .LO ( optlc_net_1397 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1399 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1399 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1470 ( .LO ( optlc_net_1398 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1400 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1400 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1471 ( .LO ( optlc_net_1399 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1401 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1401 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1472 ( .LO ( optlc_net_1400 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1402 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1402 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1473 ( .LO ( optlc_net_1401 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1403 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1403 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1474 ( .LO ( optlc_net_1402 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1404 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1404 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1475 ( .LO ( optlc_net_1403 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1405 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1405 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1477 ( .LO ( optlc_net_1404 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1406 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1406 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1478 ( .LO ( optlc_net_1405 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1407 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1407 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1479 ( .LO ( optlc_net_1406 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1408 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1408 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1480 ( .LO ( optlc_net_1407 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1409 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1409 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1481 ( .LO ( optlc_net_1408 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1410 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1410 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1482 ( .LO ( optlc_net_1409 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1411 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1411 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1483 ( .LO ( optlc_net_1410 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1412 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1412 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1484 ( .LO ( optlc_net_1411 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1413 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1413 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1485 ( .LO ( optlc_net_1412 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1414 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1414 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1487 ( .LO ( optlc_net_1413 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1415 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1415 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1488 ( .LO ( optlc_net_1414 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1416 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1416 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1489 ( .LO ( optlc_net_1415 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1417 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1417 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1490 ( .LO ( optlc_net_1416 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1418 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1418 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1491 ( .LO ( optlc_net_1417 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1419 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1419 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1492 ( .LO ( optlc_net_1418 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1420 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1420 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1494 ( .LO ( optlc_net_1419 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1421 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1421 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1495 ( .LO ( optlc_net_1420 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1422 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1422 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1496 ( .LO ( optlc_net_1421 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1423 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1423 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1497 ( .LO ( optlc_net_1422 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1424 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1424 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1498 ( .LO ( optlc_net_1423 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1425 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1425 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1500 ( .LO ( optlc_net_1424 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1426 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1426 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1501 ( .LO ( optlc_net_1425 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1427 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1427 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1503 ( .LO ( optlc_net_1426 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1428 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1428 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1504 ( .LO ( optlc_net_1427 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1429 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1429 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1505 ( .LO ( optlc_net_1428 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1430 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1430 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1507 ( .LO ( optlc_net_1429 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1431 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1431 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1508 ( .LO ( optlc_net_1430 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1432 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1432 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1509 ( .LO ( optlc_net_1431 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1433 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1433 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1510 ( .LO ( optlc_net_1432 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1434 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1434 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1511 ( .LO ( optlc_net_1433 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1435 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1435 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1513 ( .LO ( optlc_net_1434 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1436 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1436 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1514 ( .LO ( optlc_net_1435 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1437 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1437 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1515 ( .LO ( optlc_net_1436 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1438 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1438 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1517 ( .LO ( optlc_net_1437 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1439 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1439 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1518 ( .LO ( optlc_net_1438 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1440 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1440 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1519 ( .LO ( optlc_net_1439 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1441 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1441 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1521 ( .LO ( optlc_net_1440 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1442 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1442 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1522 ( .LO ( optlc_net_1441 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1443 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1443 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1523 ( .LO ( optlc_net_1442 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1444 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1444 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1524 ( .LO ( optlc_net_1443 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1445 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1445 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1525 ( .LO ( optlc_net_1444 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1446 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1446 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1526 ( .LO ( optlc_net_1445 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1447 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1447 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1527 ( .LO ( optlc_net_1446 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1448 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1448 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1528 ( .LO ( optlc_net_1447 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1449 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1449 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1529 ( .LO ( optlc_net_1448 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1450 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1450 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1531 ( .LO ( optlc_net_1449 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1451 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1451 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1532 ( .LO ( optlc_net_1450 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1452 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1452 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1533 ( .LO ( optlc_net_1451 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1453 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1453 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1534 ( .LO ( optlc_net_1452 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1454 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1454 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1536 ( .LO ( optlc_net_1453 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1455 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1455 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1537 ( .LO ( optlc_net_1454 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1456 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1456 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1538 ( .LO ( optlc_net_1455 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1457 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1457 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1539 ( .LO ( optlc_net_1456 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1458 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1458 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1540 ( .LO ( optlc_net_1457 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1459 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1459 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1541 ( .LO ( optlc_net_1458 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1460 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1460 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1543 ( .LO ( optlc_net_1459 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1461 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1461 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1545 ( .LO ( optlc_net_1460 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1462 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1462 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1547 ( .LO ( optlc_net_1461 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1463 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1463 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1549 ( .LO ( optlc_net_1462 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1464 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1464 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1550 ( .LO ( optlc_net_1463 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1465 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1465 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1551 ( .LO ( optlc_net_1464 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1466 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1466 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1553 ( .LO ( optlc_net_1465 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1467 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1467 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1555 ( .LO ( optlc_net_1466 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1468 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1468 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1556 ( .LO ( optlc_net_1467 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1469 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1469 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1558 ( .LO ( optlc_net_1468 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1470 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1470 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1560 ( .LO ( optlc_net_1469 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1471 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1471 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1562 ( .LO ( optlc_net_1470 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1472 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1472 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1563 ( .LO ( optlc_net_1471 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1473 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1473 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1564 ( .LO ( optlc_net_1472 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1474 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1474 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1565 ( .LO ( optlc_net_1473 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1475 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1475 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1567 ( .LO ( optlc_net_1474 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1476 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1476 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1568 ( .LO ( optlc_net_1475 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1477 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1477 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1569 ( .LO ( optlc_net_1476 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1478 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1478 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1570 ( .LO ( optlc_net_1477 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1479 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1479 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1571 ( .LO ( optlc_net_1478 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1480 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1480 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1572 ( .LO ( optlc_net_1479 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1481 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1481 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1574 ( .LO ( optlc_net_1480 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1482 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1482 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1575 ( .LO ( optlc_net_1481 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1483 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1483 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1576 ( .LO ( optlc_net_1482 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1484 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1484 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1577 ( .LO ( optlc_net_1483 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1485 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1485 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1579 ( .LO ( optlc_net_1484 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1486 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1486 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1580 ( .LO ( optlc_net_1485 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1487 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1487 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1581 ( .LO ( optlc_net_1486 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1488 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1488 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1582 ( .LO ( optlc_net_1487 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1489 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1489 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1584 ( .LO ( optlc_net_1488 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1490 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1490 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1585 ( .LO ( optlc_net_1489 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1491 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1491 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1587 ( .LO ( optlc_net_1490 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1492 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1492 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1588 ( .LO ( optlc_net_1491 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1493 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1493 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1590 ( .LO ( optlc_net_1492 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1494 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1494 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1592 ( .LO ( optlc_net_1493 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1495 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1495 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1594 ( .LO ( optlc_net_1494 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1496 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1496 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1595 ( .LO ( optlc_net_1495 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1497 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1497 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1597 ( .LO ( optlc_net_1496 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1498 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1498 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1599 ( .LO ( optlc_net_1497 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1499 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1499 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1600 ( .LO ( optlc_net_1498 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1500 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1500 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1601 ( .LO ( optlc_net_1499 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1501 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1501 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1602 ( .LO ( optlc_net_1500 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1502 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1502 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1604 ( .LO ( optlc_net_1501 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1503 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1503 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1605 ( .LO ( optlc_net_1502 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1504 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1504 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1607 ( .LO ( optlc_net_1503 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1505 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1505 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1608 ( .LO ( optlc_net_1504 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1506 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1506 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1610 ( .LO ( optlc_net_1505 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1507 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1507 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1611 ( .LO ( optlc_net_1506 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1508 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1508 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1613 ( .LO ( optlc_net_1507 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1509 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1509 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1614 ( .LO ( optlc_net_1508 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1510 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1510 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1615 ( .LO ( optlc_net_1509 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1511 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1511 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1616 ( .LO ( optlc_net_1510 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1512 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1512 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1619 ( .LO ( optlc_net_1511 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1513 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1513 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1621 ( .LO ( optlc_net_1512 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1514 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1514 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1622 ( .LO ( optlc_net_1513 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1515 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1515 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1623 ( .LO ( optlc_net_1514 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1516 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1516 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1624 ( .LO ( optlc_net_1515 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1517 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1517 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1626 ( .LO ( optlc_net_1516 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1518 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1518 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1627 ( .LO ( optlc_net_1517 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1519 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1519 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1629 ( .LO ( optlc_net_1518 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1520 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1520 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1630 ( .LO ( optlc_net_1519 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1521 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1521 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1631 ( .LO ( optlc_net_1520 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1522 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1522 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1632 ( .LO ( optlc_net_1521 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1523 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1523 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1633 ( .LO ( optlc_net_1522 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1524 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1524 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1634 ( .LO ( optlc_net_1523 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1525 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1525 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1636 ( .LO ( optlc_net_1524 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1526 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1526 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1637 ( .LO ( optlc_net_1525 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1527 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1527 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1639 ( .LO ( optlc_net_1526 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1528 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1528 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1641 ( .LO ( optlc_net_1527 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1529 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1529 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1642 ( .LO ( optlc_net_1528 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1530 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1530 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1644 ( .LO ( optlc_net_1529 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1531 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1531 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1646 ( .LO ( optlc_net_1530 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1532 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1532 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1647 ( .LO ( optlc_net_1531 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1533 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1533 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1648 ( .LO ( optlc_net_1532 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1534 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1534 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1650 ( .LO ( optlc_net_1533 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1535 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1535 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1651 ( .LO ( optlc_net_1534 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1536 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1536 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1652 ( .LO ( optlc_net_1535 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1537 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1537 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1653 ( .LO ( optlc_net_1536 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1538 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1538 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1654 ( .LO ( optlc_net_1537 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1539 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1539 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1655 ( .LO ( optlc_net_1538 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1540 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1540 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1657 ( .LO ( optlc_net_1539 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1541 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1541 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1659 ( .LO ( optlc_net_1540 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1542 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1542 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1660 ( .LO ( optlc_net_1541 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1543 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1543 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1662 ( .LO ( optlc_net_1542 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1544 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1544 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1663 ( .LO ( optlc_net_1543 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1545 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1545 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1665 ( .LO ( optlc_net_1544 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1546 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1546 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1666 ( .LO ( optlc_net_1545 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1547 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1547 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1668 ( .LO ( optlc_net_1546 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1548 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1548 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1670 ( .LO ( optlc_net_1547 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1549 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1549 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1672 ( .LO ( optlc_net_1548 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1550 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1550 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1673 ( .LO ( optlc_net_1549 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1551 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1551 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1675 ( .LO ( optlc_net_1550 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1552 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1552 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1677 ( .LO ( optlc_net_1551 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1553 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1553 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1679 ( .LO ( optlc_net_1552 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1554 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1554 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1681 ( .LO ( optlc_net_1553 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1555 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1555 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1682 ( .LO ( optlc_net_1554 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1556 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1556 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1683 ( .LO ( optlc_net_1555 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1557 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1557 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1685 ( .LO ( optlc_net_1556 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1558 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1558 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1686 ( .LO ( optlc_net_1557 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1559 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1559 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1687 ( .LO ( optlc_net_1558 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1560 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1560 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1689 ( .LO ( optlc_net_1559 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1561 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1561 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1690 ( .LO ( optlc_net_1560 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1562 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1562 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1691 ( .LO ( optlc_net_1561 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1563 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1563 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1692 ( .LO ( optlc_net_1562 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1564 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1564 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1693 ( .LO ( optlc_net_1563 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1565 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1565 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1695 ( .LO ( optlc_net_1564 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1566 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1566 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1697 ( .LO ( optlc_net_1565 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1567 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1567 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1699 ( .LO ( optlc_net_1566 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1568 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1568 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1701 ( .LO ( optlc_net_1567 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1569 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1569 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1703 ( .LO ( optlc_net_1568 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1570 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1570 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1704 ( .LO ( optlc_net_1569 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1571 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1571 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1705 ( .LO ( optlc_net_1570 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1572 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1572 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1706 ( .LO ( optlc_net_1571 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1573 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1573 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1707 ( .LO ( optlc_net_1572 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1574 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1574 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1709 ( .LO ( optlc_net_1573 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1575 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1575 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1711 ( .LO ( optlc_net_1574 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1576 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1576 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1712 ( .LO ( optlc_net_1575 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1577 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1577 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1714 ( .LO ( optlc_net_1576 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1578 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1578 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1715 ( .LO ( optlc_net_1577 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1579 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1579 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1716 ( .LO ( optlc_net_1578 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1580 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1580 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1717 ( .LO ( optlc_net_1579 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1581 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1581 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1719 ( .LO ( optlc_net_1580 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1582 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1582 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1720 ( .LO ( optlc_net_1581 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1583 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1583 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1721 ( .LO ( optlc_net_1582 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1584 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1584 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1723 ( .LO ( optlc_net_1583 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1585 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1585 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1724 ( .LO ( optlc_net_1584 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1586 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1586 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1725 ( .LO ( optlc_net_1585 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1587 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1587 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1726 ( .LO ( optlc_net_1586 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1588 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1588 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1728 ( .LO ( optlc_net_1587 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1589 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1589 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1730 ( .LO ( optlc_net_1588 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1590 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1590 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1732 ( .LO ( optlc_net_1589 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1591 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1591 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1733 ( .LO ( optlc_net_1590 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1592 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1592 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1735 ( .LO ( optlc_net_1591 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1593 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1593 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1737 ( .LO ( optlc_net_1592 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1594 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1594 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1738 ( .LO ( optlc_net_1593 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1595 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1595 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1739 ( .LO ( optlc_net_1594 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1596 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1596 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1741 ( .LO ( optlc_net_1595 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1597 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1597 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1742 ( .LO ( optlc_net_1596 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1598 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1598 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1744 ( .LO ( optlc_net_1597 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1599 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1599 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1746 ( .LO ( optlc_net_1598 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1600 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1600 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1748 ( .LO ( optlc_net_1599 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1601 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1601 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1750 ( .LO ( optlc_net_1600 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1602 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1602 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1751 ( .LO ( optlc_net_1601 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1603 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1603 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1753 ( .LO ( optlc_net_1602 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1604 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1604 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1754 ( .LO ( optlc_net_1603 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1605 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1605 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1755 ( .LO ( optlc_net_1604 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1606 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1606 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1756 ( .LO ( optlc_net_1605 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1607 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1607 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1757 ( .LO ( optlc_net_1606 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1608 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1608 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1758 ( .LO ( optlc_net_1607 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1609 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1609 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1760 ( .LO ( optlc_net_1608 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1610 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1610 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1761 ( .LO ( optlc_net_1609 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1611 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1611 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1762 ( .LO ( optlc_net_1610 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1612 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1612 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1764 ( .LO ( optlc_net_1611 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1613 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1613 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1766 ( .LO ( optlc_net_1612 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1614 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1614 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1767 ( .LO ( optlc_net_1613 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1615 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1615 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1769 ( .LO ( optlc_net_1614 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1616 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1616 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1771 ( .LO ( optlc_net_1615 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1617 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1617 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1772 ( .LO ( optlc_net_1616 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1618 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1618 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1774 ( .LO ( optlc_net_1617 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1619 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1619 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1775 ( .LO ( optlc_net_1618 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1620 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1620 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1777 ( .LO ( optlc_net_1619 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1621 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1621 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1779 ( .LO ( optlc_net_1620 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1622 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1622 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1781 ( .LO ( optlc_net_1621 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1623 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1623 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1783 ( .LO ( optlc_net_1622 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1624 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1624 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1784 ( .LO ( optlc_net_1623 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1625 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1625 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1785 ( .LO ( optlc_net_1624 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1626 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1626 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1786 ( .LO ( optlc_net_1625 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1627 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1627 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1787 ( .LO ( optlc_net_1626 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1628 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1628 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1788 ( .LO ( optlc_net_1627 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1629 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1629 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1789 ( .LO ( optlc_net_1628 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1630 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1630 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1790 ( .LO ( optlc_net_1629 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1631 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1631 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1792 ( .LO ( optlc_net_1630 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1632 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1632 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1794 ( .LO ( optlc_net_1631 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1633 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1633 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1796 ( .LO ( optlc_net_1632 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1634 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1634 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1797 ( .LO ( optlc_net_1633 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1635 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1635 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1798 ( .LO ( optlc_net_1634 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1636 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1636 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1799 ( .LO ( optlc_net_1635 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1637 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1637 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1800 ( .LO ( optlc_net_1636 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1638 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1638 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1801 ( .LO ( optlc_net_1637 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1639 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1639 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1802 ( .LO ( optlc_net_1638 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1640 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1640 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1803 ( .LO ( optlc_net_1639 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1641 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1641 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1804 ( .LO ( optlc_net_1640 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1642 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1642 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1805 ( .LO ( optlc_net_1641 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1643 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1643 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1806 ( .LO ( optlc_net_1642 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1644 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1644 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1807 ( .LO ( optlc_net_1643 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1645 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1645 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1808 ( .LO ( optlc_net_1644 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1646 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1646 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1809 ( .LO ( optlc_net_1645 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1647 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1647 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1810 ( .LO ( optlc_net_1646 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1648 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1648 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1811 ( .LO ( optlc_net_1647 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1649 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1649 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1812 ( .LO ( optlc_net_1648 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1650 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1650 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1813 ( .LO ( optlc_net_1649 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1651 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1651 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1814 ( .LO ( optlc_net_1650 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1652 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1652 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1815 ( .LO ( optlc_net_1651 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1653 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1653 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1816 ( .LO ( optlc_net_1652 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1654 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1654 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1817 ( .LO ( optlc_net_1653 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1655 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1655 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1818 ( .LO ( optlc_net_1654 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1656 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1656 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1819 ( .LO ( optlc_net_1655 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1657 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1657 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1820 ( .LO ( optlc_net_1656 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1658 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1658 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1821 ( .LO ( optlc_net_1657 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1659 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1659 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1822 ( .LO ( optlc_net_1658 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1660 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1660 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1823 ( .LO ( optlc_net_1659 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1661 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1661 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1824 ( .LO ( optlc_net_1660 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1662 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1662 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1825 ( .LO ( optlc_net_1661 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1663 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1663 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1826 ( .LO ( optlc_net_1662 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1664 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1664 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1827 ( .LO ( optlc_net_1663 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1665 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1665 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1828 ( .LO ( optlc_net_1664 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1666 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1666 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1829 ( .LO ( optlc_net_1665 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1667 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1667 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1830 ( .LO ( optlc_net_1666 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1668 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1668 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1831 ( .LO ( optlc_net_1667 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1669 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1669 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1832 ( .LO ( optlc_net_1668 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1670 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1670 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1833 ( .LO ( optlc_net_1669 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1671 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1671 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1834 ( .LO ( optlc_net_1670 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1672 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1672 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1835 ( .LO ( optlc_net_1671 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1673 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1673 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1836 ( .LO ( optlc_net_1672 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1674 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1674 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1837 ( .LO ( optlc_net_1673 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1675 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1675 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1838 ( .LO ( optlc_net_1674 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1676 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1676 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1839 ( .LO ( optlc_net_1675 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1677 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1677 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1840 ( .LO ( optlc_net_1676 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1678 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1678 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1841 ( .LO ( optlc_net_1677 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1679 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1679 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1842 ( .LO ( optlc_net_1678 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1680 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1680 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1843 ( .LO ( optlc_net_1679 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1681 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1681 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1844 ( .LO ( optlc_net_1680 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1682 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1682 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1846 ( .LO ( optlc_net_1681 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1683 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1683 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1847 ( .LO ( optlc_net_1682 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1684 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1684 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1848 ( .LO ( optlc_net_1683 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1685 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1685 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1849 ( .LO ( optlc_net_1684 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1686 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1686 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1850 ( .LO ( optlc_net_1685 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1687 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1687 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1851 ( .LO ( optlc_net_1686 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1688 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1688 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1852 ( .LO ( optlc_net_1687 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1689 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1689 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1853 ( .LO ( optlc_net_1688 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1690 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1690 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1854 ( .LO ( optlc_net_1689 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1691 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1691 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1855 ( .LO ( optlc_net_1690 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1692 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1692 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1856 ( .LO ( optlc_net_1691 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1693 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1693 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1857 ( .LO ( optlc_net_1692 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1694 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1694 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1858 ( .LO ( optlc_net_1693 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1695 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1695 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1859 ( .LO ( optlc_net_1694 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1696 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1696 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1860 ( .LO ( optlc_net_1695 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1697 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1697 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1861 ( .LO ( optlc_net_1696 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1698 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1698 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1862 ( .LO ( optlc_net_1697 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1699 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1699 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1863 ( .LO ( optlc_net_1698 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1700 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1700 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1864 ( .LO ( optlc_net_1699 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1701 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1701 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1865 ( .LO ( optlc_net_1700 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1702 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1702 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1866 ( .LO ( optlc_net_1701 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1703 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1703 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1867 ( .LO ( optlc_net_1702 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1704 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1704 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1868 ( .LO ( optlc_net_1703 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1705 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1705 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1869 ( .LO ( optlc_net_1704 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1706 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1706 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1870 ( .LO ( optlc_net_1705 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1707 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1707 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1871 ( .LO ( optlc_net_1706 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1708 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1708 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1872 ( .LO ( optlc_net_1707 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1709 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1709 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1873 ( .LO ( optlc_net_1708 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1710 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1710 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1874 ( .LO ( optlc_net_1709 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1711 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1711 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1875 ( .LO ( optlc_net_1710 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1712 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1712 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1876 ( .LO ( optlc_net_1711 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1713 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1713 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1877 ( .LO ( optlc_net_1712 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1714 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1714 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1878 ( .LO ( optlc_net_1713 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1715 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1715 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1879 ( .LO ( optlc_net_1714 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1716 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1716 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1880 ( .LO ( optlc_net_1715 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1717 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1717 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1881 ( .LO ( optlc_net_1716 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1718 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1718 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1882 ( .LO ( optlc_net_1717 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1719 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1719 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1883 ( .LO ( optlc_net_1718 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1720 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1720 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1884 ( .LO ( optlc_net_1719 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1721 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1721 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1885 ( .LO ( optlc_net_1720 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1722 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1722 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1886 ( .LO ( optlc_net_1721 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1723 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1723 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1887 ( .LO ( optlc_net_1722 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1724 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1724 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1888 ( .LO ( optlc_net_1723 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1725 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1725 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1889 ( .LO ( optlc_net_1724 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1726 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1726 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1890 ( .LO ( optlc_net_1725 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1727 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1727 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1891 ( .LO ( optlc_net_1726 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1728 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1728 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1892 ( .LO ( optlc_net_1727 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1729 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1729 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1893 ( .LO ( optlc_net_1728 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1730 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1730 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1894 ( .LO ( optlc_net_1729 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1731 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1731 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1895 ( .LO ( optlc_net_1730 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1732 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1732 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1896 ( .LO ( optlc_net_1731 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1733 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1733 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1897 ( .LO ( optlc_net_1732 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1734 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1734 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1898 ( .LO ( optlc_net_1733 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1735 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1735 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1899 ( .LO ( optlc_net_1734 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1736 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1736 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1900 ( .LO ( optlc_net_1735 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1737 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1737 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1901 ( .LO ( optlc_net_1736 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1738 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1738 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1902 ( .LO ( optlc_net_1737 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1739 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1739 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1903 ( .LO ( optlc_net_1738 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1740 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1740 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1904 ( .LO ( optlc_net_1739 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1741 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1741 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1905 ( .LO ( optlc_net_1740 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1742 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1742 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1906 ( .LO ( optlc_net_1741 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1743 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1743 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1907 ( .LO ( optlc_net_1742 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1744 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1744 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1908 ( .LO ( optlc_net_1743 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1745 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1745 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1910 ( .LO ( optlc_net_1744 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1746 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1746 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1911 ( .LO ( optlc_net_1745 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1747 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1747 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1912 ( .LO ( optlc_net_1746 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1748 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1748 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1913 ( .LO ( optlc_net_1747 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1749 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1749 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1915 ( .LO ( optlc_net_1748 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1750 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1750 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1916 ( .LO ( optlc_net_1749 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1751 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1751 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1917 ( .LO ( optlc_net_1750 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1752 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1752 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1919 ( .LO ( optlc_net_1751 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1753 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1753 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1920 ( .LO ( optlc_net_1752 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1754 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1754 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1922 ( .LO ( optlc_net_1753 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1755 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1755 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1923 ( .LO ( optlc_net_1754 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1756 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1756 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1924 ( .LO ( optlc_net_1755 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1757 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1757 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1925 ( .LO ( optlc_net_1756 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1758 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1758 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1926 ( .LO ( optlc_net_1757 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1759 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1759 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1927 ( .LO ( optlc_net_1758 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1760 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1760 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1928 ( .LO ( optlc_net_1759 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1761 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1761 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1929 ( .LO ( optlc_net_1760 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1762 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1762 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1930 ( .LO ( optlc_net_1761 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1763 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1763 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1931 ( .LO ( optlc_net_1762 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1764 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1764 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1932 ( .LO ( optlc_net_1763 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1765 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1765 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1933 ( .LO ( optlc_net_1764 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1766 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1766 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1934 ( .LO ( optlc_net_1765 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1767 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1767 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1935 ( .LO ( optlc_net_1766 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1768 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1768 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1936 ( .LO ( optlc_net_1767 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1769 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1769 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1937 ( .LO ( optlc_net_1768 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1770 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1770 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1939 ( .LO ( optlc_net_1769 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1771 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1771 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1940 ( .LO ( optlc_net_1770 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1772 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1772 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1941 ( .LO ( optlc_net_1771 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1773 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1773 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1942 ( .LO ( optlc_net_1772 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1774 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1774 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1943 ( .LO ( optlc_net_1773 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1775 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1775 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1945 ( .LO ( optlc_net_1774 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1776 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1776 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1947 ( .LO ( optlc_net_1775 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1777 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1777 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1948 ( .LO ( optlc_net_1776 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1778 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1778 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1949 ( .LO ( optlc_net_1777 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1779 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1779 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1951 ( .LO ( optlc_net_1778 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1780 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1780 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1953 ( .LO ( optlc_net_1779 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1781 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1781 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1954 ( .LO ( optlc_net_1780 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1782 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1782 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1956 ( .LO ( optlc_net_1781 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1783 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1783 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1957 ( .LO ( optlc_net_1782 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1784 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1784 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1958 ( .LO ( optlc_net_1783 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1785 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1785 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1959 ( .LO ( optlc_net_1784 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1786 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1786 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1960 ( .LO ( optlc_net_1785 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1787 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1787 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1962 ( .LO ( optlc_net_1786 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1788 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1788 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1963 ( .LO ( optlc_net_1787 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1789 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1789 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1964 ( .LO ( optlc_net_1788 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1790 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1790 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1965 ( .LO ( optlc_net_1789 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1791 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1791 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1967 ( .LO ( optlc_net_1790 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1792 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1792 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1969 ( .LO ( optlc_net_1791 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1793 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1793 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1971 ( .LO ( optlc_net_1792 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1794 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1794 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1973 ( .LO ( optlc_net_1793 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1795 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1795 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1974 ( .LO ( optlc_net_1794 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1796 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1796 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1975 ( .LO ( optlc_net_1795 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1797 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1797 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1976 ( .LO ( optlc_net_1796 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1798 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1798 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1977 ( .LO ( optlc_net_1797 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1799 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1799 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1978 ( .LO ( optlc_net_1798 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1800 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1800 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1979 ( .LO ( optlc_net_1799 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1801 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1801 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1980 ( .LO ( optlc_net_1800 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1802 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1802 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1981 ( .LO ( optlc_net_1801 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1803 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1803 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1983 ( .LO ( optlc_net_1802 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1804 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1804 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1984 ( .LO ( optlc_net_1803 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1805 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1805 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1985 ( .LO ( optlc_net_1804 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1806 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1806 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1986 ( .LO ( optlc_net_1805 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1807 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1807 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1988 ( .LO ( optlc_net_1806 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1808 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1808 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1990 ( .LO ( optlc_net_1807 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1809 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1809 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1991 ( .LO ( optlc_net_1808 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1810 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1810 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1993 ( .LO ( optlc_net_1809 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1811 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1811 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1994 ( .LO ( optlc_net_1810 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1812 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1812 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1995 ( .LO ( optlc_net_1811 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1813 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1813 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1997 ( .LO ( optlc_net_1812 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1814 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1814 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1998 ( .LO ( optlc_net_1813 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1815 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1815 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_1999 ( .LO ( optlc_net_1814 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1816 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1816 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2001 ( .LO ( optlc_net_1815 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1817 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1817 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2002 ( .LO ( optlc_net_1816 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1818 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1818 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2004 ( .LO ( optlc_net_1817 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1819 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1819 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2005 ( .LO ( optlc_net_1818 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1820 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1820 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2007 ( .LO ( optlc_net_1819 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1821 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1821 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2009 ( .LO ( optlc_net_1820 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1822 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1822 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2010 ( .LO ( optlc_net_1821 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1823 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1823 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2011 ( .LO ( optlc_net_1822 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1824 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1824 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2012 ( .LO ( optlc_net_1823 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1825 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1825 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2014 ( .LO ( optlc_net_1824 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1826 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1826 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2016 ( .LO ( optlc_net_1825 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1827 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1827 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2018 ( .LO ( optlc_net_1826 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1828 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1828 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2019 ( .LO ( optlc_net_1827 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1829 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1829 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2021 ( .LO ( optlc_net_1828 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1830 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1830 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2022 ( .LO ( optlc_net_1829 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1831 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1831 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2024 ( .LO ( optlc_net_1830 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1832 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1832 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2026 ( .LO ( optlc_net_1831 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1833 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1833 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2028 ( .LO ( optlc_net_1832 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1834 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1834 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2030 ( .LO ( optlc_net_1833 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1835 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1835 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2031 ( .LO ( optlc_net_1834 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1836 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1836 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2032 ( .LO ( optlc_net_1835 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1837 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1837 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2033 ( .LO ( optlc_net_1836 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1838 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1838 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2035 ( .LO ( optlc_net_1837 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1839 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1839 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2037 ( .LO ( optlc_net_1838 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1840 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1840 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2040 ( .LO ( optlc_net_1839 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1841 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1841 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2041 ( .LO ( optlc_net_1840 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1842 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1842 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2043 ( .LO ( optlc_net_1841 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1843 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1843 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2045 ( .LO ( optlc_net_1842 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1844 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1844 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2046 ( .LO ( optlc_net_1843 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1845 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1845 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2047 ( .LO ( optlc_net_1844 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1846 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1846 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2049 ( .LO ( optlc_net_1845 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1847 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1847 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2051 ( .LO ( optlc_net_1846 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1848 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1848 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2053 ( .LO ( optlc_net_1847 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1849 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1849 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2055 ( .LO ( optlc_net_1848 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1850 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1850 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2056 ( .LO ( optlc_net_1849 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1851 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1851 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2057 ( .LO ( optlc_net_1850 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1852 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1852 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2058 ( .LO ( optlc_net_1851 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1853 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1853 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2059 ( .LO ( optlc_net_1852 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1854 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1854 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2060 ( .LO ( optlc_net_1853 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1855 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1855 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2061 ( .LO ( optlc_net_1854 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1856 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1856 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2063 ( .LO ( optlc_net_1855 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1857 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1857 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2064 ( .LO ( optlc_net_1856 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1858 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1858 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2066 ( .LO ( optlc_net_1857 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1859 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1859 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2067 ( .LO ( optlc_net_1858 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1860 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1860 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2069 ( .LO ( optlc_net_1859 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1861 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1861 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2071 ( .LO ( optlc_net_1860 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1862 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1862 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2073 ( .LO ( optlc_net_1861 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1863 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1863 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2074 ( .LO ( optlc_net_1862 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1864 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1864 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2076 ( .LO ( optlc_net_1863 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1865 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1865 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2077 ( .LO ( optlc_net_1864 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1866 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1866 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2078 ( .LO ( optlc_net_1865 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1867 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1867 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2080 ( .LO ( optlc_net_1866 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1868 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1868 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2081 ( .LO ( optlc_net_1867 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1869 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1869 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2083 ( .LO ( optlc_net_1868 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1870 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1870 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2085 ( .LO ( optlc_net_1869 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1871 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1871 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2087 ( .LO ( optlc_net_1870 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1872 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1872 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2088 ( .LO ( optlc_net_1871 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1873 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1873 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2090 ( .LO ( optlc_net_1872 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1874 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1874 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2091 ( .LO ( optlc_net_1873 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1875 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1875 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2092 ( .LO ( optlc_net_1874 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1876 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1876 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2093 ( .LO ( optlc_net_1875 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1877 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1877 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2095 ( .LO ( optlc_net_1876 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1878 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1878 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2097 ( .LO ( optlc_net_1877 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1879 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1879 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2098 ( .LO ( optlc_net_1878 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1880 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1880 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2099 ( .LO ( optlc_net_1879 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1881 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1881 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2101 ( .LO ( optlc_net_1880 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1882 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1882 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2102 ( .LO ( optlc_net_1881 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1883 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1883 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2103 ( .LO ( optlc_net_1882 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1884 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1884 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2104 ( .LO ( optlc_net_1883 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1885 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1885 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2106 ( .LO ( optlc_net_1884 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1886 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1886 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2107 ( .LO ( optlc_net_1885 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1887 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1887 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2108 ( .LO ( optlc_net_1886 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1888 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1888 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2109 ( .LO ( optlc_net_1887 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1889 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1889 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2111 ( .LO ( optlc_net_1888 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1890 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1890 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2113 ( .LO ( optlc_net_1889 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1891 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1891 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2114 ( .LO ( optlc_net_1890 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1892 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1892 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2115 ( .LO ( optlc_net_1891 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1893 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1893 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2116 ( .LO ( optlc_net_1892 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1894 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1894 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2118 ( .LO ( optlc_net_1893 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1895 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1895 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2120 ( .LO ( optlc_net_1894 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1896 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1896 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2121 ( .LO ( optlc_net_1895 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1897 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1897 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2122 ( .LO ( optlc_net_1896 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1898 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1898 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2124 ( .LO ( optlc_net_1897 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1899 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1899 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2126 ( .LO ( optlc_net_1898 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1900 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1900 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2128 ( .LO ( optlc_net_1899 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1901 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1901 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2129 ( .LO ( optlc_net_1900 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1902 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1902 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2131 ( .LO ( optlc_net_1901 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1903 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1903 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2132 ( .LO ( optlc_net_1902 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1904 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1904 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2133 ( .LO ( optlc_net_1903 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1905 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1905 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2134 ( .LO ( optlc_net_1904 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1906 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1906 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2136 ( .LO ( optlc_net_1905 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1907 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1907 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2137 ( .LO ( optlc_net_1906 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1908 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1908 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2139 ( .LO ( optlc_net_1907 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1909 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1909 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2140 ( .LO ( optlc_net_1908 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1910 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1910 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2142 ( .LO ( optlc_net_1909 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1911 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1911 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2144 ( .LO ( optlc_net_1910 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1912 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1912 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2145 ( .LO ( optlc_net_1911 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1913 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1913 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2147 ( .LO ( optlc_net_1912 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1914 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1914 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2148 ( .LO ( optlc_net_1913 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1915 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1915 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2149 ( .LO ( optlc_net_1914 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1916 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1916 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2150 ( .LO ( optlc_net_1915 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1917 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1917 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2151 ( .LO ( optlc_net_1916 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1918 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1918 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2152 ( .LO ( optlc_net_1917 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1919 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1919 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2154 ( .LO ( optlc_net_1918 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1920 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1920 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2156 ( .LO ( optlc_net_1919 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1921 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1921 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2158 ( .LO ( optlc_net_1920 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1922 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1922 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2160 ( .LO ( optlc_net_1921 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1923 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1923 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2161 ( .LO ( optlc_net_1922 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1924 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1924 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2162 ( .LO ( optlc_net_1923 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1925 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1925 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2163 ( .LO ( optlc_net_1924 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1926 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1926 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2165 ( .LO ( optlc_net_1925 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1927 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1927 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2167 ( .LO ( optlc_net_1926 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1928 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1928 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2168 ( .LO ( optlc_net_1927 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1929 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1929 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2169 ( .LO ( optlc_net_1928 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1930 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1930 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2171 ( .LO ( optlc_net_1929 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1931 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1931 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2173 ( .LO ( optlc_net_1930 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1932 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1932 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2175 ( .LO ( optlc_net_1931 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1933 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1933 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2177 ( .LO ( optlc_net_1932 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1934 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1934 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2179 ( .LO ( optlc_net_1933 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1935 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1935 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2180 ( .LO ( optlc_net_1934 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1936 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1936 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2181 ( .LO ( optlc_net_1935 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1937 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1937 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2182 ( .LO ( optlc_net_1936 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1938 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1938 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2184 ( .LO ( optlc_net_1937 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1939 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1939 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2186 ( .LO ( optlc_net_1938 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1940 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1940 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2187 ( .LO ( optlc_net_1939 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1941 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1941 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2188 ( .LO ( optlc_net_1940 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1942 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1942 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2190 ( .LO ( optlc_net_1941 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1943 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1943 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2192 ( .LO ( optlc_net_1942 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1944 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1944 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2194 ( .LO ( optlc_net_1943 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1945 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1945 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2196 ( .LO ( optlc_net_1944 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1946 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1946 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2198 ( .LO ( optlc_net_1945 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1947 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1947 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2200 ( .LO ( optlc_net_1946 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1948 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1948 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2202 ( .LO ( optlc_net_1947 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1949 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1949 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2203 ( .LO ( optlc_net_1948 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1950 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1950 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2204 ( .LO ( optlc_net_1949 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1951 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1951 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2205 ( .LO ( optlc_net_1950 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1952 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1952 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2206 ( .LO ( optlc_net_1951 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1953 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1953 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2207 ( .LO ( optlc_net_1952 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1954 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1954 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2208 ( .LO ( optlc_net_1953 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1955 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1955 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2209 ( .LO ( optlc_net_1954 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1956 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1956 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2210 ( .LO ( optlc_net_1955 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1957 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1957 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2211 ( .LO ( optlc_net_1956 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1958 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1958 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2212 ( .LO ( optlc_net_1957 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1959 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1959 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2214 ( .LO ( optlc_net_1958 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1960 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1960 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2216 ( .LO ( optlc_net_1959 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1961 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1961 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2218 ( .LO ( optlc_net_1960 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1962 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1962 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2220 ( .LO ( optlc_net_1961 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1963 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1963 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2221 ( .LO ( optlc_net_1962 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1964 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1964 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2222 ( .LO ( optlc_net_1963 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1965 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1965 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2224 ( .LO ( optlc_net_1964 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1966 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1966 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2225 ( .LO ( optlc_net_1965 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1967 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1967 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2226 ( .LO ( optlc_net_1966 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1968 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1968 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2227 ( .LO ( optlc_net_1967 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1969 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1969 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2228 ( .LO ( optlc_net_1968 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1970 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1970 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2230 ( .LO ( optlc_net_1969 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1971 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1971 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2232 ( .LO ( optlc_net_1970 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1972 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1972 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2233 ( .LO ( optlc_net_1971 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1973 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1973 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2234 ( .LO ( optlc_net_1972 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1974 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1974 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2235 ( .LO ( optlc_net_1973 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1975 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1975 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2236 ( .LO ( optlc_net_1974 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1976 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1976 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2237 ( .LO ( optlc_net_1975 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1977 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1977 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2238 ( .LO ( optlc_net_1976 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1978 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1978 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2239 ( .LO ( optlc_net_1977 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1979 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1979 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2240 ( .LO ( optlc_net_1978 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1980 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1980 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2241 ( .LO ( optlc_net_1979 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1981 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1981 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2242 ( .LO ( optlc_net_1980 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1982 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1982 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2243 ( .LO ( optlc_net_1981 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1983 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1983 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2244 ( .LO ( optlc_net_1982 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1984 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1984 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2245 ( .LO ( optlc_net_1983 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1985 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1985 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2246 ( .LO ( optlc_net_1984 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1986 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1986 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2247 ( .LO ( optlc_net_1985 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1987 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1987 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2248 ( .LO ( optlc_net_1986 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1988 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1988 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2249 ( .LO ( optlc_net_1987 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1989 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1989 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2250 ( .LO ( optlc_net_1988 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1990 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1990 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2251 ( .LO ( optlc_net_1989 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1991 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1991 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2252 ( .LO ( optlc_net_1990 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1992 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1992 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2253 ( .LO ( optlc_net_1991 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1993 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1993 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2254 ( .LO ( optlc_net_1992 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1994 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1994 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2255 ( .LO ( optlc_net_1993 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1995 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1995 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2256 ( .LO ( optlc_net_1994 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1996 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1996 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2257 ( .LO ( optlc_net_1995 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1997 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1997 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2258 ( .LO ( optlc_net_1996 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1998 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1998 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2259 ( .LO ( optlc_net_1997 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_1999 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_1999 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2260 ( .LO ( optlc_net_1998 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2000 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2000 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2261 ( .LO ( optlc_net_1999 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2001 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2001 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2262 ( .LO ( optlc_net_2000 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2002 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2002 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2263 ( .LO ( optlc_net_2001 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2003 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2003 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2264 ( .LO ( optlc_net_2002 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2004 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2004 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2265 ( .LO ( optlc_net_2003 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2005 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2005 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2266 ( .LO ( optlc_net_2004 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2006 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2006 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2267 ( .LO ( optlc_net_2005 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2007 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2007 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2268 ( .LO ( optlc_net_2006 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2008 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2008 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2269 ( .LO ( optlc_net_2007 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2009 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2009 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2270 ( .LO ( optlc_net_2008 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2010 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2010 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2271 ( .LO ( optlc_net_2009 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2011 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2011 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2272 ( .LO ( optlc_net_2010 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2012 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2012 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2273 ( .LO ( optlc_net_2011 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2013 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2013 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2274 ( .LO ( optlc_net_2012 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2014 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2014 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2275 ( .LO ( optlc_net_2013 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2015 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2015 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2276 ( .LO ( optlc_net_2014 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2016 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2016 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2277 ( .LO ( optlc_net_2015 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2017 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2017 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2278 ( .LO ( optlc_net_2016 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2018 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2018 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2279 ( .LO ( optlc_net_2017 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2019 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2019 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2280 ( .LO ( optlc_net_2018 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2020 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2020 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2281 ( .LO ( optlc_net_2019 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2021 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2021 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2282 ( .LO ( optlc_net_2020 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2022 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2022 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2283 ( .LO ( optlc_net_2021 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2023 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2023 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2284 ( .LO ( optlc_net_2022 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2024 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2024 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2285 ( .LO ( optlc_net_2023 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2025 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2025 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2286 ( .LO ( optlc_net_2024 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2026 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2026 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2287 ( .LO ( optlc_net_2025 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2027 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2027 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2288 ( .LO ( optlc_net_2026 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2028 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2028 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2289 ( .LO ( optlc_net_2027 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2029 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2029 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2290 ( .LO ( optlc_net_2028 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2030 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2030 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2291 ( .LO ( optlc_net_2029 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2031 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2031 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2292 ( .LO ( optlc_net_2030 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2032 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2032 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2293 ( .LO ( optlc_net_2031 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2033 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2033 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2294 ( .LO ( optlc_net_2032 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2034 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2034 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2295 ( .LO ( optlc_net_2033 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2035 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2035 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2296 ( .LO ( optlc_net_2034 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2036 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2036 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2297 ( .LO ( optlc_net_2035 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2037 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2037 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2298 ( .LO ( optlc_net_2036 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2038 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2038 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2299 ( .LO ( optlc_net_2037 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2039 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2039 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2300 ( .LO ( optlc_net_2038 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2040 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2040 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2301 ( .LO ( optlc_net_2039 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2041 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2041 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2302 ( .LO ( optlc_net_2040 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2042 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2042 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2304 ( .LO ( optlc_net_2041 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2043 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2043 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2305 ( .LO ( optlc_net_2042 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2044 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2044 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2306 ( .LO ( optlc_net_2043 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2045 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2045 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2307 ( .LO ( optlc_net_2044 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2046 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2046 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2308 ( .LO ( optlc_net_2045 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2047 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2047 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2309 ( .LO ( optlc_net_2046 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2048 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2048 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2310 ( .LO ( optlc_net_2047 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2049 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2049 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2311 ( .LO ( optlc_net_2048 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2050 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2050 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2312 ( .LO ( optlc_net_2049 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2051 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2051 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2313 ( .LO ( optlc_net_2050 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2052 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2052 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2314 ( .LO ( optlc_net_2051 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2053 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2053 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2315 ( .LO ( optlc_net_2052 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2054 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2054 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2316 ( .LO ( optlc_net_2053 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2055 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2055 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2317 ( .LO ( optlc_net_2054 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2056 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2056 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2318 ( .LO ( optlc_net_2055 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2057 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2057 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2319 ( .LO ( optlc_net_2056 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2058 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2058 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2320 ( .LO ( optlc_net_2057 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2059 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2059 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2321 ( .LO ( optlc_net_2058 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2060 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2060 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2322 ( .LO ( optlc_net_2059 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2061 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2061 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2323 ( .LO ( optlc_net_2060 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2062 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2062 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2324 ( .LO ( optlc_net_2061 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2063 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2063 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2325 ( .LO ( optlc_net_2062 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2064 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2064 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2326 ( .LO ( optlc_net_2063 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2065 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2065 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2327 ( .LO ( optlc_net_2064 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2066 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2066 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2328 ( .LO ( optlc_net_2065 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2067 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2067 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2329 ( .LO ( optlc_net_2066 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2068 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2068 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2330 ( .LO ( optlc_net_2067 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2069 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2069 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2331 ( .LO ( optlc_net_2068 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2070 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2070 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2332 ( .LO ( optlc_net_2069 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2071 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2071 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2333 ( .LO ( optlc_net_2070 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2072 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2072 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2334 ( .LO ( optlc_net_2071 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2073 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2073 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2335 ( .LO ( optlc_net_2072 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2074 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2074 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2336 ( .LO ( optlc_net_2073 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2075 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2075 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2337 ( .LO ( optlc_net_2074 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2076 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2076 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2338 ( .LO ( optlc_net_2075 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2077 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2077 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2339 ( .LO ( optlc_net_2076 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2078 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2078 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2340 ( .LO ( optlc_net_2077 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2079 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2079 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2341 ( .LO ( optlc_net_2078 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2080 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2080 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2343 ( .LO ( optlc_net_2079 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2081 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2081 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2344 ( .LO ( optlc_net_2080 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2082 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2082 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2346 ( .LO ( optlc_net_2081 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2083 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2083 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2347 ( .LO ( optlc_net_2082 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2084 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2084 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2348 ( .LO ( optlc_net_2083 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2085 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2085 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2349 ( .LO ( optlc_net_2084 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2086 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2086 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2350 ( .LO ( optlc_net_2085 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2087 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2087 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2351 ( .LO ( optlc_net_2086 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2088 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2088 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2352 ( .LO ( optlc_net_2087 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2089 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2089 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2353 ( .LO ( optlc_net_2088 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2090 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2090 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2354 ( .LO ( optlc_net_2089 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2091 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2091 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2355 ( .LO ( optlc_net_2090 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2092 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2092 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2356 ( .LO ( optlc_net_2091 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2093 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2093 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2358 ( .LO ( optlc_net_2092 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2094 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2094 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2359 ( .LO ( optlc_net_2093 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2095 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2095 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2360 ( .LO ( optlc_net_2094 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2096 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2096 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2362 ( .LO ( optlc_net_2095 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2097 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2097 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2363 ( .LO ( optlc_net_2096 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2098 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2098 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2364 ( .LO ( optlc_net_2097 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2099 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2099 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2365 ( .LO ( optlc_net_2098 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2100 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2366 ( .LO ( optlc_net_2099 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2101 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2368 ( .LO ( optlc_net_2100 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2102 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2370 ( .LO ( optlc_net_2101 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2103 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2371 ( .LO ( optlc_net_2102 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2104 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2372 ( .LO ( optlc_net_2103 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2105 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2373 ( .LO ( optlc_net_2104 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2106 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2374 ( .LO ( optlc_net_2105 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2107 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2375 ( .LO ( optlc_net_2106 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2108 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2376 ( .LO ( optlc_net_2107 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2109 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2377 ( .LO ( optlc_net_2108 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2110 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2378 ( .LO ( optlc_net_2109 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2111 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2379 ( .LO ( optlc_net_2110 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2112 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2380 ( .LO ( optlc_net_2111 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2113 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2381 ( .LO ( optlc_net_2112 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2114 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2382 ( .LO ( optlc_net_2113 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2115 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2383 ( .LO ( optlc_net_2114 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2116 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2385 ( .LO ( optlc_net_2115 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2117 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2386 ( .LO ( optlc_net_2116 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2118 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2387 ( .LO ( optlc_net_2117 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2119 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2388 ( .LO ( optlc_net_2118 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2120 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2389 ( .LO ( optlc_net_2119 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2121 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2390 ( .LO ( optlc_net_2120 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2122 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2391 ( .LO ( optlc_net_2121 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2123 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2393 ( .LO ( optlc_net_2122 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2124 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2395 ( .LO ( optlc_net_2123 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2125 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2397 ( .LO ( optlc_net_2124 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2126 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2398 ( .LO ( optlc_net_2125 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2127 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2400 ( .LO ( optlc_net_2126 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2128 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2401 ( .LO ( optlc_net_2127 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2129 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2403 ( .LO ( optlc_net_2128 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2130 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2404 ( .LO ( optlc_net_2129 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2131 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2405 ( .LO ( optlc_net_2130 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2132 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2407 ( .LO ( optlc_net_2131 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2133 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2408 ( .LO ( optlc_net_2132 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2134 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2409 ( .LO ( optlc_net_2133 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2135 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2410 ( .LO ( optlc_net_2134 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2136 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2412 ( .LO ( optlc_net_2135 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2137 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2413 ( .LO ( optlc_net_2136 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2138 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2415 ( .LO ( optlc_net_2137 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2139 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2416 ( .LO ( optlc_net_2138 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2140 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2417 ( .LO ( optlc_net_2139 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2141 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2418 ( .LO ( optlc_net_2140 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2142 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2419 ( .LO ( optlc_net_2141 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2143 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2420 ( .LO ( optlc_net_2142 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2144 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2421 ( .LO ( optlc_net_2143 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2145 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2422 ( .LO ( optlc_net_2144 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2146 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2423 ( .LO ( optlc_net_2145 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2147 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2425 ( .LO ( optlc_net_2146 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2148 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2426 ( .LO ( optlc_net_2147 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2149 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2427 ( .LO ( optlc_net_2148 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2150 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2428 ( .LO ( optlc_net_2149 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2151 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2429 ( .LO ( optlc_net_2150 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2152 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2430 ( .LO ( optlc_net_2151 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2153 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2431 ( .LO ( optlc_net_2152 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2154 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2433 ( .LO ( optlc_net_2153 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2155 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2434 ( .LO ( optlc_net_2154 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2156 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2436 ( .LO ( optlc_net_2155 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2157 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2438 ( .LO ( optlc_net_2156 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2158 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2439 ( .LO ( optlc_net_2157 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2159 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2441 ( .LO ( optlc_net_2158 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2160 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2442 ( .LO ( optlc_net_2159 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2161 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2443 ( .LO ( optlc_net_2160 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2162 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2445 ( .LO ( optlc_net_2161 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2163 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2446 ( .LO ( optlc_net_2162 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2164 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2447 ( .LO ( optlc_net_2163 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2165 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2448 ( .LO ( optlc_net_2164 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2166 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2449 ( .LO ( optlc_net_2165 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2167 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2450 ( .LO ( optlc_net_2166 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2168 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2451 ( .LO ( optlc_net_2167 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2169 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2452 ( .LO ( optlc_net_2168 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2170 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2454 ( .LO ( optlc_net_2169 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2171 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2455 ( .LO ( optlc_net_2170 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2172 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2456 ( .LO ( optlc_net_2171 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2173 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2457 ( .LO ( optlc_net_2172 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2174 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2458 ( .LO ( optlc_net_2173 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2175 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2459 ( .LO ( optlc_net_2174 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2176 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2460 ( .LO ( optlc_net_2175 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2177 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2461 ( .LO ( optlc_net_2176 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2178 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2462 ( .LO ( optlc_net_2177 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2179 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2463 ( .LO ( optlc_net_2178 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2180 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2465 ( .LO ( optlc_net_2179 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2181 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2466 ( .LO ( optlc_net_2180 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2182 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2467 ( .LO ( optlc_net_2181 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2183 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2468 ( .LO ( optlc_net_2182 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2184 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2469 ( .LO ( optlc_net_2183 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2185 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2470 ( .LO ( optlc_net_2184 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2186 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2472 ( .LO ( optlc_net_2185 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2187 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2473 ( .LO ( optlc_net_2186 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2188 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2474 ( .LO ( optlc_net_2187 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2189 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2475 ( .LO ( optlc_net_2188 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2190 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2476 ( .LO ( optlc_net_2189 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2191 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2477 ( .LO ( optlc_net_2190 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2192 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2479 ( .LO ( optlc_net_2191 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2193 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2481 ( .LO ( optlc_net_2192 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2194 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2483 ( .LO ( optlc_net_2193 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2195 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2484 ( .LO ( optlc_net_2194 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2196 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2485 ( .LO ( optlc_net_2195 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2197 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2486 ( .LO ( optlc_net_2196 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2198 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2488 ( .LO ( optlc_net_2197 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2199 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2489 ( .LO ( optlc_net_2198 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2200 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2490 ( .LO ( optlc_net_2199 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2201 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2491 ( .LO ( optlc_net_2200 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2202 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2492 ( .LO ( optlc_net_2201 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2203 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2494 ( .LO ( optlc_net_2202 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2204 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2495 ( .LO ( optlc_net_2203 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2205 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2497 ( .LO ( optlc_net_2204 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2206 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2498 ( .LO ( optlc_net_2205 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2207 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2499 ( .LO ( optlc_net_2206 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2208 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2500 ( .LO ( optlc_net_2207 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2209 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2502 ( .LO ( optlc_net_2208 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2210 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2503 ( .LO ( optlc_net_2209 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2211 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2504 ( .LO ( optlc_net_2210 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2212 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2505 ( .LO ( optlc_net_2211 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2213 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2507 ( .LO ( optlc_net_2212 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2214 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2509 ( .LO ( optlc_net_2213 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2215 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2510 ( .LO ( optlc_net_2214 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2216 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2511 ( .LO ( optlc_net_2215 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2217 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2512 ( .LO ( optlc_net_2216 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2218 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2513 ( .LO ( optlc_net_2217 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2219 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2515 ( .LO ( optlc_net_2218 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2220 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2517 ( .LO ( optlc_net_2219 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2221 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2519 ( .LO ( optlc_net_2220 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2222 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2521 ( .LO ( optlc_net_2221 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2223 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2522 ( .LO ( optlc_net_2222 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2224 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2523 ( .LO ( optlc_net_2223 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2225 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2524 ( .LO ( optlc_net_2224 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2226 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2525 ( .LO ( optlc_net_2225 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2227 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2526 ( .LO ( optlc_net_2226 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2228 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2527 ( .LO ( optlc_net_2227 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2229 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2528 ( .LO ( optlc_net_2228 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2230 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2529 ( .LO ( optlc_net_2229 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2231 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2530 ( .LO ( optlc_net_2230 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2232 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2531 ( .LO ( optlc_net_2231 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2233 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2233 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2533 ( .LO ( optlc_net_2232 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2234 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2234 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2534 ( .LO ( optlc_net_2233 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2235 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2235 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2535 ( .LO ( optlc_net_2234 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2236 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2236 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2536 ( .LO ( optlc_net_2235 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2237 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2237 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2538 ( .LO ( optlc_net_2236 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2238 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2238 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2539 ( .LO ( optlc_net_2237 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2239 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2239 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2540 ( .LO ( optlc_net_2238 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2240 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2240 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2541 ( .LO ( optlc_net_2239 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2241 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2241 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2542 ( .LO ( optlc_net_2240 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2242 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2242 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2543 ( .LO ( optlc_net_2241 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2243 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2243 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2544 ( .LO ( optlc_net_2242 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2244 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2244 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2545 ( .LO ( optlc_net_2243 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2245 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2245 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2546 ( .LO ( optlc_net_2244 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2246 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2246 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2547 ( .LO ( optlc_net_2245 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2247 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2247 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2549 ( .LO ( optlc_net_2246 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2248 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2248 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2550 ( .LO ( optlc_net_2247 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2249 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2249 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2552 ( .LO ( optlc_net_2248 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2250 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2250 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2553 ( .LO ( optlc_net_2249 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2251 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2251 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2554 ( .LO ( optlc_net_2250 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2252 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2252 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2556 ( .LO ( optlc_net_2251 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2253 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2253 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2557 ( .LO ( optlc_net_2252 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2254 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2254 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2558 ( .LO ( optlc_net_2253 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2255 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2255 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2559 ( .LO ( optlc_net_2254 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2256 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2256 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2560 ( .LO ( optlc_net_2255 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2257 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2257 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2562 ( .LO ( optlc_net_2256 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2258 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2258 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2563 ( .LO ( optlc_net_2257 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2259 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2259 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2564 ( .LO ( optlc_net_2258 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2260 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2260 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2566 ( .LO ( optlc_net_2259 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2261 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2261 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2568 ( .LO ( optlc_net_2260 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2262 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2262 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2569 ( .LO ( optlc_net_2261 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2263 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2263 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2570 ( .LO ( optlc_net_2262 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2264 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2264 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2571 ( .LO ( optlc_net_2263 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2265 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2265 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2572 ( .LO ( optlc_net_2264 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2266 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2266 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2573 ( .LO ( optlc_net_2265 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2267 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2267 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2574 ( .LO ( optlc_net_2266 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2268 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2268 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2575 ( .LO ( optlc_net_2267 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2269 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2269 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2576 ( .LO ( optlc_net_2268 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2270 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2270 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2577 ( .LO ( optlc_net_2269 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2271 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2271 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2578 ( .LO ( optlc_net_2270 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2272 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2272 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2579 ( .LO ( optlc_net_2271 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2273 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2273 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2580 ( .LO ( optlc_net_2272 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2274 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2274 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2581 ( .LO ( optlc_net_2273 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2275 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2275 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2582 ( .LO ( optlc_net_2274 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2276 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2276 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2583 ( .LO ( optlc_net_2275 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2277 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2277 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2584 ( .LO ( optlc_net_2276 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2278 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2278 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2585 ( .LO ( optlc_net_2277 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2279 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2279 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2586 ( .LO ( optlc_net_2278 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2280 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2280 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2587 ( .LO ( optlc_net_2279 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2281 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2281 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2588 ( .LO ( optlc_net_2280 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2282 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2282 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2589 ( .LO ( optlc_net_2281 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2283 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2283 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2590 ( .LO ( optlc_net_2282 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2284 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2284 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2591 ( .LO ( optlc_net_2283 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2285 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2285 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2592 ( .LO ( optlc_net_2284 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2286 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2286 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2593 ( .LO ( optlc_net_2285 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2287 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2287 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2594 ( .LO ( optlc_net_2286 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2288 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2288 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2595 ( .LO ( optlc_net_2287 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2289 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2289 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2596 ( .LO ( optlc_net_2288 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2290 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2290 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2597 ( .LO ( optlc_net_2289 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2291 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2291 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2598 ( .LO ( optlc_net_2290 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2292 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2292 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2599 ( .LO ( optlc_net_2291 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2293 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2293 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2600 ( .LO ( optlc_net_2292 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2294 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2294 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2601 ( .LO ( optlc_net_2293 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2295 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2295 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2602 ( .LO ( optlc_net_2294 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2296 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2296 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2603 ( .LO ( optlc_net_2295 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2297 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2297 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2604 ( .LO ( optlc_net_2296 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2298 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2298 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2605 ( .LO ( optlc_net_2297 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2299 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2299 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2606 ( .LO ( optlc_net_2298 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2300 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2300 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2607 ( .LO ( optlc_net_2299 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2301 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2301 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2608 ( .LO ( optlc_net_2300 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2302 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2302 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2609 ( .LO ( optlc_net_2301 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2303 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2303 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2610 ( .LO ( optlc_net_2302 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2304 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2304 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2611 ( .LO ( optlc_net_2303 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2305 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2305 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2612 ( .LO ( optlc_net_2304 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2306 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2306 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2613 ( .LO ( optlc_net_2305 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2307 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2307 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2614 ( .LO ( optlc_net_2306 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2308 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2308 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2615 ( .LO ( optlc_net_2307 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2309 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2309 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2616 ( .LO ( optlc_net_2308 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2310 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2310 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2617 ( .LO ( optlc_net_2309 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2311 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2311 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2618 ( .LO ( optlc_net_2310 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2312 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2312 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2619 ( .LO ( optlc_net_2311 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2313 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2313 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2620 ( .LO ( optlc_net_2312 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2314 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2314 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2621 ( .LO ( optlc_net_2313 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2315 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2315 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2622 ( .LO ( optlc_net_2314 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2316 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2316 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2623 ( .LO ( optlc_net_2315 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2317 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2317 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2624 ( .LO ( optlc_net_2316 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2318 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2318 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2625 ( .LO ( optlc_net_2317 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2319 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2319 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2626 ( .LO ( optlc_net_2318 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2320 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2320 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2627 ( .LO ( optlc_net_2319 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2321 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2321 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2628 ( .LO ( optlc_net_2320 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2322 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2322 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2629 ( .LO ( optlc_net_2321 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2323 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2323 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2630 ( .LO ( optlc_net_2322 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2324 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2324 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2631 ( .LO ( optlc_net_2323 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2325 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2325 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2632 ( .LO ( optlc_net_2324 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2326 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2326 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2633 ( .LO ( optlc_net_2325 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2327 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2327 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2634 ( .LO ( optlc_net_2326 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2328 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2328 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2635 ( .LO ( optlc_net_2327 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2329 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2329 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2636 ( .LO ( optlc_net_2328 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2330 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2330 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2637 ( .LO ( optlc_net_2329 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2331 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2331 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2638 ( .LO ( optlc_net_2330 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2332 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2332 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2639 ( .LO ( optlc_net_2331 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2333 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2333 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2640 ( .LO ( optlc_net_2332 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2334 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2334 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2641 ( .LO ( optlc_net_2333 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2335 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2335 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2642 ( .LO ( optlc_net_2334 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2336 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2336 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2643 ( .LO ( optlc_net_2335 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2337 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2337 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2644 ( .LO ( optlc_net_2336 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2338 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2338 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2645 ( .LO ( optlc_net_2337 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2339 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2339 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2646 ( .LO ( optlc_net_2338 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2340 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2340 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2647 ( .LO ( optlc_net_2339 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2341 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2341 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2648 ( .LO ( optlc_net_2340 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2342 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2342 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2649 ( .LO ( optlc_net_2341 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2343 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2343 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2650 ( .LO ( optlc_net_2342 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2344 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2344 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2651 ( .LO ( optlc_net_2343 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2345 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2345 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2652 ( .LO ( optlc_net_2344 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2346 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2346 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2653 ( .LO ( optlc_net_2345 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2347 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2347 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2654 ( .LO ( optlc_net_2346 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2348 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2348 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2655 ( .LO ( optlc_net_2347 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2349 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2349 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2656 ( .LO ( optlc_net_2348 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2350 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2350 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2657 ( .LO ( optlc_net_2349 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2351 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2351 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2658 ( .LO ( optlc_net_2350 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2352 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2352 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2659 ( .LO ( optlc_net_2351 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2353 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2353 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2660 ( .LO ( optlc_net_2352 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2354 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2354 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2661 ( .LO ( optlc_net_2353 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2355 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2355 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2662 ( .LO ( optlc_net_2354 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2356 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2356 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2663 ( .LO ( optlc_net_2355 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2357 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2357 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2664 ( .LO ( optlc_net_2356 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2358 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2358 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2665 ( .LO ( optlc_net_2357 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2359 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2359 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2666 ( .LO ( optlc_net_2358 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2360 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2360 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2667 ( .LO ( optlc_net_2359 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2361 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2361 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2668 ( .LO ( optlc_net_2360 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2362 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2362 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2669 ( .LO ( optlc_net_2361 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2363 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2363 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2670 ( .LO ( optlc_net_2362 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2364 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2364 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2671 ( .LO ( optlc_net_2363 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2365 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2365 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2672 ( .LO ( optlc_net_2364 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2366 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2366 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2673 ( .LO ( optlc_net_2365 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2367 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2367 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2674 ( .LO ( optlc_net_2366 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2368 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2368 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2675 ( .LO ( optlc_net_2367 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2369 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2369 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2676 ( .LO ( optlc_net_2368 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2370 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2370 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2677 ( .LO ( optlc_net_2369 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2371 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2371 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2678 ( .LO ( optlc_net_2370 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2372 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2372 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2680 ( .LO ( optlc_net_2371 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2373 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2373 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2681 ( .LO ( optlc_net_2372 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2374 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2374 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2682 ( .LO ( optlc_net_2373 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2375 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2375 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2683 ( .LO ( optlc_net_2374 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2376 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2376 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2685 ( .LO ( optlc_net_2375 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2377 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2377 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2686 ( .LO ( optlc_net_2376 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2378 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2378 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2687 ( .LO ( optlc_net_2377 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2379 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2379 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2688 ( .LO ( optlc_net_2378 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2380 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2380 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2689 ( .LO ( optlc_net_2379 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2381 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2381 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2690 ( .LO ( optlc_net_2380 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2382 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2382 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2692 ( .LO ( optlc_net_2381 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2383 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2383 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2693 ( .LO ( optlc_net_2382 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2384 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2384 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2694 ( .LO ( optlc_net_2383 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2385 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2385 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2695 ( .LO ( optlc_net_2384 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2386 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2386 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2697 ( .LO ( optlc_net_2385 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2387 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2387 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2698 ( .LO ( optlc_net_2386 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2388 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2388 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2699 ( .LO ( optlc_net_2387 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2389 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2389 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2700 ( .LO ( optlc_net_2388 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2390 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2390 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2702 ( .LO ( optlc_net_2389 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2391 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2391 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2704 ( .LO ( optlc_net_2390 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2392 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2392 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2705 ( .LO ( optlc_net_2391 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2393 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2393 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2706 ( .LO ( optlc_net_2392 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2394 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2394 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2707 ( .LO ( optlc_net_2393 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2395 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2395 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2708 ( .LO ( optlc_net_2394 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2396 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2396 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2709 ( .LO ( optlc_net_2395 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2397 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2397 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2710 ( .LO ( optlc_net_2396 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2398 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2398 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2711 ( .LO ( optlc_net_2397 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2399 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2399 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2712 ( .LO ( optlc_net_2398 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2400 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2400 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2713 ( .LO ( optlc_net_2399 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2401 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2401 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2714 ( .LO ( optlc_net_2400 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2402 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2402 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2715 ( .LO ( optlc_net_2401 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2403 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2403 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2717 ( .LO ( optlc_net_2402 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2404 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2404 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2719 ( .LO ( optlc_net_2403 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2405 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2405 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2721 ( .LO ( optlc_net_2404 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2406 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2406 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2722 ( .LO ( optlc_net_2405 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2407 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2407 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2724 ( .LO ( optlc_net_2406 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2408 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2408 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2725 ( .LO ( optlc_net_2407 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2409 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2409 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2726 ( .LO ( optlc_net_2408 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2410 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2410 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2727 ( .LO ( optlc_net_2409 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2411 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2411 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2729 ( .LO ( optlc_net_2410 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2412 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2412 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2730 ( .LO ( optlc_net_2411 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2413 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2413 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2731 ( .LO ( optlc_net_2412 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2414 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2414 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2733 ( .LO ( optlc_net_2413 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2415 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2415 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2735 ( .LO ( optlc_net_2414 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2416 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2416 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2736 ( .LO ( optlc_net_2415 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2417 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2417 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2738 ( .LO ( optlc_net_2416 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2418 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2418 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2739 ( .LO ( optlc_net_2417 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2419 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2419 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2740 ( .LO ( optlc_net_2418 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2420 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2420 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2741 ( .LO ( optlc_net_2419 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2421 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2421 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2743 ( .LO ( optlc_net_2420 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2422 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2422 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2745 ( .LO ( optlc_net_2421 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2423 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2423 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2746 ( .LO ( optlc_net_2422 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2424 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2424 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2747 ( .LO ( optlc_net_2423 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2425 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2425 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2749 ( .LO ( optlc_net_2424 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2426 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2426 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2750 ( .LO ( optlc_net_2425 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2427 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2427 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2752 ( .LO ( optlc_net_2426 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2428 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2428 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2753 ( .LO ( optlc_net_2427 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2429 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2429 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2754 ( .LO ( optlc_net_2428 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2430 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2430 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2755 ( .LO ( optlc_net_2429 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2431 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2431 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2756 ( .LO ( optlc_net_2430 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2432 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2432 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2757 ( .LO ( optlc_net_2431 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2433 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2433 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2759 ( .LO ( optlc_net_2432 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2434 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2434 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2760 ( .LO ( optlc_net_2433 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2435 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2435 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2761 ( .LO ( optlc_net_2434 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2436 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2436 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2762 ( .LO ( optlc_net_2435 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2437 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2437 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2763 ( .LO ( optlc_net_2436 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2438 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2438 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2764 ( .LO ( optlc_net_2437 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2439 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2439 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2765 ( .LO ( optlc_net_2438 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2440 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2440 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2766 ( .LO ( optlc_net_2439 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2441 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2441 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2767 ( .LO ( optlc_net_2440 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2442 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2442 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2768 ( .LO ( optlc_net_2441 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2443 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2443 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2769 ( .LO ( optlc_net_2442 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2444 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2444 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2770 ( .LO ( optlc_net_2443 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2445 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2445 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2771 ( .LO ( optlc_net_2444 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2446 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2446 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2773 ( .LO ( optlc_net_2445 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2447 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2447 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2774 ( .LO ( optlc_net_2446 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2448 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2448 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2775 ( .LO ( optlc_net_2447 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2449 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2449 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2776 ( .LO ( optlc_net_2448 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2450 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2450 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2777 ( .LO ( optlc_net_2449 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2451 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2451 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2779 ( .LO ( optlc_net_2450 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2452 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2452 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2780 ( .LO ( optlc_net_2451 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2453 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2453 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2781 ( .LO ( optlc_net_2452 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2454 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2454 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2782 ( .LO ( optlc_net_2453 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2455 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2455 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2783 ( .LO ( optlc_net_2454 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2456 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2456 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2784 ( .LO ( optlc_net_2455 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2457 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2457 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2785 ( .LO ( optlc_net_2456 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2458 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2458 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2786 ( .LO ( optlc_net_2457 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2459 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2459 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2787 ( .LO ( optlc_net_2458 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2460 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2460 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2789 ( .LO ( optlc_net_2459 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2461 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2461 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2791 ( .LO ( optlc_net_2460 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2462 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2462 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2792 ( .LO ( optlc_net_2461 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2463 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2463 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2793 ( .LO ( optlc_net_2462 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2464 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2464 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2794 ( .LO ( optlc_net_2463 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2465 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2465 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2795 ( .LO ( optlc_net_2464 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2466 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2466 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2796 ( .LO ( optlc_net_2465 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2467 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2467 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2797 ( .LO ( optlc_net_2466 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2468 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2468 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2798 ( .LO ( optlc_net_2467 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2469 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2469 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2799 ( .LO ( optlc_net_2468 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2470 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2470 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2801 ( .LO ( optlc_net_2469 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2471 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2471 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2802 ( .LO ( optlc_net_2470 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2472 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2472 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2803 ( .LO ( optlc_net_2471 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2473 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2473 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2804 ( .LO ( optlc_net_2472 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2474 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2474 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2805 ( .LO ( optlc_net_2473 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2475 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2475 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2806 ( .LO ( optlc_net_2474 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2476 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2476 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2807 ( .LO ( optlc_net_2475 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2477 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2477 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2808 ( .LO ( optlc_net_2476 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2478 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2478 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2809 ( .LO ( optlc_net_2477 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2479 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2479 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2810 ( .LO ( optlc_net_2478 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2480 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2480 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2812 ( .LO ( optlc_net_2479 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2481 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2481 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2813 ( .LO ( optlc_net_2480 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2482 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2482 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2814 ( .LO ( optlc_net_2481 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2483 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2483 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2815 ( .LO ( optlc_net_2482 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2484 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2484 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2816 ( .LO ( optlc_net_2483 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2485 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2485 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2817 ( .LO ( optlc_net_2484 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2486 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2486 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2818 ( .LO ( optlc_net_2485 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2487 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2487 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2819 ( .LO ( optlc_net_2486 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2488 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2488 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2820 ( .LO ( optlc_net_2487 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2489 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2489 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2822 ( .LO ( optlc_net_2488 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2490 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2490 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2823 ( .LO ( optlc_net_2489 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2491 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2491 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2824 ( .LO ( optlc_net_2490 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2492 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2492 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2825 ( .LO ( optlc_net_2491 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2493 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2493 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2826 ( .LO ( optlc_net_2492 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2494 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2494 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2827 ( .LO ( optlc_net_2493 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2495 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2495 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2829 ( .LO ( optlc_net_2494 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2496 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2496 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2830 ( .LO ( optlc_net_2495 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2497 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2497 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2832 ( .LO ( optlc_net_2496 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2498 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2498 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2833 ( .LO ( optlc_net_2497 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2499 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2499 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2834 ( .LO ( optlc_net_2498 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2500 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2500 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2835 ( .LO ( optlc_net_2499 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2501 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2501 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2836 ( .LO ( optlc_net_2500 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2502 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2502 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2837 ( .LO ( optlc_net_2501 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2503 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2503 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2838 ( .LO ( optlc_net_2502 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2504 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2504 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2839 ( .LO ( optlc_net_2503 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2505 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2505 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2841 ( .LO ( optlc_net_2504 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2506 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2506 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2842 ( .LO ( optlc_net_2505 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2507 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2507 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2843 ( .LO ( optlc_net_2506 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2508 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2508 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2844 ( .LO ( optlc_net_2507 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2509 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2509 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2845 ( .LO ( optlc_net_2508 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2510 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2510 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2846 ( .LO ( optlc_net_2509 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2511 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2511 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2847 ( .LO ( optlc_net_2510 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2512 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2512 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2848 ( .LO ( optlc_net_2511 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2513 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2513 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2850 ( .LO ( optlc_net_2512 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2514 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2514 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2851 ( .LO ( optlc_net_2513 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2515 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2515 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2852 ( .LO ( optlc_net_2514 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2516 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2516 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2853 ( .LO ( optlc_net_2515 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2517 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2517 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2854 ( .LO ( optlc_net_2516 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2518 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2518 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2855 ( .LO ( optlc_net_2517 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2519 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2519 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2856 ( .LO ( optlc_net_2518 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2520 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2520 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2857 ( .LO ( optlc_net_2519 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2521 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2521 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2858 ( .LO ( optlc_net_2520 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2522 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2522 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2859 ( .LO ( optlc_net_2521 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2523 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2523 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2860 ( .LO ( optlc_net_2522 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2524 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2524 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2861 ( .LO ( optlc_net_2523 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2525 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2525 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2862 ( .LO ( optlc_net_2524 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2526 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2526 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2863 ( .LO ( optlc_net_2525 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2527 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2527 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2864 ( .LO ( optlc_net_2526 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2528 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2528 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2865 ( .LO ( optlc_net_2527 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2529 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2529 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2866 ( .LO ( optlc_net_2528 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2530 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2530 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2867 ( .LO ( optlc_net_2529 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2531 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2531 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2868 ( .LO ( optlc_net_2530 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2532 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2532 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2869 ( .LO ( optlc_net_2531 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2533 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2533 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2870 ( .LO ( optlc_net_2532 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2534 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2534 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2871 ( .LO ( optlc_net_2533 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2535 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2535 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2872 ( .LO ( optlc_net_2534 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2536 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2536 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2873 ( .LO ( optlc_net_2535 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2537 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2537 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2874 ( .LO ( optlc_net_2536 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2538 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2538 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2875 ( .LO ( optlc_net_2537 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2539 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2539 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2876 ( .LO ( optlc_net_2538 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2540 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2540 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2877 ( .LO ( optlc_net_2539 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2541 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2541 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2878 ( .LO ( optlc_net_2540 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2542 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2542 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2879 ( .LO ( optlc_net_2541 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2543 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2543 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2880 ( .LO ( optlc_net_2542 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2544 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2544 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2881 ( .LO ( optlc_net_2543 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2545 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2545 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2882 ( .LO ( optlc_net_2544 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2546 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2546 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2883 ( .LO ( optlc_net_2545 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2547 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2547 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2884 ( .LO ( optlc_net_2546 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2548 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2548 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2885 ( .LO ( optlc_net_2547 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2549 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2549 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2886 ( .LO ( optlc_net_2548 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2550 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2550 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2887 ( .LO ( optlc_net_2549 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2551 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2551 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2888 ( .LO ( optlc_net_2550 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2552 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2552 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2889 ( .LO ( optlc_net_2551 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2553 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2553 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2890 ( .LO ( optlc_net_2552 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2554 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2554 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2891 ( .LO ( optlc_net_2553 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2555 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2555 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2892 ( .LO ( optlc_net_2554 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2556 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2556 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2893 ( .LO ( optlc_net_2555 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2557 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2557 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2894 ( .LO ( optlc_net_2556 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2558 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2558 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2895 ( .LO ( optlc_net_2557 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2559 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2559 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2896 ( .LO ( optlc_net_2558 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2560 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2560 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2897 ( .LO ( optlc_net_2559 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2561 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2561 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2898 ( .LO ( optlc_net_2560 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2562 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2562 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2899 ( .LO ( optlc_net_2561 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2563 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2563 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2900 ( .LO ( optlc_net_2562 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2564 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2564 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2901 ( .LO ( optlc_net_2563 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2565 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2565 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2902 ( .LO ( optlc_net_2564 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2566 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2566 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2903 ( .LO ( optlc_net_2565 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2567 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2567 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2904 ( .LO ( optlc_net_2566 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2568 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2568 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2905 ( .LO ( optlc_net_2567 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2569 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2569 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2906 ( .LO ( optlc_net_2568 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2570 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2570 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2907 ( .LO ( optlc_net_2569 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2571 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2571 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2908 ( .LO ( optlc_net_2570 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2572 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2572 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2909 ( .LO ( optlc_net_2571 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2573 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2573 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2910 ( .LO ( optlc_net_2572 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2574 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2574 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2911 ( .LO ( optlc_net_2573 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2575 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2575 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2912 ( .LO ( optlc_net_2574 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2576 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2576 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2913 ( .LO ( optlc_net_2575 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2577 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2577 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2914 ( .LO ( optlc_net_2576 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2578 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2578 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2915 ( .LO ( optlc_net_2577 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2579 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2579 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2916 ( .LO ( optlc_net_2578 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2580 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2580 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2917 ( .LO ( optlc_net_2579 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2581 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2581 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2918 ( .LO ( optlc_net_2580 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2582 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2582 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2919 ( .LO ( optlc_net_2581 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2583 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2583 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2920 ( .LO ( optlc_net_2582 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2584 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2584 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2921 ( .LO ( optlc_net_2583 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2585 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2585 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2922 ( .LO ( optlc_net_2584 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2586 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2586 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2923 ( .LO ( optlc_net_2585 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2587 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2587 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2924 ( .LO ( optlc_net_2586 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2588 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2588 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2925 ( .LO ( optlc_net_2587 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2589 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2589 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2926 ( .LO ( optlc_net_2588 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2590 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2590 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2927 ( .LO ( optlc_net_2589 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2591 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2591 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2928 ( .LO ( optlc_net_2590 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2592 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2592 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2929 ( .LO ( optlc_net_2591 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2593 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2593 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2930 ( .LO ( optlc_net_2592 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2594 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2594 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2931 ( .LO ( optlc_net_2593 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2595 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2595 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2932 ( .LO ( optlc_net_2594 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2596 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2596 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2933 ( .LO ( optlc_net_2595 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2597 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2597 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2934 ( .LO ( optlc_net_2596 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2598 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2598 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2935 ( .LO ( optlc_net_2597 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2599 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2599 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2936 ( .LO ( optlc_net_2598 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2600 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2600 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2937 ( .LO ( optlc_net_2599 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2601 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2601 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2938 ( .LO ( optlc_net_2600 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2602 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2602 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2939 ( .LO ( optlc_net_2601 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2603 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2603 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2940 ( .LO ( optlc_net_2602 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2604 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2604 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2941 ( .LO ( optlc_net_2603 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2605 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2605 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2942 ( .LO ( optlc_net_2604 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2606 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2606 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2943 ( .LO ( optlc_net_2605 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2607 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2607 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2944 ( .LO ( optlc_net_2606 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2608 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2608 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2945 ( .LO ( optlc_net_2607 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2609 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2609 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2946 ( .LO ( optlc_net_2608 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2610 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2610 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2947 ( .LO ( optlc_net_2609 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2611 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2611 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2948 ( .LO ( optlc_net_2610 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2612 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2612 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2949 ( .LO ( optlc_net_2611 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2613 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2613 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2951 ( .LO ( optlc_net_2612 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2614 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2614 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2952 ( .LO ( optlc_net_2613 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2615 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2615 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2953 ( .LO ( optlc_net_2614 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2616 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2616 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2954 ( .LO ( optlc_net_2615 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2617 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2617 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2955 ( .LO ( optlc_net_2616 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2618 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2618 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2956 ( .LO ( optlc_net_2617 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2619 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2619 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2957 ( .LO ( optlc_net_2618 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2620 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2620 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2958 ( .LO ( optlc_net_2619 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2621 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2621 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2959 ( .LO ( optlc_net_2620 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2622 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2622 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2960 ( .LO ( optlc_net_2621 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2623 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2623 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2962 ( .LO ( optlc_net_2622 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2624 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2624 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2963 ( .LO ( optlc_net_2623 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2625 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2625 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2964 ( .LO ( optlc_net_2624 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2626 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2626 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2965 ( .LO ( optlc_net_2625 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2627 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2627 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2966 ( .LO ( optlc_net_2626 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2628 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2628 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2967 ( .LO ( optlc_net_2627 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2629 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2629 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2968 ( .LO ( optlc_net_2628 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2630 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2630 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2969 ( .LO ( optlc_net_2629 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2631 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2631 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2970 ( .LO ( optlc_net_2630 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2632 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2632 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2971 ( .LO ( optlc_net_2631 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2633 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2633 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2973 ( .LO ( optlc_net_2632 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2634 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2634 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2974 ( .LO ( optlc_net_2633 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2635 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2635 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2975 ( .LO ( optlc_net_2634 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2636 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2636 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2976 ( .LO ( optlc_net_2635 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2637 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2637 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2977 ( .LO ( optlc_net_2636 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2638 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2638 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2978 ( .LO ( optlc_net_2637 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2639 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2639 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2979 ( .LO ( optlc_net_2638 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2640 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2640 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2980 ( .LO ( optlc_net_2639 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2641 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2641 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2981 ( .LO ( optlc_net_2640 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2642 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2642 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2982 ( .LO ( optlc_net_2641 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2643 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2643 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2983 ( .LO ( optlc_net_2642 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2644 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2644 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2985 ( .LO ( optlc_net_2643 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2645 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2645 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2986 ( .LO ( optlc_net_2644 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2646 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2646 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2987 ( .LO ( optlc_net_2645 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2647 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2647 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2988 ( .LO ( optlc_net_2646 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2648 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2648 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2989 ( .LO ( optlc_net_2647 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2649 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2649 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2990 ( .LO ( optlc_net_2648 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2650 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2650 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2991 ( .LO ( optlc_net_2649 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2651 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2651 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2992 ( .LO ( optlc_net_2650 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2652 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2652 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2993 ( .LO ( optlc_net_2651 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2653 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2653 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2995 ( .LO ( optlc_net_2652 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2654 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2654 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2997 ( .LO ( optlc_net_2653 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2655 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2655 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2998 ( .LO ( optlc_net_2654 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2656 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2656 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_2999 ( .LO ( optlc_net_2655 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2657 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2657 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3000 ( .LO ( optlc_net_2656 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2658 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2658 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3001 ( .LO ( optlc_net_2657 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2659 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2659 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3002 ( .LO ( optlc_net_2658 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2660 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2660 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3003 ( .LO ( optlc_net_2659 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2661 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2661 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3004 ( .LO ( optlc_net_2660 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2662 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2662 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3005 ( .LO ( optlc_net_2661 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2663 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2663 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3006 ( .LO ( optlc_net_2662 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2664 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2664 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3007 ( .LO ( optlc_net_2663 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2665 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2665 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3008 ( .LO ( optlc_net_2664 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2666 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2666 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3009 ( .LO ( optlc_net_2665 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2667 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2667 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3010 ( .LO ( optlc_net_2666 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2668 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2668 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3011 ( .LO ( optlc_net_2667 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2669 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2669 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3013 ( .LO ( optlc_net_2668 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2670 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2670 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3014 ( .LO ( optlc_net_2669 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2671 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2671 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3015 ( .LO ( optlc_net_2670 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2672 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2672 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3016 ( .LO ( optlc_net_2671 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2673 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2673 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3017 ( .LO ( optlc_net_2672 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2674 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2674 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3019 ( .LO ( optlc_net_2673 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2675 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2675 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3020 ( .LO ( optlc_net_2674 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2676 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2676 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3021 ( .LO ( optlc_net_2675 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2677 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2677 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3022 ( .LO ( optlc_net_2676 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2678 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2678 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3023 ( .LO ( optlc_net_2677 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2679 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2679 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3024 ( .LO ( optlc_net_2678 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2680 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2680 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3025 ( .LO ( optlc_net_2679 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2681 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2681 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3026 ( .LO ( optlc_net_2680 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2682 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2682 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3027 ( .LO ( optlc_net_2681 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2683 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2683 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3028 ( .LO ( optlc_net_2682 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2684 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2684 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3030 ( .LO ( optlc_net_2683 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2685 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2685 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3031 ( .LO ( optlc_net_2684 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2686 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2686 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3032 ( .LO ( optlc_net_2685 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2687 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2687 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3034 ( .LO ( optlc_net_2686 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2688 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2688 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3035 ( .LO ( optlc_net_2687 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2689 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2689 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3037 ( .LO ( optlc_net_2688 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2690 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2690 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3038 ( .LO ( optlc_net_2689 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2691 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2691 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3039 ( .LO ( optlc_net_2690 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2692 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2692 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3040 ( .LO ( optlc_net_2691 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2693 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2693 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3041 ( .LO ( optlc_net_2692 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2694 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2694 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3042 ( .LO ( optlc_net_2693 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2695 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2695 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3043 ( .LO ( optlc_net_2694 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2696 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2696 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3044 ( .LO ( optlc_net_2695 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2697 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2697 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3045 ( .LO ( optlc_net_2696 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2698 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2698 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3046 ( .LO ( optlc_net_2697 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2699 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2699 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3047 ( .LO ( optlc_net_2698 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2700 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2700 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3048 ( .LO ( optlc_net_2699 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2701 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2701 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3049 ( .LO ( optlc_net_2700 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2702 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2702 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3050 ( .LO ( optlc_net_2701 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2703 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2703 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3051 ( .LO ( optlc_net_2702 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2704 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2704 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3052 ( .LO ( optlc_net_2703 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2705 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2705 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3053 ( .LO ( optlc_net_2704 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2706 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2706 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3054 ( .LO ( optlc_net_2705 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2707 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2707 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3055 ( .LO ( optlc_net_2706 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2708 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2708 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3056 ( .LO ( optlc_net_2707 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2709 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2709 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3057 ( .LO ( optlc_net_2708 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2710 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2710 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3058 ( .LO ( optlc_net_2709 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2711 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2711 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3059 ( .LO ( optlc_net_2710 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2712 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2712 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3060 ( .LO ( optlc_net_2711 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2713 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2713 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3061 ( .LO ( optlc_net_2712 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2714 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2714 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3062 ( .LO ( optlc_net_2713 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2715 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2715 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3063 ( .LO ( optlc_net_2714 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2716 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2716 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3064 ( .LO ( optlc_net_2715 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2717 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2717 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3065 ( .LO ( optlc_net_2716 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2718 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2718 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3066 ( .LO ( optlc_net_2717 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2719 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2719 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3067 ( .LO ( optlc_net_2718 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2720 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2720 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3068 ( .LO ( optlc_net_2719 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2721 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2721 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3069 ( .LO ( optlc_net_2720 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2722 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2722 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3070 ( .LO ( optlc_net_2721 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2723 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2723 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3071 ( .LO ( optlc_net_2722 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2724 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2724 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3073 ( .LO ( optlc_net_2723 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2725 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2725 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3074 ( .LO ( optlc_net_2724 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2726 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2726 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3075 ( .LO ( optlc_net_2725 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2727 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2727 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3076 ( .LO ( optlc_net_2726 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2728 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2728 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3077 ( .LO ( optlc_net_2727 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2729 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2729 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3079 ( .LO ( optlc_net_2728 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2730 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2730 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3080 ( .LO ( optlc_net_2729 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2731 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2731 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3081 ( .LO ( optlc_net_2730 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2732 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2732 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3082 ( .LO ( optlc_net_2731 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2733 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2733 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3083 ( .LO ( optlc_net_2732 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2734 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2734 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3084 ( .LO ( optlc_net_2733 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2735 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2735 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3085 ( .LO ( optlc_net_2734 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2736 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2736 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3086 ( .LO ( optlc_net_2735 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2737 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2737 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3087 ( .LO ( optlc_net_2736 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2738 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2738 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3088 ( .LO ( optlc_net_2737 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2739 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2739 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3089 ( .LO ( optlc_net_2738 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2740 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2740 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3090 ( .LO ( optlc_net_2739 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2741 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2741 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3091 ( .LO ( optlc_net_2740 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2742 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2742 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3092 ( .LO ( optlc_net_2741 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2743 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2743 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3093 ( .LO ( optlc_net_2742 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2744 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2744 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3094 ( .LO ( optlc_net_2743 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2745 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2745 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3095 ( .LO ( optlc_net_2744 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2746 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2746 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3096 ( .LO ( optlc_net_2745 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2747 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2747 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3097 ( .LO ( optlc_net_2746 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2748 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2748 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3098 ( .LO ( optlc_net_2747 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2749 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2749 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3099 ( .LO ( optlc_net_2748 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2750 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2750 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3100 ( .LO ( optlc_net_2749 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2751 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2751 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3101 ( .LO ( optlc_net_2750 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2752 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2752 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3102 ( .LO ( optlc_net_2751 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2753 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2753 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3103 ( .LO ( optlc_net_2752 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2754 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2754 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3104 ( .LO ( optlc_net_2753 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2755 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2755 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3105 ( .LO ( optlc_net_2754 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2756 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2756 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3106 ( .LO ( optlc_net_2755 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2757 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2757 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3107 ( .LO ( optlc_net_2756 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2758 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2758 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3108 ( .LO ( optlc_net_2757 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2759 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2759 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3109 ( .LO ( optlc_net_2758 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2760 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2760 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3110 ( .LO ( optlc_net_2759 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2761 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2761 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3111 ( .LO ( optlc_net_2760 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2762 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2762 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3112 ( .LO ( optlc_net_2761 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2763 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2763 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3113 ( .LO ( optlc_net_2762 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2764 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2764 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3114 ( .LO ( optlc_net_2763 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2765 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2765 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3115 ( .LO ( optlc_net_2764 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2766 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2766 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3116 ( .LO ( optlc_net_2765 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2767 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2767 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3117 ( .LO ( optlc_net_2766 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2768 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2768 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3118 ( .LO ( optlc_net_2767 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2769 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2769 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3119 ( .LO ( optlc_net_2768 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2770 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2770 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3120 ( .LO ( optlc_net_2769 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2771 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2771 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3121 ( .LO ( optlc_net_2770 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2772 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2772 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3122 ( .LO ( optlc_net_2771 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2773 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2773 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3123 ( .LO ( optlc_net_2772 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2774 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2774 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3124 ( .LO ( optlc_net_2773 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2775 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2775 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3125 ( .LO ( optlc_net_2774 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2776 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2776 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3126 ( .LO ( optlc_net_2775 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2777 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2777 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3127 ( .LO ( optlc_net_2776 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2778 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2778 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3128 ( .LO ( optlc_net_2777 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2779 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2779 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3129 ( .LO ( optlc_net_2778 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2780 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2780 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3130 ( .LO ( optlc_net_2779 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2781 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2781 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3131 ( .LO ( optlc_net_2780 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2782 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2782 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3132 ( .LO ( optlc_net_2781 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2783 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2783 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3133 ( .LO ( optlc_net_2782 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2784 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2784 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3134 ( .LO ( optlc_net_2783 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2785 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2785 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3135 ( .LO ( optlc_net_2784 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2786 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2786 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3136 ( .LO ( optlc_net_2785 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2787 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2787 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3137 ( .LO ( optlc_net_2786 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2788 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2788 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3138 ( .LO ( optlc_net_2787 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2789 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2789 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3139 ( .LO ( optlc_net_2788 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2790 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2790 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3140 ( .LO ( optlc_net_2789 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2791 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2791 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3141 ( .LO ( optlc_net_2790 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2792 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2792 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3142 ( .LO ( optlc_net_2791 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2793 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2793 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3143 ( .LO ( optlc_net_2792 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2794 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2794 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3144 ( .LO ( optlc_net_2793 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2795 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2795 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3145 ( .LO ( optlc_net_2794 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2796 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2796 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3146 ( .LO ( optlc_net_2795 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2797 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2797 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3147 ( .LO ( optlc_net_2796 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2798 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2798 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3148 ( .LO ( optlc_net_2797 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2799 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2799 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3149 ( .LO ( optlc_net_2798 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2800 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2800 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3150 ( .LO ( optlc_net_2799 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2801 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2801 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3151 ( .LO ( optlc_net_2800 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2802 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2802 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3152 ( .LO ( optlc_net_2801 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2803 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2803 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3153 ( .LO ( optlc_net_2802 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2804 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2804 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3154 ( .LO ( optlc_net_2803 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2805 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2805 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3156 ( .LO ( optlc_net_2804 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2806 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2806 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3157 ( .LO ( optlc_net_2805 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2807 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2807 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3158 ( .LO ( optlc_net_2806 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2808 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2808 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3159 ( .LO ( optlc_net_2807 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2809 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2809 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3160 ( .LO ( optlc_net_2808 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2810 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2810 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3161 ( .LO ( optlc_net_2809 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2811 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2811 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3162 ( .LO ( optlc_net_2810 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2812 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2812 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3163 ( .LO ( optlc_net_2811 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2813 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2813 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3164 ( .LO ( optlc_net_2812 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2814 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2814 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3166 ( .LO ( optlc_net_2813 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2815 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2815 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3167 ( .LO ( optlc_net_2814 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2816 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2816 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3168 ( .LO ( optlc_net_2815 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2817 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2817 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3170 ( .LO ( optlc_net_2816 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2818 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2818 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3171 ( .LO ( optlc_net_2817 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2819 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2819 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3172 ( .LO ( optlc_net_2818 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2820 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2820 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3173 ( .LO ( optlc_net_2819 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2821 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2821 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3174 ( .LO ( optlc_net_2820 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2822 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2822 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3175 ( .LO ( optlc_net_2821 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2823 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2823 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3176 ( .LO ( optlc_net_2822 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2824 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2824 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3177 ( .LO ( optlc_net_2823 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2825 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2825 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3178 ( .LO ( optlc_net_2824 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2826 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2826 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3179 ( .LO ( optlc_net_2825 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2827 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2827 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3180 ( .LO ( optlc_net_2826 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2828 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2828 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3181 ( .LO ( optlc_net_2827 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2829 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2829 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3182 ( .LO ( optlc_net_2828 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2830 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2830 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3183 ( .LO ( optlc_net_2829 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2831 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2831 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3184 ( .LO ( optlc_net_2830 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2832 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2832 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3185 ( .LO ( optlc_net_2831 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2833 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2833 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3186 ( .LO ( optlc_net_2832 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2834 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2834 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3187 ( .LO ( optlc_net_2833 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2835 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2835 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3188 ( .LO ( optlc_net_2834 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2836 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2836 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3190 ( .LO ( optlc_net_2835 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2837 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2837 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3191 ( .LO ( optlc_net_2836 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2838 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2838 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3192 ( .LO ( optlc_net_2837 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2839 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2839 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3193 ( .LO ( optlc_net_2838 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2840 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2840 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3194 ( .LO ( optlc_net_2839 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2841 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2841 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3195 ( .LO ( optlc_net_2840 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2842 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2842 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3196 ( .LO ( optlc_net_2841 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2843 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2843 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3197 ( .LO ( optlc_net_2842 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2844 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2844 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3198 ( .LO ( optlc_net_2843 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2845 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2845 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3199 ( .LO ( optlc_net_2844 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2846 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2846 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3200 ( .LO ( optlc_net_2845 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2847 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2847 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3201 ( .LO ( optlc_net_2846 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2848 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2848 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3202 ( .LO ( optlc_net_2847 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2849 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2849 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3204 ( .LO ( optlc_net_2848 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2850 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2850 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3205 ( .LO ( optlc_net_2849 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2851 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2851 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3206 ( .LO ( optlc_net_2850 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2852 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2852 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3207 ( .LO ( optlc_net_2851 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2853 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2853 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3208 ( .LO ( optlc_net_2852 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2854 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2854 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3209 ( .LO ( optlc_net_2853 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2855 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2855 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3210 ( .LO ( optlc_net_2854 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2856 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2856 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3211 ( .LO ( optlc_net_2855 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2857 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2857 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3212 ( .LO ( optlc_net_2856 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2858 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2858 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3213 ( .LO ( optlc_net_2857 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2859 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2859 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3214 ( .LO ( optlc_net_2858 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2860 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2860 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3215 ( .LO ( optlc_net_2859 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2861 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2861 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3216 ( .LO ( optlc_net_2860 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2862 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2862 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3217 ( .LO ( optlc_net_2861 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2863 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2863 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3218 ( .LO ( optlc_net_2862 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2864 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2864 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3219 ( .LO ( optlc_net_2863 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2865 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2865 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3220 ( .LO ( optlc_net_2864 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2866 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2866 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3221 ( .LO ( optlc_net_2865 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2867 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2867 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3222 ( .LO ( optlc_net_2866 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2868 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2868 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3223 ( .LO ( optlc_net_2867 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2869 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2869 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3224 ( .LO ( optlc_net_2868 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2870 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2870 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3225 ( .LO ( optlc_net_2869 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2871 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2871 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3226 ( .LO ( optlc_net_2870 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2872 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2872 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3227 ( .LO ( optlc_net_2871 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2873 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2873 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3228 ( .LO ( optlc_net_2872 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2874 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2874 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3229 ( .LO ( optlc_net_2873 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2875 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2875 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3230 ( .LO ( optlc_net_2874 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2876 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2876 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3231 ( .LO ( optlc_net_2875 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2877 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2877 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3232 ( .LO ( optlc_net_2876 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2878 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2878 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3233 ( .LO ( optlc_net_2877 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2879 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2879 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3234 ( .LO ( optlc_net_2878 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2880 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2880 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3235 ( .LO ( optlc_net_2879 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2881 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2881 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3236 ( .LO ( optlc_net_2880 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2882 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2882 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3237 ( .LO ( optlc_net_2881 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2883 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2883 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3238 ( .LO ( optlc_net_2882 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2884 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2884 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3240 ( .LO ( optlc_net_2883 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2885 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2885 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3241 ( .LO ( optlc_net_2884 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2886 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2886 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3242 ( .LO ( optlc_net_2885 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2887 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2887 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3243 ( .LO ( optlc_net_2886 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2888 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2888 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3244 ( .LO ( optlc_net_2887 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2889 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2889 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3245 ( .LO ( optlc_net_2888 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2890 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2890 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3246 ( .LO ( optlc_net_2889 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2891 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2891 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3247 ( .LO ( optlc_net_2890 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2892 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2892 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3248 ( .LO ( optlc_net_2891 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2893 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2893 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3249 ( .LO ( optlc_net_2892 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2894 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2894 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3250 ( .LO ( optlc_net_2893 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2895 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2895 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3251 ( .LO ( optlc_net_2894 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2896 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2896 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3252 ( .LO ( optlc_net_2895 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2897 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2897 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3253 ( .LO ( optlc_net_2896 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2898 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2898 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3254 ( .LO ( optlc_net_2897 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2899 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2899 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3255 ( .LO ( optlc_net_2898 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2900 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2900 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3256 ( .LO ( optlc_net_2899 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2901 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2901 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3257 ( .LO ( optlc_net_2900 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2902 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2902 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3258 ( .LO ( optlc_net_2901 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2903 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2903 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3259 ( .LO ( optlc_net_2902 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2904 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2904 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3260 ( .LO ( optlc_net_2903 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2905 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2905 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3261 ( .LO ( optlc_net_2904 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2906 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2906 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3262 ( .LO ( optlc_net_2905 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2907 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2907 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3263 ( .LO ( optlc_net_2906 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2908 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2908 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3264 ( .LO ( optlc_net_2907 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2909 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2909 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3265 ( .LO ( optlc_net_2908 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2910 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2910 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3266 ( .LO ( optlc_net_2909 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2911 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2911 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3267 ( .LO ( optlc_net_2910 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2912 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2912 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3268 ( .LO ( optlc_net_2911 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2913 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2913 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3269 ( .LO ( optlc_net_2912 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2914 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2914 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3270 ( .LO ( optlc_net_2913 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2915 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2915 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3271 ( .LO ( optlc_net_2914 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2916 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2916 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3272 ( .LO ( optlc_net_2915 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2917 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2917 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3273 ( .LO ( optlc_net_2916 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2918 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2918 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3274 ( .LO ( optlc_net_2917 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2919 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2919 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3275 ( .LO ( optlc_net_2918 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2920 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2920 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3276 ( .LO ( optlc_net_2919 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2921 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2921 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3277 ( .LO ( optlc_net_2920 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2922 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2922 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3278 ( .LO ( optlc_net_2921 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2923 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2923 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3279 ( .LO ( optlc_net_2922 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2924 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2924 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3280 ( .LO ( optlc_net_2923 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2925 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2925 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3281 ( .LO ( optlc_net_2924 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2926 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2926 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3282 ( .LO ( optlc_net_2925 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2927 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2927 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3283 ( .LO ( optlc_net_2926 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2928 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2928 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3284 ( .LO ( optlc_net_2927 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2929 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2929 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3285 ( .LO ( optlc_net_2928 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2930 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2930 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3286 ( .LO ( optlc_net_2929 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2931 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2931 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3287 ( .LO ( optlc_net_2930 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2932 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2932 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3288 ( .LO ( optlc_net_2931 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2933 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2933 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3289 ( .LO ( optlc_net_2932 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2934 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2934 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3290 ( .LO ( optlc_net_2933 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2935 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2935 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3291 ( .LO ( optlc_net_2934 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2936 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2936 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3292 ( .LO ( optlc_net_2935 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2937 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2937 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3293 ( .LO ( optlc_net_2936 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2938 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2938 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3294 ( .LO ( optlc_net_2937 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2939 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2939 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3295 ( .LO ( optlc_net_2938 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2940 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2940 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3296 ( .LO ( optlc_net_2939 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2941 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2941 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3297 ( .LO ( optlc_net_2940 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2942 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2942 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3298 ( .LO ( optlc_net_2941 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2943 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2943 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3299 ( .LO ( optlc_net_2942 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2944 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2944 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3300 ( .LO ( optlc_net_2943 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2945 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2945 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3301 ( .LO ( optlc_net_2944 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2946 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2946 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3302 ( .LO ( optlc_net_2945 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2947 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2947 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3303 ( .LO ( optlc_net_2946 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2948 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2948 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3304 ( .LO ( optlc_net_2947 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2949 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2949 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3305 ( .LO ( optlc_net_2948 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2950 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2950 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3306 ( .LO ( optlc_net_2949 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2951 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2951 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3307 ( .LO ( optlc_net_2950 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2952 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2952 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3308 ( .LO ( optlc_net_2951 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2953 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2953 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3309 ( .LO ( optlc_net_2952 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2954 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2954 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3310 ( .LO ( optlc_net_2953 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2955 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2955 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3311 ( .LO ( optlc_net_2954 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2956 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2956 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3312 ( .LO ( optlc_net_2955 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2957 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2957 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3313 ( .LO ( optlc_net_2956 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2958 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2958 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3314 ( .LO ( optlc_net_2957 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2959 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2959 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3315 ( .LO ( optlc_net_2958 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2960 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2960 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3316 ( .LO ( optlc_net_2959 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2961 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2961 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3317 ( .LO ( optlc_net_2960 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2962 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2962 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3318 ( .LO ( optlc_net_2961 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2963 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2963 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3319 ( .LO ( optlc_net_2962 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2964 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2964 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3320 ( .LO ( optlc_net_2963 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2965 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2965 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3321 ( .LO ( optlc_net_2964 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2966 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2966 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3322 ( .LO ( optlc_net_2965 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2967 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2967 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3323 ( .LO ( optlc_net_2966 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2968 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2968 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3324 ( .LO ( optlc_net_2967 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2969 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2969 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3325 ( .LO ( optlc_net_2968 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2970 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2970 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3326 ( .LO ( optlc_net_2969 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2971 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2971 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3327 ( .LO ( optlc_net_2970 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2972 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2972 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3328 ( .LO ( optlc_net_2971 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2973 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2973 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3329 ( .LO ( optlc_net_2972 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2974 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2974 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3330 ( .LO ( optlc_net_2973 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2975 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2975 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3331 ( .LO ( optlc_net_2974 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2976 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2976 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3332 ( .LO ( optlc_net_2975 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2977 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2977 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3333 ( .LO ( optlc_net_2976 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2978 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2978 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3334 ( .LO ( optlc_net_2977 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2979 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2979 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3335 ( .LO ( optlc_net_2978 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2980 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2980 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3336 ( .LO ( optlc_net_2979 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2981 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2981 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3337 ( .LO ( optlc_net_2980 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2982 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2982 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3338 ( .LO ( optlc_net_2981 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2983 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2983 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3339 ( .LO ( optlc_net_2982 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2984 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2984 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3340 ( .LO ( optlc_net_2983 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2985 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2985 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3341 ( .LO ( optlc_net_2984 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2986 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2986 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3342 ( .LO ( optlc_net_2985 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2987 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2987 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3343 ( .LO ( optlc_net_2986 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2988 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2988 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3344 ( .LO ( optlc_net_2987 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2989 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2989 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3345 ( .LO ( optlc_net_2988 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2990 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2990 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3346 ( .LO ( optlc_net_2989 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2991 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2991 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3347 ( .LO ( optlc_net_2990 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2992 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2992 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3348 ( .LO ( optlc_net_2991 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2993 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2993 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3349 ( .LO ( optlc_net_2992 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2994 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2994 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3350 ( .LO ( optlc_net_2993 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2995 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2995 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3351 ( .LO ( optlc_net_2994 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2996 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2996 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3352 ( .LO ( optlc_net_2995 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2997 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2997 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3353 ( .LO ( optlc_net_2996 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2998 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2998 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3354 ( .LO ( optlc_net_2997 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_2999 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_2999 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3355 ( .LO ( optlc_net_2998 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3000 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3000 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3356 ( .LO ( optlc_net_2999 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3001 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3001 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3357 ( .LO ( optlc_net_3000 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3002 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3002 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3358 ( .LO ( optlc_net_3001 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3003 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3003 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3359 ( .LO ( optlc_net_3002 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3004 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3004 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3360 ( .LO ( optlc_net_3003 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3005 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3005 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3361 ( .LO ( optlc_net_3004 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3006 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3006 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3362 ( .LO ( optlc_net_3005 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3007 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3007 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3363 ( .LO ( optlc_net_3006 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3008 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3008 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3364 ( .LO ( optlc_net_3007 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3009 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3009 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3365 ( .LO ( optlc_net_3008 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3010 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3010 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3366 ( .LO ( optlc_net_3009 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3011 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3011 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3367 ( .LO ( optlc_net_3010 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3012 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3012 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3368 ( .LO ( optlc_net_3011 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3013 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3013 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3369 ( .LO ( optlc_net_3012 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3014 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3014 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3370 ( .LO ( optlc_net_3013 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3015 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3015 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3371 ( .LO ( optlc_net_3014 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3016 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3016 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3372 ( .LO ( optlc_net_3015 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3017 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3017 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3373 ( .LO ( optlc_net_3016 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3018 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3018 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3374 ( .LO ( optlc_net_3017 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3019 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3019 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3375 ( .LO ( optlc_net_3018 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3020 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3020 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3376 ( .LO ( optlc_net_3019 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3021 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3021 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3377 ( .LO ( optlc_net_3020 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3022 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3022 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3378 ( .LO ( optlc_net_3021 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3023 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3023 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3379 ( .LO ( optlc_net_3022 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3024 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3024 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3380 ( .LO ( optlc_net_3023 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3025 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3025 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3381 ( .LO ( optlc_net_3024 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3026 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3026 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3382 ( .LO ( optlc_net_3025 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3027 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3027 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3383 ( .LO ( optlc_net_3026 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3028 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3028 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3384 ( .LO ( optlc_net_3027 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3029 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3029 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3385 ( .LO ( optlc_net_3028 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3030 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3030 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3386 ( .LO ( optlc_net_3029 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3031 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3031 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3387 ( .LO ( optlc_net_3030 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3032 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3032 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3388 ( .LO ( optlc_net_3031 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3033 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3033 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3389 ( .LO ( optlc_net_3032 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3034 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3034 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3390 ( .LO ( optlc_net_3033 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3035 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3035 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3391 ( .LO ( optlc_net_3034 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3036 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3036 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3392 ( .LO ( optlc_net_3035 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3037 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3037 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3393 ( .LO ( optlc_net_3036 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3038 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3038 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3394 ( .LO ( optlc_net_3037 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3039 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3039 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3395 ( .LO ( optlc_net_3038 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3040 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3040 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3396 ( .LO ( optlc_net_3039 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3041 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3041 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3397 ( .LO ( optlc_net_3040 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3042 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3042 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3398 ( .LO ( optlc_net_3041 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3043 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3043 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3399 ( .LO ( optlc_net_3042 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3044 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3044 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3400 ( .LO ( optlc_net_3043 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3045 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3045 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3401 ( .LO ( optlc_net_3044 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3046 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3046 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3402 ( .LO ( optlc_net_3045 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3047 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3047 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3403 ( .LO ( optlc_net_3046 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3048 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3048 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3404 ( .LO ( optlc_net_3047 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3049 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3049 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3405 ( .LO ( optlc_net_3048 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3050 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3050 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3406 ( .LO ( optlc_net_3049 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3051 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3051 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3407 ( .LO ( optlc_net_3050 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3052 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3052 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3408 ( .LO ( optlc_net_3051 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3053 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3053 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3409 ( .LO ( optlc_net_3052 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3054 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3054 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3410 ( .LO ( optlc_net_3053 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3055 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3055 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3411 ( .LO ( optlc_net_3054 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3056 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3056 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3412 ( .LO ( optlc_net_3055 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3057 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3057 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3413 ( .LO ( optlc_net_3056 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3058 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3058 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3414 ( .LO ( optlc_net_3057 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3059 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3059 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3415 ( .LO ( optlc_net_3058 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3060 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3060 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3416 ( .LO ( optlc_net_3059 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3061 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3061 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3417 ( .LO ( optlc_net_3060 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3062 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3062 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3418 ( .LO ( optlc_net_3061 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3063 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3063 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3419 ( .LO ( optlc_net_3062 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3064 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3064 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3420 ( .LO ( optlc_net_3063 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3065 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3065 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3421 ( .LO ( optlc_net_3064 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3066 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3066 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3422 ( .LO ( optlc_net_3065 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3067 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3067 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3423 ( .LO ( optlc_net_3066 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3068 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3068 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3424 ( .LO ( optlc_net_3067 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3069 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3069 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3425 ( .LO ( optlc_net_3068 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3070 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3070 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3426 ( .LO ( optlc_net_3069 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3071 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3071 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3427 ( .LO ( optlc_net_3070 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3072 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3072 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3428 ( .LO ( optlc_net_3071 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3073 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3073 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3429 ( .LO ( optlc_net_3072 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3074 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3074 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3430 ( .LO ( optlc_net_3073 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3075 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3075 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3431 ( .LO ( optlc_net_3074 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3076 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3076 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3432 ( .LO ( optlc_net_3075 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3077 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3077 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3433 ( .LO ( optlc_net_3076 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3078 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3078 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3434 ( .LO ( optlc_net_3077 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3079 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3079 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3435 ( .LO ( optlc_net_3078 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3080 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3080 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3436 ( .LO ( optlc_net_3079 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3081 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3081 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3437 ( .LO ( optlc_net_3080 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3082 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3082 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3438 ( .LO ( optlc_net_3081 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3083 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3083 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3439 ( .LO ( optlc_net_3082 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3084 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3084 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3440 ( .LO ( optlc_net_3083 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3085 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3085 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3441 ( .LO ( optlc_net_3084 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3086 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3086 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3442 ( .LO ( optlc_net_3085 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3087 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3087 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3443 ( .LO ( optlc_net_3086 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3088 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3088 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3444 ( .LO ( optlc_net_3087 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3089 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3089 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3445 ( .LO ( optlc_net_3088 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3090 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3090 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3446 ( .LO ( optlc_net_3089 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3091 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3091 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3447 ( .LO ( optlc_net_3090 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3092 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3092 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3448 ( .LO ( optlc_net_3091 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3093 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3093 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3449 ( .LO ( optlc_net_3092 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3094 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3094 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3450 ( .LO ( optlc_net_3093 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3095 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3095 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3451 ( .LO ( optlc_net_3094 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3096 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3096 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3452 ( .LO ( optlc_net_3095 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3097 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3097 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3453 ( .LO ( optlc_net_3096 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3098 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3098 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3454 ( .LO ( optlc_net_3097 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3099 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3099 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3455 ( .LO ( optlc_net_3098 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3100 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3456 ( .LO ( optlc_net_3099 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3101 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3457 ( .LO ( optlc_net_3100 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3102 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3458 ( .LO ( optlc_net_3101 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3103 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3459 ( .LO ( optlc_net_3102 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3104 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3460 ( .LO ( optlc_net_3103 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3105 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3461 ( .LO ( optlc_net_3104 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3106 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3462 ( .LO ( optlc_net_3105 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3107 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3463 ( .LO ( optlc_net_3106 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3108 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3464 ( .LO ( optlc_net_3107 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3109 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3465 ( .LO ( optlc_net_3108 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3110 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3466 ( .LO ( optlc_net_3109 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3111 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3467 ( .LO ( optlc_net_3110 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3112 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3468 ( .LO ( optlc_net_3111 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3113 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3469 ( .LO ( optlc_net_3112 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3114 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3470 ( .LO ( optlc_net_3113 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3115 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3471 ( .LO ( optlc_net_3114 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3116 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3472 ( .LO ( optlc_net_3115 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3117 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3473 ( .LO ( optlc_net_3116 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3118 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3474 ( .LO ( optlc_net_3117 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3119 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3475 ( .LO ( optlc_net_3118 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3120 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3476 ( .LO ( optlc_net_3119 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3121 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3477 ( .LO ( optlc_net_3120 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3122 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3478 ( .LO ( optlc_net_3121 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3123 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3479 ( .LO ( optlc_net_3122 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3124 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3480 ( .LO ( optlc_net_3123 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3125 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3481 ( .LO ( optlc_net_3124 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3126 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3482 ( .LO ( optlc_net_3125 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3127 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3483 ( .LO ( optlc_net_3126 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3128 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3484 ( .LO ( optlc_net_3127 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3129 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3485 ( .LO ( optlc_net_3128 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3130 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3486 ( .LO ( optlc_net_3129 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3131 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3487 ( .LO ( optlc_net_3130 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3132 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3488 ( .LO ( optlc_net_3131 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3133 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3489 ( .LO ( optlc_net_3132 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3134 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3490 ( .LO ( optlc_net_3133 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3135 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3491 ( .LO ( optlc_net_3134 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3136 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3492 ( .LO ( optlc_net_3135 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3137 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3493 ( .LO ( optlc_net_3136 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3138 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3494 ( .LO ( optlc_net_3137 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3139 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3495 ( .LO ( optlc_net_3138 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3140 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3496 ( .LO ( optlc_net_3139 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3141 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3497 ( .LO ( optlc_net_3140 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3142 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3498 ( .LO ( optlc_net_3141 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3143 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3499 ( .LO ( optlc_net_3142 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3144 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3500 ( .LO ( optlc_net_3143 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3145 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3501 ( .LO ( optlc_net_3144 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3146 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3502 ( .LO ( optlc_net_3145 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3147 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3503 ( .LO ( optlc_net_3146 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3148 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3504 ( .LO ( optlc_net_3147 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3149 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3505 ( .LO ( optlc_net_3148 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3150 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3506 ( .LO ( optlc_net_3149 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3151 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3507 ( .LO ( optlc_net_3150 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3152 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3509 ( .LO ( optlc_net_3151 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3153 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3510 ( .LO ( optlc_net_3152 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3154 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3511 ( .LO ( optlc_net_3153 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3155 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3512 ( .LO ( optlc_net_3154 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3156 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3513 ( .LO ( optlc_net_3155 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3157 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3514 ( .LO ( optlc_net_3156 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3158 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3515 ( .LO ( optlc_net_3157 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3159 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3516 ( .LO ( optlc_net_3158 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3160 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3517 ( .LO ( optlc_net_3159 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3161 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3518 ( .LO ( optlc_net_3160 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3162 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3519 ( .LO ( optlc_net_3161 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3163 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3520 ( .LO ( optlc_net_3162 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3164 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3521 ( .LO ( optlc_net_3163 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3165 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3522 ( .LO ( optlc_net_3164 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3166 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3523 ( .LO ( optlc_net_3165 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3167 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3524 ( .LO ( optlc_net_3166 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3168 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3525 ( .LO ( optlc_net_3167 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3169 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3526 ( .LO ( optlc_net_3168 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3170 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3527 ( .LO ( optlc_net_3169 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3171 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3528 ( .LO ( optlc_net_3170 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3172 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3529 ( .LO ( optlc_net_3171 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3173 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3530 ( .LO ( optlc_net_3172 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3174 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3531 ( .LO ( optlc_net_3173 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3175 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3532 ( .LO ( optlc_net_3174 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3176 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3533 ( .LO ( optlc_net_3175 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3177 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3534 ( .LO ( optlc_net_3176 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3178 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3535 ( .LO ( optlc_net_3177 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3179 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3536 ( .LO ( optlc_net_3178 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3180 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3537 ( .LO ( optlc_net_3179 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3181 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3538 ( .LO ( optlc_net_3180 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3182 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3539 ( .LO ( optlc_net_3181 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3183 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3540 ( .LO ( optlc_net_3182 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3184 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3541 ( .LO ( optlc_net_3183 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3185 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3542 ( .LO ( optlc_net_3184 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3186 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3543 ( .LO ( optlc_net_3185 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3187 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3544 ( .LO ( optlc_net_3186 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3188 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3545 ( .LO ( optlc_net_3187 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3189 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3546 ( .LO ( optlc_net_3188 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3190 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3547 ( .LO ( optlc_net_3189 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3191 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3548 ( .LO ( optlc_net_3190 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3192 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3549 ( .LO ( optlc_net_3191 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3193 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3550 ( .LO ( optlc_net_3192 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3194 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3551 ( .LO ( optlc_net_3193 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3195 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3552 ( .LO ( optlc_net_3194 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3196 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3553 ( .LO ( optlc_net_3195 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3197 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3554 ( .LO ( optlc_net_3196 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3198 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3555 ( .LO ( optlc_net_3197 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3199 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3556 ( .LO ( optlc_net_3198 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3200 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3557 ( .LO ( optlc_net_3199 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3201 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3558 ( .LO ( optlc_net_3200 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3202 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3559 ( .LO ( optlc_net_3201 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3203 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3560 ( .LO ( optlc_net_3202 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3204 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3561 ( .LO ( optlc_net_3203 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3205 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3562 ( .LO ( optlc_net_3204 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3206 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3563 ( .LO ( optlc_net_3205 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3207 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3564 ( .LO ( optlc_net_3206 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3208 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3565 ( .LO ( optlc_net_3207 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3209 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3566 ( .LO ( optlc_net_3208 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3210 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3567 ( .LO ( optlc_net_3209 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3211 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3568 ( .LO ( optlc_net_3210 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3212 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3569 ( .LO ( optlc_net_3211 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3213 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3570 ( .LO ( optlc_net_3212 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3214 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3571 ( .LO ( optlc_net_3213 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3215 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3572 ( .LO ( optlc_net_3214 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3216 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3573 ( .LO ( optlc_net_3215 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3217 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3574 ( .LO ( optlc_net_3216 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3218 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3575 ( .LO ( optlc_net_3217 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3219 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3576 ( .LO ( optlc_net_3218 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3220 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3577 ( .LO ( optlc_net_3219 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3221 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3578 ( .LO ( optlc_net_3220 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3222 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3579 ( .LO ( optlc_net_3221 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3223 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3580 ( .LO ( optlc_net_3222 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3224 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3581 ( .LO ( optlc_net_3223 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3225 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3582 ( .LO ( optlc_net_3224 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3226 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3583 ( .LO ( optlc_net_3225 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3227 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3584 ( .LO ( optlc_net_3226 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3228 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3585 ( .LO ( optlc_net_3227 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3229 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3586 ( .LO ( optlc_net_3228 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3230 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3587 ( .LO ( optlc_net_3229 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3231 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3588 ( .LO ( optlc_net_3230 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3232 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3589 ( .LO ( optlc_net_3231 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3233 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3233 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3590 ( .LO ( optlc_net_3232 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3234 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3234 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3591 ( .LO ( optlc_net_3233 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3235 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3235 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3592 ( .LO ( optlc_net_3234 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3236 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3236 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3593 ( .LO ( optlc_net_3235 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3237 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3237 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3594 ( .LO ( optlc_net_3236 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3238 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3238 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3595 ( .LO ( optlc_net_3237 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3239 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3239 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3596 ( .LO ( optlc_net_3238 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3240 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3240 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3597 ( .LO ( optlc_net_3239 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3241 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3241 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3598 ( .LO ( optlc_net_3240 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3242 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3242 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3599 ( .LO ( optlc_net_3241 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3243 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3243 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3600 ( .LO ( optlc_net_3242 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3244 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3244 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3601 ( .LO ( optlc_net_3243 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3245 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3245 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3602 ( .LO ( optlc_net_3244 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3246 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3246 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3603 ( .LO ( optlc_net_3245 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3247 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3247 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3604 ( .LO ( optlc_net_3246 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3248 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3248 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3605 ( .LO ( optlc_net_3247 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3249 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3249 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3606 ( .LO ( optlc_net_3248 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3250 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3250 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3607 ( .LO ( optlc_net_3249 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3251 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3251 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3608 ( .LO ( optlc_net_3250 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3252 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3252 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3609 ( .LO ( optlc_net_3251 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3253 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3253 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3610 ( .LO ( optlc_net_3252 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3254 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3254 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3611 ( .LO ( optlc_net_3253 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3255 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3255 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3612 ( .LO ( optlc_net_3254 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3256 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3256 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3613 ( .LO ( optlc_net_3255 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3257 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3257 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3614 ( .LO ( optlc_net_3256 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3258 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3258 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3615 ( .LO ( optlc_net_3257 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3259 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3259 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3616 ( .LO ( optlc_net_3258 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3260 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3260 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3617 ( .LO ( optlc_net_3259 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3261 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3261 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3618 ( .LO ( optlc_net_3260 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3262 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3262 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3619 ( .LO ( optlc_net_3261 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3263 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3263 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3620 ( .LO ( optlc_net_3262 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3264 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3264 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3621 ( .LO ( optlc_net_3263 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3265 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3265 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3622 ( .LO ( optlc_net_3264 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3266 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3266 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3623 ( .LO ( optlc_net_3265 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3267 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3267 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3624 ( .LO ( optlc_net_3266 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3268 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3268 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3625 ( .LO ( optlc_net_3267 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3269 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3269 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3626 ( .LO ( optlc_net_3268 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3270 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3270 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3627 ( .LO ( optlc_net_3269 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3271 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3271 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3628 ( .LO ( optlc_net_3270 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3272 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3272 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3629 ( .LO ( optlc_net_3271 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3273 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3273 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3630 ( .LO ( optlc_net_3272 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3274 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3274 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3631 ( .LO ( optlc_net_3273 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3275 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3275 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3632 ( .LO ( optlc_net_3274 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3276 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3276 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3633 ( .LO ( optlc_net_3275 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3277 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3277 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3634 ( .LO ( optlc_net_3276 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3278 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3278 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3635 ( .LO ( optlc_net_3277 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3279 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3279 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3636 ( .LO ( optlc_net_3278 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3280 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3280 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3637 ( .LO ( optlc_net_3279 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3281 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3281 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3638 ( .LO ( optlc_net_3280 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3282 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3282 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3639 ( .LO ( optlc_net_3281 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3283 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3283 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3640 ( .LO ( optlc_net_3282 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3284 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3284 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3641 ( .LO ( optlc_net_3283 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3285 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3285 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3642 ( .LO ( optlc_net_3284 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3286 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3286 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3643 ( .LO ( optlc_net_3285 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3287 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3287 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3644 ( .LO ( optlc_net_3286 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3288 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3288 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3645 ( .LO ( optlc_net_3287 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3289 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3289 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3646 ( .LO ( optlc_net_3288 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3290 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3290 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3647 ( .LO ( optlc_net_3289 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3291 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3291 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3648 ( .LO ( optlc_net_3290 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3292 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3292 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3649 ( .LO ( optlc_net_3291 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3293 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3293 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3650 ( .LO ( optlc_net_3292 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3294 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3294 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3651 ( .LO ( optlc_net_3293 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3295 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3295 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3652 ( .LO ( optlc_net_3294 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3296 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3296 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3653 ( .LO ( optlc_net_3295 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3297 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3297 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3654 ( .LO ( optlc_net_3296 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3298 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3298 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3655 ( .LO ( optlc_net_3297 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3299 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3299 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3656 ( .LO ( optlc_net_3298 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3300 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3300 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3657 ( .LO ( optlc_net_3299 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3301 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3301 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3658 ( .LO ( optlc_net_3300 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3302 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3302 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3659 ( .LO ( optlc_net_3301 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3303 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3303 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3660 ( .LO ( optlc_net_3302 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3304 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3304 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3661 ( .LO ( optlc_net_3303 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3305 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3305 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3662 ( .LO ( optlc_net_3304 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3306 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3306 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3663 ( .LO ( optlc_net_3305 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3307 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3307 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3664 ( .LO ( optlc_net_3306 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3308 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3308 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3665 ( .LO ( optlc_net_3307 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3309 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3309 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3666 ( .LO ( optlc_net_3308 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3310 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3310 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3667 ( .LO ( optlc_net_3309 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3311 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3311 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3668 ( .LO ( optlc_net_3310 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3312 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3312 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3669 ( .LO ( optlc_net_3311 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3313 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3313 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3670 ( .LO ( optlc_net_3312 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3314 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3314 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3671 ( .LO ( optlc_net_3313 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3315 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3315 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3672 ( .LO ( optlc_net_3314 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3316 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3316 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3673 ( .LO ( optlc_net_3315 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3317 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3317 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3674 ( .LO ( optlc_net_3316 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3318 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3318 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3675 ( .LO ( optlc_net_3317 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3319 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3319 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3676 ( .LO ( optlc_net_3318 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3320 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3320 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3677 ( .LO ( optlc_net_3319 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3321 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3321 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3678 ( .LO ( optlc_net_3320 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3322 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3322 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3679 ( .LO ( optlc_net_3321 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3323 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3323 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3680 ( .LO ( optlc_net_3322 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3324 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3324 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3681 ( .LO ( optlc_net_3323 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3325 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3325 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3682 ( .LO ( optlc_net_3324 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3326 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3326 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3683 ( .LO ( optlc_net_3325 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3327 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3327 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3684 ( .LO ( optlc_net_3326 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3328 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3328 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3685 ( .LO ( optlc_net_3327 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3329 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3329 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3686 ( .LO ( optlc_net_3328 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3330 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3330 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3687 ( .LO ( optlc_net_3329 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3331 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3331 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3688 ( .LO ( optlc_net_3330 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3332 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3332 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3689 ( .LO ( optlc_net_3331 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3333 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3333 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3690 ( .LO ( optlc_net_3332 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3334 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3334 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3691 ( .LO ( optlc_net_3333 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3335 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3335 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3692 ( .LO ( optlc_net_3334 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3336 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3336 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3693 ( .LO ( optlc_net_3335 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3337 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3337 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3694 ( .LO ( optlc_net_3336 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3338 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3338 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3695 ( .LO ( optlc_net_3337 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3339 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3339 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3696 ( .LO ( optlc_net_3338 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3340 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3340 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3697 ( .LO ( optlc_net_3339 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3341 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3341 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3698 ( .LO ( optlc_net_3340 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3342 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3342 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3699 ( .LO ( optlc_net_3341 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3343 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3343 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3700 ( .LO ( optlc_net_3342 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3344 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3344 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3701 ( .LO ( optlc_net_3343 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3345 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3345 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3702 ( .LO ( optlc_net_3344 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3346 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3346 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3703 ( .LO ( optlc_net_3345 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3347 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3347 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3704 ( .LO ( optlc_net_3346 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3348 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3348 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3705 ( .LO ( optlc_net_3347 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3349 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3349 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3706 ( .LO ( optlc_net_3348 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3350 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3350 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3707 ( .LO ( optlc_net_3349 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3351 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3351 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3708 ( .LO ( optlc_net_3350 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3352 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3352 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3709 ( .LO ( optlc_net_3351 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3353 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3353 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3710 ( .LO ( optlc_net_3352 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3354 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3354 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3711 ( .LO ( optlc_net_3353 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3355 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3355 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3712 ( .LO ( optlc_net_3354 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3356 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3356 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3713 ( .LO ( optlc_net_3355 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3357 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3357 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3714 ( .LO ( optlc_net_3356 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3358 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3358 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3715 ( .LO ( optlc_net_3357 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3359 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3359 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3716 ( .LO ( optlc_net_3358 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3360 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3360 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3717 ( .LO ( optlc_net_3359 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3361 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3361 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3718 ( .LO ( optlc_net_3360 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3362 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3362 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3719 ( .LO ( optlc_net_3361 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3363 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3363 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3720 ( .LO ( optlc_net_3362 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3364 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3364 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3721 ( .LO ( optlc_net_3363 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3365 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3365 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3722 ( .LO ( optlc_net_3364 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3366 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3366 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3723 ( .LO ( optlc_net_3365 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3367 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3367 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3724 ( .LO ( optlc_net_3366 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3368 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3368 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3725 ( .LO ( optlc_net_3367 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3369 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3369 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3726 ( .LO ( optlc_net_3368 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3370 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3370 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3727 ( .LO ( optlc_net_3369 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3371 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3371 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3728 ( .LO ( optlc_net_3370 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3372 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3372 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3729 ( .LO ( optlc_net_3371 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3373 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3373 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3730 ( .LO ( optlc_net_3372 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3374 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3374 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3731 ( .LO ( optlc_net_3373 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3375 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3375 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3732 ( .LO ( optlc_net_3374 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3376 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3376 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3733 ( .LO ( optlc_net_3375 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3377 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3377 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3734 ( .LO ( optlc_net_3376 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3378 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3378 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3735 ( .LO ( optlc_net_3377 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3379 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3379 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3736 ( .LO ( optlc_net_3378 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3380 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3380 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3737 ( .LO ( optlc_net_3379 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3381 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3381 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3738 ( .LO ( optlc_net_3380 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3382 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3382 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3739 ( .LO ( optlc_net_3381 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3383 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3383 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3740 ( .LO ( optlc_net_3382 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3384 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3384 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3741 ( .LO ( optlc_net_3383 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3385 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3385 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3742 ( .LO ( optlc_net_3384 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3386 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3386 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3743 ( .LO ( optlc_net_3385 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3387 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3387 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3744 ( .LO ( optlc_net_3386 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3388 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3388 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3745 ( .LO ( optlc_net_3387 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3389 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3389 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3746 ( .LO ( optlc_net_3388 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3390 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3390 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3747 ( .LO ( optlc_net_3389 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3391 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3391 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3748 ( .LO ( optlc_net_3390 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3392 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3392 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3749 ( .LO ( optlc_net_3391 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3393 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3393 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3750 ( .LO ( optlc_net_3392 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3394 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3394 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3751 ( .LO ( optlc_net_3393 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3395 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3395 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3752 ( .LO ( optlc_net_3394 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3396 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3396 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3753 ( .LO ( optlc_net_3395 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3397 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3397 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3754 ( .LO ( optlc_net_3396 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3398 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3398 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3755 ( .LO ( optlc_net_3397 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3399 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3399 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3756 ( .LO ( optlc_net_3398 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3400 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3400 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3757 ( .LO ( optlc_net_3399 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3401 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3401 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3758 ( .LO ( optlc_net_3400 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3402 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3402 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3759 ( .LO ( optlc_net_3401 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3403 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3403 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3760 ( .LO ( optlc_net_3402 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3404 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3404 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3761 ( .LO ( optlc_net_3403 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3405 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3405 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3762 ( .LO ( optlc_net_3404 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3406 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3406 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3763 ( .LO ( optlc_net_3405 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3407 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3407 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3764 ( .LO ( optlc_net_3406 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3408 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3408 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3765 ( .LO ( optlc_net_3407 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3409 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3409 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3766 ( .LO ( optlc_net_3408 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3410 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3410 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3767 ( .LO ( optlc_net_3409 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3411 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3411 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3768 ( .LO ( optlc_net_3410 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3412 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3412 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3769 ( .LO ( optlc_net_3411 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3413 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3413 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3770 ( .LO ( optlc_net_3412 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3414 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3414 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3771 ( .LO ( optlc_net_3413 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3415 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3415 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3772 ( .LO ( optlc_net_3414 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3416 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3416 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3773 ( .LO ( optlc_net_3415 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3417 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3417 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3774 ( .LO ( optlc_net_3416 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3418 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3418 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3775 ( .LO ( optlc_net_3417 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3419 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3419 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3776 ( .LO ( optlc_net_3418 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3420 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3420 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3777 ( .LO ( optlc_net_3419 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3421 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3421 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3778 ( .LO ( optlc_net_3420 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3422 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3422 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3779 ( .LO ( optlc_net_3421 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3423 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3423 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3780 ( .LO ( optlc_net_3422 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3424 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3424 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3781 ( .LO ( optlc_net_3423 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3425 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3425 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3782 ( .LO ( optlc_net_3424 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3426 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3426 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3783 ( .LO ( optlc_net_3425 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3427 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3427 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3784 ( .LO ( optlc_net_3426 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3428 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3428 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3785 ( .LO ( optlc_net_3427 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3429 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3429 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3786 ( .LO ( optlc_net_3428 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3430 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3430 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3787 ( .LO ( optlc_net_3429 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3431 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3431 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3788 ( .LO ( optlc_net_3430 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3432 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3432 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3789 ( .LO ( optlc_net_3431 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3433 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3433 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3790 ( .LO ( optlc_net_3432 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3434 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3434 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3791 ( .LO ( optlc_net_3433 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3435 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3435 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3792 ( .LO ( optlc_net_3434 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3436 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3436 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3793 ( .LO ( optlc_net_3435 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3437 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3437 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3794 ( .LO ( optlc_net_3436 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3438 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3438 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3795 ( .LO ( optlc_net_3437 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3439 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3439 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3796 ( .LO ( optlc_net_3438 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3440 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3440 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3797 ( .LO ( optlc_net_3439 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3441 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3441 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3798 ( .LO ( optlc_net_3440 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3442 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3442 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3799 ( .LO ( optlc_net_3441 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3443 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3443 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3800 ( .LO ( optlc_net_3442 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3444 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3444 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3801 ( .LO ( optlc_net_3443 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3445 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3445 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3802 ( .LO ( optlc_net_3444 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3446 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3446 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3803 ( .LO ( optlc_net_3445 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3447 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3447 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3804 ( .LO ( optlc_net_3446 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3448 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3448 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3805 ( .LO ( optlc_net_3447 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3449 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3449 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3806 ( .LO ( optlc_net_3448 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3450 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3450 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3807 ( .LO ( optlc_net_3449 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3451 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3451 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3808 ( .LO ( optlc_net_3450 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3452 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3452 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3809 ( .LO ( optlc_net_3451 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3453 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3453 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3810 ( .LO ( optlc_net_3452 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3454 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3454 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3811 ( .LO ( optlc_net_3453 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3455 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3455 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3812 ( .LO ( optlc_net_3454 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3456 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3456 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3813 ( .LO ( optlc_net_3455 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3457 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3457 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3814 ( .LO ( optlc_net_3456 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3458 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3458 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3815 ( .LO ( optlc_net_3457 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3459 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3459 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3816 ( .LO ( optlc_net_3458 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3460 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3460 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3817 ( .LO ( optlc_net_3459 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3461 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3461 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3818 ( .LO ( optlc_net_3460 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3462 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3462 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3819 ( .LO ( optlc_net_3461 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3463 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3463 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3820 ( .LO ( optlc_net_3462 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3464 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3464 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3821 ( .LO ( optlc_net_3463 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3465 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3465 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3822 ( .LO ( optlc_net_3464 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3466 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3466 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3823 ( .LO ( optlc_net_3465 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3467 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3467 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3824 ( .LO ( optlc_net_3466 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3468 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3468 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3825 ( .LO ( optlc_net_3467 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3469 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3469 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3826 ( .LO ( optlc_net_3468 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3470 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3470 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3827 ( .LO ( optlc_net_3469 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3471 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3471 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3828 ( .LO ( optlc_net_3470 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3472 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3472 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3829 ( .LO ( optlc_net_3471 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3473 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3473 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3830 ( .LO ( optlc_net_3472 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3474 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3474 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3831 ( .LO ( optlc_net_3473 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3475 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3475 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3832 ( .LO ( optlc_net_3474 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3476 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3476 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3833 ( .LO ( optlc_net_3475 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3477 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3477 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3834 ( .LO ( optlc_net_3476 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3478 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3478 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3835 ( .LO ( optlc_net_3477 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3479 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3479 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3836 ( .LO ( optlc_net_3478 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3480 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3480 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3837 ( .LO ( optlc_net_3479 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3481 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3481 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3838 ( .LO ( optlc_net_3480 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3482 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3482 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3839 ( .LO ( optlc_net_3481 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3483 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3483 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3840 ( .LO ( optlc_net_3482 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3484 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3484 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3841 ( .LO ( optlc_net_3483 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3485 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3485 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3842 ( .LO ( optlc_net_3484 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3486 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3486 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3843 ( .LO ( optlc_net_3485 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3487 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3487 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3844 ( .LO ( optlc_net_3486 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3488 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3488 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3845 ( .LO ( optlc_net_3487 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3489 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3489 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3846 ( .LO ( optlc_net_3488 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3490 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3490 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3847 ( .LO ( optlc_net_3489 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3491 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3491 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3848 ( .LO ( optlc_net_3490 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3492 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3492 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3849 ( .LO ( optlc_net_3491 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3493 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3493 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3850 ( .LO ( optlc_net_3492 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3494 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3494 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3851 ( .LO ( optlc_net_3493 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3495 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3495 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3852 ( .LO ( optlc_net_3494 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3496 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3496 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3853 ( .LO ( optlc_net_3495 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3497 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3497 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3854 ( .LO ( optlc_net_3496 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3498 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3498 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3855 ( .LO ( optlc_net_3497 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3499 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3499 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3856 ( .LO ( optlc_net_3498 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3500 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3500 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3857 ( .LO ( optlc_net_3499 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3501 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3501 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3858 ( .LO ( optlc_net_3500 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3502 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3502 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3859 ( .LO ( optlc_net_3501 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3503 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3503 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3860 ( .LO ( optlc_net_3502 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3504 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3504 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3861 ( .LO ( optlc_net_3503 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3505 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3505 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3862 ( .LO ( optlc_net_3504 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3506 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3506 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3863 ( .LO ( optlc_net_3505 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3507 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3507 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3864 ( .LO ( optlc_net_3506 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3508 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3508 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3865 ( .LO ( optlc_net_3507 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3509 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3509 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3866 ( .LO ( optlc_net_3508 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3510 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3510 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3867 ( .LO ( optlc_net_3509 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3511 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3511 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3868 ( .LO ( optlc_net_3510 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3512 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3512 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3869 ( .LO ( optlc_net_3511 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3513 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3513 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3870 ( .LO ( optlc_net_3512 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3514 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3514 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3871 ( .LO ( optlc_net_3513 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3515 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3515 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3872 ( .LO ( optlc_net_3514 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3516 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3516 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3873 ( .LO ( optlc_net_3515 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3517 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3517 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3874 ( .LO ( optlc_net_3516 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3518 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3518 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3875 ( .LO ( optlc_net_3517 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3519 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3519 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3876 ( .LO ( optlc_net_3518 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3520 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3520 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3877 ( .LO ( optlc_net_3519 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3521 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3521 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3878 ( .LO ( optlc_net_3520 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3522 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3522 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3879 ( .LO ( optlc_net_3521 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3523 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3523 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3880 ( .LO ( optlc_net_3522 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3524 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3524 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3881 ( .LO ( optlc_net_3523 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3525 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3525 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3882 ( .LO ( optlc_net_3524 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3526 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3526 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3883 ( .LO ( optlc_net_3525 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3527 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3527 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3884 ( .LO ( optlc_net_3526 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3528 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3528 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3885 ( .LO ( optlc_net_3527 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3529 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3529 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3886 ( .LO ( optlc_net_3528 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3530 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3530 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3887 ( .LO ( optlc_net_3529 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3531 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3531 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3888 ( .LO ( optlc_net_3530 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3532 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3532 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3889 ( .LO ( optlc_net_3531 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3533 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3533 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3890 ( .LO ( optlc_net_3532 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3534 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3534 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3891 ( .LO ( optlc_net_3533 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3535 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3535 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3892 ( .LO ( optlc_net_3534 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3536 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3536 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3893 ( .LO ( optlc_net_3535 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3537 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3537 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3894 ( .LO ( optlc_net_3536 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3538 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3538 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3895 ( .LO ( optlc_net_3537 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3539 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3539 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3896 ( .LO ( optlc_net_3538 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3540 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3540 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3897 ( .LO ( optlc_net_3539 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3541 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3541 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3898 ( .LO ( optlc_net_3540 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3542 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3542 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3899 ( .LO ( optlc_net_3541 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3543 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3543 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3900 ( .LO ( optlc_net_3542 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3544 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3544 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3901 ( .LO ( optlc_net_3543 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3545 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3545 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3902 ( .LO ( optlc_net_3544 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3546 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3546 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3903 ( .LO ( optlc_net_3545 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3547 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3547 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3904 ( .LO ( optlc_net_3546 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3548 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3548 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3905 ( .LO ( optlc_net_3547 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3549 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3549 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3906 ( .LO ( optlc_net_3548 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3550 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3550 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3907 ( .LO ( optlc_net_3549 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3551 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3551 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3908 ( .LO ( optlc_net_3550 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3552 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3552 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3909 ( .LO ( optlc_net_3551 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3553 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3553 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3910 ( .LO ( optlc_net_3552 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3554 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3554 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3911 ( .LO ( optlc_net_3553 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3555 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3555 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3912 ( .LO ( optlc_net_3554 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3556 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3556 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3913 ( .LO ( optlc_net_3555 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3557 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3557 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3914 ( .LO ( optlc_net_3556 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3558 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3558 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3915 ( .LO ( optlc_net_3557 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3559 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3559 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3916 ( .LO ( optlc_net_3558 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3560 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3560 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3917 ( .LO ( optlc_net_3559 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3561 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3561 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3918 ( .LO ( optlc_net_3560 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3562 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3562 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3919 ( .LO ( optlc_net_3561 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3563 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3563 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3920 ( .LO ( optlc_net_3562 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3564 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3564 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3921 ( .LO ( optlc_net_3563 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3565 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3565 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3922 ( .LO ( optlc_net_3564 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3566 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3566 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3923 ( .LO ( optlc_net_3565 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3567 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3567 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3924 ( .LO ( optlc_net_3566 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3568 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3568 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3925 ( .LO ( optlc_net_3567 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3569 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3569 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3926 ( .LO ( optlc_net_3568 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3570 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3570 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3927 ( .LO ( optlc_net_3569 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3571 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3571 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3928 ( .LO ( optlc_net_3570 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3572 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3572 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3929 ( .LO ( optlc_net_3571 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3573 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3573 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3930 ( .LO ( optlc_net_3572 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3574 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3574 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3931 ( .LO ( optlc_net_3573 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3575 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3575 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3932 ( .LO ( optlc_net_3574 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3576 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3576 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3933 ( .LO ( optlc_net_3575 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3577 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3577 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3934 ( .LO ( optlc_net_3576 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3578 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3578 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3935 ( .LO ( optlc_net_3577 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3579 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3579 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3936 ( .LO ( optlc_net_3578 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3580 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3580 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3937 ( .LO ( optlc_net_3579 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3581 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3581 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3938 ( .LO ( optlc_net_3580 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3582 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3582 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3939 ( .LO ( optlc_net_3581 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3583 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3583 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3940 ( .LO ( optlc_net_3582 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3584 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3584 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3941 ( .LO ( optlc_net_3583 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3585 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3585 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3942 ( .LO ( optlc_net_3584 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3586 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3586 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3943 ( .LO ( optlc_net_3585 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3587 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3587 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3944 ( .LO ( optlc_net_3586 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3588 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3588 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3945 ( .LO ( optlc_net_3587 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3589 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3589 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3946 ( .LO ( optlc_net_3588 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3590 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3590 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3947 ( .LO ( optlc_net_3589 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3591 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3591 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3948 ( .LO ( optlc_net_3590 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3592 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3592 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3949 ( .LO ( optlc_net_3591 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3593 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3593 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3950 ( .LO ( optlc_net_3592 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3594 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3594 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3951 ( .LO ( optlc_net_3593 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3595 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3595 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3952 ( .LO ( optlc_net_3594 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3596 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3596 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3953 ( .LO ( optlc_net_3595 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3597 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3597 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3954 ( .LO ( optlc_net_3596 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3598 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3598 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3955 ( .LO ( optlc_net_3597 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3599 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3599 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3956 ( .LO ( optlc_net_3598 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3600 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3600 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3957 ( .LO ( optlc_net_3599 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3601 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3601 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3958 ( .LO ( optlc_net_3600 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3602 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3602 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3959 ( .LO ( optlc_net_3601 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3603 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3603 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3960 ( .LO ( optlc_net_3602 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3604 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3604 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3961 ( .LO ( optlc_net_3603 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3605 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3605 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3962 ( .LO ( optlc_net_3604 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3606 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3606 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3963 ( .LO ( optlc_net_3605 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3607 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3607 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3964 ( .LO ( optlc_net_3606 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3608 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3608 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 sky130_fd_sc_hd__conb_1 optlc_3965 ( .LO ( optlc_net_3607 ) , 
-    .HI ( SYNOPSYS_UNCONNECTED_3609 ) ) ;
+    .HI ( SYNOPSYS_UNCONNECTED_3609 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
 endmodule
 
 

verilog/gl/user_project_wrapper.v

diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v
index ff068f0..5a442ea 100644
--- a/verilog/gl/user_project_wrapper.v
+++ b/verilog/gl/user_project_wrapper.v
@@ -1,56 +1,116 @@
-/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
+module user_project_wrapper(
+// Power pins
+    vccd1, vssd1, vccd2, vssd2,
+    vdda1, vssa1, vdda2, vssa2,
+// Power pins
+    wb_rst_i, wbs_ack_o, wbs_cyc_i,
+    wbs_stb_i, wbs_we_i, wb_clk_i,
+    wbs_adr_i, wbs_dat_i, wbs_dat_o, wbs_sel_i
+// Logic analyser pins
+    io_in, io_oeb, io_out, la_oen,
+    la_data_in, la_data_out,
+// analog_io
+    analog_io,
+// User clock
+    user_clock2);
 
-module user_project_wrapper(user_clock2, wb_clk_i, wb_rst_i, wbs_ack_o, wbs_cyc_i, wbs_stb_i, wbs_we_i, vccd1, vssd1, vccd2, vssd2, vdda1, vssa1, vdda2, vssa2, analog_io, io_in, io_oeb, io_out, la_data_in, la_data_out, la_oen, wbs_adr_i, wbs_dat_i, wbs_dat_o, wbs_sel_i);
-  inout [30:0] analog_io;
-  input [37:0] io_in;
-  output [37:0] io_oeb;
-  output [37:0] io_out;
-  input [127:0] la_data_in;
-  output [127:0] la_data_out;
-  input [127:0] la_oen;
-  input user_clock2;
-  input vccd1;
-  input vccd2;
-  input vdda1;
-  input vdda2;
-  input vssa1;
-  input vssa2;
-  input vssd1;
-  input vssd2;
-  input wb_clk_i;
-  input wb_rst_i;
-  output wbs_ack_o;
-  input [31:0] wbs_adr_i;
-  input wbs_cyc_i;
-  input [31:0] wbs_dat_i;
-  output [31:0] wbs_dat_o;
-  input [3:0] wbs_sel_i;
-  input wbs_stb_i;
-  input wbs_we_i;
-  user_proj_example mprj (
-    .io_in(io_in),
-    .io_oeb(io_oeb),
-    .io_out(io_out),
+// Power pins
+input vccd1;
+input vccd2;
+input vdda1;
+input vdda2;
+input vssa1;
+input vssa2;
+input vssd1;
+input vssd2;
+// Power pins
+input wb_clk_i;
+input wb_rst_i;
+output wbs_ack_o;
+input [31:0] wbs_adr_i;
+input [31:0] wbs_dat_i;
+output [31:0] wbs_dat_o;
+input [3:0] wbs_sel_i;
+input wbs_stb_i;
+input wbs_we_i;
+input wbs_cyc_i;
+// Logic analyser pins
+input [37:0] io_in;
+output [37:0] io_oeb;
+output [37:0] io_out;
+input [127:0] la_data_in;
+output [127:0] la_data_out;
+input [127:0] la_oen;
+// Analog_pin
+inout [30:0] analog_io;
+// User clock
+input user_clock2;
+
+
+// Short all power rails/domains
+assign vcca1 = vdda2;
+assign vssa1 = vssa2;
+assign vccd2 = vdda1;
+assign vssd2 = vssa1;
+assign vccd1 = vccd2;
+assign vssd1 = vssd2;
+
+module fpga_top fpga_top_uut (
+// Power connections
+    .VDD(vccd1)
+    .VSS(vssd1)
+// Wishbone connections
+    .wb_clk_i(wb_clk_i),
+    .wb_rst_i(wb_rst_i),
+    .wbs_stb_i(wbs_stb_i),
+    .wbs_cyc_i(wbs_cyc_i),
+    .wbs_we_i(wbs_we_i),
+    .wbs_sel_i(wbs_sel_i),
+    .wbs_dat_i(wbs_dat_i),
+    .wbs_adr_i(wbs_adr_i),
+    .wbs_ack_o(wbs_ack_o),
+    .wbs_dat_o(wbs_dat_o),
+// Logic analyser connections
     .la_data_in(la_data_in),
     .la_data_out(la_data_out),
     .la_oen(la_oen),
-    .vccd1(vccd1),
-    .vccd2(vccd2),
-    .vdda1(vdda1),
-    .vdda2(vdda2),
-    .vssa1(vssa1),
-    .vssa2(vssa2),
-    .vssd1(vssd1),
-    .vssd2(vssd2),
-    .wb_clk_i(wb_clk_i),
-    .wb_rst_i(wb_rst_i),
-    .wbs_ack_o(wbs_ack_o),
-    .wbs_adr_i(wbs_adr_i),
-    .wbs_cyc_i(wbs_cyc_i),
-    .wbs_dat_i(wbs_dat_i),
-    .wbs_dat_o(wbs_dat_o),
-    .wbs_sel_i(wbs_sel_i),
-    .wbs_stb_i(wbs_stb_i),
-    .wbs_we_i(wbs_we_i)
-  );
-endmodule
+    .io_in(io_in),
+    .io_out(io_out),
+    .io_oeb(io_oeb),
+// Analog ports
+    .analog_io_0_(analog_io_0_),
+    .analog_io_1_(analog_io_1_),
+    .analog_io_2_(analog_io_2_),
+    .analog_io_3_(analog_io_3_),
+    .analog_io_4_(analog_io_4_),
+    .analog_io_5_(analog_io_5_),
+    .analog_io_6_(analog_io_6_),
+    .analog_io_7_(analog_io_7_),
+    .analog_io_8_(analog_io_8_),
+    .analog_io_9_(analog_io_9_),
+    .analog_io_10_(analog_io_10_),
+    .analog_io_11_(analog_io_11_),
+    .analog_io_12_(analog_io_12_),
+    .analog_io_13_(analog_io_13_),
+    .analog_io_14_(analog_io_14_),
+    .analog_io_15_(analog_io_15_),
+    .analog_io_16_(analog_io_16_),
+    .analog_io_17_(analog_io_17_),
+    .analog_io_18_(analog_io_18_),
+    .analog_io_19_(analog_io_19_),
+    .analog_io_20_(analog_io_20_),
+    .analog_io_21_(analog_io_21_),
+    .analog_io_22_(analog_io_22_),
+    .analog_io_23_(analog_io_23_),
+    .analog_io_24_(analog_io_24_),
+    .analog_io_25_(analog_io_25_),
+    .analog_io_26_(analog_io_26_),
+    .analog_io_27_(analog_io_27_),
+    .analog_io_28_(analog_io_28_),
+    .analog_io_29_(analog_io_29_),
+    .analog_io_30_(analog_io_30_),
+// User Clock
+    .user_clock2(user_clock2)
+    ) ;
+
+endmodule
\ No newline at end of file