commit	56f4613884ad4a778bf05eaf63c04bf05efc0dc8	[log] [tgz]
author	Jeff DiCorpo <jeffdi@efabless.com>	Fri Jun 11 11:10:58 2021 -0700
committer	Jeff DiCorpo <jeffdi@efabless.com>	Fri Jun 11 11:10:58 2021 -0700
tree	8c6f1eb6f8a4585433bd9efdf71d89f631815641
parent	3ac18ca1abfb9140d3a8cdb763818de6d421389f [diff]

caravel_fix

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tree: 8c6f1eb6f8a4585433bd9efdf71d89f631815641

README.md

Caravel-QLSOFA-HD

Highlights

Opensource 12x12 FPGA designed using OpenFPGA prototyping tool
Designed with Skywater130nm PDK with HD standard cell library + and Custom Transmission Gate Cells
Base K4 architecture from VPR with 60 vertical and horizontal channels
Soft adder implementation
Designed using commercial PnR tool

Contribution

NOTE

This repository is created for The eFabless Open MPW shuttle program submission
The repository is auto-updated. For any commits issues and feature requests, please check Skywater-OpenFPGA

Caravel design and CIIC Harness

For caravel related updated refer efabless/caravel