checks/compare_caravel.txt

 .travis.yml                                        |    39 -
 .travisCI/runPrecheck.sh                           |    35 -
 .travisCI/travisBuild.sh                           |    28 -
 OpenFPGA_task/arch/fabric_key.xml                  |   678 +
 OpenFPGA_task/arch/openfpga_arch.xml               |   330 +
 OpenFPGA_task/arch/vpr_arch.xml                    |   737 +
 OpenFPGA_task/config/task.conf                     |    39 +
 OpenFPGA_task/config/task_generation.conf          |    39 +
 OpenFPGA_task/config/task_simulation.conf          |    33 +
 OpenFPGA_task/design_variables.yml                 |     1 +
 OpenFPGA_task/generate_fabric.openfpga             |    57 +
 OpenFPGA_task/generate_testbench.openfpga          |    70 +
 OpenFPGA_task/micro_benchmark/and.act              |     3 +
 OpenFPGA_task/micro_benchmark/and.blif             |     8 +
 OpenFPGA_task/micro_benchmark/and.v                |    14 +
 OpenFPGA_task/process_top_def.sh                   |    46 +
 OpenFPGA_task/sc_verilog/decoder2to4_post_synth.v  |    20 +
 OpenFPGA_task/sc_verilog/digital_io_hd.v           |    55 +
 .../sc_verilog/fd_hd_mux_custom_cells_tt.v         |    69 +
 OpenFPGA_task/sc_verilog/fpga_top.v                |   483 +
 .../sc_verilog/local_encoder1to1_post_synth.v      |    18 +
 .../sc_verilog/local_encoder1to2_post_synth.v      |    21 +
 .../sc_verilog/local_encoder2to3_post_synth.v      |    23 +
 .../sc_verilog/local_encoder2to4_post_synth.v      |    24 +
 OpenFPGA_task/sc_verilog/sky130_fd_sc_hd_wrapper.v |    20 +
 OpenFPGA_task/user_project_wrapper_empty.def       |  1219 +
 OpenFPGA_task/user_project_wrapper_template.def    |  3768 +
 README.md                                          |   158 +-
 checks/caravel.magic.drc                           |   104 +
 checks/caravel.magic.drc.mag                       | 80938 +++++++++++++++++++
 checks/caravel.magic.namelist                      |     1 +
 checks/caravel.magic.rdb                           |    63 +
 checks/caravel.magic.typelist                      |     1 +
 checks/full_log.log                                |    56 +
 checks/magic_drc.log                               |  5095 ++
 checks/magic_extract.log                           | 15850 ++++
 checks/magic_merge_user_project_wrapper.log        |  5250 ++
 checks/manifest_check.mag.log                      |     2 +
 checks/manifest_check.maglef.log                   |    13 +
 checks/manifest_check.rtl.log                      |    37 +
 checks/mprj.magic.namelist                         |     1 +
 checks/mprj.magic.typelist                         |     1 +
 checks/spdx_compliance_report.log                  |   122 +
 gds/caravel.gds.gz                                 |   Bin 52991493 -> 59154257 bytes
 gds/user_proj_example.gds.gz                       |   Bin 742584 -> 0 bytes
 gds/user_project_wrapper.gds.gz                    |   Bin 6394035 -> 3558908 bytes
 gds/user_project_wrapper_empty.gds.gz              |   Bin 73084 -> 0 bytes
 info.yaml                                          |     6 +-
 mag/.magicrc                                       |    16 -
 mag/user_project_wrapper_empty.mag                 |     3 +
 qflow/digital_pll_controller/tech                  |     1 -
 qflow/ring_osc2x13/tech                            |     1 -
 source_commit_hash.txt                             |    11 +
 verilog/OpenFPGA_Verilog/InstancesMap.txt          |     1 +
 verilog/OpenFPGA_Verilog/define_simulation.v       |    18 +
 verilog/OpenFPGA_Verilog/fabric_netlists.v         |    72 +
 verilog/OpenFPGA_Verilog/fpga_core.v               | 49530 ++++++++++++
 verilog/OpenFPGA_Verilog/fpga_defines.v            |    10 +
 verilog/OpenFPGA_Verilog/fpga_top.v                | 41442 ++++++++++
 verilog/OpenFPGA_Verilog/lb/grid_clb.v             |   272 +
 .../lb/logical_tile_clb_mode_clb_.v                |   758 +
 .../lb/logical_tile_clb_mode_default__fle.v        |   173 +
 ...e_clb_mode_default__fle_mode_physical__fabric.v |   242 +
 ...t__fle_mode_physical__fabric_mode_default__ff.v |    61 +
 ...ode_physical__fabric_mode_default__frac_logic.v |   151 +
 ...ault__frac_logic_mode_default__carry_follower.v |    52 +
 ...e_default__frac_logic_mode_default__frac_lut4.v |    79 +
 .../OpenFPGA_Verilog/lb/logical_tile_io_mode_io_.v |    86 +
 .../lb/logical_tile_io_mode_physical__iopad.v      |    79 +
 verilog/OpenFPGA_Verilog/routing/cbx_1__0_.v       |   548 +
 verilog/OpenFPGA_Verilog/routing/cbx_1__1_.v       |   671 +
 verilog/OpenFPGA_Verilog/routing/cbx_1__2_.v       |   589 +
 verilog/OpenFPGA_Verilog/routing/cby_0__1_.v       |   145 +
 verilog/OpenFPGA_Verilog/routing/cby_1__1_.v       |   670 +
 verilog/OpenFPGA_Verilog/routing/cby_2__1_.v       |   563 +
 verilog/OpenFPGA_Verilog/routing/sb_0__0_.v        |   910 +
 verilog/OpenFPGA_Verilog/routing/sb_0__1_.v        |  1295 +
 verilog/OpenFPGA_Verilog/routing/sb_0__2_.v        |   922 +
 verilog/OpenFPGA_Verilog/routing/sb_1__0_.v        |  1331 +
 verilog/OpenFPGA_Verilog/routing/sb_1__1_.v        |  1468 +
 verilog/OpenFPGA_Verilog/routing/sb_1__2_.v        |  1282 +
 verilog/OpenFPGA_Verilog/routing/sb_2__0_.v        |  1341 +
 verilog/OpenFPGA_Verilog/routing/sb_2__1_.v        |  1289 +
 verilog/OpenFPGA_Verilog/routing/sb_2__2_.v        |  1335 +
 verilog/OpenFPGA_Verilog/sub_module/arch_encoder.v |    10 +
 .../sub_module/decoder2to4_post_synth.v            |    20 +
 .../OpenFPGA_Verilog/sub_module/digital_io_hd.v    |    55 +
 .../sub_module/fd_hd_mux_custom_cells_tt.v         |    69 +
 verilog/OpenFPGA_Verilog/sub_module/fpga_top.v     |   483 +
 .../OpenFPGA_Verilog/sub_module/inv_buf_passgate.v |    43 +
 .../sub_module/local_encoder1to1_post_synth.v      |    18 +
 .../sub_module/local_encoder1to2_post_synth.v      |    21 +
 .../sub_module/local_encoder2to3_post_synth.v      |    23 +
 .../sub_module/local_encoder2to4_post_synth.v      |    24 +
 verilog/OpenFPGA_Verilog/sub_module/luts.v         |   112 +
 verilog/OpenFPGA_Verilog/sub_module/memories.v     |  1059 +
 .../OpenFPGA_Verilog/sub_module/mux_primitives.v   |   404 +
 verilog/OpenFPGA_Verilog/sub_module/muxes.v        |  1289 +
 .../sub_module/sky130_fd_sc_hd_wrapper.v           |    20 +
 verilog/OpenFPGA_Verilog/sub_module/wires.v        |    34 +
 verilog/OpenFPGA_Verilog/top_include_netlists.v    |    31 +
 101 files changed, 226439 insertions(+), 268 deletions(-)