| commit | 08dd4834e6abdd71874acb712134f8a3f616a44d | [log] [tgz] |
|---|---|---|
| author | manarabdelaty <manarabdelatty@aucegypt.edu> | Thu Dec 03 19:27:08 2020 +0200 |
| committer | manarabdelaty <manarabdelatty@aucegypt.edu> | Thu Dec 03 19:27:08 2020 +0200 |
| tree | 23ee3456c8ddbe7917b65999d813cbcfde5f268e | |
| parent | 57c50fae6746801e490d5b7ac5098c689d009c19 [diff] [blame] |
Added global default value for the clock divisor
diff --git a/verilog/rtl/defines.v b/verilog/rtl/defines.v index 1aec155..a72f0c8 100644 --- a/verilog/rtl/defines.v +++ b/verilog/rtl/defines.v
@@ -18,4 +18,7 @@ // not really parameterized but just to easily keep track of the number // of ram_block across different modules -`define RAM_BLOCKS 2 \ No newline at end of file +`define RAM_BLOCKS 2 + +// Clock divisor default value +`define CLK_DIV 3'b010 \ No newline at end of file