diff --git a/verilog/rtl/defines.v b/verilog/rtl/defines.v
index 1aec155..a72f0c8 100644
--- a/verilog/rtl/defines.v
+++ b/verilog/rtl/defines.v
@@ -18,4 +18,7 @@
 
 // not really parameterized but just to easily keep track of the number
 // of ram_block across different modules
-`define RAM_BLOCKS 2
\ No newline at end of file
+`define RAM_BLOCKS 2
+
+// Clock divisor default value
+`define CLK_DIV 3'b010
\ No newline at end of file