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18
Tim Edwardsc0cd7c22020-11-24 20:36:36 -050019The qflow directory entries are only used to verify the all-digital frequency
20locked loop circuit by running the verilog modules ring_osc2x13 and
21digital_pll_controller seperately through synthesis.
22
23The ring_osc2x13 module is all gate-level except for a small amount of trivial
24glue logic, so the fact that it is synthesized in qflow instead of openlane
25(with a different setup passed to yosys) does not change the core part of the
26ring oscillator that needs to be simulated. The synthesis results in a SPICE
27netlist that can be simulated.
28
29For the digital_pll_controller, it is only needed to have a functional xspice
30circuit of the digital part that can be used in the ngspice simulation.
31
32See the caravel/ngspice/digital_pll directory for the ngspice simulations.
33
34None of the files in this tree are used for the actual synthesis, placement,
35and routing. The source files for qflow are pointers back to the verilog
36module files in caravel/verilog/rtl/ directory.
37
38Qflow was only run through the "synthesis" stage to obtain the necessary
39netlists. These can be recreated on demand from qflow, so the required
40netlists were copied back to caravel/ngspice/digital_pll and the qflow
41directory cleaned out.
42
43To reproduce the results, it is necessary to have the "tech" directory as a
44symbolic link pointing to the open_pdks installation of sky130A.