agorararmard | 312a1cd | 2020-12-10 18:35:12 +0200 | [diff] [blame] | 1 | <!--- |
| 2 | # SPDX-FileCopyrightText: 2020 Efabless Corporation |
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| 18 | |
Tim Edwards | c0cd7c2 | 2020-11-24 20:36:36 -0500 | [diff] [blame] | 19 | The qflow directory entries are only used to verify the all-digital frequency |
| 20 | locked loop circuit by running the verilog modules ring_osc2x13 and |
| 21 | digital_pll_controller seperately through synthesis. |
| 22 | |
| 23 | The ring_osc2x13 module is all gate-level except for a small amount of trivial |
| 24 | glue logic, so the fact that it is synthesized in qflow instead of openlane |
| 25 | (with a different setup passed to yosys) does not change the core part of the |
| 26 | ring oscillator that needs to be simulated. The synthesis results in a SPICE |
| 27 | netlist that can be simulated. |
| 28 | |
| 29 | For the digital_pll_controller, it is only needed to have a functional xspice |
| 30 | circuit of the digital part that can be used in the ngspice simulation. |
| 31 | |
| 32 | See the caravel/ngspice/digital_pll directory for the ngspice simulations. |
| 33 | |
| 34 | None of the files in this tree are used for the actual synthesis, placement, |
| 35 | and routing. The source files for qflow are pointers back to the verilog |
| 36 | module files in caravel/verilog/rtl/ directory. |
| 37 | |
| 38 | Qflow was only run through the "synthesis" stage to obtain the necessary |
| 39 | netlists. These can be recreated on demand from qflow, so the required |
| 40 | netlists were copied back to caravel/ngspice/digital_pll and the qflow |
| 41 | directory cleaned out. |
| 42 | |
| 43 | To reproduce the results, it is necessary to have the "tech" directory as a |
| 44 | symbolic link pointing to the open_pdks installation of sky130A. |