blob: 5dacab8e07035d8cad0fc60a1244c4890aea82bf [file] [log] [blame]
Tim Edwardsef8312e2020-09-22 17:20:06 -04001/*--------------------------------------------------------------*/
2/* caravel, a project harness for the Google/SkyWater sky130 */
3/* fabrication process and open source PDK */
4/* */
5/* Copyright 2020 efabless, Inc. */
6/* Written by Tim Edwards, December 2019 */
7/* and Mohamed Shalan, August 2020 */
8/* This file is open source hardware released under the */
9/* Apache 2.0 license. See file LICENSE. */
10/* */
11/*--------------------------------------------------------------*/
12
13`timescale 1 ns / 1 ps
14
Tim Edwardse2ef6732020-10-12 17:25:12 -040015`define USE_POWER_PINS
Tim Edwardsc5265b82020-09-25 17:08:59 -040016`define UNIT_DELAY #1
Tim Edwardsef8312e2020-09-22 17:20:06 -040017
Ahmed Ghazy22d29d62020-10-28 03:42:02 +020018`include "defines.v"
Tim Edwardsef8312e2020-09-22 17:20:06 -040019`include "pads.v"
20
Tim Edwards4286ae12020-10-11 14:52:01 -040021/* NOTE: Need to pass the PDK root directory to iverilog with option -I */
Tim Edwardsef8312e2020-09-22 17:20:06 -040022
Tim Edwards4286ae12020-10-11 14:52:01 -040023`include "libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
Tim Edwards4c733352020-10-12 16:32:36 -040024`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
Tim Edwards4286ae12020-10-11 14:52:01 -040025
26`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
27`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
28`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
29`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
Tim Edwardsef8312e2020-09-22 17:20:06 -040030
31`include "mgmt_soc.v"
Tim Edwards44bab472020-10-04 22:09:54 -040032`include "housekeeping_spi.v"
Tim Edwardsef8312e2020-09-22 17:20:06 -040033`include "digital_pll.v"
Tim Edwards3245e2f2020-10-10 14:02:11 -040034`include "caravel_clocking.v"
Tim Edwardsef8312e2020-09-22 17:20:06 -040035`include "mgmt_core.v"
Tim Edwards53d92182020-10-11 21:47:40 -040036`include "mgmt_protect.v"
Tim Edwardsef8312e2020-09-22 17:20:06 -040037`include "mprj_io.v"
38`include "chip_io.v"
Tim Edwards04ba17f2020-10-02 22:27:50 -040039`include "user_id_programming.v"
Tim Edwardsb86fc842020-10-13 17:11:54 -040040`include "user_project_wrapper.v"
Tim Edwards04ba17f2020-10-02 22:27:50 -040041`include "gpio_control_block.v"
Tim Edwards3245e2f2020-10-10 14:02:11 -040042`include "clock_div.v"
Tim Edwardsf51dd082020-10-05 16:30:24 -040043`include "simple_por.v"
Manar55ec3692020-10-30 16:32:18 +020044`include "storage_bridge_wb.v"
Ahmed Ghazy2517fa82020-11-08 23:34:41 +020045`include "DFFRAM.v"
Manar68e03632020-11-09 13:25:13 +020046`include "DFFRAMBB.v"
Manar55ec3692020-10-30 16:32:18 +020047`include "sram_1rw1r_32_256_8_sky130.v"
48`include "storage.v"
Tim Edwardsef8312e2020-09-22 17:20:06 -040049
Tim Edwards05537512020-10-06 14:59:26 -040050/*------------------------------*/
51/* Include user project here */
52/*------------------------------*/
53`include "user_proj_example.v"
54
Manar55ec3692020-10-30 16:32:18 +020055// `ifdef USE_OPENRAM
56// `include "sram_1rw1r_32_256_8_sky130.v"
57// `endif
Tim Edwardsef8312e2020-09-22 17:20:06 -040058
59module caravel (
Tim Edwards9eda80d2020-10-08 21:36:44 -040060 inout vddio, // Common 3.3V padframe/ESD power
61 inout vssio, // Common padframe/ESD ground
62 inout vdda, // Management 3.3V power
63 inout vssa, // Common analog ground
64 inout vccd, // Management/Common 1.8V power
65 inout vssd, // Common digital ground
66 inout vdda1, // User area 1 3.3V power
67 inout vdda2, // User area 2 3.3V power
68 inout vssa1, // User area 1 analog ground
69 inout vssa2, // User area 2 analog ground
70 inout vccd1, // User area 1 1.8V power
71 inout vccd2, // User area 2 1.8V power
72 inout vssd1, // User area 1 digital ground
73 inout vssd2, // User area 2 digital ground
74
Tim Edwards04ba17f2020-10-02 22:27:50 -040075 inout gpio, // Used for external LDO control
Tim Edwardsef8312e2020-09-22 17:20:06 -040076 inout [`MPRJ_IO_PADS-1:0] mprj_io,
Tim Edwardsba328902020-10-27 15:03:22 -040077 output [`MPRJ_PWR_PADS-1:0] pwr_ctrl_out,
Tim Edwardsef8312e2020-09-22 17:20:06 -040078 input clock, // CMOS core clock input, not a crystal
Tim Edwards04ba17f2020-10-02 22:27:50 -040079 input resetb,
80
81 // Note that only two pins are available on the flash so dual and
82 // quad flash modes are not available.
83
Tim Edwardsef8312e2020-09-22 17:20:06 -040084 output flash_csb,
85 output flash_clk,
86 output flash_io0,
Tim Edwards04ba17f2020-10-02 22:27:50 -040087 output flash_io1
Tim Edwardsef8312e2020-09-22 17:20:06 -040088);
89
Tim Edwards04ba17f2020-10-02 22:27:50 -040090 //------------------------------------------------------------
91 // This value is uniquely defined for each user project.
92 //------------------------------------------------------------
93 parameter USER_PROJECT_ID = 32'h0;
Tim Edwardsef8312e2020-09-22 17:20:06 -040094
Tim Edwards04ba17f2020-10-02 22:27:50 -040095 // These pins are overlaid on mprj_io space. They have the function
96 // below when the management processor is in reset, or in the default
97 // configuration. They are assigned to uses in the user space by the
98 // configuration program running off of the SPI flash. Note that even
99 // when the user has taken control of these pins, they can be restored
100 // to the original use by setting the resetb pin low. The SPI pins and
101 // UART pins can be connected directly to an FTDI chip as long as the
102 // FTDI chip sets these lines to high impedence (input function) at
103 // all times except when holding the chip in reset.
104
105 // JTAG = mprj_io[0] (inout)
106 // SDO = mprj_io[1] (output)
107 // SDI = mprj_io[2] (input)
108 // CSB = mprj_io[3] (input)
109 // SCK = mprj_io[4] (input)
110 // ser_rx = mprj_io[5] (input)
111 // ser_tx = mprj_io[6] (output)
112 // irq = mprj_io[7] (input)
113
114 // These pins are reserved for any project that wants to incorporate
115 // its own processor and flash controller. While a user project can
116 // technically use any available I/O pins for the purpose, these
117 // four pins connect to a pass-through mode from the SPI slave (pins
118 // 1-4 above) so that any SPI flash connected to these specific pins
119 // can be accessed through the SPI slave even when the processor is in
120 // reset.
121
Tim Edwards44bab472020-10-04 22:09:54 -0400122 // user_flash_csb = mprj_io[8]
123 // user_flash_sck = mprj_io[9]
124 // user_flash_io0 = mprj_io[10]
125 // user_flash_io1 = mprj_io[11]
Tim Edwards04ba17f2020-10-02 22:27:50 -0400126
127 // One-bit GPIO dedicated to management SoC (outside of user control)
128 wire gpio_out_core;
129 wire gpio_in_core;
130 wire gpio_mode0_core;
131 wire gpio_mode1_core;
132 wire gpio_outenb_core;
133 wire gpio_inenb_core;
134
Tim Edwards6d9739d2020-10-19 11:00:49 -0400135 // User Project Control (pad-facing)
Tim Edwards04ba17f2020-10-02 22:27:50 -0400136 wire mprj_io_loader_resetn;
137 wire mprj_io_loader_clock;
138 wire mprj_io_loader_data;
139
Tim Edwardsef8312e2020-09-22 17:20:06 -0400140 wire [`MPRJ_IO_PADS-1:0] mprj_io_hldh_n;
141 wire [`MPRJ_IO_PADS-1:0] mprj_io_enh;
142 wire [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis;
Tim Edwards44bab472020-10-04 22:09:54 -0400143 wire [`MPRJ_IO_PADS-1:0] mprj_io_oeb;
Tim Edwardsef8312e2020-09-22 17:20:06 -0400144 wire [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel;
Tim Edwards04ba17f2020-10-02 22:27:50 -0400145 wire [`MPRJ_IO_PADS-1:0] mprj_io_vtrip_sel;
146 wire [`MPRJ_IO_PADS-1:0] mprj_io_slow_sel;
147 wire [`MPRJ_IO_PADS-1:0] mprj_io_holdover;
Tim Edwardsef8312e2020-09-22 17:20:06 -0400148 wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_en;
149 wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel;
150 wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol;
151 wire [`MPRJ_IO_PADS*3-1:0] mprj_io_dm;
152 wire [`MPRJ_IO_PADS-1:0] mprj_io_in;
153 wire [`MPRJ_IO_PADS-1:0] mprj_io_out;
154
Tim Edwards6d9739d2020-10-19 11:00:49 -0400155 // User Project Control (user-facing)
Tim Edwards44bab472020-10-04 22:09:54 -0400156 wire [`MPRJ_IO_PADS-1:0] user_io_oeb;
Tim Edwards04ba17f2020-10-02 22:27:50 -0400157 wire [`MPRJ_IO_PADS-1:0] user_io_in;
158 wire [`MPRJ_IO_PADS-1:0] user_io_out;
159
160 /* Padframe control signals */
161 wire [`MPRJ_IO_PADS-1:0] gpio_serial_link;
162 wire mgmt_serial_clock;
163 wire mgmt_serial_resetn;
164
Tim Edwards6d9739d2020-10-19 11:00:49 -0400165 // User Project Control management I/O
Tim Edwards44bab472020-10-04 22:09:54 -0400166 // There are two types of GPIO connections:
167 // (1) Full Bidirectional: Management connects to in, out, and oeb
168 // Uses: JTAG and SDO
169 // (2) Selectable bidirectional: Management connects to in and out,
170 // which are tied together. oeb is grounded (oeb from the
171 // configuration is used)
172
173 // SDI = mprj_io[2] (input)
174 // CSB = mprj_io[3] (input)
175 // SCK = mprj_io[4] (input)
176 // ser_rx = mprj_io[5] (input)
177 // ser_tx = mprj_io[6] (output)
178 // irq = mprj_io[7] (input)
179
180 wire [`MPRJ_IO_PADS-1:0] mgmt_io_in;
181 wire jtag_out, sdo_out;
182 wire jtag_outenb, sdo_outenb;
183
184 wire [`MPRJ_IO_PADS-3:0] mgmt_io_nc1; /* no-connects */
185 wire [`MPRJ_IO_PADS-3:0] mgmt_io_nc3; /* no-connects */
186 wire [1:0] mgmt_io_nc2; /* no-connects */
187
Tim Edwards04ba17f2020-10-02 22:27:50 -0400188 // Power-on-reset signal. The reset pad generates the sense-inverted
189 // reset at 3.3V. The 1.8V signal and the inverted 1.8V signal are
190 // derived.
191
Tim Edwardsef8312e2020-09-22 17:20:06 -0400192 wire porb_h;
193 wire porb_l;
Tim Edwardsef8312e2020-09-22 17:20:06 -0400194
Tim Edwardsf51dd082020-10-05 16:30:24 -0400195 wire rstb_h;
196 wire rstb_l;
197
Tim Edwards44bab472020-10-04 22:09:54 -0400198 // To be considered: Master hold signal on all user pads (?)
199 // For now, set holdh_n to 1 (NOTE: This is in the 3.3V domain)
200 // and setting enh to porb_h.
Tim Edwards9eda80d2020-10-08 21:36:44 -0400201 assign mprj_io_hldh_n = {`MPRJ_IO_PADS{vddio}};
Tim Edwards44bab472020-10-04 22:09:54 -0400202 assign mprj_io_enh = {`MPRJ_IO_PADS{porb_h}};
203
Tim Edwardsef8312e2020-09-22 17:20:06 -0400204 chip_io padframe(
205 // Package Pins
Tim Edwards9eda80d2020-10-08 21:36:44 -0400206 .vddio(vddio),
207 .vssio(vssio),
208 .vdda(vdda),
209 .vssa(vssa),
210 .vccd(vccd),
211 .vssd(vssd),
212 .vdda1(vdda1),
213 .vdda2(vdda2),
214 .vssa1(vssa1),
215 .vssa2(vssa2),
216 .vccd1(vccd1),
217 .vccd2(vccd2),
218 .vssd1(vssd1),
219 .vssd2(vssd2),
220
Tim Edwardsef8312e2020-09-22 17:20:06 -0400221 .gpio(gpio),
222 .mprj_io(mprj_io),
223 .clock(clock),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400224 .resetb(resetb),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400225 .flash_csb(flash_csb),
226 .flash_clk(flash_clk),
227 .flash_io0(flash_io0),
228 .flash_io1(flash_io1),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400229 // SoC Core Interface
Tim Edwardsef8312e2020-09-22 17:20:06 -0400230 .porb_h(porb_h),
Tim Edwardsf51dd082020-10-05 16:30:24 -0400231 .resetb_core_h(rstb_h),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400232 .clock_core(clock_core),
233 .gpio_out_core(gpio_out_core),
234 .gpio_in_core(gpio_in_core),
235 .gpio_mode0_core(gpio_mode0_core),
236 .gpio_mode1_core(gpio_mode1_core),
237 .gpio_outenb_core(gpio_outenb_core),
238 .gpio_inenb_core(gpio_inenb_core),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400239 .flash_csb_core(flash_csb_core),
240 .flash_clk_core(flash_clk_core),
241 .flash_csb_oeb_core(flash_csb_oeb_core),
242 .flash_clk_oeb_core(flash_clk_oeb_core),
243 .flash_io0_oeb_core(flash_io0_oeb_core),
244 .flash_io1_oeb_core(flash_io1_oeb_core),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400245 .flash_csb_ieb_core(flash_csb_ieb_core),
246 .flash_clk_ieb_core(flash_clk_ieb_core),
247 .flash_io0_ieb_core(flash_io0_ieb_core),
248 .flash_io1_ieb_core(flash_io1_ieb_core),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400249 .flash_io0_do_core(flash_io0_do_core),
250 .flash_io1_do_core(flash_io1_do_core),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400251 .flash_io0_di_core(flash_io0_di_core),
252 .flash_io1_di_core(flash_io1_di_core),
Tim Edwards44bab472020-10-04 22:09:54 -0400253 .por(~porb_l),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400254 .mprj_io_in(mprj_io_in),
255 .mprj_io_out(mprj_io_out),
Tim Edwards44bab472020-10-04 22:09:54 -0400256 .mprj_io_oeb(mprj_io_oeb),
Manar14d35ac2020-10-21 22:47:15 +0200257 .mprj_io_hldh_n(mprj_io_hldh_n),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400258 .mprj_io_enh(mprj_io_enh),
Manar14d35ac2020-10-21 22:47:15 +0200259 .mprj_io_inp_dis(mprj_io_inp_dis),
260 .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
261 .mprj_io_vtrip_sel(mprj_io_vtrip_sel),
262 .mprj_io_slow_sel(mprj_io_slow_sel),
263 .mprj_io_holdover(mprj_io_holdover),
264 .mprj_io_analog_en(mprj_io_analog_en),
265 .mprj_io_analog_sel(mprj_io_analog_sel),
266 .mprj_io_analog_pol(mprj_io_analog_pol),
267 .mprj_io_dm(mprj_io_dm)
Tim Edwardsef8312e2020-09-22 17:20:06 -0400268 );
269
270 // SoC core
Tim Edwards04ba17f2020-10-02 22:27:50 -0400271 wire caravel_clk;
Tim Edwards7a8cbb12020-10-12 11:32:11 -0400272 wire caravel_clk2;
Tim Edwards04ba17f2020-10-02 22:27:50 -0400273 wire caravel_rstn;
Tim Edwardsef8312e2020-09-22 17:20:06 -0400274
275 wire [7:0] spi_ro_config_core;
276
277 // LA signals
278 wire [127:0] la_output_core; // From CPU to MPRJ
279 wire [127:0] la_data_in_mprj; // From CPU to MPRJ
280 wire [127:0] la_data_out_mprj; // From CPU to MPRJ
281 wire [127:0] la_output_mprj; // From MPRJ to CPU
282 wire [127:0] la_oen; // LA output enable from CPU perspective (active-low)
283
Tim Edwards6d9739d2020-10-19 11:00:49 -0400284 // WB MI A (User Project)
Tim Edwardsef8312e2020-09-22 17:20:06 -0400285 wire mprj_cyc_o_core;
286 wire mprj_stb_o_core;
287 wire mprj_we_o_core;
288 wire [3:0] mprj_sel_o_core;
289 wire [31:0] mprj_adr_o_core;
290 wire [31:0] mprj_dat_o_core;
291 wire mprj_ack_i_core;
292 wire [31:0] mprj_dat_i_core;
293
294 // WB MI B (xbar)
295 wire xbar_cyc_o_core;
296 wire xbar_stb_o_core;
297 wire xbar_we_o_core;
298 wire [3:0] xbar_sel_o_core;
299 wire [31:0] xbar_adr_o_core;
300 wire [31:0] xbar_dat_o_core;
301 wire xbar_ack_i_core;
302 wire [31:0] xbar_dat_i_core;
303
Tim Edwards04ba17f2020-10-02 22:27:50 -0400304 // Mask revision
305 wire [31:0] mask_rev;
306
Manar14d35ac2020-10-21 22:47:15 +0200307 wire mprj_clock;
308 wire mprj_clock2;
309 wire mprj_resetn;
310 wire mprj_cyc_o_user;
311 wire mprj_stb_o_user;
312 wire mprj_we_o_user;
313 wire [3:0] mprj_sel_o_user;
314 wire [31:0] mprj_adr_o_user;
315 wire [31:0] mprj_dat_o_user;
316 wire mprj_vcc_pwrgood;
317 wire mprj2_vcc_pwrgood;
318 wire mprj_vdd_pwrgood;
319 wire mprj2_vdd_pwrgood;
320
Manar55ec3692020-10-30 16:32:18 +0200321 // Storage area
322 // Management R/W interface
323 wire [`MGMT_BLOCKS-1:0] mgmt_ena;
324 wire [`MGMT_BLOCKS-1:0] mgmt_wen;
325 wire [(`MGMT_BLOCKS*4)-1:0] mgmt_wen_mask;
326 wire [7:0] mgmt_addr;
327 wire [31:0] mgmt_wdata;
328 wire [(`MGMT_BLOCKS*32)-1:0] mgmt_rdata;
329 // Management RO interface
330 wire [`USER_BLOCKS-1:0] mgmt_user_ena;
331 wire [7:0] mgmt_user_addr;
332 wire [(`USER_BLOCKS*32)-1:0] mgmt_user_rdata;
333 // User R/W interface
334 wire [`USER_BLOCKS-1:0] user_ena;
335 wire [`USER_BLOCKS-1:0] user_wen;
336 wire [(`USER_BLOCKS*4)-1:0] user_wen_mask;
337 wire [7:0] user_addr;
338 wire [31:0] user_wdata;
339 wire [(`USER_BLOCKS*32)-1:0] user_rdata;
340 // User RO interface
341 wire [`MGMT_BLOCKS-1:0] user_mgmt_ena;
342 wire [7:0] user_mgmt_addr;
343 wire [(`MGMT_BLOCKS*32)-1:0] user_mgmt_rdata;
344
Ahmed Ghazy22d29d62020-10-28 03:42:02 +0200345 mgmt_core soc (
Tim Edwardsef8312e2020-09-22 17:20:06 -0400346 `ifdef LVS
Manar68e03632020-11-09 13:25:13 +0200347 .vdd1v8(vccd),
Tim Edwards9eda80d2020-10-08 21:36:44 -0400348 .vss(vssa),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400349 `endif
Tim Edwards04ba17f2020-10-02 22:27:50 -0400350 // GPIO (1 pin)
Tim Edwardsef8312e2020-09-22 17:20:06 -0400351 .gpio_out_pad(gpio_out_core),
352 .gpio_in_pad(gpio_in_core),
353 .gpio_mode0_pad(gpio_mode0_core),
354 .gpio_mode1_pad(gpio_mode1_core),
355 .gpio_outenb_pad(gpio_outenb_core),
356 .gpio_inenb_pad(gpio_inenb_core),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400357 // Primary SPI flash controller
Tim Edwardsef8312e2020-09-22 17:20:06 -0400358 .flash_csb(flash_csb_core),
359 .flash_clk(flash_clk_core),
360 .flash_csb_oeb(flash_csb_oeb_core),
361 .flash_clk_oeb(flash_clk_oeb_core),
362 .flash_io0_oeb(flash_io0_oeb_core),
363 .flash_io1_oeb(flash_io1_oeb_core),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400364 .flash_csb_ieb(flash_csb_ieb_core),
365 .flash_clk_ieb(flash_clk_ieb_core),
366 .flash_io0_ieb(flash_io0_ieb_core),
367 .flash_io1_ieb(flash_io1_ieb_core),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400368 .flash_io0_do(flash_io0_do_core),
369 .flash_io1_do(flash_io1_do_core),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400370 .flash_io0_di(flash_io0_di_core),
371 .flash_io1_di(flash_io1_di_core),
Tim Edwardsf51dd082020-10-05 16:30:24 -0400372 // Master Reset
373 .resetb(rstb_l),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400374 .porb(porb_l),
375 // Clocks and reset
Tim Edwardsef8312e2020-09-22 17:20:06 -0400376 .clock(clock_core),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400377 .core_clk(caravel_clk),
Tim Edwards7a8cbb12020-10-12 11:32:11 -0400378 .user_clk(caravel_clk2),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400379 .core_rstn(caravel_rstn),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400380 // Logic Analyzer
381 .la_input(la_data_out_mprj),
382 .la_output(la_output_core),
383 .la_oen(la_oen),
Tim Edwards6d9739d2020-10-19 11:00:49 -0400384 // User Project IO Control
Tim Edwards05ad4fc2020-10-19 22:12:33 -0400385 .mprj_vcc_pwrgood(mprj_vcc_pwrgood),
386 .mprj2_vcc_pwrgood(mprj2_vcc_pwrgood),
387 .mprj_vdd_pwrgood(mprj_vdd_pwrgood),
388 .mprj2_vdd_pwrgood(mprj2_vdd_pwrgood),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400389 .mprj_io_loader_resetn(mprj_io_loader_resetn),
390 .mprj_io_loader_clock(mprj_io_loader_clock),
391 .mprj_io_loader_data(mprj_io_loader_data),
Tim Edwards44bab472020-10-04 22:09:54 -0400392 .mgmt_in_data(mgmt_io_in),
Tim Edwardsca2f3182020-10-06 10:05:11 -0400393 .mgmt_out_data({mgmt_io_in[(`MPRJ_IO_PADS-1):2], mgmt_io_nc2}),
Tim Edwardsba328902020-10-27 15:03:22 -0400394 .pwr_ctrl_out(pwr_ctrl_out),
Tim Edwardsca2f3182020-10-06 10:05:11 -0400395 .sdo_out(sdo_out),
396 .sdo_outenb(sdo_outenb),
397 .jtag_out(jtag_out),
398 .jtag_outenb(jtag_outenb),
Tim Edwards6d9739d2020-10-19 11:00:49 -0400399 // User Project Slave ports (WB MI A)
Tim Edwardsef8312e2020-09-22 17:20:06 -0400400 .mprj_cyc_o(mprj_cyc_o_core),
401 .mprj_stb_o(mprj_stb_o_core),
402 .mprj_we_o(mprj_we_o_core),
403 .mprj_sel_o(mprj_sel_o_core),
404 .mprj_adr_o(mprj_adr_o_core),
405 .mprj_dat_o(mprj_dat_o_core),
406 .mprj_ack_i(mprj_ack_i_core),
407 .mprj_dat_i(mprj_dat_i_core),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400408 // mask data
Manar55ec3692020-10-30 16:32:18 +0200409 .mask_rev(mask_rev),
410 // MGMT area R/W interface for mgmt RAM
411 .mgmt_ena(mgmt_ena),
412 .mgmt_wen_mask(mgmt_wen_mask),
413 .mgmt_wen(mgmt_wen),
414 .mgmt_addr(mgmt_addr),
415 .mgmt_wdata(mgmt_wdata),
416 .mgmt_rdata(mgmt_rdata),
417 // MGMT area RO interface for user RAM
418 .user_ena(mgmt_user_ena),
419 .user_addr(mgmt_user_addr),
420 .user_rdata(mgmt_user_rdata)
Tim Edwardsef8312e2020-09-22 17:20:06 -0400421 );
422
Tim Edwards53d92182020-10-11 21:47:40 -0400423 /* Clock and reset to user space are passed through a tristate */
424 /* buffer like the above, but since they are intended to be */
425 /* always active, connect the enable to the logic-1 output from */
426 /* the vccd1 domain. */
427
Tim Edwards53d92182020-10-11 21:47:40 -0400428 mgmt_protect mgmt_buffers (
Tim Edwards53d92182020-10-11 21:47:40 -0400429 .vccd(vccd),
430 .vssd(vssd),
431 .vccd1(vccd1),
432 .vssd1(vssd1),
Tim Edwards05ad4fc2020-10-19 22:12:33 -0400433 .vdda1(vdda1),
434 .vssa1(vssa1),
435 .vdda2(vdda2),
436 .vssa2(vssa2),
Tim Edwards21a9aac2020-10-12 22:05:18 -0400437
Tim Edwards53d92182020-10-11 21:47:40 -0400438 .caravel_clk(caravel_clk),
Tim Edwards7a8cbb12020-10-12 11:32:11 -0400439 .caravel_clk2(caravel_clk2),
Tim Edwards53d92182020-10-11 21:47:40 -0400440 .caravel_rstn(caravel_rstn),
441 .mprj_cyc_o_core(mprj_cyc_o_core),
442 .mprj_stb_o_core(mprj_stb_o_core),
443 .mprj_we_o_core(mprj_we_o_core),
444 .mprj_sel_o_core(mprj_sel_o_core),
445 .mprj_adr_o_core(mprj_adr_o_core),
446 .mprj_dat_o_core(mprj_dat_o_core),
447 .la_output_core(la_output_core),
448 .la_oen(la_oen),
449
450 .user_clock(mprj_clock),
Tim Edwards7a8cbb12020-10-12 11:32:11 -0400451 .user_clock2(mprj_clock2),
Tim Edwards53d92182020-10-11 21:47:40 -0400452 .user_resetn(mprj_resetn),
453 .mprj_cyc_o_user(mprj_cyc_o_user),
454 .mprj_stb_o_user(mprj_stb_o_user),
455 .mprj_we_o_user(mprj_we_o_user),
456 .mprj_sel_o_user(mprj_sel_o_user),
457 .mprj_adr_o_user(mprj_adr_o_user),
458 .mprj_dat_o_user(mprj_dat_o_user),
Tim Edwards32d05422020-10-19 19:43:52 -0400459 .la_data_in_mprj(la_data_in_mprj),
Tim Edwards05ad4fc2020-10-19 22:12:33 -0400460 .user1_vcc_powergood(mprj_vcc_pwrgood),
461 .user2_vcc_powergood(mprj2_vcc_pwrgood),
462 .user1_vdd_powergood(mprj_vdd_pwrgood),
463 .user2_vdd_powergood(mprj2_vdd_pwrgood)
Tim Edwardsef8312e2020-09-22 17:20:06 -0400464 );
Tim Edwards53d92182020-10-11 21:47:40 -0400465
Tim Edwardsef8312e2020-09-22 17:20:06 -0400466
Tim Edwardsb86fc842020-10-13 17:11:54 -0400467 /*----------------------------------------------*/
468 /* Wrapper module around the user project */
469 /*----------------------------------------------*/
Tim Edwards05537512020-10-06 14:59:26 -0400470
Ahmed Ghazy22d29d62020-10-28 03:42:02 +0200471 user_project_wrapper mprj (
Tim Edwards21a9aac2020-10-12 22:05:18 -0400472 .vdda1(vdda1), // User area 1 3.3V power
473 .vdda2(vdda2), // User area 2 3.3V power
474 .vssa1(vssa1), // User area 1 analog ground
475 .vssa2(vssa2), // User area 2 analog ground
476 .vccd1(vccd1), // User area 1 1.8V power
477 .vccd2(vccd2), // User area 2 1.8V power
478 .vssd1(vssd1), // User area 1 digital ground
479 .vssd2(vssd2), // User area 2 digital ground
480
Tim Edwards53d92182020-10-11 21:47:40 -0400481 .wb_clk_i(mprj_clock),
482 .wb_rst_i(!mprj_resetn),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400483 // MGMT SoC Wishbone Slave
Tim Edwards53d92182020-10-11 21:47:40 -0400484 .wbs_cyc_i(mprj_cyc_o_user),
485 .wbs_stb_i(mprj_stb_o_user),
486 .wbs_we_i(mprj_we_o_user),
487 .wbs_sel_i(mprj_sel_o_user),
488 .wbs_adr_i(mprj_adr_o_user),
489 .wbs_dat_i(mprj_dat_o_user),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400490 .wbs_ack_o(mprj_ack_i_core),
491 .wbs_dat_o(mprj_dat_i_core),
492 // Logic Analyzer
493 .la_data_in(la_data_in_mprj),
494 .la_data_out(la_data_out_mprj),
495 .la_oen (la_oen),
496 // IO Pads
Tim Edwards05537512020-10-06 14:59:26 -0400497 .io_in (user_io_in),
Tim Edwardsef2b68d2020-10-11 17:00:44 -0400498 .io_out(user_io_out),
Tim Edwardsb86fc842020-10-13 17:11:54 -0400499 .io_oeb(user_io_oeb),
500 // Independent clock
501 .user_clock2(mprj_clock2)
Tim Edwardsef8312e2020-09-22 17:20:06 -0400502 );
503
Tim Edwards05537512020-10-06 14:59:26 -0400504 /*--------------------------------------*/
505 /* End user project instantiation */
506 /*--------------------------------------*/
507
Tim Edwards04ba17f2020-10-02 22:27:50 -0400508 wire [`MPRJ_IO_PADS-1:0] gpio_serial_link_shifted;
509
Tim Edwards251e0df2020-10-05 11:02:12 -0400510 assign gpio_serial_link_shifted = {gpio_serial_link[`MPRJ_IO_PADS-2:0], mprj_io_loader_data};
Tim Edwards04ba17f2020-10-02 22:27:50 -0400511
Tim Edwards251e0df2020-10-05 11:02:12 -0400512 // Each control block sits next to an I/O pad in the user area.
513 // It gets input through a serial chain from the previous control
514 // block and passes it to the next control block. Due to the nature
515 // of the shift register, bits are presented in reverse, as the first
516 // bit in ends up as the last bit of the last I/O pad control block.
Tim Edwards44bab472020-10-04 22:09:54 -0400517
Tim Edwards89f09242020-10-05 15:17:34 -0400518 // There are two types of block; the first two are configured to be
519 // full bidirectional under control of the management Soc (JTAG and
520 // SDO). The rest are configured to be default (input).
521
Tim Edwards251e0df2020-10-05 11:02:12 -0400522 gpio_control_block #(
Tim Edwards89f09242020-10-05 15:17:34 -0400523 .DM_INIT(3'b110), // Mode = output, strong up/down
Tim Edwards496a08a2020-10-26 15:44:51 -0400524 .OENB_INIT(1'b1) // Enable output signaling from wire
Tim Edwards89f09242020-10-05 15:17:34 -0400525 ) gpio_control_bidir [1:0] (
Tim Edwards53d92182020-10-11 21:47:40 -0400526 `ifdef LVS
Manar68e03632020-11-09 13:25:13 +0200527 .vccd(vccd),
528 .vssd(vssd),
529 .vccd1(vccd1),
530 .vssd1(vssd1),
Tim Edwards53d92182020-10-11 21:47:40 -0400531 `endif
Tim Edwards44bab472020-10-04 22:09:54 -0400532
Tim Edwards04ba17f2020-10-02 22:27:50 -0400533 // Management Soc-facing signals
534
Tim Edwardsc18c4742020-10-03 11:26:39 -0400535 .resetn(mprj_io_loader_resetn),
536 .serial_clock(mprj_io_loader_clock),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400537
Tim Edwards89f09242020-10-05 15:17:34 -0400538 .mgmt_gpio_in(mgmt_io_in[1:0]),
539 .mgmt_gpio_out({sdo_out, jtag_out}),
540 .mgmt_gpio_oeb({sdo_outenb, jtag_outenb}),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400541
542 // Serial data chain for pad configuration
Tim Edwards89f09242020-10-05 15:17:34 -0400543 .serial_data_in(gpio_serial_link_shifted[1:0]),
544 .serial_data_out(gpio_serial_link[1:0]),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400545
546 // User-facing signals
Tim Edwards89f09242020-10-05 15:17:34 -0400547 .user_gpio_out(user_io_out[1:0]),
548 .user_gpio_oeb(user_io_oeb[1:0]),
549 .user_gpio_in(user_io_in[1:0]),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400550
551 // Pad-facing signals (Pad GPIOv2)
Tim Edwards89f09242020-10-05 15:17:34 -0400552 .pad_gpio_inenb(mprj_io_inp_dis[1:0]),
553 .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[1:0]),
554 .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[1:0]),
555 .pad_gpio_slow_sel(mprj_io_slow_sel[1:0]),
556 .pad_gpio_holdover(mprj_io_holdover[1:0]),
557 .pad_gpio_ana_en(mprj_io_analog_en[1:0]),
558 .pad_gpio_ana_sel(mprj_io_analog_sel[1:0]),
559 .pad_gpio_ana_pol(mprj_io_analog_pol[1:0]),
560 .pad_gpio_dm(mprj_io_dm[5:0]),
561 .pad_gpio_outenb(mprj_io_oeb[1:0]),
562 .pad_gpio_out(mprj_io_out[1:0]),
563 .pad_gpio_in(mprj_io_in[1:0])
564 );
565
566 gpio_control_block gpio_control_in [`MPRJ_IO_PADS-1:2] (
Tim Edwards53d92182020-10-11 21:47:40 -0400567 `ifdef LVS
Manar68e03632020-11-09 13:25:13 +0200568 .vccd(vccd),
569 .vssd(vssd),
570 .vccd1(vccd1),
571 .vssd1(vssd1),
Tim Edwards53d92182020-10-11 21:47:40 -0400572 `endif
Tim Edwards89f09242020-10-05 15:17:34 -0400573
574 // Management Soc-facing signals
575
576 .resetn(mprj_io_loader_resetn),
577 .serial_clock(mprj_io_loader_clock),
578
579 .mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-1):2]),
580 .mgmt_gpio_out(mgmt_io_in[(`MPRJ_IO_PADS-1):2]),
581 .mgmt_gpio_oeb(1'b1),
582
583 // Serial data chain for pad configuration
584 .serial_data_in(gpio_serial_link_shifted[(`MPRJ_IO_PADS-1):2]),
585 .serial_data_out(gpio_serial_link[(`MPRJ_IO_PADS-1):2]),
586
587 // User-facing signals
588 .user_gpio_out(user_io_out[(`MPRJ_IO_PADS-1):2]),
589 .user_gpio_oeb(user_io_oeb[(`MPRJ_IO_PADS-1):2]),
590 .user_gpio_in(user_io_in[(`MPRJ_IO_PADS-1):2]),
591
592 // Pad-facing signals (Pad GPIOv2)
593 .pad_gpio_inenb(mprj_io_inp_dis[(`MPRJ_IO_PADS-1):2]),
594 .pad_gpio_ib_mode_sel(mprj_io_ib_mode_sel[(`MPRJ_IO_PADS-1):2]),
595 .pad_gpio_vtrip_sel(mprj_io_vtrip_sel[(`MPRJ_IO_PADS-1):2]),
596 .pad_gpio_slow_sel(mprj_io_slow_sel[(`MPRJ_IO_PADS-1):2]),
597 .pad_gpio_holdover(mprj_io_holdover[(`MPRJ_IO_PADS-1):2]),
598 .pad_gpio_ana_en(mprj_io_analog_en[(`MPRJ_IO_PADS-1):2]),
599 .pad_gpio_ana_sel(mprj_io_analog_sel[(`MPRJ_IO_PADS-1):2]),
600 .pad_gpio_ana_pol(mprj_io_analog_pol[(`MPRJ_IO_PADS-1):2]),
601 .pad_gpio_dm(mprj_io_dm[(`MPRJ_IO_PADS*3-1):6]),
602 .pad_gpio_outenb(mprj_io_oeb[(`MPRJ_IO_PADS-1):2]),
603 .pad_gpio_out(mprj_io_out[(`MPRJ_IO_PADS-1):2]),
604 .pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS-1):2])
Tim Edwards04ba17f2020-10-02 22:27:50 -0400605 );
606
Tim Edwardsf51dd082020-10-05 16:30:24 -0400607 sky130_fd_sc_hvl__lsbufhv2lv porb_level (
Tim Edwards21a9aac2020-10-12 22:05:18 -0400608 .VPWR(vddio),
609 .VPB(vddio),
610 .LVPWR(vccd),
611 .VNB(vssio),
612 .VGND(vssio),
Tim Edwardsef8312e2020-09-22 17:20:06 -0400613 .A(porb_h),
614 .X(porb_l)
615 );
616
Tim Edwards04ba17f2020-10-02 22:27:50 -0400617 user_id_programming #(
618 .USER_PROJECT_ID(USER_PROJECT_ID)
619 ) user_id_value (
Tim Edwards21a9aac2020-10-12 22:05:18 -0400620 .vdd1v8(vccd),
621 .vss(vssd),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400622 .mask_rev(mask_rev)
623 );
624
Tim Edwardsf51dd082020-10-05 16:30:24 -0400625 // Power-on-reset circuit
626 simple_por por (
Tim Edwards9eda80d2020-10-08 21:36:44 -0400627 .vdd3v3(vddio),
628 .vss(vssio),
Tim Edwardsf51dd082020-10-05 16:30:24 -0400629 .porb_h(porb_h)
630 );
631
632 // XRES (chip input pin reset) reset level converter
633 sky130_fd_sc_hvl__lsbufhv2lv rstb_level (
Tim Edwards21a9aac2020-10-12 22:05:18 -0400634 .VPWR(vddio),
635 .VPB(vddio),
636 .LVPWR(vccd),
637 .VNB(vssio),
638 .VGND(vssio),
Tim Edwardsf51dd082020-10-05 16:30:24 -0400639 .A(rstb_h),
640 .X(rstb_l)
641 );
642
Manar55ec3692020-10-30 16:32:18 +0200643 // Storage area
644 storage #(
645 .MGMT_BLOCKS(`MGMT_BLOCKS),
646 .USER_BLOCKS(`USER_BLOCKS)
647 ) storage(
648 .mgmt_clk(caravel_clk),
649 .mgmt_ena(mgmt_ena),
650 .mgmt_wen(mgmt_wen),
651 .mgmt_wen_mask(mgmt_wen_mask),
652 .mgmt_addr(mgmt_addr),
653 .mgmt_wdata(mgmt_wdata),
654 .mgmt_rdata(mgmt_rdata),
655 // Management RO interface
656 .mgmt_user_ena(mgmt_user_ena),
657 .mgmt_user_addr(mgmt_user_addr),
658 .mgmt_user_rdata(mgmt_user_rdata),
659
660 // User R/W interface
661 .user_clk(caravel_clk2),
662 .user_ena(user_ena),
663 .user_wen(user_wen),
664 .user_wen_mask(user_wen_mask),
665 .user_addr(user_addr),
666 .user_wdata(user_wdata),
667 .user_rdata(user_rdata),
668 // User RO interface
669 .user_mgmt_ena(user_mgmt_ena),
670 .user_mgmt_addr(user_mgmt_addr),
671 .user_mgmt_rdata(user_mgmt_rdata)
672 );
673
Tim Edwardsef8312e2020-09-22 17:20:06 -0400674endmodule