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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-034 / 9eda80dd074325b1d42354785b1aece24ce83017 / . / verilog / rtl / pads.v
blob: b17bf1d18031a0a8744ee7d0f254eecc89c6ac1b [file] [log] [blame]
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]1`ifndef TOP_ROUTING
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame^]2 `define USER1_ABUTMENT_PINS \
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]3 .amuxbus_a(analog_a),\
4 .amuxbus_b(analog_b),\
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame^]5 .vssa(vssa1),\
6 .vdda(vdda1),\
7 .vswitch(vddio),\
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]8 .vddio_q(vddio_q),\
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame^]9 .vcchib(vccd),\
10 .vddio(vddio),\
11 .vccd(vccd1),\
12 .vssio(vssio),\
13 .vssd(vssd1),\
14 .vssio_q(vssio_q),
15
16 `define USER2_ABUTMENT_PINS \
17 .amuxbus_a(analog_a),\
18 .amuxbus_b(analog_b),\
19 .vssa(vssa2),\
20 .vdda(vdda2),\
21 .vswitch(vddio),\
22 .vddio_q(vddio_q),\
23 .vcchib(vccd),\
24 .vddio(vddio),\
25 .vccd(vccd2),\
26 .vssio(vssio),\
27 .vssd(vssd2),\
28 .vssio_q(vssio_q),
29
30 `define MGMT_ABUTMENT_PINS \
31 .amuxbus_a(analog_a),\
32 .amuxbus_b(analog_b),\
33 .vssa(vssa),\
34 .vdda(vdda),\
35 .vswitch(vddio),\
36 .vddio_q(vddio_q),\
37 .vcchib(vccd),\
38 .vddio(vddio),\
39 .vccd(vccd),\
40 .vssio(vssio),\
41 .vssd(vssa),\
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]42 .vssio_q(vssio_q),
43`else
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame^]44 `define USER1_ABUTMENT_PINS
45 `define USER2_ABUTMENT_PINS
46 `define MGMT_ABUTMENT_PINS
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]47`endif
48
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame^]49`define HVCLAMP_PINS \
50 .drn_hvc(), \
51 .src_bdy_hvc()
52
53`define LVCLAMP_PINS \
54 .bdy2_b2b(), \
55 .drn_lvc1(), \
56 .drn_lvc2(), \
57 .src_bdy_lvc1(), \
58 .src_bdy_lvc2()
59
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]60`define INPUT_PAD(X,Y) \
61 wire loop_``X; \
62 s8iom0_gpiov2_pad X``_pad ( \
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame^]63 `MGMT_ABUTMENT_PINS \
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]64 `ifndef TOP_ROUTING \
65 .pad(X), \
66 `endif \
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame^]67 .out(vssa), \
68 .oe_n(vccd), \
69 .hld_h_n(vddio), \
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]70 .enable_h(porb_h), \
71 .enable_inp_h(loop_``X), \
72 .enable_vdda_h(porb_h), \
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame^]73 .enable_vswitch_h(vssa), \
74 .enable_vddio(vccd), \
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]75 .inp_dis(por), \
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame^]76 .ib_mode_sel(vssa), \
77 .vtrip_sel(vssa), \
78 .slow(vssa), \
79 .hld_ovr(vssa), \
80 .analog_en(vssa), \
81 .analog_sel(vssa), \
82 .analog_pol(vssa), \
83 .dm({vssa, vssa, vccd}), \
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]84 .pad_a_noesd_h(), \
85 .pad_a_esd_0_h(), \
86 .pad_a_esd_1_h(), \
87 .in(Y), \
88 .in_h(), \
89 .tie_hi_esd(), \
90 .tie_lo_esd(loop_``X) )
91
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]92`define OUTPUT_PAD(X,Y,INP_DIS,OUT_EN_N) \
93 wire loop_``X; \
94 s8iom0_gpiov2_pad X``_pad ( \
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame^]95 `MGMT_ABUTMENT_PINS \
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]96 `ifndef TOP_ROUTING \
97 .pad(X), \
98 `endif \
99 .out(Y), \
100 .oe_n(OUT_EN_N), \
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame^]101 .hld_h_n(vddio), \
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]102 .enable_h(porb_h), \
103 .enable_inp_h(loop_``X), \
104 .enable_vdda_h(porb_h), \
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame^]105 .enable_vswitch_h(vssa), \
106 .enable_vddio(vccd), \
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]107 .inp_dis(INP_DIS), \
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame^]108 .ib_mode_sel(vssa), \
109 .vtrip_sel(vssa), \
110 .slow(vssa), \
111 .hld_ovr(vssa), \
112 .analog_en(vssa), \
113 .analog_sel(vssa), \
114 .analog_pol(vssa), \
115 .dm({vccd, vccd, vssa}), \
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]116 .pad_a_noesd_h(), \
117 .pad_a_esd_0_h(), \
118 .pad_a_esd_1_h(), \
119 .in(), \
120 .in_h(), \
121 .tie_hi_esd(), \
122 .tie_lo_esd(loop_``X))
123
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]124`define INOUT_PAD(X,Y,Y_OUT,INP_DIS,OUT_EN_N,MODE) \
125 s8iom0_gpiov2_pad X``_pad ( \
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame^]126 `MGMT_ABUTMENT_PINS \
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]127 `ifndef TOP_ROUTING \
128 .pad(X),\
129 `endif \
130 .out(Y_OUT), \
131 .oe_n(OUT_EN_N), \
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame^]132 .hld_h_n(vddio), \
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]133 .enable_h(porb_h), \
134 .enable_inp_h(loop_``X), \
135 .enable_vdda_h(porb_h), \
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame^]136 .enable_vswitch_h(vssa), \
137 .enable_vddio(vccd), \
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]138 .inp_dis(INP_DIS), \
Tim Edwards9eda80d2020-10-08 21:36:44 -0400[diff] [blame^]139 .ib_mode_sel(vssa), \
140 .vtrip_sel(vssa), \
141 .slow(vssa), \
142 .hld_ovr(vssa), \
143 .analog_en(vssa), \
144 .analog_sel(vssa), \
145 .analog_pol(vssa), \
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]146 .dm(MODE), \
147 .pad_a_noesd_h(), \
148 .pad_a_esd_0_h(), \
149 .pad_a_esd_1_h(), \
150 .in(Y), \
151 .in_h(), \
152 .tie_hi_esd(), \
153 .tie_lo_esd(loop_``X) )
154