| Ahmed Ghazy | 7215439 | 2020-11-11 14:56:52 +0200 | [diff] [blame^] | 1 | # This is an analog design. It will be designed by hand. |
| 2 | # This is a placeholder to get things going. |
| 3 | set script_dir [file dirname [file normalize [info script]]] |
| 4 | # User config |
| 5 | set ::env(DESIGN_NAME) simple_por |
| 6 | set ::env(STD_CELL_LIBRARY) sky130_fd_sc_hvl |
| 7 | |
| 8 | # Change if needed |
| 9 | set ::env(VERILOG_FILES) $script_dir/../../verilog/rtl/simple_por.v |
| 10 | set ::env(SYNTH_READ_BLACKBOX_LIB) 1 |
| 11 | |
| 12 | # Fill this |
| 13 | set ::env(CLOCK_TREE_SYNTH) 0 |
| 14 | |
| 15 | set ::env(CELL_PAD) 8 |
| 16 | |
| 17 | set ::env(FP_CORE_UTIL) 30 |
| 18 | set ::env(PL_TARGET_DENSITY) 0.5 |
