blob: 6c2d37655fede207a746b172ee7430313f10d33e [file] [log] [blame]
shalanfd13eb52020-08-21 16:48:07 +02001module sysctrl_wb #(
Tim Edwards32d05422020-10-19 19:43:52 -04002 parameter BASE_ADR = 32'h2F00_0000,
3 parameter PWRGOOD = 8'h00,
4 parameter CLK_OUT = 8'h04,
5 parameter TRAP_OUT = 8'h08,
6 parameter IRQ_SRC = 8'h0c
shalanfd13eb52020-08-21 16:48:07 +02007) (
8 input wb_clk_i,
9 input wb_rst_i,
10
11 input [31:0] wb_dat_i,
12 input [31:0] wb_adr_i,
13 input [3:0] wb_sel_i,
14 input wb_cyc_i,
15 input wb_stb_i,
16 input wb_we_i,
17
18 output [31:0] wb_dat_o,
19 output wb_ack_o,
20
Tim Edwards05ad4fc2020-10-19 22:12:33 -040021 input usr1_vcc_pwrgood,
22 input usr2_vcc_pwrgood,
23 input usr1_vdd_pwrgood,
24 input usr2_vdd_pwrgood,
Tim Edwards32d05422020-10-19 19:43:52 -040025 output clk1_output_dest,
26 output clk2_output_dest,
Tim Edwardsef8312e2020-09-22 17:20:06 -040027 output trap_output_dest,
Tim Edwards32d05422020-10-19 19:43:52 -040028 output irq_7_inputsrc,
29 output irq_8_inputsrc
shalanfd13eb52020-08-21 16:48:07 +020030
31);
32
33 wire resetn;
34 wire valid;
35 wire ready;
36 wire [3:0] iomem_we;
37
38 assign resetn = ~wb_rst_i;
39 assign valid = wb_stb_i && wb_cyc_i;
40
41 assign iomem_we = wb_sel_i & {4{wb_we_i}};
42 assign wb_ack_o = ready;
43
44 sysctrl #(
45 .BASE_ADR(BASE_ADR),
Tim Edwards32d05422020-10-19 19:43:52 -040046 .PWRGOOD(PWRGOOD),
47 .CLK_OUT(CLK_OUT),
shalanfd13eb52020-08-21 16:48:07 +020048 .TRAP_OUT(TRAP_OUT),
Tim Edwards32d05422020-10-19 19:43:52 -040049 .IRQ_SRC(IRQ_SRC)
shalanfd13eb52020-08-21 16:48:07 +020050 ) sysctrl (
51 .clk(wb_clk_i),
52 .resetn(resetn),
53
shalanfd13eb52020-08-21 16:48:07 +020054 .iomem_addr(wb_adr_i),
55 .iomem_valid(valid),
56 .iomem_wstrb(iomem_we),
57 .iomem_wdata(wb_dat_i),
58 .iomem_rdata(wb_dat_o),
59 .iomem_ready(ready),
60
Tim Edwards05ad4fc2020-10-19 22:12:33 -040061 .usr1_vcc_pwrgood(usr1_vcc_pwrgood),
62 .usr2_vcc_pwrgood(usr2_vcc_pwrgood),
63 .usr1_vdd_pwrgood(usr1_vdd_pwrgood),
64 .usr2_vdd_pwrgood(usr2_vdd_pwrgood),
Tim Edwards32d05422020-10-19 19:43:52 -040065 .clk1_output_dest(clk1_output_dest),
66 .clk2_output_dest(clk2_output_dest),
shalanfd13eb52020-08-21 16:48:07 +020067 .trap_output_dest(trap_output_dest),
Tim Edwards32d05422020-10-19 19:43:52 -040068 .irq_8_inputsrc(irq_8_inputsrc),
Tim Edwards04ba17f2020-10-02 22:27:50 -040069 .irq_7_inputsrc(irq_7_inputsrc)
shalanfd13eb52020-08-21 16:48:07 +020070 );
71
72endmodule
73
74module sysctrl #(
75 parameter BASE_ADR = 32'h2300_0000,
Tim Edwards32d05422020-10-19 19:43:52 -040076 parameter PWRGOOD = 8'h00,
77 parameter CLK_OUT = 8'h04,
78 parameter TRAP_OUT = 8'h08,
79 parameter IRQ_SRC = 8'h0c
shalanfd13eb52020-08-21 16:48:07 +020080) (
81 input clk,
82 input resetn,
83
shalanfd13eb52020-08-21 16:48:07 +020084 input [31:0] iomem_addr,
85 input iomem_valid,
86 input [3:0] iomem_wstrb,
87 input [31:0] iomem_wdata,
88 output reg [31:0] iomem_rdata,
89 output reg iomem_ready,
90
Tim Edwards05ad4fc2020-10-19 22:12:33 -040091 input usr1_vcc_pwrgood,
92 input usr2_vcc_pwrgood,
93 input usr1_vdd_pwrgood,
94 input usr2_vdd_pwrgood,
Tim Edwards32d05422020-10-19 19:43:52 -040095 output clk1_output_dest,
96 output clk2_output_dest,
Tim Edwardsef8312e2020-09-22 17:20:06 -040097 output trap_output_dest,
Tim Edwards32d05422020-10-19 19:43:52 -040098 output irq_7_inputsrc,
99 output irq_8_inputsrc
shalanfd13eb52020-08-21 16:48:07 +0200100);
shalanfd13eb52020-08-21 16:48:07 +0200101
Tim Edwards32d05422020-10-19 19:43:52 -0400102 reg clk1_output_dest;
103 reg clk2_output_dest;
Tim Edwardsef8312e2020-09-22 17:20:06 -0400104 reg trap_output_dest;
105 reg irq_7_inputsrc;
Tim Edwards32d05422020-10-19 19:43:52 -0400106 reg irq_8_inputsrc;
Tim Edwardsef8312e2020-09-22 17:20:06 -0400107
Tim Edwards05ad4fc2020-10-19 22:12:33 -0400108 wire usr1_vcc_pwrgood;
109 wire usr2_vcc_pwrgood;
110 wire usr1_vdd_pwrgood;
111 wire usr2_vdd_pwrgood;
Tim Edwards32d05422020-10-19 19:43:52 -0400112
113 assign pwrgood_sel = (iomem_addr[7:0] == PWRGOOD);
114 assign clk_out_sel = (iomem_addr[7:0] == CLK_OUT);
shalanfd13eb52020-08-21 16:48:07 +0200115 assign trap_out_sel = (iomem_addr[7:0] == TRAP_OUT);
Tim Edwards32d05422020-10-19 19:43:52 -0400116 assign irq_sel = (iomem_addr[7:0] == IRQ_SRC);
shalanfd13eb52020-08-21 16:48:07 +0200117
shalanfd13eb52020-08-21 16:48:07 +0200118 always @(posedge clk) begin
119 if (!resetn) begin
Tim Edwards32d05422020-10-19 19:43:52 -0400120 clk1_output_dest <= 0;
121 clk2_output_dest <= 0;
shalanfd13eb52020-08-21 16:48:07 +0200122 trap_output_dest <= 0;
123 irq_7_inputsrc <= 0;
Tim Edwards32d05422020-10-19 19:43:52 -0400124 irq_8_inputsrc <= 0;
shalanfd13eb52020-08-21 16:48:07 +0200125 end else begin
126 iomem_ready <= 0;
127 if (iomem_valid && !iomem_ready && iomem_addr[31:8] == BASE_ADR[31:8]) begin
128 iomem_ready <= 1'b 1;
129
Tim Edwards32d05422020-10-19 19:43:52 -0400130 if (pwrgood_sel) begin
Tim Edwards05ad4fc2020-10-19 22:12:33 -0400131 iomem_rdata <= {28'd0, usr2_vdd_pwrgood, usr1_vdd_pwrgood,
132 usr2_vcc_pwrgood, usr1_vcc_pwrgood};
Tim Edwards32d05422020-10-19 19:43:52 -0400133 // These are read-only bits; no write behavior on wstrb.
134
135 end else if (clk_out_sel) begin
136 iomem_rdata <= {30'd0, clk2_output_dest, clk1_output_dest};
137 if (iomem_wstrb[0]) begin
138 clk1_output_dest <= iomem_wdata[0];
139 clk2_output_dest <= iomem_wdata[1];
140 end
shalanfd13eb52020-08-21 16:48:07 +0200141
142 end else if (trap_out_sel) begin
Tim Edwardsef8312e2020-09-22 17:20:06 -0400143 iomem_rdata <= {31'd0, trap_output_dest};
shalanfd13eb52020-08-21 16:48:07 +0200144 if (iomem_wstrb[0])
Tim Edwardsef8312e2020-09-22 17:20:06 -0400145 trap_output_dest <= iomem_wdata[0];
shalanfd13eb52020-08-21 16:48:07 +0200146
Tim Edwards32d05422020-10-19 19:43:52 -0400147 end else if (irq_sel) begin
148 iomem_rdata <= {30'd0, irq_8_inputsrc, irq_7_inputsrc};
149 if (iomem_wstrb[0]) begin
Tim Edwardsef8312e2020-09-22 17:20:06 -0400150 irq_7_inputsrc <= iomem_wdata[0];
Tim Edwards32d05422020-10-19 19:43:52 -0400151 irq_8_inputsrc <= iomem_wdata[1];
152 end
shalanfd13eb52020-08-21 16:48:07 +0200153 end
154 end
155 end
156 end
157
Tim Edwardsef8312e2020-09-22 17:20:06 -0400158endmodule