shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 1 | module sysctrl_wb #( |
Tim Edwards | 32d0542 | 2020-10-19 19:43:52 -0400 | [diff] [blame] | 2 | parameter BASE_ADR = 32'h2F00_0000, |
| 3 | parameter PWRGOOD = 8'h00, |
| 4 | parameter CLK_OUT = 8'h04, |
| 5 | parameter TRAP_OUT = 8'h08, |
| 6 | parameter IRQ_SRC = 8'h0c |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 7 | ) ( |
| 8 | input wb_clk_i, |
| 9 | input wb_rst_i, |
| 10 | |
| 11 | input [31:0] wb_dat_i, |
| 12 | input [31:0] wb_adr_i, |
| 13 | input [3:0] wb_sel_i, |
| 14 | input wb_cyc_i, |
| 15 | input wb_stb_i, |
| 16 | input wb_we_i, |
| 17 | |
| 18 | output [31:0] wb_dat_o, |
| 19 | output wb_ack_o, |
| 20 | |
Tim Edwards | 05ad4fc | 2020-10-19 22:12:33 -0400 | [diff] [blame] | 21 | input usr1_vcc_pwrgood, |
| 22 | input usr2_vcc_pwrgood, |
| 23 | input usr1_vdd_pwrgood, |
| 24 | input usr2_vdd_pwrgood, |
Tim Edwards | 32d0542 | 2020-10-19 19:43:52 -0400 | [diff] [blame] | 25 | output clk1_output_dest, |
| 26 | output clk2_output_dest, |
Tim Edwards | ef8312e | 2020-09-22 17:20:06 -0400 | [diff] [blame] | 27 | output trap_output_dest, |
Tim Edwards | 32d0542 | 2020-10-19 19:43:52 -0400 | [diff] [blame] | 28 | output irq_7_inputsrc, |
| 29 | output irq_8_inputsrc |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 30 | |
| 31 | ); |
| 32 | |
| 33 | wire resetn; |
| 34 | wire valid; |
| 35 | wire ready; |
| 36 | wire [3:0] iomem_we; |
| 37 | |
| 38 | assign resetn = ~wb_rst_i; |
| 39 | assign valid = wb_stb_i && wb_cyc_i; |
| 40 | |
| 41 | assign iomem_we = wb_sel_i & {4{wb_we_i}}; |
| 42 | assign wb_ack_o = ready; |
| 43 | |
| 44 | sysctrl #( |
| 45 | .BASE_ADR(BASE_ADR), |
Tim Edwards | 32d0542 | 2020-10-19 19:43:52 -0400 | [diff] [blame] | 46 | .PWRGOOD(PWRGOOD), |
| 47 | .CLK_OUT(CLK_OUT), |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 48 | .TRAP_OUT(TRAP_OUT), |
Tim Edwards | 32d0542 | 2020-10-19 19:43:52 -0400 | [diff] [blame] | 49 | .IRQ_SRC(IRQ_SRC) |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 50 | ) sysctrl ( |
| 51 | .clk(wb_clk_i), |
| 52 | .resetn(resetn), |
| 53 | |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 54 | .iomem_addr(wb_adr_i), |
| 55 | .iomem_valid(valid), |
| 56 | .iomem_wstrb(iomem_we), |
| 57 | .iomem_wdata(wb_dat_i), |
| 58 | .iomem_rdata(wb_dat_o), |
| 59 | .iomem_ready(ready), |
| 60 | |
Tim Edwards | 05ad4fc | 2020-10-19 22:12:33 -0400 | [diff] [blame] | 61 | .usr1_vcc_pwrgood(usr1_vcc_pwrgood), |
| 62 | .usr2_vcc_pwrgood(usr2_vcc_pwrgood), |
| 63 | .usr1_vdd_pwrgood(usr1_vdd_pwrgood), |
| 64 | .usr2_vdd_pwrgood(usr2_vdd_pwrgood), |
Tim Edwards | 32d0542 | 2020-10-19 19:43:52 -0400 | [diff] [blame] | 65 | .clk1_output_dest(clk1_output_dest), |
| 66 | .clk2_output_dest(clk2_output_dest), |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 67 | .trap_output_dest(trap_output_dest), |
Tim Edwards | 32d0542 | 2020-10-19 19:43:52 -0400 | [diff] [blame] | 68 | .irq_8_inputsrc(irq_8_inputsrc), |
Tim Edwards | 04ba17f | 2020-10-02 22:27:50 -0400 | [diff] [blame] | 69 | .irq_7_inputsrc(irq_7_inputsrc) |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 70 | ); |
| 71 | |
| 72 | endmodule |
| 73 | |
| 74 | module sysctrl #( |
| 75 | parameter BASE_ADR = 32'h2300_0000, |
Tim Edwards | 32d0542 | 2020-10-19 19:43:52 -0400 | [diff] [blame] | 76 | parameter PWRGOOD = 8'h00, |
| 77 | parameter CLK_OUT = 8'h04, |
| 78 | parameter TRAP_OUT = 8'h08, |
| 79 | parameter IRQ_SRC = 8'h0c |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 80 | ) ( |
| 81 | input clk, |
| 82 | input resetn, |
| 83 | |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 84 | input [31:0] iomem_addr, |
| 85 | input iomem_valid, |
| 86 | input [3:0] iomem_wstrb, |
| 87 | input [31:0] iomem_wdata, |
| 88 | output reg [31:0] iomem_rdata, |
| 89 | output reg iomem_ready, |
| 90 | |
Tim Edwards | 05ad4fc | 2020-10-19 22:12:33 -0400 | [diff] [blame] | 91 | input usr1_vcc_pwrgood, |
| 92 | input usr2_vcc_pwrgood, |
| 93 | input usr1_vdd_pwrgood, |
| 94 | input usr2_vdd_pwrgood, |
Tim Edwards | 32d0542 | 2020-10-19 19:43:52 -0400 | [diff] [blame] | 95 | output clk1_output_dest, |
| 96 | output clk2_output_dest, |
Tim Edwards | ef8312e | 2020-09-22 17:20:06 -0400 | [diff] [blame] | 97 | output trap_output_dest, |
Tim Edwards | 32d0542 | 2020-10-19 19:43:52 -0400 | [diff] [blame] | 98 | output irq_7_inputsrc, |
| 99 | output irq_8_inputsrc |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 100 | ); |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 101 | |
Tim Edwards | 32d0542 | 2020-10-19 19:43:52 -0400 | [diff] [blame] | 102 | reg clk1_output_dest; |
| 103 | reg clk2_output_dest; |
Tim Edwards | ef8312e | 2020-09-22 17:20:06 -0400 | [diff] [blame] | 104 | reg trap_output_dest; |
| 105 | reg irq_7_inputsrc; |
Tim Edwards | 32d0542 | 2020-10-19 19:43:52 -0400 | [diff] [blame] | 106 | reg irq_8_inputsrc; |
Tim Edwards | ef8312e | 2020-09-22 17:20:06 -0400 | [diff] [blame] | 107 | |
Tim Edwards | 05ad4fc | 2020-10-19 22:12:33 -0400 | [diff] [blame] | 108 | wire usr1_vcc_pwrgood; |
| 109 | wire usr2_vcc_pwrgood; |
| 110 | wire usr1_vdd_pwrgood; |
| 111 | wire usr2_vdd_pwrgood; |
Tim Edwards | 32d0542 | 2020-10-19 19:43:52 -0400 | [diff] [blame] | 112 | |
| 113 | assign pwrgood_sel = (iomem_addr[7:0] == PWRGOOD); |
| 114 | assign clk_out_sel = (iomem_addr[7:0] == CLK_OUT); |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 115 | assign trap_out_sel = (iomem_addr[7:0] == TRAP_OUT); |
Tim Edwards | 32d0542 | 2020-10-19 19:43:52 -0400 | [diff] [blame] | 116 | assign irq_sel = (iomem_addr[7:0] == IRQ_SRC); |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 117 | |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 118 | always @(posedge clk) begin |
| 119 | if (!resetn) begin |
Tim Edwards | 32d0542 | 2020-10-19 19:43:52 -0400 | [diff] [blame] | 120 | clk1_output_dest <= 0; |
| 121 | clk2_output_dest <= 0; |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 122 | trap_output_dest <= 0; |
| 123 | irq_7_inputsrc <= 0; |
Tim Edwards | 32d0542 | 2020-10-19 19:43:52 -0400 | [diff] [blame] | 124 | irq_8_inputsrc <= 0; |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 125 | end else begin |
| 126 | iomem_ready <= 0; |
| 127 | if (iomem_valid && !iomem_ready && iomem_addr[31:8] == BASE_ADR[31:8]) begin |
| 128 | iomem_ready <= 1'b 1; |
| 129 | |
Tim Edwards | 32d0542 | 2020-10-19 19:43:52 -0400 | [diff] [blame] | 130 | if (pwrgood_sel) begin |
Tim Edwards | 05ad4fc | 2020-10-19 22:12:33 -0400 | [diff] [blame] | 131 | iomem_rdata <= {28'd0, usr2_vdd_pwrgood, usr1_vdd_pwrgood, |
| 132 | usr2_vcc_pwrgood, usr1_vcc_pwrgood}; |
Tim Edwards | 32d0542 | 2020-10-19 19:43:52 -0400 | [diff] [blame] | 133 | // These are read-only bits; no write behavior on wstrb. |
| 134 | |
| 135 | end else if (clk_out_sel) begin |
| 136 | iomem_rdata <= {30'd0, clk2_output_dest, clk1_output_dest}; |
| 137 | if (iomem_wstrb[0]) begin |
| 138 | clk1_output_dest <= iomem_wdata[0]; |
| 139 | clk2_output_dest <= iomem_wdata[1]; |
| 140 | end |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 141 | |
| 142 | end else if (trap_out_sel) begin |
Tim Edwards | ef8312e | 2020-09-22 17:20:06 -0400 | [diff] [blame] | 143 | iomem_rdata <= {31'd0, trap_output_dest}; |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 144 | if (iomem_wstrb[0]) |
Tim Edwards | ef8312e | 2020-09-22 17:20:06 -0400 | [diff] [blame] | 145 | trap_output_dest <= iomem_wdata[0]; |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 146 | |
Tim Edwards | 32d0542 | 2020-10-19 19:43:52 -0400 | [diff] [blame] | 147 | end else if (irq_sel) begin |
| 148 | iomem_rdata <= {30'd0, irq_8_inputsrc, irq_7_inputsrc}; |
| 149 | if (iomem_wstrb[0]) begin |
Tim Edwards | ef8312e | 2020-09-22 17:20:06 -0400 | [diff] [blame] | 150 | irq_7_inputsrc <= iomem_wdata[0]; |
Tim Edwards | 32d0542 | 2020-10-19 19:43:52 -0400 | [diff] [blame] | 151 | irq_8_inputsrc <= iomem_wdata[1]; |
| 152 | end |
shalan | fd13eb5 | 2020-08-21 16:48:07 +0200 | [diff] [blame] | 153 | end |
| 154 | end |
| 155 | end |
| 156 | end |
| 157 | |
Tim Edwards | ef8312e | 2020-09-22 17:20:06 -0400 | [diff] [blame] | 158 | endmodule |