Made a few testbench corrections and added the missing OEB lines from the
user project. All existing testbench tests are now passing.
diff --git a/verilog/rtl/housekeeping_spi.v b/verilog/rtl/housekeeping_spi.v
index 879aff8..10ea1b3 100644
--- a/verilog/rtl/housekeeping_spi.v
+++ b/verilog/rtl/housekeeping_spi.v
@@ -177,7 +177,7 @@
(iaddr == 8'h06) ? mask_rev[15:8] : // Mask rev (metal programmed)
(iaddr == 8'h07) ? mask_rev[7:0] : // Mask rev (metal programmed)
- (iaddr == 8'h08) ? {6'b0000000, pll_dco_ena, pll_ena} :
+ (iaddr == 8'h08) ? {6'b000000, pll_dco_ena, pll_ena} :
(iaddr == 8'h09) ? {7'b0000000, pll_bypass} :
(iaddr == 8'h0a) ? {7'b0000000, irq} :
(iaddr == 8'h0b) ? {7'b0000000, reset} :
