Made a few testbench corrections and added the missing OEB lines from the
user project. All existing testbench tests are now passing.
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 3c711fd..463f127 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -413,7 +413,8 @@
.la_oen (la_oen),
// IO Pads
.io_in (user_io_in),
- .io_out(user_io_out)
+ .io_out(user_io_out),
+ .io_oeb(user_io_oeb)
);
/*--------------------------------------*/
diff --git a/verilog/rtl/housekeeping_spi.v b/verilog/rtl/housekeeping_spi.v
index 879aff8..10ea1b3 100644
--- a/verilog/rtl/housekeeping_spi.v
+++ b/verilog/rtl/housekeeping_spi.v
@@ -177,7 +177,7 @@
(iaddr == 8'h06) ? mask_rev[15:8] : // Mask rev (metal programmed)
(iaddr == 8'h07) ? mask_rev[7:0] : // Mask rev (metal programmed)
- (iaddr == 8'h08) ? {6'b0000000, pll_dco_ena, pll_ena} :
+ (iaddr == 8'h08) ? {6'b000000, pll_dco_ena, pll_ena} :
(iaddr == 8'h09) ? {7'b0000000, pll_bypass} :
(iaddr == 8'h0a) ? {7'b0000000, irq} :
(iaddr == 8'h0b) ? {7'b0000000, reset} :
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 742977c..4c2a6b9 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -54,11 +54,16 @@
// IOs
input [IO_PADS-1:0] io_in,
- output [IO_PADS-1:0] io_out
+ output [IO_PADS-1:0] io_out,
+ output [IO_PADS-1:0] io_oeb
);
wire clk;
wire rst;
+ wire [IO_PADS-1:0] io_in;
+ wire [IO_PADS-1:0] io_out;
+ wire [IO_PADS-1:0] io_oeb;
+
wire [31:0] rdata;
wire [31:0] wdata;
wire [BITS-1:0] count;
@@ -75,6 +80,7 @@
// IO
assign io_out = count;
+ assign io_oeb = {(IO_PADS-1){rst}};
// LA
assign la_data_out = {{(127-BITS){1'b0}}, count};
