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foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-001
/
slot-034
/
825d7ba70ef2b1eb47e9d9e7f8ab40177a9ee02e
/
.
/
verilog
/
rtl
/
fpga250
/
transmission_gate_cell.v
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module
transmission_gate_cell
(
inout A
,
inout B
,
input C
,
input
Cnot
);
// Use the verilog primitive where available, in which case c_not is not
// used.
tranif1
(
A
,
B
,
C
);
endmodule