Corrected the mess caused by introducing default_nettype none into the design
verification netlists. Also cleaned up the broken power-on-reset signaling,
and added connections from the user space to the I/O pad direct-to-pad analog
signal pins.
diff --git a/verilog/rtl/sysctrl.v b/verilog/rtl/sysctrl.v
index 8a0ac42..7f11f75 100644
--- a/verilog/rtl/sysctrl.v
+++ b/verilog/rtl/sysctrl.v
@@ -111,6 +111,11 @@
wire usr1_vdd_pwrgood;
wire usr2_vdd_pwrgood;
+ wire pwrgood_sel;
+ wire clk_out_sel;
+ wire trap_out_sel;
+ wire irq_sel;
+
assign pwrgood_sel = (iomem_addr[7:0] == PWRGOOD);
assign clk_out_sel = (iomem_addr[7:0] == CLK_OUT);
assign trap_out_sel = (iomem_addr[7:0] == TRAP_OUT);
@@ -157,3 +162,4 @@
end
endmodule
+`default_nettype wire
