diff --git a/verilog/rtl/sysctrl.v b/verilog/rtl/sysctrl.v
index 8a0ac42..7f11f75 100644
--- a/verilog/rtl/sysctrl.v
+++ b/verilog/rtl/sysctrl.v
@@ -111,6 +111,11 @@
     wire usr1_vdd_pwrgood;
     wire usr2_vdd_pwrgood;
 
+    wire pwrgood_sel;
+    wire clk_out_sel;
+    wire trap_out_sel;
+    wire irq_sel;
+
     assign pwrgood_sel  = (iomem_addr[7:0] == PWRGOOD);
     assign clk_out_sel  = (iomem_addr[7:0] == CLK_OUT);
     assign trap_out_sel = (iomem_addr[7:0] == TRAP_OUT);
@@ -157,3 +162,4 @@
     end
 
 endmodule
+`default_nettype wire