verilog/dv/caravel/fpga_250/Makefile

# ---- Test patterns for fpga 250 ----

.SUFFIXES:
.SILENT: clean all

PATTERNS = basic_config

all:  ${PATTERNS}
	for i in ${PATTERNS}; do \
		( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
	done

clean:  ${PATTERNS}
	for i in ${PATTERNS}; do \
		( cd $$i && make clean ) ; \
	done

.PHONY: clean all