scripts/update_from_class_repos.sh

#!/bin/bash
# TODO(aryap): Replace this script with just a single submodule (that is rid of unnecessary fluff).

# TODO(aryap): Get source of current script, etc.
CARAVEL_ROOT=.
CLASS_REPO_ROOT=/home/arya/src/mpw-one-a/openlane/designs/250
USER_PROJECT_WRAPPER_RUN=user_project_wrapper

# Update final GDS, LEF, MAG, etc.
FPGA_RUN="final5b_wrongclb"
PHY_SOURCE="${CLASS_REPO_ROOT}/asic_config/fpga/runs/${FPGA_RUN}/results/magic"
#PHY_SOURCE="${CLASS_REPO_ROOT}/gds/${PHY_SOURCE}"
for file_type in lef gds mag; do
  cp -v "${PHY_SOURCE}/fpga.${file_type}" "${CARAVEL_ROOT}/${file_type}" &
done

CLB_RUN="predecode_a_2"
PHY_SOURCE="${CLASS_REPO_ROOT}/asic_config/clb_tile/runs/${CLB_RUN}/results/magic"
for file_type in lef gds mag; do
  cp -v "${PHY_SOURCE}/clb_tile.${file_type}" "${CARAVEL_ROOT}/${file_type}" &
done

WB_RUN_00="360_noscope_a"
WB_RUN_10="360_noscope_a"
PHY_SOURCE="${CLASS_REPO_ROOT}/config_team/asic_config/wishbone_configuratorinator/runs/${WB_RUN}/results/magic"
for file_type in lef gds mag; do
  cp -v "${PHY_SOURCE}/wishbone_configuratorinator.${file_type}" "${CARAVEL_ROOT}/${file_type}" &
done

# Gate-level synthesised netlists.
GL_USER_PROJECT_WRAPPER="${CARAVEL_ROOT}/openlane/user_project_wrapper/runs/${USER_PROJECT_WRAPPER_RUN}/results/synthesis/user_project_wrapper.synthesis.v"
GL_SOURCE="
${CLASS_REPO_ROOT}/asic_config/fpga/runs/${FPGA_RUN}/results/synthesis/fpga.synthesis.v
${CLASS_REPO_ROOT}/asic_config/clb_tile/runs/${CLB_RUN}/results/synthesis/clb_tile.synthesis.v
${CLASS_REPO_ROOT}/config_team/asic_config/wishbone_configuratorinator_00/runs/${WB_RUN_00}/results/synthesis/wishbone_configuratorinator_00.synthesis.v
${CLASS_REPO_ROOT}/config_team/asic_config/wishbone_configuratorinator_10/runs/${WB_RUN_10}/results/synthesis/wishbone_configuratorinator_10.synthesis.v
"

GL_DEST="${CARAVEL_ROOT}/verilog/gl/user_project_wrapper.v"
cat > ${GL_DEST} << EOF
/** $(date)
 * Generated by:
 *   ${BASH_SOURCE[0]}
 * From:
 *   ${GL_SOURCE}
 *   ${GL_USER_PROJECT_WRAPPER}
 */
EOF
for source in ${GL_SOURCE}; do
  cat ${source} >> ${GL_DEST}
done
cat ${GL_USER_PROJECT_WRAPPER} >> ${GL_DEST}

# TODO(aryap): final_summary_report.csv
# Do these still exist?

VERILOG_DEST="${CARAVEL_ROOT}/verilog/rtl/fpga250"
VERILOG_SOURCES="
${CLASS_REPO_ROOT}/config_team/src/behavioral/wishbone_configuratorinator.v
${CLASS_REPO_ROOT}/src/clb_tile.v
${CLASS_REPO_ROOT}/config_team/src/behavioral/config_tile.v
${CLASS_REPO_ROOT}/config_team/src/behavioral/shift_chain.v
${CLASS_REPO_ROOT}/config_team/src/behavioral/config_latch.v
${CLASS_REPO_ROOT}/src/baked/baked_clb_switch_box.v
${CLASS_REPO_ROOT}/ix_yukio/src/clb_switch_box.v
${CLASS_REPO_ROOT}/ix_yukio/src/universal_switch_box.v
${CLASS_REPO_ROOT}/ix_yukio/src/switch_box_element_two.v
${CLASS_REPO_ROOT}/ix_yukio/src/transmission_gate.v
${CLASS_REPO_ROOT}/ix_yukio/src/transmission_gate_cell.v
${CLASS_REPO_ROOT}/src/baked/baked_slicel.v
${CLASS_REPO_ROOT}/clb_team/src/behavioral/slicel.v
${CLASS_REPO_ROOT}/clb_team/src/behavioral/lut_sXX_softcode.v
${CLASS_REPO_ROOT}/clb_team/src/behavioral/lut.v
${CLASS_REPO_ROOT}/clb_team/src/behavioral/block_config_latches.v
${CLASS_REPO_ROOT}/clb_team/src/behavioral/mux_f_slice.v
${CLASS_REPO_ROOT}/clb_team/src/behavioral/carry_chain.v
${CLASS_REPO_ROOT}/src/baked/baked_connection_block.v
${CLASS_REPO_ROOT}/src/baked/baked_connection_block_east.v
${CLASS_REPO_ROOT}/src/baked/baked_connection_block_north.v
${CLASS_REPO_ROOT}/ix_yukio/src/connection_block.v
${CLASS_REPO_ROOT}/ix_yukio/src/transmission_gate_oneway.v
${CLASS_REPO_ROOT}/src/fpga.v
"

for file in ${VERILOG_SOURCES}; do
  cp -v ${file} ${VERILOG_DEST};
done