forgot to enable output in user_project

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index dc96039..1b8c800 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -111,12 +111,18 @@
 
 // This is done by hand :/
 assign gpio_north[8:0] = io_in[23:15];
-assign gpio_east[9:0] = io_in[9:0];
-assign gpio_north[9] = io_in[10];
+assign gpio_east[9:0]  = io_in[9:0];
+assign gpio_north[9]   = io_in[10];
+
 assign io_out[14:11] = gpio_south[7:4];
 assign io_out[37:28] = gpio_west[9:0];
 assign io_out[27:24] = gpio_south[3:0];
 
+// output-enable (bar)
+assign io_oeb[14:11] = 4'b0;
+assign io_oeb[37:28] = 10'b0;
+assign io_oeb[27:24] = 4'b0;
+
 fpga #(
   .IO_NORTH(IO_NORTH),
   .IO_SOUTH(IO_SOUTH),