added makefile for vcs simulation in standalone test (no caravel)

verilog/dv/caravel/fpga_250/standalone_test/Makefile

diff --git a/verilog/dv/caravel/fpga_250/standalone_test/Makefile b/verilog/dv/caravel/fpga_250/standalone_test/Makefile
new file mode 100644
index 0000000..ca1b8cc
--- /dev/null
+++ b/verilog/dv/caravel/fpga_250/standalone_test/Makefile
@@ -0,0 +1,29 @@
+VCS = vcs -full64
+
+FIRMWARE_PATH      = ../..
+RTL_PATH           = ../../../../rtl
+IP_PATH            = ../../../../ip
+BEHAVIOURAL_MODELS = ../..
+PDK_PATH           = $(PDK_ROOT)/sky130A
+SCRIPTS            = ../../../../../scripts
+
+GCC_PATH = /tools/B/tan.nqd/riscv64-unknown-elf-gcc/bin
+GCC_PREFIX?=riscv64-unknown-elf
+
+INCS = $(RTL_PATH)+$(IP_PATH)+$(BEHAVIOURAL_MODELS)+$(PDK_PATH)+./
+
+SRCS = user_project_wrapper_tb.v
+
+# Bare minimum required VCS flag
+OPTS = -sverilog
+
+SIMV = ./standalone_test.simv
+
+$(SIMV): $(SRCS) $(HEX)
+	$(VCS) $(OPTS) +incdir+$(INCS) +define+SIM+FUNCTIONAL+USE_POWER_PINS+UNIT_DELAY="#0.1" $(SRCS) -o $@
+
+sim-rtl: $(SIMV)
+	$(SIMV) -q +ntb_random_seed_automatic +load_config=bitstream.txt +load_sync_output=sync_output.txt +load_comb_output=comb_output.txt +load_gpio_output=gpio_output.txt
+
+clean:
+	rm -rf *simv* csrc ucli.key *.elf *.bin *.vcd *.log

verilog/dv/caravel/fpga_250/standalone_test/user_project_wrapper_tb.v

diff --git a/verilog/dv/caravel/fpga_250/standalone_test/user_project_wrapper_tb.v b/verilog/dv/caravel/fpga_250/standalone_test/user_project_wrapper_tb.v
index 72d4484..4216fd8 100644
--- a/verilog/dv/caravel/fpga_250/standalone_test/user_project_wrapper_tb.v
+++ b/verilog/dv/caravel/fpga_250/standalone_test/user_project_wrapper_tb.v
@@ -1,7 +1,7 @@
 // This is an adaptation of [fabric_team]/testbench/fpga_test_harness.v for
 // the user_project_wrapper in Caravel.
 
-`timescale 1ns/1ns
+`timescale 1ns/1ps
 
 `include "defines.v"
 
@@ -10,6 +10,7 @@
 
 `include "fpga_consts.vh"
 `include "user_project_wrapper.v"
+
 module user_project_wrapper_tb();
 
   reg clk, rst;