Updates cargo/lis and cargo README and Makefile (improves verification).
diff --git a/cargo/Makefile b/cargo/Makefile
index ed461d6..8b4e981 100644
--- a/cargo/Makefile
+++ b/cargo/Makefile
@@ -24,6 +24,13 @@
cd $(TOP_TEST_PATH); make all; cd -;
make move_back_user_proj_example
+run_all:
+ make move_user_proj_example
+ make verilog_lis
+ make test_lis
+ cd $(TOP_TEST_PATH); make all; cd -;
+ make move_back_user_proj_example
+
clean_top:
cd $(TOP_TEST_PATH); make clean; cd -;
diff --git a/cargo/README.md b/cargo/README.md
index 99d7b3f..3ba0e5e 100644
--- a/cargo/README.md
+++ b/cargo/README.md
@@ -10,33 +10,54 @@
This directory contains following submodules and directories:
* Submodule `lis` - contains a linear insertion sorter (LIS) generator written in [Chisel ](http://www.chisel-lang.org) hardware design language. It comprises description of three types of the linear insertion sorter, parameter definition, setup explanation and many other useful information related to blocks that are depicted at presented global block scheme.
-* Submodule `wb2axip` - contains wishbone to AXI4 bridge. Current submodule is forked version of the [ZipCPU/wb2axip](https://github.com/ZipCPU/wb2axip). While all blocks inside LINSORTER use AXI4 memory mapped bus, this bridge was necessary to attach so that correct connection between processor and linear insertion sorters is established.
+* Submodule `wb2axip` - contains wishbone to AXI4 bridge. Current submodule is forked version of the [ZipCPU/wb2axip](https://github.com/ZipCPU/wb2axip).
* `doc` - contains global block scheme of the LINSORTER in svg and png format.
* `top/dv/LISTest` - contains verilog testbenches for LINSORTER integrated with Caravel
* `top/rtl/LISTest` - contains `user_proj_example.v` which is the top level verilog file for LINSORTER
* Makefile - has targets for verilog and test generation
-## Useful commands
+## Verilog generation and Chisel tests
-In order to generate verilog file LISTest.v which contains verilog code for LinearINsertion SORTER, run command:
+**Prerequisites:**
+The following software packages should be installed prior to generate Verilog code and Chisel tests:
+* [sbt](http://www.scala-sbt.org)
+* [Verilator](http://www.veripool.org/wiki/verilator)
+
+In order to generate `LISTest.v` which contains verilog code for LinearINsertion SORTER, run command:
$ make verilog_lis
-To run chisel tests, run command:
+To run Chisel tests, run command:
$ make test_lis
-In order to run verilog tests for LINSORTER connected to Caravel, PDK_ROOT and RISCV32 paths must be set. RISCV32 is path to RV32I Toolchain. For RV32I toolchain installation click [here](https://github.com/cliffordwolf/picorv32#building-a-pure-rv32i-toolchain). To check if paths are set, run command:
+## Verilog tests
+
+In order to run Verilog tests for LINSORTER connected to Caravel, PDK_ROOT and RISCV32 paths must be set. RISCV32 is path to RV32I Toolchain. For RV32I toolchain installation click [here](https://github.com/cliffordwolf/picorv32#building-a-pure-rv32i-toolchain). To check if paths are set, run command:
$ make check-env
-In order to test LINSORTER attached to the Caravel, run command:
+There are six different tests for LINSORTER connected to Caravel available inside `top/dv/LISTest/lis` directory:
+* BIST_LISFIFO_POUT - data path is: BIST-> LIS FIFO -> outStream (8b AXI4-Stream)
+* BIST_LISFixed_POUT - data path is: BIST-> LIS Fixed -> outStream (8b AXI4-Stream)
+* BIST_LISInput_POUT - data path is: BIST-> LIS Input -> outStream (8b AXI4-Stream)
+* PIN_LISFIFO_POUT - data path is: inStream (8b AXI4-Stream) -> LIS FIFO -> outStream (8b AXI4-Stream)
+* PIN_LISFixed_POUT - data path is: inStream (8b AXI4-Stream) -> LIS Fixed -> outStream (8b AXI4-Stream)
+* PIN_LISInput_POUT - data path is: inStream (8b AXI4-Stream) -> LIS Input-> outStream (8b AXI4-Stream)
+
+All tests contain C code for appropriate control registers configurations. Output of the LINSORTER is compared with golden model generated by Chisel. Golden model outputs are available inside `test_run_dir` directory of the `lis` submodule so there is no need to run Chisel tests prior to running Verilog tests.
+
+So, for testing LINSORTER attached to the Caravel, run command:
$ make test_top
-To clean data generated by verilog testbenches, run:
+To clean data generated by Verilog testbenches, run:
$ make clean_top
+
+In order to regenerate Verilog code, run Chisel and Verilog tests, type following command:
+
+ $ make run_all
## Address space for LINSORTER
```
diff --git a/cargo/lis b/cargo/lis
index be02358..20506e7 160000
--- a/cargo/lis
+++ b/cargo/lis
@@ -1 +1 @@
-Subproject commit be02358aad24d7e680b2d769e423504e069a31f8
+Subproject commit 20506e72a26f9ed7e24e52b20cf44fc1e59c251d
