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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-032 / 61dce92ffadeb8742dadd290f03bc354f1405b8d / . / verilog / rtl / DFFRAMBB.v
blob: abe1f44868a9c01d5ed5d218b3394e23d9c4f3a1 [file] [log] [blame]
Manar68e03632020-11-09 13:25:13 +0200[diff] [blame]1/*
2 Building blocks for DFF based RAM compiler for SKY130
3 WORD : 32-bit memory word with select and byte-level WE
4 DEC6x64 : 6x64 Binary decoder
5 SRAM64x32 : Tri-state based 64x32 DFF RAM
6*/
7
8module BYTE (
Manar61dce922020-11-10 19:26:28 +0200[diff] [blame^]9`ifdef USE_POWER_PINS
10 input VPWR,
11 input VGND,
12`endif
Manar68e03632020-11-09 13:25:13 +0200[diff] [blame]13 input CLK,
14 input WE,
15 input SEL,
16 input [7:0] Di,
Manar61dce922020-11-10 19:26:28 +0200[diff] [blame^]17 output [7:0] Do
Manar68e03632020-11-09 13:25:13 +0200[diff] [blame]18);
19
20 wire [7:0] q_wire;
21 wire we_wire;
22 wire SEL_B;
23 wire GCLK;
24
Manar61dce922020-11-10 19:26:28 +0200[diff] [blame^]25 sky130_fd_sc_hd__inv_1 INV(
26 `ifdef USE_POWER_PINS
27 .VPWR(VPWR),
28 .VGND(VGND),
29 .VPB(VPWR),
30 .VNB(VGND),
31 `endif
32 .Y(SEL_B),
33 .A(SEL)
34 );
35
36 sky130_fd_sc_hd__and2_1 CGAND(
37 `ifdef USE_POWER_PINS
38 .VPWR(VPWR),
39 .VGND(VGND),
40 .VPB(VPWR),
41 .VNB(VGND),
42 `endif
43 .A(SEL),
44 .B(WE),
45 .X(we_wire)
46 );
47
48 sky130_fd_sc_hd__dlclkp_1 CG(
49 `ifdef USE_POWER_PINS
50 .VPWR(VPWR),
51 .VGND(VGND),
52 .VPB(VPWR),
53 .VNB(VGND),
54 `endif
55 .CLK(CLK),
56 .GCLK(GCLK),
57 .GATE(we_wire)
58 );
Manar68e03632020-11-09 13:25:13 +0200[diff] [blame]59
60 generate
61 genvar i;
62 for(i=0; i<8; i=i+1) begin : BIT
Manar61dce922020-11-10 19:26:28 +0200[diff] [blame^]63 sky130_fd_sc_hd__dfxtp_1 FF (
64 `ifdef USE_POWER_PINS
65 .VPWR(VPWR),
66 .VGND(VGND),
67 .VPB(VPWR),
68 .VNB(VGND),
69 `endif
70 .D(Di[i]),
71 .Q(q_wire[i]),
72 .CLK(GCLK)
73 );
74 sky130_fd_sc_hd__ebufn_2 OBUF (
75 `ifdef USE_POWER_PINS
76 .VPWR(VPWR),
77 .VGND(VGND),
78 .VPB(VPWR),
79 .VNB(VGND),
80 `endif
81 .A(q_wire[i]),
82 .Z(Do[i]),
83 .TE_B(SEL_B)
84 );
Manar68e03632020-11-09 13:25:13 +0200[diff] [blame]85 end
86 endgenerate
87
88endmodule
89
90
91module WORD32 (
Manar61dce922020-11-10 19:26:28 +0200[diff] [blame^]92`ifdef USE_POWER_PINS
93 input VPWR,
94 input VGND,
95`endif
Manar68e03632020-11-09 13:25:13 +0200[diff] [blame]96 input CLK,
97 input [3:0] WE,
98 input SEL,
99 input [31:0] Di,
Manar61dce922020-11-10 19:26:28 +0200[diff] [blame^]100 output [31:0] Do
Manar68e03632020-11-09 13:25:13 +0200[diff] [blame]101);
102
Manar61dce922020-11-10 19:26:28 +0200[diff] [blame^]103 BYTE B0 (
104 `ifdef USE_POWER_PINS
105 .VPWR(VPWR),
106 .VGND(VGND),
107 `endif
108 .CLK(CLK),
109 .WE(WE[0]),
110 .SEL(SEL),
111 .Di(Di[7:0]),
112 .Do(Do[7:0])
113 );
114 BYTE B1 (
115 `ifdef USE_POWER_PINS
116 .VPWR(VPWR),
117 .VGND(VGND),
118 `endif
119 .CLK(CLK),
120 .WE(WE[1]),
121 .SEL(SEL),
122 .Di(Di[15:8]),
123 .Do(Do[15:8])
124 );
125 BYTE B2 (
126 `ifdef USE_POWER_PINS
127 .VPWR(VPWR),
128 .VGND(VGND),
129 `endif
130 .CLK(CLK),
131 .WE(WE[2]),
132 .SEL(SEL),
133 .Di(Di[23:16]),
134 .Do(Do[23:16])
135 );
136
137 BYTE B3 (
138 `ifdef USE_POWER_PINS
139 .VPWR(VPWR),
140 .VGND(VGND),
141 `endif
142 .CLK(CLK),
143 .WE(WE[3]),
144 .SEL(SEL),
145 .Di(Di[31:24]),
146 .Do(Do[31:24])
147 );
Manar68e03632020-11-09 13:25:13 +0200[diff] [blame]148
149endmodule
150
151module DEC2x4 (
Manar61dce922020-11-10 19:26:28 +0200[diff] [blame^]152`ifdef USE_POWER_PINS
153 input VPWR,
154 input VGND,
155`endif
Manar68e03632020-11-09 13:25:13 +0200[diff] [blame]156 input EN,
157 input [1:0] A,
Manar61dce922020-11-10 19:26:28 +0200[diff] [blame^]158 output [3:0] SEL
Manar68e03632020-11-09 13:25:13 +0200[diff] [blame]159);
Manar61dce922020-11-10 19:26:28 +0200[diff] [blame^]160 sky130_fd_sc_hd__nor3b_2 AND0 (
161 `ifdef USE_POWER_PINS
162 .VPWR(VPWR),
163 .VGND(VGND),
164 .VPB(VPWR),
165 .VNB(VGND),
166 `endif
167 .Y(SEL[0]),
168 .A(A[0]),
169 .B(A[1]),
170 .C_N(EN)
171 );
172 sky130_fd_sc_hd__and3b_2 AND1 (
173 `ifdef USE_POWER_PINS
174 .VPWR(VPWR),
175 .VGND(VGND),
176 .VPB(VPWR),
177 .VNB(VGND),
178 `endif
179 .X(SEL[1]),
180 .A_N(A[1]),
181 .B(A[0]),
182 .C(EN)
183 );
184
185 sky130_fd_sc_hd__and3b_2 AND2 (
186 `ifdef USE_POWER_PINS
187 .VPWR(VPWR),
188 .VGND(VGND),
189 .VPB(VPWR),
190 .VNB(VGND),
191 `endif
192 .X(SEL[2]),
193 .A_N(A[0]),
194 .B(A[1]),
195 .C(EN)
196 );
197
198 sky130_fd_sc_hd__and3_2 AND3 (
199 `ifdef USE_POWER_PINS
200 .VPWR(VPWR),
201 .VGND(VGND),
202 .VPB(VPWR),
203 .VNB(VGND),
204 `endif
205 .X(SEL[3]),
206 .A(A[1]),
207 .B(A[0]),
208 .C(EN)
209 );
Manar68e03632020-11-09 13:25:13 +0200[diff] [blame]210
211endmodule
212
213module DEC3x8 (
Manar61dce922020-11-10 19:26:28 +0200[diff] [blame^]214`ifdef USE_POWER_PINS
215 input VPWR,
216 input VGND,
217`endif
Manar68e03632020-11-09 13:25:13 +0200[diff] [blame]218 input EN,
219 input [2:0] A,
Manar61dce922020-11-10 19:26:28 +0200[diff] [blame^]220 output [7:0] SEL
Manar68e03632020-11-09 13:25:13 +0200[diff] [blame]221);
Manar61dce922020-11-10 19:26:28 +0200[diff] [blame^]222 sky130_fd_sc_hd__nor4b_2 AND0 (
223 `ifdef USE_POWER_PINS
224 .VPWR(VPWR),
225 .VGND(VGND),
226 .VPB(VPWR),
227 .VNB(VGND),
228 `endif
229 .Y(SEL[0]),
230 .A(A[0]),
231 .B(A[1]),
232 .C(A[2]),
233 .D_N(EN)
234 ); // 000
235
236 sky130_fd_sc_hd__and4bb_2 AND1 (
237 `ifdef USE_POWER_PINS
238 .VPWR(VPWR),
239 .VGND(VGND),
240 .VPB(VPWR),
241 .VNB(VGND),
242 `endif
243 .X(SEL[1]),
244 .A_N(A[2]),
245 .B_N(A[1]),
246 .C(A[0]),
247 .D(EN)
248 ); // 001
249
250 sky130_fd_sc_hd__and4bb_2 AND2 (
251 `ifdef USE_POWER_PINS
252 .VPWR(VPWR),
253 .VGND(VGND),
254 .VPB(VPWR),
255 .VNB(VGND),
256 `endif
257 .X(SEL[2]),
258 .A_N(A[2]),
259 .B_N(A[0]),
260 .C(A[1]),
261 .D(EN)
262 ); // 010
263
264 sky130_fd_sc_hd__and4b_2 AND3 (
265 `ifdef USE_POWER_PINS
266 .VPWR(VPWR),
267 .VGND(VGND),
268 .VPB(VPWR),
269 .VNB(VGND),
270 `endif
271 .X(SEL[3]),
272 .A_N(A[2]),
273 .B(A[1]),
274 .C(A[0]),
275 .D(EN)
276 ); // 011
277
278 sky130_fd_sc_hd__and4bb_2 AND4 (
279 `ifdef USE_POWER_PINS
280 .VPWR(VPWR),
281 .VGND(VGND),
282 .VPB(VPWR),
283 .VNB(VGND),
284 `endif
285 .X(SEL[4]),
286 .A_N(A[0]),
287 .B_N(A[1]),
288 .C(A[2]),
289 .D(EN)
290 ); // 100
291
292 sky130_fd_sc_hd__and4b_2 AND5 (
293 `ifdef USE_POWER_PINS
294 .VPWR(VPWR),
295 .VGND(VGND),
296 .VPB(VPWR),
297 .VNB(VGND),
298 `endif
299 .X(SEL[5]),
300 .A_N(A[1]),
301 .B(A[0]),
302 .C(A[2]),
303 .D(EN)
304 ); // 101
305
306 sky130_fd_sc_hd__and4b_2 AND6 (
307 `ifdef USE_POWER_PINS
308 .VPWR(VPWR),
309 .VGND(VGND),
310 .VPB(VPWR),
311 .VNB(VGND),
312 `endif
313 .X(SEL[6]),
314 .A_N(A[0]),
315 .B(A[1]),
316 .C(A[2]),
317 .D(EN)
318 ); // 110
319
320 sky130_fd_sc_hd__and4_2 AND7 (
321 `ifdef USE_POWER_PINS
322 .VPWR(VPWR),
323 .VGND(VGND),
324 .VPB(VPWR),
325 .VNB(VGND),
326 `endif
327 .X(SEL[7]),
328 .A(A[0]),
329 .B(A[1]),
330 .C(A[2]),
331 .D(EN)
332 ); // 111
Manar68e03632020-11-09 13:25:13 +0200[diff] [blame]333endmodule
334
335
336module DEC6x64 (
Manar61dce922020-11-10 19:26:28 +0200[diff] [blame^]337`ifdef USE_POWER_PINS
338 input VPWR,
339 input VGND,
340`endif
Manar68e03632020-11-09 13:25:13 +0200[diff] [blame]341 input EN,
342 input [5:0] A,
Manar61dce922020-11-10 19:26:28 +0200[diff] [blame^]343 output [63:0] SEL
Manar68e03632020-11-09 13:25:13 +0200[diff] [blame]344);
345 wire [7:0] SEL0_w ;
Manar61dce922020-11-10 19:26:28 +0200[diff] [blame^]346 DEC3x8 DEC_L0 (
347 `ifdef USE_POWER_PINS
348 .VPWR(VPWR),
349 .VGND(VGND),
350 `endif
351 .EN(EN), .A(A[5:3]), .SEL(SEL0_w) );
Manar68e03632020-11-09 13:25:13 +0200[diff] [blame]352
353 generate
354 genvar i;
355 for(i=0; i<8; i=i+1) begin : DEC_L1
Manar61dce922020-11-10 19:26:28 +0200[diff] [blame^]356 DEC3x8 U (
357 `ifdef USE_POWER_PINS
358 .VPWR(VPWR),
359 .VGND(VGND),
360 `endif
361 .EN(SEL0_w[i]), .A(A[2:0]), .SEL(SEL[7+8*i: 8*i]) );
Manar68e03632020-11-09 13:25:13 +0200[diff] [blame]362 end
363 endgenerate
364endmodule
365
366module MUX4x1_32(
Manar61dce922020-11-10 19:26:28 +0200[diff] [blame^]367`ifdef USE_POWER_PINS
368 input VPWR,
369 input VGND,
370`endif
Manar68e03632020-11-09 13:25:13 +0200[diff] [blame]371 input [31:0] A0, A1, A2, A3,
372 input [1:0] S,
Manar61dce922020-11-10 19:26:28 +0200[diff] [blame^]373 output [31:0] X
Manar68e03632020-11-09 13:25:13 +0200[diff] [blame]374);
Manar61dce922020-11-10 19:26:28 +0200[diff] [blame^]375 sky130_fd_sc_hd__mux4_1 MUX[31:0] (
376 `ifdef USE_POWER_PINS
377 .VPWR(VPWR),
378 .VGND(VGND),
379 .VPB(VPWR),
380 .VNB(VGND),
381 `endif
382 .A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S[0]), .S1(S[1]), .X(X) );
Manar68e03632020-11-09 13:25:13 +0200[diff] [blame]383endmodule
384
385module SRAM64x32(
Manar61dce922020-11-10 19:26:28 +0200[diff] [blame^]386`ifdef USE_POWER_PINS
387 input VPWR,
388 input VGND,
389`endif
Manar68e03632020-11-09 13:25:13 +0200[diff] [blame]390 input CLK,
391 input [3:0] WE,
392 input EN,
393 input [31:0] Di,
394 output [31:0] Do,
Manar61dce922020-11-10 19:26:28 +0200[diff] [blame^]395 input [5:0] A
Manar68e03632020-11-09 13:25:13 +0200[diff] [blame]396);
397
398 wire [63:0] SEL;
399 wire [31:0] Do_pre;
400 wire [31:0] Di_buf;
401 wire CLK_buf;
402 wire [3:0] WE_buf;
403
Manar61dce922020-11-10 19:26:28 +0200[diff] [blame^]404 sky130_fd_sc_hd__clkbuf_16 CLKBUF (
405 `ifdef USE_POWER_PINS
406 .VPWR(VPWR),
407 .VGND(VGND),
408 .VPB(VPWR),
409 .VNB(VGND),
410 `endif
411 .X(CLK_buf),
412 .A(CLK)
413 );
Manar68e03632020-11-09 13:25:13 +0200[diff] [blame]414
Manar61dce922020-11-10 19:26:28 +0200[diff] [blame^]415 sky130_fd_sc_hd__clkbuf_16 WEBUF[3:0] (
416 `ifdef USE_POWER_PINS
417 .VPWR(VPWR),
418 .VGND(VGND),
419 .VPB(VPWR),
420 .VNB(VGND),
421 `endif
422 .X(WE_buf),
423 .A(WE)
424 );
425
426 sky130_fd_sc_hd__clkbuf_16 DIBUF[31:0] (
427 `ifdef USE_POWER_PINS
428 .VPWR(VPWR),
429 .VGND(VGND),
430 .VPB(VPWR),
431 .VNB(VGND),
432 `endif
433 .X(Di_buf),
434 .A(Di)
435 );
436
437 DEC6x64 DEC (
438 `ifdef USE_POWER_PINS
439 .VPWR(VPWR),
440 .VGND(VGND),
441 `endif
442 .EN(EN),
443 .A(A),
444 .SEL(SEL)
445 );
Manar68e03632020-11-09 13:25:13 +0200[diff] [blame]446
447 generate
448 genvar i;
449 for (i=0; i< 64; i=i+1) begin : WORD
Manar61dce922020-11-10 19:26:28 +0200[diff] [blame^]450 WORD32 W (
451 `ifdef USE_POWER_PINS
452 .VPWR(VPWR),
453 .VGND(VGND),
454 `endif
455 .CLK(CLK_buf),
456 .WE(WE_buf),
457 .SEL(SEL[i]),
458 .Di(Di_buf),
459 .Do(Do_pre)
460 );
Manar68e03632020-11-09 13:25:13 +0200[diff] [blame]461 end
462 endgenerate
463
464 // Ensure that the Do_pre lines are not floating when EN = 0
Manar61dce922020-11-10 19:26:28 +0200[diff] [blame^]465 sky130_fd_sc_hd__ebufn_4 FLOATBUF[31:0] (
466 `ifdef USE_POWER_PINS
467 .VPWR(VPWR),
468 .VGND(VGND),
469 .VPB(VPWR),
470 .VNB(VGND),
471 `endif
472 .A({32{EN}}),
473 .Z(Do_pre),
474 .TE_B({32{EN}})
475 );
Manar68e03632020-11-09 13:25:13 +0200[diff] [blame]476
477 generate
478 //genvar i;
479 for(i=0; i<32; i=i+1) begin : OUT
Manar61dce922020-11-10 19:26:28 +0200[diff] [blame^]480 sky130_fd_sc_hd__dfxtp_1 FF (
481 `ifdef USE_POWER_PINS
482 .VPWR(VPWR),
483 .VGND(VGND),
484 .VPB(VPWR),
485 .VNB(VGND),
486 `endif
487 .D(Do_pre[i]),
488 .Q(Do[i]),
489 .CLK(CLK)
490 );
Manar68e03632020-11-09 13:25:13 +0200[diff] [blame]491 end
492 endgenerate
493
494endmodule
495