verilog/dv/caravel/user_proj_example/files_fast_sim.list

../DFFRAM_beh.v

../../../../rtl/user_project/AHB_sys_0/AHBlite_sys_0.v 
../../../../rtl/user_project/AHB_sys_0/AHBlite_bus0.v
../../../../rtl/user_project/AHB_sys_0/AHBlite_GPIO.v
../../../../rtl/user_project/AHB_sys_0/AHBlite_db_reg.v

../../../../rtl/user_project/AHB_sys_0/APB_sys_0/APB_WDT32.v
../../../../rtl/user_project/AHB_sys_0/APB_sys_0/APB_TIMER32.v
../../../../rtl/user_project/AHB_sys_0/APB_sys_0/APB_PWM32.v
../../../../rtl/user_project/AHB_sys_0/APB_sys_0/AHB_2_APB.v
../../../../rtl/user_project/AHB_sys_0/APB_sys_0/APB_bus0.v
../../../../rtl/user_project/AHB_sys_0/APB_sys_0/APB_sys_0.v

../../../../rtl/user_project/IPs/TIMER32.v
../../../../rtl/user_project/IPs/PWM32.v
../../../../rtl/user_project/IPs/WDT32.v
../../../../rtl/user_project/IPs/spi_master.v
../../../../rtl/user_project/IPs/i2c_master.v
../../../../rtl/user_project/IPs/GPIO.v
../../../../rtl/user_project/IPs/APB_UART.v
../../../../rtl/user_project/IPs/APB_SPI.v
../../../../rtl/user_project/IPs/APB_I2C.v
../../../../rtl/user_project/IPs/AHBSRAM.v
../../../../rtl/user_project/IPs/DFFRAM.v
../../../../rtl/user_project/IPs/DFFRAMBB.v
../../../../rtl/user_project/acc/AHB_SPM.v
+define+NO_HC_CACHE=1
../../../../rtl/user_project/IPs/QSPI_XIP_CTRL.v
../../../../rtl/user_project/IPs/DMC_32x16HC.v
+define+NO_DFFRAM=1
#../../../../rtl/user_project/IPs/RAM_4Kx32.v
../../../../rtl/user_project/IPs/RAM_3Kx32.v

../../../../rtl/user_project/DFFRFile.v 
+define+NO_HC_REGF=1
../../../../rtl/user_project/NfiVe32.v 
../../../../rtl/user_project/soc_core.v

N5_SoC_TB.v
sst26wf080b.v
23LC512.v