| parameter integer MEM_WORDS = 256 |
| wire [3:0] wen; // write enable |
| assign valid = wb_cyc_i & wb_stb_i; |
| assign ram_wen = wb_we_i && valid; |
| assign wen = wb_sel_i & {4{ram_wen}} ; |
| - write transaction: asserted upon receiving adr_i & dat_i |
| - read transaction : asserted one clock cycle after receiving the adr_i & dat_i |
| always @(posedge wb_clk_i) begin |
| if (wb_rst_i == 1'b 1) begin |
| // wb_ack_read <= {2{valid}} & {1'b1, wb_ack_read[1]}; |
| wb_ack_o <= wb_we_i? (valid & !wb_ack_o): wb_ack_read; |
| wb_ack_read <= (valid & !wb_ack_o) & !wb_ack_read; |
| parameter integer WORDS = 8192 |
| reg [31:0] mem [0:WORDS-1]; |
| always @(posedge clk) begin |
| if (wen[0]) mem[addr][ 7: 0] <= wdata[ 7: 0]; |
| if (wen[1]) mem[addr][15: 8] <= wdata[15: 8]; |
| if (wen[2]) mem[addr][23:16] <= wdata[23:16]; |
| if (wen[3]) mem[addr][31:24] <= wdata[31:24]; |
| /* Using Port 0 Only - Size: 1KB, 256x32 bits */ |
| //sram_1rw1r_32_256_8_scn4m_subm |
| sram_1rw1r_32_8192_8_sky130 SRAM( |