commit 0d14e6eb07affadbc58815c657f701914bb37a2a
author shalan Mon Aug 31 16:50:48 2020 +0200
committer shalan Mon Aug 31 16:50:48 2020 +0200
tree 279aab06f9ab27ba838682595e28214f9d58acc9
parent fd13eb528fb15e206e969380e4b4fb529931790d

harness phase1 initial commit

verilog/rtl/mem_wb.v

diff --git a/verilog/rtl/mem_wb.v b/verilog/rtl/mem_wb.v
index e0b6599..bacf52c 100644
--- a/verilog/rtl/mem_wb.v
+++ b/verilog/rtl/mem_wb.v
@@ -34,15 +34,17 @@
             - read transaction : asserted one clock cycle after receiving the adr_i & dat_i
     */ 
 
-    reg [2:0] wb_ack_read;
-   
-    assign wb_ack_o = wb_we_i ? valid : &wb_ack_read;
+    reg wb_ack_read;
+    reg wb_ack_o;
 
     always @(posedge wb_clk_i) begin
         if (wb_rst_i == 1'b 1) begin
-            wb_ack_read <= 3'b 00;
+            wb_ack_read <= 1'b0;
+            wb_ack_o <= 1'b0;
         end else begin
-            wb_ack_read <= {3{valid}} & {1'b1, wb_ack_read[2:1]};
+            // wb_ack_read <= {2{valid}} & {1'b1, wb_ack_read[1]};
+            wb_ack_o    <= wb_we_i? (valid & !wb_ack_o): wb_ack_read;
+            wb_ack_read <= (valid & !wb_ack_o) & !wb_ack_read;
         end
     end
 
@@ -62,7 +64,7 @@
 module soc_mem 
 `ifndef USE_OPENRAM
 #(
-    parameter integer WORDS = 256
+    parameter integer WORDS = 8192
 )
 `endif
  ( 
@@ -91,12 +93,12 @@
     
     /* Using Port 0 Only - Size: 1KB, 256x32 bits */
     //sram_1rw1r_32_256_8_scn4m_subm 
-    sram_1rw1r_32_256_8_sky130 SRAM(
+    sram_1rw1r_32_8192_8_sky130 SRAM(
             .clk0(clk), 
             .csb0(~ena), 
             .web0(~|wen),
             .wmask0(wen),
-            .addr0(addr[7:0]),
+            .addr0(addr[12:0]),
             .din0(wdata),
             .dout0(rdata)
       );