harness phase1 initial commit
diff --git a/README.md b/README.md index f8317e7..1232c21 100644 --- a/README.md +++ b/README.md
@@ -1 +1,29 @@ -# caravel \ No newline at end of file +# CIIC Harness (Phase 1) + +A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below. + +<p align=”center”> +<img src="/doc/ciic_harness.png" width="70%" height="70%"> +</p> + +## Managment SoC +The managment SoC runs firmware taht can be used to: +- Configure Mega Project I/O pads +- Observe and control Mega Project signals (through on-chip logic analyzer probes) +- Control the Mega Project power supply + +The memory map of the management SoC is given below <br> +<img src="/doc/mgmt_soc_memory_map.png" width="40%" height="40%"> + +## Mega Project Area +This is the user space. It has limitted silicon area (???) as well as a fixed number of I/O pads (???). +The repoo contains a [sample mega project](/verilog/rtl/mprj_counter.v) that contains a binary 32-bit up counter. </br> + +<p align=”center”> +<img src="/doc/counter_32.png" width="40%" height="40%"> +</p> + +The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided: +1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: [IO_Ports Test](verilog/dv/harness/mprj_counter/io_ports). +2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: [LA_Test1](verilog/dv/harness/mprj_counter/la_test1). +3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: [LA_Test2](verilog/dv/harness/mprj_counter/la_test2).
diff --git a/doc/README.md b/doc/README.md index 76f6c83..8b13789 100644 --- a/doc/README.md +++ b/doc/README.md
@@ -1 +1 @@ -This folder contains key documents related to this project +
diff --git a/doc/ciic_harness.png b/doc/ciic_harness.png new file mode 100644 index 0000000..7d01257 --- /dev/null +++ b/doc/ciic_harness.png Binary files differ
diff --git a/doc/counter_32.png b/doc/counter_32.png new file mode 100644 index 0000000..cbe7e06 --- /dev/null +++ b/doc/counter_32.png Binary files differ
diff --git a/doc/mgmt_soc_memory_map.png b/doc/mgmt_soc_memory_map.png new file mode 100644 index 0000000..ff29081 --- /dev/null +++ b/doc/mgmt_soc_memory_map.png Binary files differ
diff --git a/verilog/README.md b/verilog/README.md deleted file mode 100644 index 86dd11a..0000000 --- a/verilog/README.md +++ /dev/null
@@ -1 +0,0 @@ -This folder contains all *.v files related to this project
diff --git a/verilog/dv/README.md b/verilog/dv/README.md new file mode 100644 index 0000000..5a3fba1 --- /dev/null +++ b/verilog/dv/README.md
@@ -0,0 +1,13 @@ +# DV Tests + +Organized into two subdirectories: + * harness: contains tests for both the mangement SoC and the mega-project. + * wb_utests: contains unit tests for the wishbone components residing at the management SoC private bus + +<pre> +├── harness +│ ├── mgmt_soc +│ ├── mprj_counter +└── wb_utests +</pre> +
diff --git a/verilog/dv/harness/mgmt_soc/defs.h b/verilog/dv/harness/defs.h similarity index 66% rename from verilog/dv/harness/mgmt_soc/defs.h rename to verilog/dv/harness/defs.h index e2d777f..d9eec3a 100644 --- a/verilog/dv/harness/mgmt_soc/defs.h +++ b/verilog/dv/harness/defs.h
@@ -12,15 +12,17 @@ extern uint32_t flashio_worker_begin; extern uint32_t flashio_worker_end; -// IOs: UART (0x2000_0000), GPIO (0x2100_0000), LA (0x2200_0000) +// UART (0x2000_0000) #define reg_uart_clkdiv (*(volatile uint32_t*)0x20000000) #define reg_uart_data (*(volatile uint32_t*)0x20000004) +// GPIO (0x2100_0000) #define reg_gpio_data (*(volatile uint32_t*)0x21000000) #define reg_gpio_ena (*(volatile uint32_t*)0x21000004) #define reg_gpio_pu (*(volatile uint32_t*)0x21000008) #define reg_gpio_pd (*(volatile uint32_t*)0x2100000c) +// Logic Analyzer (0x2200_0000) #define reg_la0_data (*(volatile uint32_t*)0x22000000) #define reg_la1_data (*(volatile uint32_t*)0x22000004) #define reg_la2_data (*(volatile uint32_t*)0x22000008) @@ -31,6 +33,49 @@ #define reg_la2_ena (*(volatile uint32_t*)0x22000018) #define reg_la3_ena (*(volatile uint32_t*)0x2200001c) +// Mega Project Control (0x2300_0000) +#define reg_mprj_io_0 (*(volatile uint32_t*)0x23000000) +#define reg_mprj_io_1 (*(volatile uint32_t*)0x23000004) +#define reg_mprj_io_2 (*(volatile uint32_t*)0x23000008) +#define reg_mprj_io_3 (*(volatile uint32_t*)0x2300000c) +#define reg_mprj_io_4 (*(volatile uint32_t*)0x23000010) +#define reg_mprj_io_5 (*(volatile uint32_t*)0x23000014) +#define reg_mprj_io_6 (*(volatile uint32_t*)0x23000018) + +#define reg_mprj_io_7 (*(volatile uint32_t*)0x2300001c) +#define reg_mprj_io_8 (*(volatile uint32_t*)0x23000020) +#define reg_mprj_io_9 (*(volatile uint32_t*)0x23000024) +#define reg_mprj_io_10 (*(volatile uint32_t*)0x23000028) + +#define reg_mprj_io_11 (*(volatile uint32_t*)0x2300002c) +#define reg_mprj_io_12 (*(volatile uint32_t*)0x23000030) +#define reg_mprj_io_13 (*(volatile uint32_t*)0x23000034) +#define reg_mprj_io_14 (*(volatile uint32_t*)0x23000038) + +#define reg_mprj_io_15 (*(volatile uint32_t*)0x2300003c) +#define reg_mprj_io_16 (*(volatile uint32_t*)0x23000040) +#define reg_mprj_io_17 (*(volatile uint32_t*)0x23000044) +#define reg_mprj_io_18 (*(volatile uint32_t*)0x23000048) + +#define reg_mprj_io_19 (*(volatile uint32_t*)0x2300004c) +#define reg_mprj_io_20 (*(volatile uint32_t*)0x23000050) +#define reg_mprj_io_21 (*(volatile uint32_t*)0x23000054) +#define reg_mprj_io_22 (*(volatile uint32_t*)0x23000058) + +#define reg_mprj_io_23 (*(volatile uint32_t*)0x2300005c) +#define reg_mprj_io_24 (*(volatile uint32_t*)0x23000060) +#define reg_mprj_io_25 (*(volatile uint32_t*)0x23000064) +#define reg_mprj_io_26 (*(volatile uint32_t*)0x23000068) + +#define reg_mprj_io_27 (*(volatile uint32_t*)0x2300006c) +#define reg_mprj_io_28 (*(volatile uint32_t*)0x23000070) +#define reg_mprj_io_29 (*(volatile uint32_t*)0x23000074) +#define reg_mprj_io_30 (*(volatile uint32_t*)0x23000078) +#define reg_mprj_io_31 (*(volatile uint32_t*)0x2300007c) + +// Mega Project Slaves (0x3000_0000) +#define reg_mprj_slave (*(volatile uint32_t*)0x30000000) + // Flash Control SPI Configuration (2D00_0000) #define reg_spictrl (*(volatile uint32_t*)0x2D000000)
diff --git a/verilog/dv/harness/mgmt_soc/Makefile b/verilog/dv/harness/mgmt_soc/Makefile index c934af3..9f185c0 100644 --- a/verilog/dv/harness/mgmt_soc/Makefile +++ b/verilog/dv/harness/mgmt_soc/Makefile
@@ -3,7 +3,7 @@ .SUFFIXES: .SILENT: clean all -PATTERNS = gpio mem uart perf hkspi sysctrl xbar +PATTERNS = gpio mem uart perf hkspi sysctrl mprj_ctrl all: ${PATTERNS} for i in ${PATTERNS}; do \
diff --git a/verilog/dv/harness/mgmt_soc/gpio/Makefile b/verilog/dv/harness/mgmt_soc/gpio/Makefile index e9253c0..719e42b 100644 --- a/verilog/dv/harness/mgmt_soc/gpio/Makefile +++ b/verilog/dv/harness/mgmt_soc/gpio/Makefile
@@ -1,3 +1,8 @@ +FIRMWARE_PATH = ../.. +RTL_PATH = ../../../../rtl +IP_PATH = ../../../../ip +BEHAVIOURAL_MODELS = ../../ + .SUFFIXES: PATTERN = gpio @@ -7,14 +12,14 @@ hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -I ../ -I ../../../../ip -I ../../../../rtl \ + iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ %.vcd: %.vvp vvp $< -%.elf: %.c ../sections.lds ../start.s - /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ ../start.s $< +%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s + /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< %.hex: %.elf /ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@
diff --git a/verilog/dv/harness/mgmt_soc/gpio/gpio.c b/verilog/dv/harness/mgmt_soc/gpio/gpio.c index 17a4885..0d9caf5 100644 --- a/verilog/dv/harness/mgmt_soc/gpio/gpio.c +++ b/verilog/dv/harness/mgmt_soc/gpio/gpio.c
@@ -1,4 +1,4 @@ -#include "../defs.h" +#include "../../defs.h" // --------------------------------------------------------
diff --git a/verilog/dv/harness/mgmt_soc/gpio/gpio_tb.v b/verilog/dv/harness/mgmt_soc/gpio/gpio_tb.v index c20ba26..35c8cf3 100644 --- a/verilog/dv/harness/mgmt_soc/gpio/gpio_tb.v +++ b/verilog/dv/harness/mgmt_soc/gpio/gpio_tb.v
@@ -20,7 +20,7 @@ `timescale 1 ns / 1 ps -`include "harness.v" +`include "harness_chip.v" `include "spiflash.v" module gpio_tb; @@ -151,7 +151,7 @@ assign VSS = 1'b0; assign VDD1V8 = 1'b1; - harness uut ( + harness_chip uut ( .vdd (VDD3V3), .vdd1v8 (VDD1V8), .vss (VSS),
diff --git a/verilog/dv/harness/mgmt_soc/hkspi/Makefile b/verilog/dv/harness/mgmt_soc/hkspi/Makefile index 2850baa..07ea208 100644 --- a/verilog/dv/harness/mgmt_soc/hkspi/Makefile +++ b/verilog/dv/harness/mgmt_soc/hkspi/Makefile
@@ -1,3 +1,8 @@ +FIRMWARE_PATH = ../.. +RTL_PATH = ../../../../rtl +IP_PATH = ../../../../ip +BEHAVIOURAL_MODELS = ../../ + .SUFFIXES: PATTERN = hkspi @@ -7,14 +12,14 @@ hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -I ../ -I ../../../../ip -I ../../../../rtl \ + iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ - + %.vcd: %.vvp vvp $< -%.elf: %.c ../sections.lds ../start.s - /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ ../start.s $< +%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s + /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< %.hex: %.elf /ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< /dev/stdout | sed -e '1 s/@10000000/@00000000/; 2,65537 d;' > $@
diff --git a/verilog/dv/harness/mgmt_soc/hkspi/hkspi.c b/verilog/dv/harness/mgmt_soc/hkspi/hkspi.c index d572727..a415214 100644 --- a/verilog/dv/harness/mgmt_soc/hkspi/hkspi.c +++ b/verilog/dv/harness/mgmt_soc/hkspi/hkspi.c
@@ -1,4 +1,4 @@ -#include "../defs.h" +#include "../../defs.h" // --------------------------------------------------------
diff --git a/verilog/dv/harness/mgmt_soc/hkspi/hkspi_tb.v b/verilog/dv/harness/mgmt_soc/hkspi/hkspi_tb.v index 0edc43d..09d1dab 100644 --- a/verilog/dv/harness/mgmt_soc/hkspi/hkspi_tb.v +++ b/verilog/dv/harness/mgmt_soc/hkspi/hkspi_tb.v
@@ -4,7 +4,7 @@ `timescale 1 ns / 1 ps -`include "harness.v" +`include "harness_chip.v" `include "spiflash.v" `include "tbuart.v" @@ -167,31 +167,31 @@ write_byte(8'h00); // Address (register 3 = product ID) read_byte(tbdata); $display("Read register 0 = 0x%02x (should be 0x00)", tbdata); - if(tbdata != 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end + if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end read_byte(tbdata); $display("Read register 1 = 0x%02x (should be 0x04)", tbdata); - if(tbdata != 8'h14) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end + if(tbdata !== 8'h14) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end read_byte(tbdata); $display("Read register 2 = 0x%02x (should be 0x56)", tbdata); - if(tbdata != 8'h56) begin $display("Monitor: Test HK SPI (RTL) Failed, %02x", tbdata); $finish; end + if(tbdata !== 8'h56) begin $display("Monitor: Test HK SPI (RTL) Failed, %02x", tbdata); $finish; end read_byte(tbdata); $display("Read register 3 = 0x%02x (should be 0x05)", tbdata); - if(tbdata != 8'h05) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end + if(tbdata !== 8'h05) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end read_byte(tbdata); $display("Read register 4 = 0x%02x (should be 0x07)", tbdata); - if(tbdata != 8'h07) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end + if(tbdata !== 8'h07) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end read_byte(tbdata); $display("Read register 5 = 0x%02x (should be 0x01)", tbdata); - if(tbdata != 8'h01) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end + if(tbdata !== 8'h01) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end read_byte(tbdata); $display("Read register 6 = 0x%02x (should be 0x00)", tbdata); - if(tbdata != 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end + if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end read_byte(tbdata); $display("Read register 7 = 0x%02x (should be 0x00)", tbdata); - if(tbdata != 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end + if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end read_byte(tbdata); $display("Read register 8 = 0x%02x (should be 0x00)", tbdata); - if(tbdata != 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end + if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end end_csb(); @@ -209,7 +209,7 @@ assign VSS = 1'b0; assign VDD1V8 = 1'b1; - harness uut ( + harness_chip uut ( .vdd (VDD3V3), .vdd1v8 (VDD1V8), .vss (VSS),
diff --git a/verilog/dv/harness/mgmt_soc/mem/Makefile b/verilog/dv/harness/mgmt_soc/mem/Makefile index d63df1b..fc85291 100644 --- a/verilog/dv/harness/mgmt_soc/mem/Makefile +++ b/verilog/dv/harness/mgmt_soc/mem/Makefile
@@ -1,4 +1,9 @@ +FIRMWARE_PATH = ../.. +RTL_PATH = ../../../../rtl +IP_PATH = ../../../../ip +BEHAVIOURAL_MODELS = ../../ + .SUFFIXES: PATTERN = mem @@ -8,14 +13,14 @@ hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -I ../ -I ../../../../ip -I ../../../../rtl \ + iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ %.vcd: %.vvp vvp $< -%.elf: %.c ../sections.lds ../start.s - /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ ../start.s $< +%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s + /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< %.hex: %.elf /ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@
diff --git a/verilog/dv/harness/mgmt_soc/mem/mem.c b/verilog/dv/harness/mgmt_soc/mem/mem.c index 0bff65d..31d0f75 100644 --- a/verilog/dv/harness/mgmt_soc/mem/mem.c +++ b/verilog/dv/harness/mgmt_soc/mem/mem.c
@@ -1,4 +1,4 @@ -#include "../defs.h" +#include "../../defs.h" // --------------------------------------------------------
diff --git a/verilog/dv/harness/mgmt_soc/mem/mem_tb.v b/verilog/dv/harness/mgmt_soc/mem/mem_tb.v index 09bb0a7..0d0c93d 100644 --- a/verilog/dv/harness/mgmt_soc/mem/mem_tb.v +++ b/verilog/dv/harness/mgmt_soc/mem/mem_tb.v
@@ -20,7 +20,7 @@ `timescale 1 ns / 1 ps -`include "harness.v" +`include "harness_chip.v" `include "spiflash.v" module mem_tb; @@ -146,7 +146,7 @@ assign VDD3V3 = 1'b1; assign VDD1V8 = 1'b1; - harness uut ( + harness_chip uut ( .vdd (VDD3V3), .vdd1v8 (VDD1V8), .vss (VSS),
diff --git a/verilog/dv/harness/mgmt_soc/mprj_ctrl/Makefile b/verilog/dv/harness/mgmt_soc/mprj_ctrl/Makefile new file mode 100644 index 0000000..3b396d7 --- /dev/null +++ b/verilog/dv/harness/mgmt_soc/mprj_ctrl/Makefile
@@ -0,0 +1,37 @@ +FIRMWARE_PATH = ../.. +RTL_PATH = ../../../../rtl +IP_PATH = ../../../../ip +BEHAVIOURAL_MODELS = ../../ + +.SUFFIXES: + +PATTERN = mprj_ctrl + +all: ${PATTERN:=.vcd} + +hex: ${PATTERN:=.hex} + +%.vvp: %_tb.v %.hex + iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \ + $< -o $@ + +%.vcd: %.vvp + vvp $< + +%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s + /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T, $(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + +%.hex: %.elf + /ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@ + # to fix flash base address + sed -i 's/@10000000/@00000000/g' $@ + +%.bin: %.elf + /ef/apps/bin/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ + +# ---- Clean ---- + +clean: + rm -f *.elf *.hex *.bin *.vvp *.vcd *.log + +.PHONY: clean hex all \ No newline at end of file
diff --git a/verilog/dv/harness/mgmt_soc/mprj_ctrl/mprj_ctrl.c b/verilog/dv/harness/mgmt_soc/mprj_ctrl/mprj_ctrl.c new file mode 100644 index 0000000..97b8148 --- /dev/null +++ b/verilog/dv/harness/mgmt_soc/mprj_ctrl/mprj_ctrl.c
@@ -0,0 +1,38 @@ +#include "../../defs.h" + +// -------------------------------------------------------- + +/* + Mega-Project IO Control Test +*/ + +void main() +{ + /* All GPIO pins are configured to be output */ + reg_gpio_data = 0; + reg_gpio_ena = 0x0000; + + // start test + reg_gpio_data = 0xA040; + + // Write to IO Control + reg_mprj_io_0 = 0x004F; + if(0x004F != reg_mprj_io_0) reg_gpio_data = 0xAB40; + reg_gpio_data = 0xAB41; + + // Write to IO Control + reg_mprj_io_1 = 0x005F; + if(0x005F != reg_mprj_io_1) reg_gpio_data = 0xAB50; + reg_gpio_data = 0xAB51; + + // Write to IO Control + reg_mprj_io_2 = 0x006F; + if(0x006F != reg_mprj_io_2) reg_gpio_data = 0xAB60; + reg_gpio_data = 0xAB61; + + // Write to IO Control + reg_mprj_io_3 = 0xF0F5; + if(0xF0F5 != reg_mprj_io_3) reg_gpio_data = 0xAB70; + reg_gpio_data = 0xAB71; +} +
diff --git a/verilog/dv/harness/mgmt_soc/xbar/xbar_tb.v b/verilog/dv/harness/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v similarity index 60% rename from verilog/dv/harness/mgmt_soc/xbar/xbar_tb.v rename to verilog/dv/harness/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v index b9357f0..bcbbe12 100644 --- a/verilog/dv/harness/mgmt_soc/xbar/xbar_tb.v +++ b/verilog/dv/harness/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
@@ -1,10 +1,10 @@ `timescale 1 ns / 1 ps -`include "harness.v" +`include "harness_chip.v" `include "spiflash.v" -module xbar_tb; +module mprj_ctrl_tb; reg XCLK; reg XI; @@ -22,6 +22,10 @@ wire flash_io3; wire SDO; + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + always #10 XCLK <= (XCLK === 1'b0); always #220 XI <= (XI === 1'b0); @@ -31,57 +35,41 @@ end initial begin - $dumpfile("xbar_tb.vcd"); - $dumpvars(0, xbar_tb); + $dumpfile("mprj_ctrl_tb.vcd"); + $dumpvars(0, mprj_ctrl_tb); repeat (25) begin repeat (1000) @(posedge XCLK); $display("+1000 cycles"); end $display("%c[1;31m",27); - $display ("Monitor: Timeout, Test Crossbar Switch (RTL) Failed"); - $display("%c[0m", 27); + $display ("Monitor: Timeout, Test Mega-Project (RTL) Failed"); + $display("%c[0m",27); $finish; end always @(gpio) begin if(gpio == 16'hA040) begin - $display("Crossbar Switch Test started"); + $display("Mega-Project control Test started"); end else if(gpio == 16'hAB40) begin $display("%c[1;31m",27); - $display("Monitor: Crossbar test R/W from QSPI CTRL slave failed."); + $display("Monitor: IO control R/W failed"); $display("%c[0m",27); $finish; end else if(gpio == 16'hAB41) begin - $display("Monitor: Crossbar test R/W from QSPI CTRL slave passed"); + $display("Monitor: IO control R/W passed"); end else if(gpio == 16'hAB50) begin $display("%c[1;31m",27); - $display("Monitor: Crossbar test R/W from storage area failed."); + $display("Monitor: power control R/W failed"); $display("%c[0m",27); $finish; end else if(gpio == 16'hAB51) begin - $display("Monitor: Crossbar test R/W from storage area passed."); - end - else if(gpio == 16'hAB60) begin - $display("%c[1;31m",27); - $display("Monitor: Crossbar test R/W from mega project 1st slave failed."); - $display("%c[0m",27); - $finish; - end else if(gpio == 16'hAB61) begin - $display("Monitor: Crossbar test R/W from mega project 1st slave passed."); - end - else if(gpio == 16'hAB70) begin - $display("%c[1;31m",27); - $display("Monitor: Crossbar test R/W from mega project 2nd slave passed."); - $display("%c[0m",27); - $finish; - end else if(gpio == 16'hAB71) begin - $display("Monitor: Crossbar test R/W from mega project 2nd slave passed."); - $display("Monitor: Timeout, Test Crossbar Switch (RTL) Passed."); + $display("Monitor: power control R/W passed"); + $display("Monitor: Mega-Project control (RTL) test passed."); $finish; - end + end end initial begin @@ -107,11 +95,11 @@ assign VDD1V8 = 1'b1; assign VDD3V3 = 1'b1; - harness uut ( + harness_chip uut ( .vdd (VDD3V3), .vdd1v8 (VDD1V8), .vss (VSS), - .xi (XI), + .xi (XI), .xclk (XCLK), .SDI (SDI), .SDO (SDO), @@ -137,7 +125,7 @@ ); spiflash #( - .FILENAME("xbar.hex") + .FILENAME("mprj_ctrl.hex") ) spiflash ( .csb(flash_csb), .clk(flash_clk),
diff --git a/verilog/dv/harness/mgmt_soc/perf/Makefile b/verilog/dv/harness/mgmt_soc/perf/Makefile index dad371f..b24bd84 100644 --- a/verilog/dv/harness/mgmt_soc/perf/Makefile +++ b/verilog/dv/harness/mgmt_soc/perf/Makefile
@@ -1,3 +1,8 @@ +FIRMWARE_PATH = ../.. +RTL_PATH = ../../../../rtl +IP_PATH = ../../../../ip +BEHAVIOURAL_MODELS = ../../ + .SUFFIXES: PATTERN = perf @@ -7,14 +12,14 @@ hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -I ../ -I ../../../../ip -I ../../../../rtl \ + iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ %.vcd: %.vvp vvp $< -%.elf: %.c ../sections.lds ../start.s - /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ ../start.s $< +%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s + /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< %.hex: %.elf /ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@
diff --git a/verilog/dv/harness/mgmt_soc/perf/perf.c b/verilog/dv/harness/mgmt_soc/perf/perf.c index 4dc34b1..bd94f5d 100644 --- a/verilog/dv/harness/mgmt_soc/perf/perf.c +++ b/verilog/dv/harness/mgmt_soc/perf/perf.c
@@ -1,4 +1,4 @@ -#include "../defs.h" +#include "../../defs.h" // --------------------------------------------------------
diff --git a/verilog/dv/harness/mgmt_soc/perf/perf_tb.v b/verilog/dv/harness/mgmt_soc/perf/perf_tb.v index edd10ba..3e5edbc 100644 --- a/verilog/dv/harness/mgmt_soc/perf/perf_tb.v +++ b/verilog/dv/harness/mgmt_soc/perf/perf_tb.v
@@ -20,7 +20,7 @@ `timescale 1 ns / 1 ps -`include "harness.v" +`include "harness_chip.v" `include "spiflash.v" module striVe_perf_tb; @@ -122,7 +122,7 @@ assign VDD1V8 = 1'b1; assign VDD3V3 = 1'b1; - harness uut ( + harness_chip uut ( .vdd (VDD3V3 ), .vdd1v8 (VDD1V8), .vss (VSS),
diff --git a/verilog/dv/harness/mgmt_soc/sysctrl/Makefile b/verilog/dv/harness/mgmt_soc/sysctrl/Makefile index 0b43365..a4a14a6 100644 --- a/verilog/dv/harness/mgmt_soc/sysctrl/Makefile +++ b/verilog/dv/harness/mgmt_soc/sysctrl/Makefile
@@ -1,3 +1,8 @@ +FIRMWARE_PATH = ../.. +RTL_PATH = ../../../../rtl +IP_PATH = ../../../../ip +BEHAVIOURAL_MODELS = ../../ + .SUFFIXES: PATTERN = sysctrl @@ -7,14 +12,14 @@ hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -I ../ -I ../../../../ip -I ../../../../rtl \ + iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ %.vcd: %.vvp vvp $< -%.elf: %.c ../sections.lds ../start.s - /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ ../start.s $< +%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s + /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< %.hex: %.elf /ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@
diff --git a/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl.c b/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl.c index a4a6762..023a08c 100644 --- a/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl.c +++ b/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl.c
@@ -1,4 +1,4 @@ -#include "../defs.h" +#include "../../defs.h" // --------------------------------------------------------
diff --git a/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl_tb.v b/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl_tb.v index d1e4439..4932e0d 100644 --- a/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl_tb.v +++ b/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl_tb.v
@@ -1,7 +1,7 @@ `timescale 1 ns / 1 ps -`include "harness.v" +`include "harness_chip.v" `include "spiflash.v" module sysctrl_tb; @@ -127,7 +127,7 @@ assign VDD1V8 = 1'b1; assign VDD3V3 = 1'b1; - harness uut ( + harness_chip uut ( .vdd (VDD3V3), .vdd1v8 (VDD1V8), .vss (VSS),
diff --git a/verilog/dv/harness/mgmt_soc/uart/Makefile b/verilog/dv/harness/mgmt_soc/uart/Makefile index 057be64..3ce3936 100644 --- a/verilog/dv/harness/mgmt_soc/uart/Makefile +++ b/verilog/dv/harness/mgmt_soc/uart/Makefile
@@ -1,4 +1,8 @@ # ---- Test patterns for project striVe ---- +FIRMWARE_PATH = ../.. +RTL_PATH = ../../../../rtl +IP_PATH = ../../../../ip +BEHAVIOURAL_MODELS = ../../ .SUFFIXES: @@ -9,14 +13,14 @@ hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -I ../ -I ../../../../ip -I ../../../../rtl \ + iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ %.vcd: %.vvp vvp $< -%.elf: %.c ../sections.lds ../start.s - /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ ../start.s $< +%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s + /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< %.hex: %.elf /ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@
diff --git a/verilog/dv/harness/mgmt_soc/uart/uart.c b/verilog/dv/harness/mgmt_soc/uart/uart.c index fe362f8..bf21144 100644 --- a/verilog/dv/harness/mgmt_soc/uart/uart.c +++ b/verilog/dv/harness/mgmt_soc/uart/uart.c
@@ -1,19 +1,5 @@ -#include "../defs.h" - -// -------------------------------------------------------- - -void putchar(char c) -{ - if (c == '\n') - putchar('\r'); - reg_uart_data = c; -} - -void print(const char *p) -{ - while (*p) - putchar(*(p++)); -} +#include "../../defs.h" +#include "../stub.c" // --------------------------------------------------------
diff --git a/verilog/dv/harness/mgmt_soc/uart/uart_tb.v b/verilog/dv/harness/mgmt_soc/uart/uart_tb.v index 56c76f2..c031659 100644 --- a/verilog/dv/harness/mgmt_soc/uart/uart_tb.v +++ b/verilog/dv/harness/mgmt_soc/uart/uart_tb.v
@@ -20,7 +20,7 @@ `timescale 1 ns / 1 ps -`include "harness.v" +`include "harness_chip.v" `include "spiflash.v" `include "tbuart.v" @@ -105,7 +105,7 @@ assign VDD1V8 = 1'b1; assign VDD3V3 = 1'b1; - harness uut ( + harness_chip uut ( .vdd (VDD3V3), .vdd1v8 (VDD1V8), .vss (VSS),
diff --git a/verilog/dv/harness/mgmt_soc/xbar/Makefile b/verilog/dv/harness/mgmt_soc/xbar/Makefile deleted file mode 100644 index 5302d06..0000000 --- a/verilog/dv/harness/mgmt_soc/xbar/Makefile +++ /dev/null
@@ -1,32 +0,0 @@ -.SUFFIXES: - -PATTERN = xbar - -all: ${PATTERN:=.vcd} - -hex: ${PATTERN:=.hex} - -%.vvp: %_tb.v %.hex - iverilog -I ../ -I ../../../../ip -I ../../../../rtl \ - $< -o $@ - -%.vcd: %.vvp - vvp $< - -%.elf: %.c ../sections.lds ../start.s - /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ ../start.s $< - -%.hex: %.elf - /ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@ - # to fix flash base address - sed -i 's/@10000000/@00000000/g' $@ - -%.bin: %.elf - /ef/apps/bin/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ - -# ---- Clean ---- - -clean: - rm -f *.elf *.hex *.bin *.vvp *.vcd *.log - -.PHONY: clean hex all
diff --git a/verilog/dv/harness/mgmt_soc/xbar/xbar.c b/verilog/dv/harness/mgmt_soc/xbar/xbar.c deleted file mode 100644 index 5565f1f..0000000 --- a/verilog/dv/harness/mgmt_soc/xbar/xbar.c +++ /dev/null
@@ -1,41 +0,0 @@ -#include "../defs.h" - -// -------------------------------------------------------- - -/* - Crosbbar Switch Test - - Reads default value of SPI-Controlled registers - - Flags failure/success using gpio -*/ -void main() -{ - int i; - - reg_gpio_data = 0; - reg_gpio_ena = 0x0000; - - // start test - reg_gpio_data = 0xA040; - - // Write & Read from QSPI CTRL Slave - qspi_ctrl_slave = 0xA0A1; - if(0xA0A1 != qspi_ctrl_slave) reg_gpio_data = 0xAB40; - reg_gpio_data = 0xAB41; - - // Write & Read from storage area Slave - storage_area_slave = 0xB0B1; - if(0xB0B1 != storage_area_slave) reg_gpio_data = 0xAB50; - reg_gpio_data = 0xAB51; - - // Write & Read from Mega Project 1st slave - mega_any_slave1 = 0xC0C1; - if(0xC0C1 != mega_any_slave1) reg_gpio_data = 0xAB60; - reg_gpio_data = 0xAB61; - - // Write & Read from Mega Project 1st slave - mega_any_slave2 = 0xD0D1; - if(0xD0D1 != mega_any_slave2) reg_gpio_data = 0xAB70; - reg_gpio_data = 0xAB71; - -} -
diff --git a/verilog/dv/wb/Makefile b/verilog/dv/harness/mprj_counter/Makefile similarity index 80% rename from verilog/dv/wb/Makefile rename to verilog/dv/harness/mprj_counter/Makefile index 7b0e09b..6b5248c 100644 --- a/verilog/dv/wb/Makefile +++ b/verilog/dv/harness/mprj_counter/Makefile
@@ -3,7 +3,7 @@ .SUFFIXES: .SILENT: clean all -PATTERNS = gpio_wb intercon_wb spimemio_wb uart_wb crossbar_wb arbiter_wb +PATTERNS = io_ports la_test1 la_test2 all: ${PATTERNS} for i in ${PATTERNS}; do \
diff --git a/verilog/dv/harness/mprj_counter/README.md b/verilog/dv/harness/mprj_counter/README.md new file mode 100644 index 0000000..16afd68 --- /dev/null +++ b/verilog/dv/harness/mprj_counter/README.md
@@ -0,0 +1,20 @@ +# Mega-Project Counter Tests + +The directory includes three tests for the counter mega-project example: + +1) IO Ports Test: + + * Configures the Mega-project lower 8 IO pins as outputs + * Observes the counter value through the configured pins in the testbench + + 2) Logic Analyzer Test 1: + + * Configures LA probes [31:0] as inputs to the management SoC to monitor the counter value + * Configures LA probes [63:32] as outputs from the management SoC to set the counter initial value + * Flags when counter value exceeds 500 through the management SoC gpio + * Outputs message to the UART when the test concludes successfuly + + 3) Logic Analyzer Test 2: + + * Configures LA probes [64] and [65] as outputs from the management SoC to set counter clock and reset values + * Provides counter clock and monitors the counter value after five clock cycles
diff --git a/verilog/dv/harness/mprj_counter/io_ports/Makefile b/verilog/dv/harness/mprj_counter/io_ports/Makefile new file mode 100644 index 0000000..8f0cd33 --- /dev/null +++ b/verilog/dv/harness/mprj_counter/io_ports/Makefile
@@ -0,0 +1,37 @@ +FIRMWARE_PATH = ../.. +RTL_PATH = ../../../../rtl +IP_PATH = ../../../../ip +BEHAVIOURAL_MODELS = ../../ + +.SUFFIXES: + +PATTERN = io_ports + +all: ${PATTERN:=.vcd} + +hex: ${PATTERN:=.hex} + +%.vvp: %_tb.v %.hex + iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \ + $< -o $@ + +%.vcd: %.vvp + vvp $< + +%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s + /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + +%.hex: %.elf + /ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@ + # to fix flash base address + sed -i 's/@10000000/@00000000/g' $@ + +%.bin: %.elf + /ef/apps/bin/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ + +# ---- Clean ---- + +clean: + rm -f *.elf *.hex *.bin *.vvp *.vcd *.log + +.PHONY: clean hex all \ No newline at end of file
diff --git a/verilog/dv/harness/mprj_counter/io_ports/io_ports.c b/verilog/dv/harness/mprj_counter/io_ports/io_ports.c new file mode 100644 index 0000000..e4b9cf4 --- /dev/null +++ b/verilog/dv/harness/mprj_counter/io_ports/io_ports.c
@@ -0,0 +1,40 @@ +#include "../../defs.h" + +/* + IO Test: + - Configures MPRJ lower 8-IO pins as outputs + - Observes counter value through the MPRJ lower 8 IO pins (in the testbench) +*/ + +void main() +{ + /* + IO Control Registers + + | DM | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | ENH | HLDH_N | OEB_N | + | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | + + Output: 0000_0110_0000_1110 (0x060E) + | DM | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | ENH | HLDH_N | OEB_N | + | 110 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | + + + Input: 0000_0001_0000_1111 (0x010F) + | DM | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | ENH | HLDH_N | OEB_N | + | 001 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | + + */ + + // Configure lower 8-IOs as output + // Observe counter value in the testbench + reg_mprj_io_0 = 0x060E; + reg_mprj_io_1 = 0x060E; + reg_mprj_io_2 = 0x060E; + reg_mprj_io_3 = 0x060E; + reg_mprj_io_4 = 0x060E; + reg_mprj_io_5 = 0x060E; + reg_mprj_io_6 = 0x060E; + reg_mprj_io_7 = 0x060E; + +} +
diff --git a/verilog/dv/harness/mprj_counter/io_ports/io_ports_tb.v b/verilog/dv/harness/mprj_counter/io_ports/io_ports_tb.v new file mode 100644 index 0000000..e30f139 --- /dev/null +++ b/verilog/dv/harness/mprj_counter/io_ports/io_ports_tb.v
@@ -0,0 +1,139 @@ + +`timescale 1 ns / 1 ps + +`include "harness_chip.v" +`include "spiflash.v" + +module io_ports_tb; + reg XCLK; + reg XI; + + reg real adc_h, adc_l; + reg real adc_0, adc_1; + reg real comp_n, comp_p; + reg SDI, CSB, SCK, RSTB; + wire SDO; + + wire [15:0] gpio; + wire [31:0] mprj_io; + wire [7:0] mprj_io_0; + + assign mprj_io_0 = mprj_io[7:0]; + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 XCLK <= (XCLK === 1'b0); + always #220 XI <= (XI === 1'b0); + + initial begin + XI = 0; + XCLK = 0; + end + + initial begin + $dumpfile("io_ports.vcd"); + $dumpvars(0, io_ports_tb); + + // Repeat cycles of 1000 XCLK edges as needed to complete testbench + repeat (25) begin + repeat (1000) @(posedge XCLK); + // $display("+1000 cycles"); + end + $display("%c[1;31m",27); + $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed"); + $display("%c[0m",27); + $finish; + end + + initial begin + // Observe Output pins [7:0] + wait(mprj_io_0==8'h01); + wait(mprj_io_0==8'h02); + wait(mprj_io_0==8'h03); + wait(mprj_io_0==8'h04); + wait(mprj_io_0==8'h05); + wait(mprj_io_0==8'h06); + wait(mprj_io_0==8'h07); + wait(mprj_io_0==8'h08); + wait(mprj_io_0==8'h09); + wait(mprj_io_0==8'h0A); + wait(mprj_io_0==8'hFF); + wait(mprj_io_0==8'h00); + $display("Monitor: Test 1 Mega-Project IO (RTL) Passed"); + $finish; + end + + initial begin + CSB <= 1'b1; + SCK <= 1'b0; + SDI <= 1'b0; + RSTB <= 1'b0; + #1000; + RSTB <= 1'b1; // Release reset + #2000; + CSB <= 1'b0; // Apply CSB to start transmission + end + + always @(mprj_io) begin + #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]); + end + + wire VDD1V8; + wire VDD3V3; + wire VSS; + + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; + wire flash_io2; + wire flash_io3; + + assign VSS = 1'b0; + assign VDD1V8 = 1'b1; + assign VDD3V3 = 1'b1; + + harness_chip uut ( + .vdd (VDD3V3), + .vdd1v8 (VDD1V8), + .vss (VSS), + .xi (XI), + .xclk (XCLK), + .SDI (SDI), + .SDO (SDO), + .CSB (CSB), + .SCK (SCK), + .ser_rx (1'b0), + .ser_tx (tbuart_rx), + .irq (1'b0), + .gpio (gpio), + .mprj_io (mprj_io), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .flash_io2(flash_io2), + .flash_io3(flash_io3), + .adc_high (adc_h), + .adc_low (adc_l), + .adc0_in (adc_0), + .adc1_in (adc_1), + .RSTB (RSTB), + .comp_inp (comp_p), + .comp_inn (comp_n) + ); + + spiflash #( + .FILENAME("io_ports.hex") + ) spiflash ( + .csb(flash_csb), + .clk(flash_clk), + .io0(flash_io0), + .io1(flash_io1), + .io2(flash_io2), + .io3(flash_io3) + ); + +endmodule
diff --git a/verilog/dv/harness/mprj_counter/la_test1/Makefile b/verilog/dv/harness/mprj_counter/la_test1/Makefile new file mode 100644 index 0000000..da557a6 --- /dev/null +++ b/verilog/dv/harness/mprj_counter/la_test1/Makefile
@@ -0,0 +1,37 @@ +FIRMWARE_PATH = ../.. +RTL_PATH = ../../../../rtl +IP_PATH = ../../../../ip +BEHAVIOURAL_MODELS = ../../ + +.SUFFIXES: + +PATTERN = la_test1 + +all: ${PATTERN:=.vcd} + +hex: ${PATTERN:=.hex} + +%.vvp: %_tb.v %.hex + iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \ + $< -o $@ + +%.vcd: %.vvp + vvp $< + +%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s + /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + +%.hex: %.elf + /ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@ + # to fix flash base address + sed -i 's/@10000000/@00000000/g' $@ + +%.bin: %.elf + /ef/apps/bin/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ + +# ---- Clean ---- + +clean: + rm -f *.elf *.hex *.bin *.vvp *.vcd *.log + +.PHONY: clean hex all \ No newline at end of file
diff --git a/verilog/dv/harness/mprj_counter/la_test1/la_test1.c b/verilog/dv/harness/mprj_counter/la_test1/la_test1.c new file mode 100644 index 0000000..1404a1e --- /dev/null +++ b/verilog/dv/harness/mprj_counter/la_test1/la_test1.c
@@ -0,0 +1,51 @@ +#include "../../defs.h" +#include "../../stub.c" + +// -------------------------------------------------------- + +/* + MPRJ Logic Analyzer Test: + - Observes counter value through LA probes [31:0] + - Sets counter initial value through LA probes [63:32] + - Flags when counter value exceeds 500 through the management SoC gpio + - Outputs message to the UART when the test concludes successfuly +*/ + +void main() +{ + + // All GPIO pins are configured to be output + // Used to flad the start/end of a test + reg_gpio_data = 0; + reg_gpio_ena = 0x0000; + + // Set UART clock to 64 kbaud + reg_uart_clkdiv = 625; + + // Configure LA probes [31:0], [127:64] as inputs to the cpu + // Configure LA probes [63:32] as outputs from the cpu + reg_la0_ena = 0xFFFFFFFF; // [31:0] + reg_la1_ena = 0x00000000; // [63:32] + reg_la2_ena = 0xFFFFFFFF; // [95:64] + reg_la3_ena = 0xFFFFFFFF; // [127:96] + + // Flag start of the test + reg_gpio_data = 0xAB40; + + // Set Counter value to zero through LA probes [63:32] + reg_la1_data = 0x00000000; + + // Configure LA probes from [63:32] as inputs to disable counter write + reg_la1_ena = 0xFFFFFFFF; + + while (1) { + if (reg_la0_data > 0x1F4) { + reg_gpio_data = 0xAB41; + break; + } + } + print("\n"); + print("Monitor: Test 2 Passed\n\n"); + reg_gpio_data = 0xAB51; +} +
diff --git a/verilog/dv/harness/mprj_counter/la_test1/la_test1_tb.v b/verilog/dv/harness/mprj_counter/la_test1/la_test1_tb.v new file mode 100644 index 0000000..1eb6885 --- /dev/null +++ b/verilog/dv/harness/mprj_counter/la_test1/la_test1_tb.v
@@ -0,0 +1,132 @@ + +`timescale 1 ns / 1 ps + +`include "harness_chip.v" +`include "spiflash.v" +`include "tbuart.v" + +module la_test1_tb; + reg XCLK; + reg XI; + + reg real adc_h, adc_l; + reg real adc_0, adc_1; + reg real comp_n, comp_p; + reg SDI, CSB, SCK, RSTB; + wire SDO; + + wire [15:0] gpio; + wire [31:0] mprj_io; + wire [7:0] mprj_io_0; + + assign mprj_io_0 = mprj_io[7:0]; + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 XCLK <= (XCLK === 1'b0); + always #220 XI <= (XI === 1'b0); + + initial begin + XI = 0; + XCLK = 0; + end + + initial begin + $dumpfile("la_test1.vcd"); + $dumpvars(0, la_test1_tb); + + // Repeat cycles of 1000 XCLK edges as needed to complete testbench + repeat (200) begin + repeat (1000) @(posedge XCLK); + // $display("+1000 cycles"); + end + $display("%c[1;31m",27); + $display ("Monitor: Timeout, Test Mega-Project IO (RTL) Failed"); + $display("%c[0m",27); + $finish; + end + + initial begin + wait(gpio == 16'hAB40); + $display("LA Test 1 started"); + wait(gpio == 16'hAB41); + wait(gpio == 16'hAB51); + #10000; + $finish; + end + + initial begin + CSB <= 1'b1; + SCK <= 1'b0; + SDI <= 1'b0; + RSTB <= 1'b0; + #1000; + RSTB <= 1'b1; // Release reset + #2000; + CSB <= 1'b0; // Apply CSB to start transmission + end + + wire VDD1V8; + wire VDD3V3; + wire VSS; + + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; + wire flash_io2; + wire flash_io3; + + assign VSS = 1'b0; + assign VDD1V8 = 1'b1; + assign VDD3V3 = 1'b1; + + harness_chip uut ( + .vdd (VDD3V3), + .vdd1v8 (VDD1V8), + .vss (VSS), + .xi (XI), + .xclk (XCLK), + .SDI (SDI), + .SDO (SDO), + .CSB (CSB), + .SCK (SCK), + .ser_rx (1'b0), + .ser_tx (tbuart_rx), + .irq (1'b0), + .gpio (gpio), + .mprj_io (mprj_io), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .flash_io2(flash_io2), + .flash_io3(flash_io3), + .adc_high (adc_h), + .adc_low (adc_l), + .adc0_in (adc_0), + .adc1_in (adc_1), + .RSTB (RSTB), + .comp_inp (comp_p), + .comp_inn (comp_n) + ); + + spiflash #( + .FILENAME("la_test1.hex") + ) spiflash ( + .csb(flash_csb), + .clk(flash_clk), + .io0(flash_io0), + .io1(flash_io1), + .io2(flash_io2), + .io3(flash_io3) + ); + + // Testbench UART + tbuart tbuart ( + .ser_rx(tbuart_rx) + ); + +endmodule
diff --git a/verilog/dv/harness/mprj_counter/la_test2/Makefile b/verilog/dv/harness/mprj_counter/la_test2/Makefile new file mode 100644 index 0000000..c8b727b --- /dev/null +++ b/verilog/dv/harness/mprj_counter/la_test2/Makefile
@@ -0,0 +1,37 @@ +FIRMWARE_PATH = ../.. +RTL_PATH = ../../../../rtl +IP_PATH = ../../../../ip +BEHAVIOURAL_MODELS = ../../ + +.SUFFIXES: + +PATTERN = la_test2 + +all: ${PATTERN:=.vcd} + +hex: ${PATTERN:=.hex} + +%.vvp: %_tb.v %.hex + iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \ + $< -o $@ + +%.vcd: %.vvp + vvp $< + +%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s + /ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + +%.hex: %.elf + /ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@ + # to fix flash base address + sed -i 's/@10000000/@00000000/g' $@ + +%.bin: %.elf + /ef/apps/bin/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ + +# ---- Clean ---- + +clean: + rm -f *.elf *.hex *.bin *.vvp *.vcd *.log + +.PHONY: clean hex all \ No newline at end of file
diff --git a/verilog/dv/harness/mprj_counter/la_test2/la_test2.c b/verilog/dv/harness/mprj_counter/la_test2/la_test2.c new file mode 100644 index 0000000..e9f5ece --- /dev/null +++ b/verilog/dv/harness/mprj_counter/la_test2/la_test2.c
@@ -0,0 +1,47 @@ +#include "../../defs.h" +#include "../../stub.c" + +/* + MPRJ LA Test: + - Sets counter clk through LA[64] + - Sets counter rst through LA[65] + - Observes count value for five clk cycle through LA[31:0] +*/ + +int clk = 0; +int i; + +void main() +{ + // All GPIO pins are configured to be output + // Used to flad the start/end of a test + reg_gpio_data = 0; + reg_gpio_ena = 0x0000; + + // Configure All LA probes as inputs to the cpu + reg_la0_ena = 0xFFFFFFFF; // [31:0] + reg_la1_ena = 0xFFFFFFFF; // [63:32] + reg_la2_ena = 0xFFFFFFFF; // [95:64] + reg_la3_ena = 0xFFFFFFFF; // [127:96] + + // Flag start of the test + reg_gpio_data = 0xAB60; + + // Configure LA[64] LA[65] as outputs from the cpu + reg_la2_ena = 0xFFFFFFFC; + + // Set clk & reset to one + reg_la2_data = 0x00000003; + + // Toggle clk & de-assert reset + for (i=0; i<11; i=i+1) { + clk = !clk; + reg_la2_data = 0x00000000 | clk; + } + + if (reg_la0_data == 0x05) { + reg_gpio_data = 0xAB61; + } + +} +
diff --git a/verilog/dv/harness/mprj_counter/la_test2/la_test2_tb.v b/verilog/dv/harness/mprj_counter/la_test2/la_test2_tb.v new file mode 100644 index 0000000..a3e6223 --- /dev/null +++ b/verilog/dv/harness/mprj_counter/la_test2/la_test2_tb.v
@@ -0,0 +1,125 @@ + +`timescale 1 ns / 1 ps + +`include "harness_chip.v" +`include "spiflash.v" + +module la_test2_tb; + reg XCLK; + reg XI; + + reg real adc_h, adc_l; + reg real adc_0, adc_1; + reg real comp_n, comp_p; + reg SDI, CSB, SCK, RSTB; + wire SDO; + + wire [15:0] gpio; + wire [31:0] mprj_io; + wire [7:0] mprj_io_0; + + assign mprj_io_0 = mprj_io[7:0]; + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 XCLK <= (XCLK === 1'b0); + always #220 XI <= (XI === 1'b0); + + initial begin + XI = 0; + XCLK = 0; + end + + initial begin + $dumpfile("la_test2.vcd"); + $dumpvars(0, la_test2_tb); + + // Repeat cycles of 1000 XCLK edges as needed to complete testbench + repeat (30) begin + repeat (1000) @(posedge XCLK); + // $display("+1000 cycles"); + end + $display("%c[1;31m",27); + $display ("Monitor: Timeout, Test Mega-Project IO (RTL) Failed"); + $display("%c[0m",27); + $finish; + end + + initial begin + wait(gpio == 16'h AB60); + $display("Monitor: Test 2 MPRJ-Logic Analyzer Started"); + wait(gpio == 16'h AB61); + $display("Monitor: Test 2 MPRJ-Logic Analyzer Passed"); + $finish; + end + + initial begin + CSB <= 1'b1; + SCK <= 1'b0; + SDI <= 1'b0; + RSTB <= 1'b0; + #1000; + RSTB <= 1'b1; // Release reset + #2000; + CSB <= 1'b0; // Apply CSB to start transmission + end + + wire VDD1V8; + wire VDD3V3; + wire VSS; + + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; + wire flash_io2; + wire flash_io3; + + assign VSS = 1'b0; + assign VDD1V8 = 1'b1; + assign VDD3V3 = 1'b1; + + harness_chip uut ( + .vdd (VDD3V3), + .vdd1v8 (VDD1V8), + .vss (VSS), + .xi (XI), + .xclk (XCLK), + .SDI (SDI), + .SDO (SDO), + .CSB (CSB), + .SCK (SCK), + .ser_rx (1'b0), + .ser_tx (), + .irq (1'b0), + .gpio (gpio), + .mprj_io (mprj_io), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .flash_io2(flash_io2), + .flash_io3(flash_io3), + .adc_high (adc_h), + .adc_low (adc_l), + .adc0_in (adc_0), + .adc1_in (adc_1), + .RSTB (RSTB), + .comp_inp (comp_p), + .comp_inn (comp_n) + ); + + spiflash #( + .FILENAME("la_test2.hex") + ) spiflash ( + .csb(flash_csb), + .clk(flash_clk), + .io0(flash_io0), + .io1(flash_io1), + .io2(flash_io2), + .io3(flash_io3) + ); + +endmodule
diff --git a/verilog/dv/harness/mgmt_soc/sections.lds b/verilog/dv/harness/sections.lds similarity index 93% rename from verilog/dv/harness/mgmt_soc/sections.lds rename to verilog/dv/harness/sections.lds index 4392c6d..8482887 100644 --- a/verilog/dv/harness/mgmt_soc/sections.lds +++ b/verilog/dv/harness/sections.lds
@@ -1,6 +1,6 @@ MEMORY { FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x400000 /* 4MB */ - RAM(xrw) : ORIGIN = 0x00000000, LENGTH = 0x400 /* 256 words ( 1024 ? ) */ + RAM(xrw) : ORIGIN = 0x00000000, LENGTH = 0x8000 /* 8192 words ( 32 KB) */ } SECTIONS {
diff --git a/verilog/dv/harness/mgmt_soc/spiflash.v b/verilog/dv/harness/spiflash.v similarity index 100% rename from verilog/dv/harness/mgmt_soc/spiflash.v rename to verilog/dv/harness/spiflash.v
diff --git a/verilog/dv/harness/mgmt_soc/start.s b/verilog/dv/harness/start.s similarity index 100% rename from verilog/dv/harness/mgmt_soc/start.s rename to verilog/dv/harness/start.s
diff --git a/verilog/dv/harness/stub.c b/verilog/dv/harness/stub.c new file mode 100644 index 0000000..4d9c970 --- /dev/null +++ b/verilog/dv/harness/stub.c
@@ -0,0 +1,12 @@ +void putchar(char c) +{ + if (c == '\n') + putchar('\r'); + reg_uart_data = c; +} + +void print(const char *p) +{ + while (*p) + putchar(*(p++)); +} \ No newline at end of file
diff --git a/verilog/dv/harness/mgmt_soc/tbuart.v b/verilog/dv/harness/tbuart.v similarity index 100% rename from verilog/dv/harness/mgmt_soc/tbuart.v rename to verilog/dv/harness/tbuart.v
diff --git a/verilog/dv/harness/mgmt_soc/verify.log b/verilog/dv/harness/verify.log similarity index 100% rename from verilog/dv/harness/mgmt_soc/verify.log rename to verilog/dv/harness/verify.log
diff --git a/verilog/dv/wb/arbiter_wb/arbiter_wb_tb.v b/verilog/dv/wb/arbiter_wb/arbiter_wb_tb.v deleted file mode 100644 index 164d526..0000000 --- a/verilog/dv/wb/arbiter_wb/arbiter_wb_tb.v +++ /dev/null
@@ -1,232 +0,0 @@ - -`timescale 1 ns / 1 ps - -`include "arbiter.v" -`include "dummy_slave.v" - -`ifndef AW -`define AW 32 -`endif -`ifndef DW -`define DW 32 -`endif -`ifndef NM -`define NM 2 -`endif - -module arbiter_wb_tb; - - localparam SEL = `DW / 8; - - reg wb_clk_i; - reg wb_rst_i; - - // Masters Interface - reg [`NM-1:0] wbm_stb_i; - reg [`NM-1:0] wbm_cyc_i; - reg [`NM-1:0] wbm_we_i; - reg [`NM*SEL-1:0] wbm_sel_i; - reg [`NM*`DW-1:0] wbm_dat_i; - reg [`NM*`AW-1:0] wbm_adr_i; - - wire [`NM-1:0] wbm_ack_o; - wire [`NM-1:0] wbm_err_o; - wire [`NM*`DW-1:0] wbm_dat_o; - - // Slave Interface - reg wbs_ack_i; - reg wbs_err_i; - wire [`DW-1:0] wbs_dat_i; - wire wbs_stb_i; - wire wbs_cyc_i; - wire wbs_we_i; - wire [SEL-1:0] wbs_sel_i; - wire [`AW-1:0] wbs_adr_i; - wire [`DW-1:0] wbs_dat_o; - - wb_arbiter #( - .AW(`AW), - .DW(`DW), - .NM(`NM) - ) uut ( - .wb_clk_i(wb_clk_i), - .wb_rst_i(wb_rst_i), - - // Masters Interface - .wbm_stb_i(wbm_stb_i), - .wbm_cyc_i(wbm_cyc_i), - .wbm_we_i(wbm_we_i), - .wbm_sel_i(wbm_sel_i), - .wbm_dat_i(wbm_dat_i), - .wbm_adr_i(wbm_adr_i), - - .wbm_ack_o(wbm_ack_o), - .wbm_err_o(wbm_err_o), - .wbm_dat_o(wbm_dat_o), - - // Slave Interface - .wbs_ack_i(wbs_ack_o), - .wbs_err_i(wbs_err_o), - .wbs_dat_i(wbs_dat_o), - .wbs_stb_o(wbs_stb_i), - .wbs_cyc_o(wbs_cyc_i), - .wbs_we_o(wbs_we_i), - .wbs_sel_o(wbs_sel_i), - .wbs_adr_o(wbs_adr_i), - .wbs_dat_o(wbs_dat_i) - ); - - // Instantiate one dummy slave for testing - dummy_slave dummy_slave ( - .wb_clk_i(wb_clk_i), - .wb_rst_i(wb_rst_i), - .wb_stb_i(wbs_stb_i), - .wb_cyc_i(wbs_cyc_i), - .wb_we_i(wbs_we_i), - .wb_sel_i(wbs_sel_i), - .wb_adr_i(wbs_adr_i), - .wb_dat_i(wbs_dat_i), - .wb_dat_o(wbs_dat_o), - .wb_ack_o(wbs_ack_o) - ); - - always #1 wb_clk_i = ~wb_clk_i; - - initial begin - wb_clk_i = 0; - wb_rst_i = 0; - wbm_stb_i = 0; - wbm_cyc_i = 0; - wbm_we_i = 0; - wbm_sel_i = 0; - wbm_dat_i = 0; - wbm_adr_i = 0; - wbs_ack_i = 0; - wbs_err_i = 0; - end - - initial begin - $dumpfile("arbiter_wb_tb.vcd"); - $dumpvars(0, arbiter_wb_tb); - repeat (50) begin - repeat (1000) @(posedge wb_clk_i); - end - $display("%c[1;31m",27); - $display ("Monitor: Timeout, Test Arbiter Failed"); - $display("%c[0m",27); - $finish; - end - - - reg [`DW-1:0] data; - reg [`AW-1:0] address; - - integer i; - - initial begin - wb_rst_i = 1; - #2; - wb_rst_i = 0; - #2; - - // Case 1: Initiate W/R requests from M0 -- MN - for (i=0; i<`NM; i=i+1) begin - data = $urandom_range(0, 255); - address = $urandom_range(0, 255); - write(address,data,i); - #2; - read(i); - if (wbm_dat_i[i*`DW +: `DW] !== data) begin - $display("Request Error from master %0b", i); - $finish; - end - end - - #10; - - // Case 2: Initiate W/R requests from MN -- M0 - for (i=`NM-1; i>=0; i=i-1) begin - data = $urandom_range(0, 255); - address = $urandom_range(0, 255); - write(address,data,i); - #2; - read(i); - if (wbm_dat_i[i*`DW +: `DW] !== data) begin - $display("Request Error from master %0b", i); - $finish; - end - end - - // Case 3: Initiate concurrent W/R requests from all masters - address = $urandom_range(0, 255); - wbm_stb_i = {`NM{1'b1}}; - wbm_cyc_i = {`NM{1'b1}}; - wbm_we_i = {`NM{1'b1}}; - wbm_sel_i = {`NM{4'hF}}; - wbm_adr_i = {`NM{address}}; - for (i=`NM-1; i>=0; i=i-1) begin - wbm_dat_i[i*`DW+: `DW] = $urandom_range(0, 2**32); - end - - // Make sure that served request is master 0 (highest priority) - wait(wbm_ack_o[0]); - if (wbm_ack_o[`NM-1:1] !== 0) begin - $display("Arbitration failed"); - $finish; - end - - // Read - wbm_we_i = {`NM{1'b0}}; - wait(wbm_ack_o[0]); - - // Make sure that the second master doesn't receive an ack - if (wbm_ack_o[`NM-1:1] !== 0) begin - $display("Arbitration failed"); - $finish; - end - #10; - $finish; - end - - task read; - input mindex; - begin - @(posedge wb_clk_i) begin - wbm_stb_i[mindex] = 1; - wbm_cyc_i[mindex] = 1; - wbm_we_i[mindex] = 0; - $display("Read Cycle from master %0b started", mindex); - end - wait(wbm_ack_o[mindex]); - wait(!wbm_ack_o[mindex]); - wbm_stb_i[mindex] = 0; - wbm_cyc_i[mindex] = 0; - $display("Read Cycle from master %0b ended.", mindex); - end - endtask - - task write; - input [`AW-1:0] adr; - input [`DW-1:0] data; - input integer mindex; - - begin - @(posedge wb_clk_i) begin - wbm_stb_i[mindex] = 1; - wbm_cyc_i[mindex] = 1; - wbm_we_i[mindex] = 1; - wbm_sel_i[mindex*SEL+: SEL] = {SEL{1'b1}}; - wbm_adr_i[mindex*`AW+: `AW] = adr; - wbm_dat_i[mindex*`DW+: `DW] = data; - $display("Write Cycle from master %0b started", mindex); - end - - wait(wbm_ack_o[mindex]); - wait(!wbm_ack_o[mindex]); - wbm_stb_i[mindex] = 0; - wbm_cyc_i[mindex] = 0; - $display("Write Cycle from master %0b ended.", mindex); - end - endtask - -endmodule \ No newline at end of file
diff --git a/verilog/dv/wb/crossbar_wb/Makefile b/verilog/dv/wb/crossbar_wb/Makefile deleted file mode 100644 index fcd10cc..0000000 --- a/verilog/dv/wb/crossbar_wb/Makefile +++ /dev/null
@@ -1,17 +0,0 @@ -.SUFFIXES: - -PATTERN = crossbar_wb - -all: ${PATTERN:=.vcd} - -%.vvp: %_tb.v - iverilog -I .. -I ../../ -I ../../../ip -I ../../../rtl \ - $< -o $@ - -%.vcd: %.vvp - vvp $< - -clean: - rm -f *.vvp *.vcd *.log - -.PHONY: clean all
diff --git a/verilog/dv/wb/crossbar_wb/crossbar_wb_tb.v b/verilog/dv/wb/crossbar_wb/crossbar_wb_tb.v deleted file mode 100644 index a9a35b4..0000000 --- a/verilog/dv/wb/crossbar_wb/crossbar_wb_tb.v +++ /dev/null
@@ -1,292 +0,0 @@ - -`timescale 1 ns / 1 ps - -`include "crossbar.v" -`include "dummy_slave.v" - -`ifndef AW - `define AW 32 -`endif -`ifndef DW - `define DW 32 -`endif -`ifndef NM - `define NM 2 -`endif - -`ifndef NS - `define NS 4 -`endif - -`ifndef SLAVE_ADR - `define SLAVE_ADR { \ - {8'hB0, {24{1'b0}}},\ - {8'hA0, {24{1'b0}}},\ - {8'h90, {24{1'b0}}},\ - {8'h80, {24{1'b0}}}\ - }\ -`endif - -`ifndef ADR_MASK - `define ADR_MASK { \ - {8'hFF, {24{1'b0}}}, \ - {8'hFF, {24{1'b0}}}, \ - {8'hFF, {24{1'b0}}}, \ - {8'hFF, {24{1'b0}}} \ - }\ -`endif - -module crossbar_wb_tb; - - localparam SEL = `DW / 8; - - reg wb_clk_i; - reg wb_rst_i; - - // Masters interface - reg [`NM-1:0] wbm_cyc_i; - reg [`NM-1:0] wbm_stb_i; - reg [`NM-1:0] wbm_we_i; - reg [(`NM*(`DW/8))-1:0] wbm_sel_i; - reg [(`NM*`AW)-1:0] wbm_adr_i; - reg [(`NM*`DW)-1:0] wbm_dat_i; - wire [`NM-1:0] wbm_ack_o; - wire [`NM-1:0] wbm_err_o; - wire [(`NM*`DW)-1:0] wbm_dat_o; - - // Slaves interfaces - wire [`NS-1:0] wbs_ack_o; - wire [(`NS*`DW)-1:0] wbs_dat_i; - wire [`NS-1:0] wbs_cyc_o; - wire [`NS-1:0] wbs_stb_o; - wire [`NS-1:0] wbs_we_o; - wire [(`NS*(`DW/8))-1:0] wbs_sel_o; - wire [(`NS*`AW)-1:0] wbs_adr_o; - wire [(`NS*`DW)-1:0] wbs_dat_o; - - wb_xbar #( - .NM(`NM), - .NS(`NS), - .AW(`AW), - .DW(`DW), - .SLAVE_ADR(`SLAVE_ADR), - .ADR_MASK(`ADR_MASK) - ) - wb_xbar( - .wb_clk_i(wb_clk_i), - .wb_rst_i(wb_rst_i), - // Masters interface - .wbm_cyc_i(wbm_cyc_i), - .wbm_stb_i(wbm_stb_i), - .wbm_we_i (wbm_we_i), - .wbm_sel_i(wbm_sel_i), - .wbm_adr_i(wbm_adr_i), - .wbm_dat_i(wbm_dat_i), - .wbm_ack_o(wbm_ack_o), - .wbm_dat_o(wbm_dat_o), - // Slaves interfaces - .wbs_ack_i(wbs_ack_o), - .wbs_dat_i(wbs_dat_o), - .wbs_cyc_o(wbs_cyc_o), - .wbs_stb_o(wbs_stb_o), - .wbs_we_o(wbs_we_o), - .wbs_sel_o(wbs_sel_o), - .wbs_adr_o(wbs_adr_o), - .wbs_dat_o(wbs_dat_i) - ); - - // Instantiate four dummy slaves for testing - dummy_slave dummy_slaves [`NS-1:0]( - .wb_clk_i({`NS{wb_clk_i}}), - .wb_rst_i({`NS{wb_rst_i}}), - .wb_stb_i(wbs_stb_o), - .wb_cyc_i(wbs_cyc_o), - .wb_we_i(wbs_we_o), - .wb_sel_i(wbs_sel_o), - .wb_adr_i(wbs_adr_o), - .wb_dat_i(wbs_dat_i), - .wb_dat_o(wbs_dat_o), - .wb_ack_o(wbs_ack_o) - ); - - initial begin - wb_clk_i = 0; - wb_rst_i = 0; - wbm_cyc_i = 0; - wbm_stb_i = 0; - wbm_we_i = 0; - wbm_sel_i = 0; - wbm_adr_i = 0; - wbm_dat_i = 0; - end - - always #1 wb_clk_i = ~wb_clk_i; - - initial begin - $dumpfile("crossbar_wb_tb.vcd"); - $dumpvars(0, crossbar_wb_tb); - repeat (50) begin - repeat (1000) @(posedge wb_clk_i); - end - $display("%c[1;31m",27); - $display ("Monitor: Timeout, Test Crossbar Switch Failed"); - $display("%c[0m",27); - $finish; - end - - integer i; - - reg [`AW*`NS-1:0] addresses = { - {8'hB0, {24{1'b0}}}, - {8'hA0, {24{1'b0}}}, - {8'h90, {24{1'b0}}}, - {8'h80, {24{1'b0}}} - }; - - reg [`DW-1:0] m0_slave_data; - reg [`DW-1:0] m1_slave_data; - reg [`AW-1:0] slave_adr; - - initial begin - wb_rst_i = 1; - #2; - wb_rst_i = 0; - #2; - - // Case 1: Master0 addresses slave 0 and Master 2 Addresses slave 1 - slave_adr = addresses[`AW-1:0]; - m0_slave_data = $urandom_range(0, 2**(`DW-2)); - write(slave_adr, m0_slave_data, 0); - - #2; - read(slave_adr, 0); - if (wbm_dat_o[0*`DW+: `DW] !== m0_slave_data) begin - $display("Error reading from slave"); - $finish; - end - - #10; - slave_adr = addresses[`AW*2-1:`AW*1]; - m1_slave_data = $urandom_range(0, 2**(`DW-2)); - write(slave_adr, m1_slave_data, 1); - #2; - read(slave_adr, 1); - #10; - if (wbm_dat_o[1*`DW+: `DW] !== m1_slave_data) begin - $display("Error reading from slave"); - $finish; - end - #10; - // Case 2: Master0 addresses slave 0 and Master 2 Addresses slave 1 simultaenously - slave_adr = addresses[`AW-1:0]; - m0_slave_data = $urandom_range(0, 2**(`DW-2)); - - wbm_stb_i[0] = 1; - wbm_cyc_i[0] = 1; - wbm_we_i [0] = 1; - wbm_sel_i[0*SEL+: SEL] = {SEL{1'b1}}; - wbm_adr_i[0*`AW+: `AW] = slave_adr; - wbm_dat_i[0*`DW+: `DW] = m0_slave_data; - - slave_adr = addresses[`AW*2-1:`AW*1]; - m1_slave_data = $urandom_range(0, 2**(`DW-2)); - - wbm_stb_i[1] = 1; - wbm_cyc_i[1] = 1; - wbm_we_i[1] = 1; - wbm_sel_i[1*SEL+: SEL] = {SEL{1'b1}}; - wbm_adr_i[1*`AW+: `AW] = slave_adr; - wbm_dat_i[1*`DW+: `DW] = m1_slave_data; - - wait(wbm_ack_o[0] && wbm_ack_o[1]); - wait(!wbm_ack_o[0] && !wbm_ack_o[1]); - - // Read - wbm_we_i = 2'b00; - wait(wbm_ack_o[0] && wbm_ack_o[1]); - wait(!wbm_ack_o[0] && !wbm_ack_o[1]); - - if (wbm_dat_o[0*`DW+: `DW] !== m0_slave_data) begin - $display("Error reading from slave"); - $finish; - end - - // Case 3: Master0 addresses slave 0 and Master 2 Addresses slave 1 simultaenously - slave_adr = addresses[`AW-1:0]; - m0_slave_data = $urandom_range(0, 2**(`DW-2)); - - wbm_stb_i[0] = 1; - wbm_cyc_i[0] = 1; - wbm_we_i [0] = 1; - wbm_sel_i[0*SEL+: SEL] = {SEL{1'b1}}; - wbm_adr_i[0*`AW+: `AW] = slave_adr; - wbm_dat_i[0*`DW+: `DW] = m0_slave_data; - - slave_adr = addresses[`AW-1:0]; - m1_slave_data = $urandom_range(0, 2**(`DW-2)); - - wbm_stb_i[1] = 1; - wbm_cyc_i[1] = 1; - wbm_we_i [1] = 1; - wbm_sel_i[1*SEL+: SEL] = {SEL{1'b1}}; - wbm_adr_i[1*`AW+: `AW] = slave_adr; - wbm_dat_i[1*`DW+: `DW] = m1_slave_data; - - wait(wbm_ack_o[0] && !wbm_ack_o[1]); - wait(!wbm_ack_o[0] && !wbm_ack_o[1]); - - // Read - wbm_we_i = 2'b00; - wait(wbm_ack_o[0]); - wait(!wbm_ack_o[0]); - if (wbm_dat_o[0*`DW+: `DW] !== m0_slave_data) begin - $display("Error reading from slave"); - $finish; - end - - $finish; - end - - task read; - input addr; - input mindex; - begin - @(posedge wb_clk_i) begin - wbm_stb_i[mindex] = 1; - wbm_cyc_i[mindex] = 1; - wbm_we_i[mindex] = 0; - $display("Read cycle from master %0b started", mindex); - end - wait(wbm_ack_o[mindex]); - wait(!wbm_ack_o[mindex]); - wbm_stb_i[mindex] = 0; - wbm_cyc_i[mindex] = 0; - $display("Read cycle from master %0b ended.", mindex); - end - endtask - - task write; - input [`AW-1:0] adr; - input [`DW-1:0] data; - input integer mindex; - - begin - @(posedge wb_clk_i) begin - wbm_stb_i[mindex] = 1; - wbm_cyc_i[mindex] = 1; - wbm_we_i[mindex] = 1; - wbm_sel_i[mindex*SEL+: SEL] = {SEL{1'b1}}; - wbm_adr_i[mindex*`AW+: `AW] = adr; - wbm_dat_i[mindex*`DW+: `DW] = data; - $display("Write cycle from master %0b started", mindex); - end - - wait(wbm_ack_o[mindex]); - wait(!wbm_ack_o[mindex]); - wbm_stb_i[mindex] = 0; - wbm_cyc_i[mindex] = 0; - $display("Write cycle from master %0b ended.", mindex); - end - endtask - -endmodule \ No newline at end of file
diff --git a/verilog/dv/wb/distributor/Makefile b/verilog/dv/wb/distributor/Makefile deleted file mode 100644 index f3a1273..0000000 --- a/verilog/dv/wb/distributor/Makefile +++ /dev/null
@@ -1,17 +0,0 @@ -.SUFFIXES: - -PATTERN = distributor - -all: ${PATTERN:=.vcd} - -%.vvp: %_tb.v - iverilog -I .. -I ../../ -I ../../../ip -I ../../../rtl \ - $< -o $@ - -%.vcd: %.vvp - vvp $< - -clean: - rm -f *.vvp *.vcd *.log - -.PHONY: clean all
diff --git a/verilog/dv/wb/distributor/distributor_tb.v b/verilog/dv/wb/distributor/distributor_tb.v deleted file mode 100644 index ab8f929..0000000 --- a/verilog/dv/wb/distributor/distributor_tb.v +++ /dev/null
@@ -1,226 +0,0 @@ - -`timescale 1 ns / 1 ps - -`include "distributor.v" -`include "dummy_slave.v" - -`ifndef AW - `define AW 32 -`endif -`ifndef DW - `define DW 32 -`endif - -`ifndef NS - `define NS 4 -`endif - -`ifndef SLAVE_ADR - `define SLAVE_ADR { \ - {8'hB0, {24{1'b0}}},\ - {8'hA0, {24{1'b0}}},\ - {8'h90, {24{1'b0}}},\ - {8'h80, {24{1'b0}}}\ - }\ -`endif - -`ifndef ADR_MASK - `define ADR_MASK { \ - {8'hFF, {24{1'b0}}}, \ - {8'hFF, {24{1'b0}}}, \ - {8'hFF, {24{1'b0}}}, \ - {8'hFF, {24{1'b0}}} \ - }\ -`endif - -module distributor_tb; - - localparam SEL = `DW / 8; - - reg wb_clk_i; - reg wb_rst_i; - - // Masters interface - reg wbm_cyc_i; - reg wbm_stb_i; - reg wbm_we_i; - reg [(`DW/8)-1:0] wbm_sel_i; - reg [`AW-1:0] wbm_adr_i; - reg [`DW-1:0] wbm_dat_i; - wire wbm_ack_o; - wire [`DW-1:0] wbm_dat_o; - - // Slaves interfaces - wire [`NS-1:0] wbs_ack_o; - wire [(`NS*`DW)-1:0] wbs_dat_i; - wire [`NS-1:0] wbs_cyc_o; - wire [`NS-1:0] wbs_stb_o; - wire [`NS-1:0] wbs_we_o; - wire [(`NS*(`DW/8))-1:0] wbs_sel_o; - wire [(`NS*`AW)-1:0] wbs_adr_o; - wire [(`NS*`DW)-1:0] wbs_dat_o; - - distributor #( - .NS(`NS), - .AW(`AW), - .DW(`DW), - .ADR_MASK(`ADR_MASK), - .SLAVE_ADR(`SLAVE_ADR) - ) - uut ( - .wb_clk_i(wb_clk_i), - .wb_rst_i(wb_rst_i), - // Masters interface - .wbm_cyc_i(wbm_cyc_i), - .wbm_stb_i(wbm_stb_i), - .wbm_we_i (wbm_we_i), - .wbm_sel_i(wbm_sel_i), - .wbm_adr_i(wbm_adr_i), - .wbm_dat_i(wbm_dat_i), - .wbm_ack_o(wbm_ack_o), - .wbm_dat_o(wbm_dat_o), - - // Slaves interfaces - .wbs_ack_i(wbs_ack_o), - .wbs_dat_i(wbs_dat_o), - .wbs_cyc_o(wbs_cyc_o), - .wbs_stb_o(wbs_stb_o), - .wbs_we_o(wbs_we_o), - .wbs_sel_o(wbs_sel_o), - .wbs_adr_o(wbs_adr_o), - .wbs_dat_o(wbs_dat_i) - ); - - // Instantiate four dummy slaves for testing - dummy_slave dummy_slaves [`NS-1:0]( - .wb_clk_i({`NS{wb_clk_i}}), - .wb_rst_i({`NS{wb_rst_i}}), - .wb_stb_i(wbs_stb_o), - .wb_cyc_i(wbs_cyc_o), - .wb_we_i(wbs_we_o), - .wb_sel_i(wbs_sel_o), - .wb_adr_i(wbs_adr_o), - .wb_dat_i(wbs_dat_i), - .wb_dat_o(wbs_dat_o), - .wb_ack_o(wbs_ack_o) - ); - - initial begin - wb_clk_i = 0; - wb_rst_i = 0; - wbm_cyc_i = 0; - wbm_stb_i = 0; - wbm_we_i = 0; - wbm_sel_i = 0; - wbm_adr_i = 0; - wbm_dat_i = 0; - end - - always #1 wb_clk_i = ~wb_clk_i; - - initial begin - $dumpfile("distributor_tb.vcd"); - $dumpvars(0, distributor_tb); - repeat (50) begin - repeat (1000) @(posedge wb_clk_i); - end - $display("%c[1;31m",27); - $display ("Monitor: Timeout, Test Distributor Failed"); - $display("%c[0m",27); - $finish; - end - - integer i; - - reg [`DW-1:0] slave_data; - reg [`AW-1:0] slave_adr; - - initial begin - wb_rst_i = 1; - #2; - wb_rst_i = 0; - #2; - - slave_adr = 32'h 8000_0000; - slave_data = $urandom_range(0, 2**(`DW-2)); - write(slave_adr, slave_data); - #2; - read(slave_adr); - if (wbm_dat_i !== slave_data) begin - $display("Failed R/W from slave"); - end - - #2; - slave_adr = 32'h 9000_0000; - slave_data = $urandom_range(0, 2**(`DW-2)); - write(slave_adr, slave_data); - #2; - read(slave_adr); - if (wbm_dat_i !== slave_data) begin - $display("Failed R/W from slave"); - end - #2; - - slave_adr = 32'h A000_0000; - slave_data = $urandom_range(0, 2**(`DW-2)); - write(slave_adr, slave_data); - #2; - read(slave_adr); - if (wbm_dat_i !== slave_data) begin - $display("Failed R/W from slave"); - end - - #2; - slave_adr = 32'h B000_0000; - slave_data = $urandom_range(0, 2**(`DW-2)); - write(slave_adr, slave_data); - #2; - read(slave_adr); - if (wbm_dat_i !== slave_data) begin - $display("Failed R/W from slave"); - end - - - $finish; - end - - task read; - input [`AW-1:0] addr; - begin - @(posedge wb_clk_i) begin - wbm_stb_i = 1; - wbm_cyc_i = 1; - wbm_we_i = 0; - wbm_adr_i = addr; - $display("Read Cycle Started"); - end - wait(wbm_ack_o); - wait(!wbm_ack_o); - wbm_stb_i = 0; - wbm_cyc_i = 0; - $display("Read cycle Ended"); - end - endtask - - task write; - input [`AW-1:0] adr; - input [`DW-1:0] data; - begin - @(posedge wb_clk_i) begin - wbm_stb_i = 1; - wbm_cyc_i = 1; - wbm_we_i = 1; - wbm_sel_i = {SEL{1'b1}}; - wbm_adr_i = adr; - wbm_dat_i = data; - $display("Write cycle started"); - end - wait(wbm_ack_o); - wait(!wbm_ack_o); - wbm_stb_i = 0; - wbm_cyc_i = 0; - $display("Write cycle ended."); - end - endtask - -endmodule \ No newline at end of file
diff --git a/verilog/dv/wb/distributor/distributor_tb.vcd b/verilog/dv/wb/distributor/distributor_tb.vcd deleted file mode 100644 index 12f7ae8..0000000 --- a/verilog/dv/wb/distributor/distributor_tb.vcd +++ /dev/null
@@ -1,963 +0,0 @@ -$date - Fri Aug 21 14:18:15 2020 -$end -$version - Icarus Verilog -$end -$timescale - 1ps -$end -$scope module distributor_tb $end -$var wire 4 ! wbs_we_o [3:0] $end -$var wire 4 " wbs_stb_o [3:0] $end -$var wire 16 # wbs_sel_o [15:0] $end -$var wire 128 $ wbs_dat_o [127:0] $end -$var wire 128 % wbs_dat_i [127:0] $end -$var wire 4 & wbs_cyc_o [3:0] $end -$var wire 128 ' wbs_adr_o [127:0] $end -$var wire 4 ( wbs_ack_o [3:0] $end -$var wire 32 ) wbm_dat_o [31:0] $end -$var wire 1 * wbm_ack_o $end -$var reg 32 + slave_adr [31:0] $end -$var reg 32 , slave_data [31:0] $end -$var reg 1 - wb_clk_i $end -$var reg 1 . wb_rst_i $end -$var reg 32 / wbm_adr_i [31:0] $end -$var reg 1 0 wbm_cyc_i $end -$var reg 32 1 wbm_dat_i [31:0] $end -$var reg 4 2 wbm_sel_i [3:0] $end -$var reg 1 3 wbm_stb_i $end -$var reg 1 4 wbm_we_i $end -$scope module dummy_slaves[0] $end -$var wire 1 5 valid $end -$var wire 32 6 wb_adr_i [31:0] $end -$var wire 1 7 wb_clk_i $end -$var wire 1 8 wb_cyc_i $end -$var wire 32 9 wb_dat_i [31:0] $end -$var wire 1 : wb_rst_i $end -$var wire 4 ; wb_sel_i [3:0] $end -$var wire 1 < wb_stb_i $end -$var wire 1 = wb_we_i $end -$var reg 32 > store [31:0] $end -$var reg 1 ? wb_ack_o $end -$var reg 32 @ wb_dat_o [31:0] $end -$upscope $end -$scope module dummy_slaves[1] $end -$var wire 1 A valid $end -$var wire 32 B wb_adr_i [31:0] $end -$var wire 1 C wb_clk_i $end -$var wire 1 D wb_cyc_i $end -$var wire 32 E wb_dat_i [31:0] $end -$var wire 1 F wb_rst_i $end -$var wire 4 G wb_sel_i [3:0] $end -$var wire 1 H wb_stb_i $end -$var wire 1 I wb_we_i $end -$var reg 32 J store [31:0] $end -$var reg 1 K wb_ack_o $end -$var reg 32 L wb_dat_o [31:0] $end -$upscope $end -$scope module dummy_slaves[2] $end -$var wire 1 M valid $end -$var wire 32 N wb_adr_i [31:0] $end -$var wire 1 O wb_clk_i $end -$var wire 1 P wb_cyc_i $end -$var wire 32 Q wb_dat_i [31:0] $end -$var wire 1 R wb_rst_i $end -$var wire 4 S wb_sel_i [3:0] $end -$var wire 1 T wb_stb_i $end -$var wire 1 U wb_we_i $end -$var reg 32 V store [31:0] $end -$var reg 1 W wb_ack_o $end -$var reg 32 X wb_dat_o [31:0] $end -$upscope $end -$scope module dummy_slaves[3] $end -$var wire 1 Y valid $end -$var wire 32 Z wb_adr_i [31:0] $end -$var wire 1 [ wb_clk_i $end -$var wire 1 \ wb_cyc_i $end -$var wire 32 ] wb_dat_i [31:0] $end -$var wire 1 ^ wb_rst_i $end -$var wire 4 _ wb_sel_i [3:0] $end -$var wire 1 ` wb_stb_i $end -$var wire 1 a wb_we_i $end -$var reg 32 b store [31:0] $end -$var reg 1 c wb_ack_o $end -$var reg 32 d wb_dat_o [31:0] $end -$upscope $end -$scope module uut $end -$var wire 1 - wb_clk_i $end -$var wire 1 . wb_rst_i $end -$var wire 32 e wbm_adr_i [31:0] $end -$var wire 1 0 wbm_cyc_i $end -$var wire 32 f wbm_dat_i [31:0] $end -$var wire 4 g wbm_sel_i [3:0] $end -$var wire 1 3 wbm_stb_i $end -$var wire 1 4 wbm_we_i $end -$var wire 4 h wbs_ack_i [3:0] $end -$var wire 4 i wbs_cyc_o [3:0] $end -$var wire 128 j wbs_dat_i [127:0] $end -$var wire 4 k wbs_stb_o [3:0] $end -$var wire 4 l wbs_we_o [3:0] $end -$var wire 16 m wbs_sel_o [15:0] $end -$var wire 128 n wbs_dat_o [127:0] $end -$var wire 128 o wbs_adr_o [127:0] $end -$var wire 1 * wbm_ack_o $end -$var wire 4 p slave_sel [3:0] $end -$var reg 32 q wbm_dat_o [31:0] $end -$var integer 32 r i [31:0] $end -$scope begin genblk1[0] $end -$upscope $end -$scope begin genblk1[1] $end -$upscope $end -$scope begin genblk1[2] $end -$upscope $end -$scope begin genblk1[3] $end -$upscope $end -$upscope $end -$scope task read $end -$var reg 32 s addr [31:0] $end -$upscope $end -$scope task write $end -$var reg 32 t adr [31:0] $end -$var reg 32 u data [31:0] $end -$upscope $end -$upscope $end -$enddefinitions $end -#0 -$dumpvars -bx u -bx t -bx s -b10000000 r -b0 q -b0 p -b0 o -b0 n -b0 m -b0 l -b0 k -bx j -b0 i -bx h -b0 g -b0 f -b0 e -bx d -xc -bx b -0a -0` -b0 _ -1^ -b0 ] -0\ -0[ -b0 Z -0Y -bx X -xW -bx V -0U -0T -b0 S -1R -b0 Q -0P -0O -b0 N -0M -bx L -xK -bx J -0I -0H -b0 G -1F -b0 E -0D -0C -b0 B -0A -bx @ -x? -bx > -0= -0< -b0 ; -1: -b0 9 -08 -07 -b0 6 -05 -04 -03 -b0 2 -b0 1 -00 -b0 / -1. -0- -bx , -bx + -0* -b0 ) -bx ( -b0 ' -b0 & -b0 % -bx $ -b0 # -b0 " -b0 ! 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-b1111 l -14 -10 -13 -1- -b1100011111000001010110011001 u -b10110000000000000000000000000000 t -b1100011111000001010110011001 , -b10110000000000000000000000000000 + -#42000 -07 -0C -0O -0[ -0- -#43000 -1* -b10000000 r -b1100011111000001010110011001 ) -b1100011111000001010110011001 q -b1100011111000001010110011001 @ -b1100011111000001010110011001 L -b1100011111000001010110011001 X -b1000 ( -b1000 h -1c -b1100011111000001010110011001000011000111110000010101100110010000110001111100000101011001100100001100011111000001010110011001 $ -b1100011111000001010110011001000011000111110000010101100110010000110001111100000101011001100100001100011111000001010110011001 j -b1100011111000001010110011001 d -17 -1C -1O -1[ -1- -#44000 -07 -0C -0O -0[ -0- -#45000 -0Y -0\ -0` -b0 & -b0 i -b0 " -b0 k -00 -03 -0* -b0 ( -b0 h -0c -17 -1C -1O -1[ -1- -#46000 -07 -0C -0O -0[ -0- -#47000 -1Y -1\ -1` -0= -0I -0U -0a -b1000 & -b1000 i -b1000 " -b1000 k -17 -1C -1O -1[ -b0 ! -b0 l -04 -10 -13 -1- -b10110000000000000000000000000000 s -#48000 -07 -0C -0O -0[ -0- -#49000 -1* -b1000 ( -b1000 h -1c -17 -1C -1O -1[ -1- -#50000 -07 -0C -0O -0[ -0- -#51000 -0Y -0\ -0` -b0 & -b0 i -b0 " -b0 k -00 -03 -0* -b0 ( -b0 h -0c -17 -1C -1O -1[ -1-
diff --git a/verilog/dv/wb/la_wb/la_wb_tb.vcd b/verilog/dv/wb/la_wb/la_wb_tb.vcd deleted file mode 100644 index 9a9969d..0000000 --- a/verilog/dv/wb/la_wb/la_wb_tb.vcd +++ /dev/null
@@ -1,635 +0,0 @@ -$date - Fri Aug 21 14:19:50 2020 -$end -$version - Icarus Verilog -$end -$timescale - 1ps -$end -$scope module la_wb_tb $end -$var wire 32 ! la_data_adr_0 [31:0] $end -$var wire 32 " la_data_adr_1 [31:0] $end -$var wire 32 # la_data_adr_2 [31:0] $end -$var wire 32 $ la_data_adr_3 [31:0] $end -$var wire 32 % la_ena_adr_0 [31:0] $end -$var wire 32 & la_ena_adr_1 [31:0] $end -$var wire 32 ' la_ena_adr_2 [31:0] $end -$var wire 32 ( la_ena_adr_3 [31:0] $end -$var wire 32 ) wb_dat_o [31:0] $end -$var wire 1 * wb_ack_o $end -$var reg 32 + la_data_0 [31:0] $end -$var reg 32 , la_data_1 [31:0] $end -$var reg 32 - la_data_2 [31:0] $end -$var reg 32 . la_data_3 [31:0] $end -$var reg 32 / la_ena_0 [31:0] $end -$var reg 32 0 la_ena_1 [31:0] $end -$var reg 32 1 la_ena_2 [31:0] $end -$var reg 32 2 la_ena_3 [31:0] $end -$var reg 32 3 wb_adr_i [31:0] $end -$var reg 1 4 wb_clk_i $end -$var reg 1 5 wb_cyc_i $end -$var reg 32 6 wb_dat_i [31:0] $end -$var reg 1 7 wb_rst_i $end -$var reg 4 8 wb_sel_i [3:0] $end -$var reg 1 9 wb_stb_i $end -$var reg 1 : wb_we_i $end -$scope module uut $end -$var wire 4 ; iomem_we [3:0] $end -$var wire 1 < resetn $end -$var wire 1 = valid $end -$var wire 1 * wb_ack_o $end -$var wire 32 > wb_adr_i [31:0] $end -$var wire 1 4 wb_clk_i $end -$var wire 1 5 wb_cyc_i $end -$var wire 32 ? wb_dat_i [31:0] $end -$var wire 1 7 wb_rst_i $end -$var wire 4 @ wb_sel_i [3:0] $end -$var wire 1 9 wb_stb_i $end -$var wire 1 : wb_we_i $end -$var wire 32 A wb_dat_o [31:0] $end -$var wire 1 B ready $end -$var wire 128 C la_ena [127:0] $end -$var wire 128 D la_data [127:0] $end -$scope module la_ctrl $end -$var wire 1 4 clk $end -$var wire 32 E iomem_addr [31:0] $end -$var wire 1 = iomem_valid $end -$var wire 32 F iomem_wdata [31:0] $end -$var wire 4 G iomem_wstrb [3:0] $end -$var wire 1 < resetn $end -$var wire 4 H la_ena_sel [3:0] $end -$var wire 128 I la_ena [127:0] $end -$var wire 4 J la_data_sel [3:0] $end -$var wire 128 K la_data [127:0] $end -$var reg 32 L iomem_rdata [31:0] $end -$var reg 1 B iomem_ready $end -$var reg 32 M la_data_0 [31:0] $end -$var reg 32 N la_data_1 [31:0] $end -$var reg 32 O la_data_2 [31:0] $end -$var reg 32 P la_data_3 [31:0] $end -$var reg 32 Q la_ena_0 [31:0] $end -$var reg 32 R la_ena_1 [31:0] $end -$var reg 32 S la_ena_2 [31:0] $end -$var reg 32 T la_ena_3 [31:0] $end -$upscope $end -$upscope $end -$scope task read $end -$var reg 33 U addr [32:0] $end -$upscope $end -$scope task write $end -$var reg 33 V addr [32:0] $end -$var reg 33 W data [32:0] $end -$upscope $end -$upscope $end -$enddefinitions $end -#0 -$dumpvars -bx W -bx V -bx U -bx T -bx S -bx R -bx Q -bx P -bx O -bx N -bx M -bx L -bx K -b1 J -bx I -b0 H -b0 G -b0 F -b0 E -bx D -bx C -xB -bx A -b0 @ -b0 ? -b0 > -0= -0< -b0 ; -0: -09 -b0 8 -17 -b0 6 -05 -04 -b0 3 -bx 2 -bx 1 -bx 0 -bx / -bx . -bx - -bx , -bx + -x* -bx ) -b100010000000000000000000011100 ( -b100010000000000000000000011000 ' -b100010000000000000000000010100 & -b100010000000000000000000010000 % -b100010000000000000000000001100 $ -b100010000000000000000000001000 # -b100010000000000000000000000100 " -b100010000000000000000000000000 ! -$end -#1000 -b0 T -b0 S -b0 R -b0 C -b0 I -b0 Q -b0 P -b0 O -b0 N -b0 D -b0 K -b0 M -14 -#2000 -1< -04 -07 -#3000 -0* -0B -14 -#4000 -04 -b0 W -b100010000000000000000000000000 V -b0 . -b0 - -b0 , -b0 + -#5000 -b1111 ; -b1111 G -1= -b100010000000000000000000000000 3 -b100010000000000000000000000000 > -b100010000000000000000000000000 E -1: -b1111 8 -b1111 @ -15 -19 -14 -#6000 -04 -#7000 -b0 ) -b0 A -b0 L -1* -1B -14 -#8000 -04 -#9000 -0= -b100010000000000000000000000100 V -09 -05 -0* -0B -14 -#10000 -04 -#11000 -b10 J -1= -b100010000000000000000000000100 3 -b100010000000000000000000000100 > -b100010000000000000000000000100 E -15 -19 -14 -#12000 -04 -#13000 -1* -1B -14 -#14000 -04 -#15000 -0= -b100010000000000000000000001000 V -09 -05 -0* -0B -14 -#16000 -04 -#17000 -b100 J -1= -b100010000000000000000000001000 3 -b100010000000000000000000001000 > -b100010000000000000000000001000 E -15 -19 -14 -#18000 -04 -#19000 -1* -1B -14 -#20000 -04 -#21000 -0= -b100010000000000000000000001100 V -09 -05 -0* -0B -14 -#22000 -04 -#23000 -b1000 J -1= -b100010000000000000000000001100 3 -b100010000000000000000000001100 > -b100010000000000000000000001100 E -15 -19 -14 -#24000 -04 -#25000 -1* -1B -14 -#26000 -04 -#27000 -0= -09 -05 -0* -0B -14 -#28000 -04 -#29000 -b1 J -b0 ; -b0 G -1= -b100010000000000000000000000000 3 -b100010000000000000000000000000 > -b100010000000000000000000000000 E -0: -15 -19 -14 -b100010000000000000000000000000 U -#30000 -04 -#31000 -1* -1B -14 -#32000 -04 -#33000 -0= -b100010000000000000000000000100 U -09 -05 -0* -0B -14 -#34000 -04 -#35000 -b10 J -1= -b100010000000000000000000000100 3 -b100010000000000000000000000100 > -b100010000000000000000000000100 E -15 -19 -14 -#36000 -04 -#37000 -1* -1B -14 -#38000 -04 -#39000 -0= -b100010000000000000000000001000 U -09 -05 -0* -0B -14 -#40000 -04 -#41000 -b100 J -1= -b100010000000000000000000001000 3 -b100010000000000000000000001000 > -b100010000000000000000000001000 E -15 -19 -14 -#42000 -04 -#43000 -1* -1B -14 -#44000 -04 -#45000 -0= -b100010000000000000000000001100 U -09 -05 -0* -0B -14 -#46000 -04 -#47000 -b1000 J -1= -b100010000000000000000000001100 3 -b100010000000000000000000001100 > -b100010000000000000000000001100 E -15 -19 -14 -#48000 -04 -#49000 -1* -1B -14 -#50000 -04 -#51000 -0= -b100010000000000000000000010000 V -b0 2 -b0 1 -b0 0 -b0 / -09 -05 -0* -0B -14 -#52000 -04 -#53000 -b0 J -b1 H -b1111 ; -b1111 G -1= -b100010000000000000000000010000 3 -b100010000000000000000000010000 > -b100010000000000000000000010000 E -1: -15 -19 -14 -#54000 -04 -#55000 -1* -1B -14 -#56000 -04 -#57000 -0= -b100010000000000000000000010100 V -09 -05 -0* -0B -14 -#58000 -04 -#59000 -b10 H -1= -b100010000000000000000000010100 3 -b100010000000000000000000010100 > -b100010000000000000000000010100 E -15 -19 -14 -#60000 -04 -#61000 -1* -1B -14 -#62000 -04 -#63000 -0= -b100010000000000000000000011000 V -09 -05 -0* -0B -14 -#64000 -04 -#65000 -b100 H -1= -b100010000000000000000000011000 3 -b100010000000000000000000011000 > -b100010000000000000000000011000 E -15 -19 -14 -#66000 -04 -#67000 -1* -1B -14 -#68000 -04 -#69000 -0= -b100010000000000000000000011100 V -09 -05 -0* -0B -14 -#70000 -04 -#71000 -b1000 H -1= -b100010000000000000000000011100 3 -b100010000000000000000000011100 > -b100010000000000000000000011100 E -15 -19 -14 -#72000 -04 -#73000 -1* -1B -14 -#74000 -04 -#75000 -0= -09 -05 -0* -0B -14 -#76000 -04 -#77000 -b1 H -b0 ; -b0 G -1= -b100010000000000000000000010000 3 -b100010000000000000000000010000 > -b100010000000000000000000010000 E -0: -15 -19 -14 -b100010000000000000000000010000 U -#78000 -04 -#79000 -1* -1B -14 -#80000 -04 -#81000 -0= -b100010000000000000000000010100 U -09 -05 -0* -0B -14 -#82000 -04 -#83000 -b10 H -1= -b100010000000000000000000010100 3 -b100010000000000000000000010100 > -b100010000000000000000000010100 E -15 -19 -14 -#84000 -04 -#85000 -1* -1B -14 -#86000 -04 -#87000 -0= -b100010000000000000000000011000 U -09 -05 -0* -0B -14 -#88000 -04 -#89000 -b100 H -1= -b100010000000000000000000011000 3 -b100010000000000000000000011000 > -b100010000000000000000000011000 E -15 -19 -14 -#90000 -04 -#91000 -1* -1B -14 -#92000 -04 -#93000 -0= -b100010000000000000000000011100 U -09 -05 -0* -0B -14 -#94000 -04 -#95000 -b1000 H -1= -b100010000000000000000000011100 3 -b100010000000000000000000011100 > -b100010000000000000000000011100 E -15 -19 -14 -#96000 -04 -#97000 -1* -1B -14 -#98000 -04 -#99000 -0= -09 -05 -0* -0B -14 -#100000 -04 -#101000 -14 -#102000 -04 -#103000 -14 -#104000 -04 -#105000 -14
diff --git a/verilog/dv/wb/la_wb/ldo_wb_tb.vcd b/verilog/dv/wb/la_wb/ldo_wb_tb.vcd deleted file mode 100644 index a0e252e..0000000 --- a/verilog/dv/wb/la_wb/ldo_wb_tb.vcd +++ /dev/null
@@ -1,635 +0,0 @@ -$date - Thu Aug 20 00:22:06 2020 -$end -$version - Icarus Verilog -$end -$timescale - 1ps -$end -$scope module ldo_wb_tb $end -$var wire 32 ! ldo_data_adr_0 [31:0] $end -$var wire 32 " ldo_data_adr_1 [31:0] $end -$var wire 32 # ldo_data_adr_2 [31:0] $end -$var wire 32 $ ldo_data_adr_3 [31:0] $end -$var wire 32 % ldo_ena_adr_0 [31:0] $end -$var wire 32 & ldo_ena_adr_1 [31:0] $end -$var wire 32 ' ldo_ena_adr_2 [31:0] $end -$var wire 32 ( ldo_ena_adr_3 [31:0] $end -$var wire 32 ) wb_dat_o [31:0] $end -$var wire 1 * wb_ack_o $end -$var reg 32 + ldo_data_0 [31:0] $end -$var reg 32 , ldo_data_1 [31:0] $end -$var reg 32 - ldo_data_2 [31:0] $end -$var reg 32 . ldo_data_3 [31:0] $end -$var reg 32 / ldo_ena_0 [31:0] $end -$var reg 32 0 ldo_ena_1 [31:0] $end -$var reg 32 1 ldo_ena_2 [31:0] $end -$var reg 32 2 ldo_ena_3 [31:0] $end -$var reg 32 3 wb_adr_i [31:0] $end -$var reg 1 4 wb_clk_i $end -$var reg 1 5 wb_cyc_i $end -$var reg 32 6 wb_dat_i [31:0] $end -$var reg 1 7 wb_rst_i $end -$var reg 4 8 wb_sel_i [3:0] $end -$var reg 1 9 wb_stb_i $end -$var reg 1 : wb_we_i $end -$scope module uut $end -$var wire 4 ; iomem_we [3:0] $end -$var wire 1 < resetn $end -$var wire 1 = valid $end -$var wire 1 * wb_ack_o $end -$var wire 32 > wb_adr_i [31:0] $end -$var wire 1 4 wb_clk_i $end -$var wire 1 5 wb_cyc_i $end -$var wire 32 ? wb_dat_i [31:0] $end -$var wire 1 7 wb_rst_i $end -$var wire 4 @ wb_sel_i [3:0] $end -$var wire 1 9 wb_stb_i $end -$var wire 1 : wb_we_i $end -$var wire 32 A wb_dat_o [31:0] $end -$var wire 1 B ready $end -$var wire 128 C ldo_ena [127:0] $end -$var wire 128 D ldo_data [127:0] $end -$scope module ldo_ctrl $end -$var wire 1 4 clk $end -$var wire 32 E iomem_addr [31:0] $end -$var wire 1 = iomem_valid $end -$var wire 32 F iomem_wdata [31:0] $end -$var wire 4 G iomem_wstrb [3:0] $end -$var wire 1 < resetn $end -$var wire 4 H ldo_ena_sel [3:0] $end -$var wire 128 I ldo_ena [127:0] $end -$var wire 4 J ldo_data_sel [3:0] $end -$var wire 128 K ldo_data [127:0] $end -$var reg 32 L iomem_rdata [31:0] $end -$var reg 1 B iomem_ready $end -$var reg 32 M ldo_data_0 [31:0] $end -$var reg 32 N ldo_data_1 [31:0] $end -$var reg 32 O ldo_data_2 [31:0] $end -$var reg 32 P ldo_data_3 [31:0] $end -$var reg 32 Q ldo_ena_0 [31:0] $end -$var reg 32 R ldo_ena_1 [31:0] $end -$var reg 32 S ldo_ena_2 [31:0] $end -$var reg 32 T ldo_ena_3 [31:0] $end -$upscope $end -$upscope $end -$scope task read $end -$var reg 33 U addr [32:0] $end -$upscope $end -$scope task write $end -$var reg 33 V addr [32:0] $end -$var reg 33 W data [32:0] $end -$upscope $end -$upscope $end -$enddefinitions $end -#0 -$dumpvars -bx W -bx V -bx U -bx T -bx S -bx R -bx Q -bx P -bx O -bx N -bx M -bx L -bx K -b1 J -bx I -b0 H -b0 G -b0 F -b0 E -bx D -bx C -xB -bx A -b0 @ -b0 ? -b0 > -0= -0< -b0 ; -0: -09 -b0 8 -17 -b0 6 -05 -04 -b0 3 -bx 2 -bx 1 -bx 0 -bx / -bx . -bx - -bx , -bx + -x* -bx ) -b100010000000000000000000011100 ( -b100010000000000000000000011000 ' -b100010000000000000000000010100 & -b100010000000000000000000010000 % -b100010000000000000000000001100 $ -b100010000000000000000000001000 # -b100010000000000000000000000100 " -b100010000000000000000000000000 ! -$end -#1000 -b0 T -b0 S -b0 R -b0 C -b0 I -b0 Q -b0 P -b0 O -b0 N -b0 D -b0 K -b0 M -14 -#2000 -1< -04 -07 -#3000 -0* -0B -14 -#4000 -04 -b0 W -b100010000000000000000000000000 V -b0 . -b0 - -b0 , -b0 + -#5000 -b1111 ; -b1111 G -1= -b100010000000000000000000000000 3 -b100010000000000000000000000000 > -b100010000000000000000000000000 E -1: -b1111 8 -b1111 @ -15 -19 -14 -#6000 -04 -#7000 -b0 ) -b0 A -b0 L -1* -1B -14 -#8000 -04 -#9000 -0= -b100010000000000000000000000100 V -09 -05 -0* -0B -14 -#10000 -04 -#11000 -b10 J -1= -b100010000000000000000000000100 3 -b100010000000000000000000000100 > -b100010000000000000000000000100 E -15 -19 -14 -#12000 -04 -#13000 -1* -1B -14 -#14000 -04 -#15000 -0= -b100010000000000000000000001000 V -09 -05 -0* -0B -14 -#16000 -04 -#17000 -b100 J -1= -b100010000000000000000000001000 3 -b100010000000000000000000001000 > -b100010000000000000000000001000 E -15 -19 -14 -#18000 -04 -#19000 -1* -1B -14 -#20000 -04 -#21000 -0= -b100010000000000000000000001100 V -09 -05 -0* -0B -14 -#22000 -04 -#23000 -b1000 J -1= -b100010000000000000000000001100 3 -b100010000000000000000000001100 > -b100010000000000000000000001100 E -15 -19 -14 -#24000 -04 -#25000 -1* -1B -14 -#26000 -04 -#27000 -0= -09 -05 -0* -0B -14 -#28000 -04 -#29000 -b1 J -b0 ; -b0 G -1= -b100010000000000000000000000000 3 -b100010000000000000000000000000 > -b100010000000000000000000000000 E -0: -15 -19 -14 -b100010000000000000000000000000 U -#30000 -04 -#31000 -1* -1B -14 -#32000 -04 -#33000 -0= -b100010000000000000000000000100 U -09 -05 -0* -0B -14 -#34000 -04 -#35000 -b10 J -1= -b100010000000000000000000000100 3 -b100010000000000000000000000100 > -b100010000000000000000000000100 E -15 -19 -14 -#36000 -04 -#37000 -1* -1B -14 -#38000 -04 -#39000 -0= -b100010000000000000000000001000 U -09 -05 -0* -0B -14 -#40000 -04 -#41000 -b100 J -1= -b100010000000000000000000001000 3 -b100010000000000000000000001000 > -b100010000000000000000000001000 E -15 -19 -14 -#42000 -04 -#43000 -1* -1B -14 -#44000 -04 -#45000 -0= -b100010000000000000000000001100 U -09 -05 -0* -0B -14 -#46000 -04 -#47000 -b1000 J -1= -b100010000000000000000000001100 3 -b100010000000000000000000001100 > -b100010000000000000000000001100 E -15 -19 -14 -#48000 -04 -#49000 -1* -1B -14 -#50000 -04 -#51000 -0= -b100010000000000000000000010000 V -b0 2 -b0 1 -b0 0 -b0 / -09 -05 -0* -0B -14 -#52000 -04 -#53000 -b0 J -b1 H -b1111 ; -b1111 G -1= -b100010000000000000000000010000 3 -b100010000000000000000000010000 > -b100010000000000000000000010000 E -1: -15 -19 -14 -#54000 -04 -#55000 -1* -1B -14 -#56000 -04 -#57000 -0= -b100010000000000000000000010100 V -09 -05 -0* -0B -14 -#58000 -04 -#59000 -b10 H -1= -b100010000000000000000000010100 3 -b100010000000000000000000010100 > -b100010000000000000000000010100 E -15 -19 -14 -#60000 -04 -#61000 -1* -1B -14 -#62000 -04 -#63000 -0= -b100010000000000000000000011000 V -09 -05 -0* -0B -14 -#64000 -04 -#65000 -b100 H -1= -b100010000000000000000000011000 3 -b100010000000000000000000011000 > -b100010000000000000000000011000 E -15 -19 -14 -#66000 -04 -#67000 -1* -1B -14 -#68000 -04 -#69000 -0= -b100010000000000000000000011100 V -09 -05 -0* -0B -14 -#70000 -04 -#71000 -b1000 H -1= -b100010000000000000000000011100 3 -b100010000000000000000000011100 > -b100010000000000000000000011100 E -15 -19 -14 -#72000 -04 -#73000 -1* -1B -14 -#74000 -04 -#75000 -0= -09 -05 -0* -0B -14 -#76000 -04 -#77000 -b1 H -b0 ; -b0 G -1= -b100010000000000000000000010000 3 -b100010000000000000000000010000 > -b100010000000000000000000010000 E -0: -15 -19 -14 -b100010000000000000000000010000 U -#78000 -04 -#79000 -1* -1B -14 -#80000 -04 -#81000 -0= -b100010000000000000000000010100 U -09 -05 -0* -0B -14 -#82000 -04 -#83000 -b10 H -1= -b100010000000000000000000010100 3 -b100010000000000000000000010100 > -b100010000000000000000000010100 E -15 -19 -14 -#84000 -04 -#85000 -1* -1B -14 -#86000 -04 -#87000 -0= -b100010000000000000000000011000 U -09 -05 -0* -0B -14 -#88000 -04 -#89000 -b100 H -1= -b100010000000000000000000011000 3 -b100010000000000000000000011000 > -b100010000000000000000000011000 E -15 -19 -14 -#90000 -04 -#91000 -1* -1B -14 -#92000 -04 -#93000 -0= -b100010000000000000000000011100 U -09 -05 -0* -0B -14 -#94000 -04 -#95000 -b1000 H -1= -b100010000000000000000000011100 3 -b100010000000000000000000011100 > -b100010000000000000000000011100 E -15 -19 -14 -#96000 -04 -#97000 -1* -1B -14 -#98000 -04 -#99000 -0= -09 -05 -0* -0B -14 -#100000 -04 -#101000 -14 -#102000 -04 -#103000 -14 -#104000 -04 -#105000 -14
diff --git a/verilog/dv/wb/spi_sysctrl_wb/spi_sysctrl_wb_tb.vcd b/verilog/dv/wb/spi_sysctrl_wb/spi_sysctrl_wb_tb.vcd deleted file mode 100644 index 3abe514..0000000 --- a/verilog/dv/wb/spi_sysctrl_wb/spi_sysctrl_wb_tb.vcd +++ /dev/null
@@ -1,460 +0,0 @@ -$date - Fri Aug 21 14:21:00 2020 -$end -$version - Icarus Verilog -$end -$timescale - 1ps -$end -$scope module spi_sysctrl_wb_tb $end -$var wire 32 ! spi_cfg [31:0] $end -$var wire 32 " spi_ena [31:0] $end -$var wire 32 # spi_mask_rev [31:0] $end -$var wire 32 $ spi_mfgr_id [31:0] $end -$var wire 32 % spi_pll_bypass [31:0] $end -$var wire 32 & spi_pll_cfg [31:0] $end -$var wire 32 ' spi_prod_id [31:0] $end -$var wire 8 ( spi_ro_config [7:0] $end -$var wire 12 ) spi_ro_mfgr_id [11:0] $end -$var wire 8 * spi_ro_prod_id [7:0] $end -$var wire 32 + wb_dat_o [31:0] $end -$var wire 1 , wb_ack_o $end -$var wire 1 - spi_ro_xtal_ena $end -$var wire 1 . spi_ro_reg_ena $end -$var wire 26 / spi_ro_pll_trim [25:0] $end -$var wire 3 0 spi_ro_pll_sel [2:0] $end -$var wire 5 1 spi_ro_pll_div [4:0] $end -$var wire 1 2 spi_ro_pll_dco_ena $end -$var wire 1 3 spi_ro_pll_bypass $end -$var wire 4 4 spi_ro_mask_rev [3:0] $end -$var wire 1 5 por $end -$var wire 1 6 irq_spi $end -$var wire 1 7 ext_reset $end -$var wire 1 8 SDO_enb $end -$var wire 1 9 SDO $end -$var reg 1 : CSB $end -$var reg 1 ; RSTB $end -$var reg 1 < SCK $end -$var reg 1 = SDI $end -$var reg 4 > mask_rev_in [3:0] $end -$var reg 1 ? trap $end -$var reg 32 @ wb_adr_i [31:0] $end -$var reg 1 A wb_clk_i $end -$var reg 1 B wb_cyc_i $end -$var reg 32 C wb_dat_i [31:0] $end -$var reg 1 D wb_rst_i $end -$var reg 4 E wb_sel_i [3:0] $end -$var reg 1 F wb_stb_i $end -$var reg 1 G wb_we_i $end -$scope module hkspi $end -$var wire 1 : CSB $end -$var wire 1 5 RST $end -$var wire 1 ; RSTB $end -$var wire 1 < SCK $end -$var wire 1 = SDI $end -$var wire 4 H mask_rev [3:0] $end -$var wire 4 I mask_rev_in [3:0] $end -$var wire 12 J mfgr_id [11:0] $end -$var wire 8 K prod_id [7:0] $end -$var wire 1 ? trap $end -$var wire 1 L wrstb $end -$var wire 1 8 sdo_enb $end -$var wire 1 M rdstb $end -$var wire 8 N odata [7:0] $end -$var wire 8 O idata [7:0] $end -$var wire 8 P iaddr [7:0] $end -$var wire 1 9 SDO $end -$var reg 1 6 irq $end -$var reg 1 3 pll_bypass $end -$var reg 1 2 pll_dco_ena $end -$var reg 5 Q pll_div [4:0] $end -$var reg 3 R pll_sel [2:0] $end -$var reg 26 S pll_trim [25:0] $end -$var reg 1 . reg_ena $end -$var reg 1 7 reset $end -$var reg 1 - xtal_ena $end -$scope module U1 $end -$var wire 1 : CSB $end -$var wire 1 < SCK $end -$var wire 1 = SDI $end -$var wire 8 T idata [7:0] $end -$var wire 8 U odata [7:0] $end -$var wire 8 V oaddr [7:0] $end -$var wire 1 9 SDO $end -$var reg 8 W addr [7:0] $end -$var reg 3 X count [2:0] $end -$var reg 3 Y fixed [2:0] $end -$var reg 8 Z ldata [7:0] $end -$var reg 7 [ predata [6:0] $end -$var reg 1 M rdstb $end -$var reg 1 \ readmode $end -$var reg 1 8 sdoenb $end -$var reg 2 ] state [1:0] $end -$var reg 1 ^ writemode $end -$var reg 1 L wrstb $end -$upscope $end -$upscope $end -$scope module uut $end -$var wire 4 _ iomem_we [3:0] $end -$var wire 1 3 pll_bypass $end -$var wire 1 ` resetn $end -$var wire 8 a spi_ro_config [7:0] $end -$var wire 4 b spi_ro_mask_rev [3:0] $end -$var wire 12 c spi_ro_mfgr_id [11:0] $end -$var wire 1 2 spi_ro_pll_dco_ena $end -$var wire 5 d spi_ro_pll_div [4:0] $end -$var wire 3 e spi_ro_pll_sel [2:0] $end -$var wire 26 f spi_ro_pll_trim [25:0] $end -$var wire 8 g spi_ro_prod_id [7:0] $end -$var wire 1 . spi_ro_reg_ena $end -$var wire 1 - spi_ro_xtal_ena $end -$var wire 1 h valid $end -$var wire 1 , wb_ack_o $end -$var wire 32 i wb_adr_i [31:0] $end -$var wire 1 A wb_clk_i $end -$var wire 1 B wb_cyc_i $end -$var wire 32 j wb_dat_i [31:0] $end -$var wire 1 D wb_rst_i $end -$var wire 4 k wb_sel_i [3:0] $end -$var wire 1 F wb_stb_i $end -$var wire 1 G wb_we_i $end -$var wire 32 l wb_dat_o [31:0] $end -$var wire 1 m ready $end -$scope module spi_sysctrl $end -$var wire 1 A clk $end -$var wire 32 n iomem_addr [31:0] $end -$var wire 1 h iomem_valid $end -$var wire 32 o iomem_wdata [31:0] $end -$var wire 4 p iomem_wstrb [3:0] $end -$var wire 1 3 pll_bypass $end -$var wire 1 ` resetn $end -$var wire 8 q spi_ro_config [7:0] $end -$var wire 4 r spi_ro_mask_rev [3:0] $end -$var wire 12 s spi_ro_mfgr_id [11:0] $end -$var wire 1 2 spi_ro_pll_dco_ena $end -$var wire 5 t spi_ro_pll_div [4:0] $end -$var wire 3 u spi_ro_pll_sel [2:0] $end -$var wire 26 v spi_ro_pll_trim [25:0] $end -$var wire 8 w spi_ro_prod_id [7:0] $end -$var wire 1 . spi_ro_reg_ena $end -$var wire 1 - spi_ro_xtal_ena $end -$var wire 1 x spi_prod_sel $end -$var wire 1 y spi_mfgr_sel $end -$var wire 1 z spi_maskrev_sel $end -$var wire 1 { spi_ena_sel $end -$var wire 1 | spi_cfg_sel $end -$var wire 1 } pll_cfg_sel $end -$var wire 1 ~ pll_bypass_sel $end -$var reg 32 !" iomem_rdata [31:0] $end -$var reg 1 m iomem_ready $end -$upscope $end -$upscope $end -$scope task read $end -$var reg 33 "" addr [32:0] $end -$upscope $end -$upscope $end -$enddefinitions $end -#0 -$dumpvars -bx "" -bx !" -0~ -0} -1| -0{ -0z -0y -0x -b101 w -b11111111111110111111111111 v -b0 u -b100 t -b10001010110 s -bx r -bz q -b0 p -b0 o -b0 n -xm -bx l -b0 k -b0 j -b0 i -0h -b101 g -b11111111111110111111111111 f -b0 e -b100 d -b10001010110 c -bx b -bz a -0` -b0 _ -0^ -b0 ] -0\ -b0 [ -b0 Z -b0 Y -b0 X -b0 W -b0 V -b0 U -b0 T -b11111111111110111111111111 S -b0 R -b100 Q -b0 P -b0 O -b0 N -0M -0L -b101 K -b10001010110 J -bx I -bx H -0G -0F -b0 E -1D -b0 C -0B -0A -b0 @ -x? -bx > -0= -0< -0; -1: -09 -18 -07 -06 -15 -bx 4 -13 -12 -b100 1 -b0 0 -b11111111111110111111111111 / -1. -1- -x, -bx + -b101 * -b10001010110 ) -bz ( -b101110000000000000000000010000 ' -b101110000000000000000000001000 & -b101110000000000000000000011000 % -b101110000000000000000000001100 $ -b101110000000000000000000010100 # -b101110000000000000000000000100 " -b101110000000000000000000000000 ! -$end -#1000 -0, -0m -1A -#2000 -05 -1` -0A -1; -0D -#3000 -1A -#4000 -0A -b101110000000000000000000010100 "" -b1111 4 -b1111 H -b1111 b -b1111 r -b1111 > -b1111 I -#5000 -0| -1z -1h -b101110000000000000000000010100 @ -b101110000000000000000000010100 i -b101110000000000000000000010100 n -1B -1F -1A -#6000 -0A -#7000 -b1111 + -b1111 l -b1111 !" -1, -1m -1A -#8000 -0A -#9000 -0h -b101110000000000000000000001100 "" -0F -0B -0, -0m -1A -#10000 -0A -#11000 -1y -0z -1h -b101110000000000000000000001100 @ -b101110000000000000000000001100 i -b101110000000000000000000001100 n -1B -1F -1A -#12000 -0A -#13000 -b10001010110 + -b10001010110 l -b10001010110 !" -1, -1m -1A -#14000 -0A -#15000 -0h -b101110000000000000000000010000 "" -0F -0B -0, -0m -1A -#16000 -0A -#17000 -0y -1x -1h -b101110000000000000000000010000 @ -b101110000000000000000000010000 i -b101110000000000000000000010000 n -1B -1F -1A -#18000 -0A -#19000 -b101 + -b101 l -b101 !" -1, -1m -1A -#20000 -0A -#21000 -0h -b101110000000000000000000011000 "" -0F -0B -0, -0m -1A -#22000 -0A -#23000 -0x -1~ -1h -b101110000000000000000000011000 @ -b101110000000000000000000011000 i -b101110000000000000000000011000 n -1B -1F -1A -#24000 -0A -#25000 -b1 + -b1 l -b1 !" -1, -1m -1A -#26000 -0A -#27000 -0h -b101110000000000000000000001000 "" -0F -0B -0, -0m -1A -#28000 -0A -#29000 -1} -0~ -1h -b101110000000000000000000001000 @ -b101110000000000000000000001000 i -b101110000000000000000000001000 n -1B -1F -1A -#30000 -0A -#31000 -b111111111111101111111111111 + -b111111111111101111111111111 l -b111111111111101111111111111 !" -1, -1m -1A -#32000 -0A -#33000 -0h -b101110000000000000000000000100 "" -0F -0B -0, -0m -1A -#34000 -0A -#35000 -1{ -0} -1h -b101110000000000000000000000100 @ -b101110000000000000000000000100 i -b101110000000000000000000000100 n -1B -1F -1A -#36000 -0A -#37000 -b10000011 + -b10000011 l -b10000011 !" -1, -1m -1A -#38000 -0A -#39000 -0h -0F -0B -0, -0m -1A
diff --git a/verilog/dv/wb/Makefile b/verilog/dv/wb_utests/Makefile similarity index 77% copy from verilog/dv/wb/Makefile copy to verilog/dv/wb_utests/Makefile index 7b0e09b..930e5b5 100644 --- a/verilog/dv/wb/Makefile +++ b/verilog/dv/wb_utests/Makefile
@@ -3,7 +3,7 @@ .SUFFIXES: .SILENT: clean all -PATTERNS = gpio_wb intercon_wb spimemio_wb uart_wb crossbar_wb arbiter_wb +PATTERNS = gpio_wb intercon_wb la_wb mem_wb mprj_ctrl spi_sysctrl_wb spimemio_wb uart_wb all: ${PATTERNS} for i in ${PATTERNS}; do \
diff --git a/verilog/dv/wb/gpio_wb/Makefile b/verilog/dv/wb_utests/gpio_wb/Makefile similarity index 100% rename from verilog/dv/wb/gpio_wb/Makefile rename to verilog/dv/wb_utests/gpio_wb/Makefile
diff --git a/verilog/dv/wb/gpio_wb/gpio_wb_tb.v b/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v similarity index 100% rename from verilog/dv/wb/gpio_wb/gpio_wb_tb.v rename to verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v
diff --git a/verilog/dv/wb/intercon_wb/Makefile b/verilog/dv/wb_utests/intercon_wb/Makefile similarity index 100% rename from verilog/dv/wb/intercon_wb/Makefile rename to verilog/dv/wb_utests/intercon_wb/Makefile
diff --git a/verilog/dv/wb/intercon_wb/intercon_wb_tb.v b/verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v similarity index 100% rename from verilog/dv/wb/intercon_wb/intercon_wb_tb.v rename to verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v
diff --git a/verilog/dv/wb/la_wb/Makefile b/verilog/dv/wb_utests/la_wb/Makefile similarity index 100% rename from verilog/dv/wb/la_wb/Makefile rename to verilog/dv/wb_utests/la_wb/Makefile
diff --git a/verilog/dv/wb/la_wb/la_wb_tb.v b/verilog/dv/wb_utests/la_wb/la_wb_tb.v similarity index 100% rename from verilog/dv/wb/la_wb/la_wb_tb.v rename to verilog/dv/wb_utests/la_wb/la_wb_tb.v
diff --git a/verilog/dv/wb/mem_wb/Makefile b/verilog/dv/wb_utests/mem_wb/Makefile similarity index 100% rename from verilog/dv/wb/mem_wb/Makefile rename to verilog/dv/wb_utests/mem_wb/Makefile
diff --git a/verilog/dv/wb/mem_wb/mem_wb_tb.v b/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v similarity index 96% rename from verilog/dv/wb/mem_wb/mem_wb_tb.v rename to verilog/dv/wb_utests/mem_wb/mem_wb_tb.v index eb45e22..2c2afd7 100644 --- a/verilog/dv/wb/mem_wb/mem_wb_tb.v +++ b/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
@@ -4,7 +4,7 @@ `define USE_OPENRAM -`include "sram_1rw1r_32_256_8_sky130.v" +`include "sram_1rw1r_32_8192_8_sky130.v" `include "mem_wb.v" module mem_wb_tb; @@ -62,7 +62,7 @@ // Randomly Write to memory array for ( i = 0; i < 1; i = i + 1) begin - ref_data[i] = $urandom_range(0, 2**32); + ref_data[i] = $urandom_range(0, 2**30); write(i, ref_data[i]); #2; end
diff --git a/verilog/dv/wb/arbiter_wb/Makefile b/verilog/dv/wb_utests/mprj_ctrl/Makefile similarity index 62% rename from verilog/dv/wb/arbiter_wb/Makefile rename to verilog/dv/wb_utests/mprj_ctrl/Makefile index e792a4d..841be9e 100644 --- a/verilog/dv/wb/arbiter_wb/Makefile +++ b/verilog/dv/wb_utests/mprj_ctrl/Makefile
@@ -1,11 +1,11 @@ .SUFFIXES: -PATTERN = arbiter_wb +PATTERN = mprj_ctrl all: ${PATTERN:=.vcd} %.vvp: %_tb.v - iverilog -I ../../../ip -I .. -I ../../ -I ../../../rtl \ + iverilog -I ../../../rtl \ $< -o $@ %.vcd: %.vvp @@ -14,4 +14,4 @@ clean: rm -f *.vvp *.vcd *.log -.PHONY: clean all +.PHONY: clean all \ No newline at end of file
diff --git a/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v b/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v new file mode 100644 index 0000000..a4c01d0 --- /dev/null +++ b/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v
@@ -0,0 +1,142 @@ + + +`timescale 1 ns / 1 ps + +`include "mprj_ctrl.v" + +module mprj_ctrl_tb; + + reg wb_clk_i; + reg wb_rst_i; + + reg wb_stb_i; + reg wb_cyc_i; + reg wb_we_i; + reg [3:0] wb_sel_i; + reg [31:0] wb_dat_i; + reg [31:0] wb_adr_i; + + wire wb_ack_o; + wire [31:0] wb_dat_o; + + initial begin + wb_clk_i = 0; + wb_rst_i = 0; + wb_stb_i = 0; + wb_cyc_i = 0; + wb_sel_i = 0; + wb_we_i = 0; + wb_dat_i = 0; + wb_adr_i = 0; + end + + always #1 wb_clk_i = ~wb_clk_i; + + // Mega Project Control Registers + wire [31:0] mprj_ctrl = uut.BASE_ADR; + wire [31:0] pwr_ctrl = uut.BASE_ADR + uut.IO_PADS*4; + + initial begin + $dumpfile("mprj_ctrl_tb.vcd"); + $dumpvars(0, mprj_ctrl_tb); + repeat (50) begin + repeat (1000) @(posedge wb_clk_i); + end + $display("%c[1;31m",27); + $display ("Monitor: Timeout, Test Mega-Project Control Failed"); + $display("%c[0m",27); + $finish; + end + + integer i; + + reg [31:0] data; + + initial begin + // Reset Operation + wb_rst_i = 1; + #2; + wb_rst_i = 0; + #2; + + for (i=0; i<uut.IO_PADS; i=i+1) begin + data = $urandom_range(0, 2**(7)); + write(mprj_ctrl+i*4, data); + #2; + read(mprj_ctrl+i*4); + if (wb_dat_o !== data) begin + $display("Monitor: R/W from IO-CTRL Failed."); + $finish; + end + end + + for (i=0; i<uut.PWR_CTRL; i=i+1) begin + data = $urandom_range(0, 2**(7)); + write(pwr_ctrl+i*4, data); + #2; + read(pwr_ctrl+i*4); + if (wb_dat_o !== data) begin + $display("Monitor: R/W from POWER-CTRL Failed."); + $finish; + end + end + + $display("Success!"); + $finish; + end + + task write; + input [32:0] addr; + input [32:0] data; + begin + @(posedge wb_clk_i) begin + wb_stb_i = 1; + wb_cyc_i = 1; + wb_sel_i = 4'hF; + wb_we_i = 1; + wb_adr_i = addr; + wb_dat_i = data; + $display("Write Cycle Started."); + end + // Wait for an ACK + wait(wb_ack_o == 1); + wait(wb_ack_o == 0); + wb_cyc_i = 0; + wb_stb_i = 0; + $display("Write Cycle Ended."); + end + endtask + + task read; + input [32:0] addr; + begin + @(posedge wb_clk_i) begin + wb_stb_i = 1; + wb_cyc_i = 1; + wb_we_i = 0; + wb_adr_i = addr; + $display("Read Cycle Started."); + end + // Wait for an ACK + wait(wb_ack_o == 1); + wait(wb_ack_o == 0); + wb_cyc_i = 0; + wb_stb_i = 0; + $display("Read Cycle Ended."); + end + endtask + + mprj_ctrl_wb uut( + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + .wb_stb_i(wb_stb_i), + .wb_cyc_i(wb_cyc_i), + .wb_sel_i(wb_sel_i), + .wb_we_i(wb_we_i), + .wb_dat_i(wb_dat_i), + .wb_adr_i(wb_adr_i), + .wb_ack_o(wb_ack_o), + .wb_dat_o(wb_dat_o) + ); + +endmodule \ No newline at end of file
diff --git a/verilog/dv/wb/spi_sysctrl_wb/Makefile b/verilog/dv/wb_utests/spi_sysctrl_wb/Makefile similarity index 100% rename from verilog/dv/wb/spi_sysctrl_wb/Makefile rename to verilog/dv/wb_utests/spi_sysctrl_wb/Makefile
diff --git a/verilog/dv/wb/spi_sysctrl_wb/spi_sysctrl_wb_tb.v b/verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v similarity index 100% rename from verilog/dv/wb/spi_sysctrl_wb/spi_sysctrl_wb_tb.v rename to verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v
diff --git a/verilog/dv/wb/spimemio_wb/Makefile b/verilog/dv/wb_utests/spimemio_wb/Makefile similarity index 100% rename from verilog/dv/wb/spimemio_wb/Makefile rename to verilog/dv/wb_utests/spimemio_wb/Makefile
diff --git a/verilog/dv/wb/spimemio_wb/flash.hex b/verilog/dv/wb_utests/spimemio_wb/flash.hex similarity index 100% rename from verilog/dv/wb/spimemio_wb/flash.hex rename to verilog/dv/wb_utests/spimemio_wb/flash.hex
diff --git a/verilog/dv/wb/spimemio_wb/spimemio_wb_tb.v b/verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v similarity index 100% rename from verilog/dv/wb/spimemio_wb/spimemio_wb_tb.v rename to verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v
diff --git a/verilog/dv/wb/sysctrl_wb/Makefile b/verilog/dv/wb_utests/sysctrl_wb/Makefile similarity index 100% rename from verilog/dv/wb/sysctrl_wb/Makefile rename to verilog/dv/wb_utests/sysctrl_wb/Makefile
diff --git a/verilog/dv/wb/sysctrl_wb/sysctrl_wb_tb.v b/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v similarity index 100% rename from verilog/dv/wb/sysctrl_wb/sysctrl_wb_tb.v rename to verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
diff --git a/verilog/dv/wb/sysctrl_wb/sysctrl_wb_tb.vcd b/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.vcd similarity index 100% rename from verilog/dv/wb/sysctrl_wb/sysctrl_wb_tb.vcd rename to verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.vcd
diff --git a/verilog/dv/wb/uart_wb/Makefile b/verilog/dv/wb_utests/uart_wb/Makefile similarity index 100% rename from verilog/dv/wb/uart_wb/Makefile rename to verilog/dv/wb_utests/uart_wb/Makefile
diff --git a/verilog/dv/wb/uart_wb/uart_wb_tb.v b/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v similarity index 100% rename from verilog/dv/wb/uart_wb/uart_wb_tb.v rename to verilog/dv/wb_utests/uart_wb/uart_wb_tb.v
diff --git a/verilog/ip/arbiter.v b/verilog/ip/arbiter.v deleted file mode 100644 index f599173..0000000 --- a/verilog/ip/arbiter.v +++ /dev/null
@@ -1,135 +0,0 @@ -module wb_arbiter #( - parameter AW = 32, - parameter DW = 32, - parameter NM = 2 -)( - - input wb_clk_i, - input wb_rst_i, - - // Masters Interface - input [NM-1:0] wbm_stb_i, - input [NM-1:0] wbm_cyc_i, - input [NM-1:0] wbm_we_i, - input [NM*(DW/8)-1:0] wbm_sel_i, - input [NM*DW-1:0] wbm_dat_i, - input [NM*AW-1:0] wbm_adr_i, - - output [NM-1:0] wbm_ack_o, - output [NM-1:0] wbm_err_o, - output [NM*DW-1:0] wbm_dat_o, - - // Slave Interface - input wbs_ack_i, - input wbs_err_i, - input [DW-1:0] wbs_dat_i, - output reg wbs_stb_o, - output reg wbs_cyc_o, - output wbs_we_o, - output reg [(DW/8)-1:0] wbs_sel_o, - output reg [AW-1:0] wbs_adr_o, - output reg [DW-1:0] wbs_dat_o -); - -localparam SEL = DW / 8; - -// Current elected master (one hot) -reg [NM-1:0] cur_master; -reg capture_req; - -wire [NM-1:0] master_sel; -wire [NM-1:0] requests; -wire any_req; -wire any_acks; - -assign requests = wbm_cyc_i & wbm_stb_i; -assign any_req = |requests; -assign any_ack = |{wbs_ack_i, wbs_err_i}; - -genvar iM; -generate - assign master_sel[0] = requests[0]; - for (iM=1; iM<NM; iM=iM+1) begin - assign master_sel[iM] = requests[iM] & (~master_sel[iM-1]); - end -endgenerate - -// Current-elected master -always @(posedge wb_clk_i) - if(wb_rst_i) begin - cur_master <= {NM{1'b0}}; - end else if (capture_req) begin - cur_master <= master_sel; - end - -// Finite State Machine -localparam IDLE = 1'b0; -localparam BUSY = 1'b1; - -reg state = IDLE; -reg next_state; - -always @(*) -begin: FSM_COMB -case (state) - IDLE: if (any_req) begin - wbs_stb_o = 1'b1; - wbs_cyc_o = 1'b1; - capture_req = 1'b1; - next_state = BUSY; - end else begin - wbs_stb_o = 1'b0; - wbs_cyc_o = 1'b0; - capture_req = 1'b0; - next_state = IDLE; - end - BUSY: begin - if (any_ack & !any_req) begin - next_state = IDLE; - end if (any_ack & any_req) begin - capture_req = 1'b1; - end - end - default: next_state = IDLE; -endcase -end - -always @(posedge wb_clk_i) - if (wb_rst_i) - state <= IDLE; - else - state <= next_state; - -// Masters Output Assignment -assign wbm_dat_o = {NM{wbs_dat_i}}; -assign wbm_ack_o = {NM{wbs_ack_i}} & cur_master; -assign wbm_err_o = {NM{wbs_err_i}} & cur_master; - -// Multiplexed signal to the slave - -assign wbs_we_o = |(cur_master & wbm_we_i); - -integer k; -always @(*) begin - wbs_sel_o = {SEL{1'b0}}; - for (k=0; k<(NM*SEL); k=k+1) - wbs_sel_o[k%SEL] = wbs_sel_o[k%SEL] | (cur_master[k/SEL] & wbm_sel_i[k]); -end - -integer l; -always @(*) begin - wbs_adr_o = {AW{1'b0}}; - for (l=0; l<(NM*AW); l=l+1) - wbs_adr_o[l%AW] = wbs_adr_o[l%AW] | (cur_master[l/AW] & wbm_adr_i[l]); -end - -integer o; -always @(*) begin - wbs_dat_o = {DW{1'b0}}; - for (o=0; o<(NM*DW); o=o+1) - wbs_dat_o[o%DW] = wbs_dat_o[o%DW] | (cur_master[o/DW] & wbm_dat_i[o]); -end - - -endmodule -
diff --git a/verilog/ip/crossbar.v b/verilog/ip/crossbar.v deleted file mode 100644 index ee07d5e..0000000 --- a/verilog/ip/crossbar.v +++ /dev/null
@@ -1,172 +0,0 @@ - -`include "distributor.v" -`include "arbiter.v" - -module wb_xbar #( - parameter NM = 2, - parameter NS = 4, - parameter AW = 32, - parameter DW = 32 -) ( - - input wb_clk_i, - input wb_rst_i, - - // Masters interface - input [NM-1:0] wbm_cyc_i, - input [NM-1:0] wbm_stb_i, - input [NM-1:0] wbm_we_i, - input [(NM*(DW/8))-1:0] wbm_sel_i, - input [(NM*AW)-1:0] wbm_adr_i, - input [(NM*DW)-1:0] wbm_dat_i, - output [NM-1:0] wbm_ack_o, - output [NM-1:0] wbm_err_o, - output [(NM*DW)-1:0] wbm_dat_o, - - // Slaves interfaces - input [NS-1:0] wbs_ack_i, - input [(NS*DW)-1:0] wbs_dat_i, - output [NS-1:0] wbs_cyc_o, - output [NS-1:0] wbs_stb_o, - output [NS-1:0] wbs_we_o, - output [(NS*(DW/8))-1:0] wbs_sel_o, - output [(NS*AW)-1:0] wbs_adr_o, - output [(NS*DW)-1:0] wbs_dat_o -); - parameter ADR_MASK = { - {8'hFF, {24{1'b0}}}, - {8'hFF, {24{1'b0}}}, - {8'hFF, {24{1'b0}}}, - {8'hFF, {24{1'b0}}} - }; - - parameter SLAVE_ADR = { - {8'hB0, {24{1'b0}}}, - {8'hA0, {24{1'b0}}}, - {8'h90, {24{1'b0}}}, - {8'h80, {24{1'b0}}} - }; - - localparam SEL = DW / 8; - - wire [(NM*NS)-1:0] distributor_cyc_o; - wire [(NM*NS)-1:0] distributor_stb_o; - wire [(NM*NS)-1:0] distributor_we_o; - wire [(NM*NS*SEL)-1:0] distributor_sel_o; - wire [(NM*NS*AW)-1:0] distributor_adr_o; - wire [(NM*NS*DW)-1:0] distributor_dat_o; - wire [(NM*NS)-1:0] distributor_ack_i; - wire [(NM*NS)-1:0] distributor_err_i; - wire [(NM*NS)-1:0] distributor_rty_i; - wire [(NM*NS*DW)-1:0] distributor_dat_i; - - //Arbiter busses: - wire [(NM*NS)-1:0] arbiter_cyc_i; - wire [(NM*NS)-1:0] arbiter_stb_i; - wire [(NM*NS)-1:0] arbiter_we_i; - wire [(NM*NS*SEL)-1:0] arbiter_sel_i; - wire [(NM*NS*AW)-1:0] arbiter_adr_i; - wire [(NM*NS*DW)-1:0] arbiter_dat_i; - wire [(NM*NS)-1:0] arbiter_ack_o; - wire [(NM*NS)-1:0] arbiter_err_o; - wire [(NM*NS*DW)-1:0] arbiter_dat_o; - - //Instantiate distributors - generate - genvar i; - for (i=0; i<NM; i=i+1) - begin - distributor #( - .NS(NS), - .AW(AW), - .DW(DW), - .SLAVE_ADR(SLAVE_ADR), - .ADR_MASK(ADR_MASK) - ) distributor ( - .wb_clk_i(wb_clk_i), - .wb_rst_i(wb_rst_i), - - .wbm_cyc_i(wbm_cyc_i[i]), - .wbm_stb_i(wbm_stb_i[i]), - .wbm_we_i(wbm_we_i[i]), - .wbm_sel_i(wbm_sel_i[(SEL*(i+1))-1:(SEL*i)]), - .wbm_adr_i(wbm_adr_i[(AW*(i+1))-1:(AW*i)]), - .wbm_dat_i(wbm_dat_i[(DW*(i+1))-1:(DW*i)]), - .wbm_ack_o(wbm_ack_o[i]), - .wbm_dat_o(wbm_dat_o[(DW*(i+1))-1:(DW*i)]), - - // Slave interfaces - .wbs_cyc_o (distributor_cyc_o[(NS*(i+1))-1:NS*i]), - .wbs_stb_o (distributor_stb_o[(NS*(i+1))-1:NS*i]), - .wbs_we_o (distributor_we_o [(NS*(i+1))-1:NS*i]), - .wbs_sel_o (distributor_sel_o[(NS*SEL*(i+1))-1:NS*SEL*i]), - .wbs_adr_o (distributor_adr_o[(NS*AW*(i+1))-1:NS*AW*i]), - .wbs_dat_o (distributor_dat_o[(NS*DW*(i+1))-1:NS*DW*i]), - .wbs_ack_i (distributor_ack_i[(NS*(i+1))-1:NS*i]), - .wbs_dat_i (distributor_dat_i[(NS*DW*(i+1))-1:NS*DW*i]) - ); - end - endgenerate - - //Instantiate arbiters - generate - genvar j; - for (j=0; j<NS; j=j+1) - begin - wb_arbiter #( - .NM(NM), - .AW(AW), - .DW(DW) - ) arbiter ( - .wb_clk_i(wb_clk_i), - .wb_rst_i(wb_rst_i), - // Masters Interface - .wbm_cyc_i (arbiter_cyc_i[(NM*(j+1))-1:NM*j]), - .wbm_stb_i (arbiter_stb_i[(NM*(j+1))-1:NM*j]), - .wbm_we_i (arbiter_we_i [(NM*(j+1))-1:NM*j]), - .wbm_sel_i (arbiter_sel_i[(NM*SEL*(j+1))-1:NM*SEL*j]), - .wbm_adr_i (arbiter_adr_i[(NM*AW*(j+1))-1:NM*AW*j]), - .wbm_dat_i (arbiter_dat_i[(NM*DW*(j+1))-1:NM*DW*j]), - .wbm_ack_o (arbiter_ack_o[(NM*(j+1))-1:NM*j]), - .wbm_dat_o (arbiter_dat_o[(NM*DW*(j+1))-1:NM*DW*j]), - - // Slave interfaces - .wbs_cyc_o (wbs_cyc_o[j]), - .wbs_stb_o (wbs_stb_o[j]), - .wbs_we_o (wbs_we_o[j]), - .wbs_sel_o (wbs_sel_o[(SEL*(j+1))-1:(SEL*j)]), - .wbs_adr_o (wbs_adr_o[(AW*(j+1))-1:(AW*j)]), - .wbs_dat_o (wbs_dat_o[(DW*(j+1))-1:(DW*j)]), - .wbs_ack_i (wbs_ack_i[j]), - .wbs_dat_i (wbs_dat_i[(DW*(j+1))-1:(DW*j)]) - ); - end - endgenerate - - //Crossbar connections - generate - genvar k, l, m, indx; - for (k=0; k<NM; k=k+1) - for (l=0; l<NS; l=l+1) - begin - assign arbiter_cyc_i[(NM*l)+k] = distributor_cyc_o[(NS*k)+l]; - assign arbiter_stb_i[(NM*l)+k] = distributor_stb_o[(NS*k)+l]; - assign arbiter_we_i [(NM*l)+k] = distributor_we_o [(NS*k)+l]; - - assign arbiter_sel_i[(((NM*l)+k)*SEL)+(SEL-1):((NM*l)+k)*SEL] = - distributor_sel_o[(((NS*k)+l)*SEL)+(SEL-1):((NS*k)+l)*SEL]; - - assign arbiter_adr_i[(((NM*l)+k)*AW)+(AW-1) : ((NM*l)+k)*AW] = - distributor_adr_o[(((NS*k)+l)*AW)+(AW-1) : ((NS*k)+l)*AW]; - - assign arbiter_dat_i[(((NM*l)+k)*AW)+(AW-1) : ((NM*l)+k)*AW] = - distributor_dat_o[(((NS*k)+l)*AW)+(AW-1) : ((NS*k)+l)*AW]; - - assign distributor_dat_i[(((NS*k)+l)*DW)+(DW-1) : ((NS*k)+l)*DW] = - arbiter_dat_o[(((NM*l)+k)*DW)+(DW-1) : ((NM*l)+k)*DW]; - - assign distributor_ack_i[(NS*k)+l] = arbiter_ack_o[(NM*l)+k]; - end - endgenerate - -endmodule \ No newline at end of file
diff --git a/verilog/ip/distributor.v b/verilog/ip/distributor.v deleted file mode 100644 index 78aa374..0000000 --- a/verilog/ip/distributor.v +++ /dev/null
@@ -1,77 +0,0 @@ -module distributor #( - parameter AW = 32, - parameter DW = 32, - parameter NS = 4 -) ( - input wb_clk_i, - input wb_rst_i, - - // Master Interface - input wbm_cyc_i, - input wbm_stb_i, - input wbm_we_i, - input [(DW/8)-1:0] wbm_sel_i, - input [AW-1:0] wbm_adr_i, - input [DW-1:0] wbm_dat_i, - output wbm_ack_o, - output reg [DW-1:0] wbm_dat_o, - - // Slave interfaces - input [NS-1:0] wbs_ack_i, - input [(NS*DW)-1:0] wbs_dat_i, - - output [NS-1:0] wbs_cyc_o, - output [NS-1:0] wbs_stb_o, - output [NS-1:0] wbs_we_o, - output [(NS*(DW/8))-1:0] wbs_sel_o, - output [(NS*AW)-1:0] wbs_adr_o, - output [(NS*DW)-1:0] wbs_dat_o - -); - -parameter ADR_MASK = { - {8'hFF, {24{1'b0}}}, - {8'hFF, {24{1'b0}}}, - {8'hFF, {24{1'b0}}}, - {8'hFF, {24{1'b0}}} -}; - -parameter SLAVE_ADR = { - {8'hB0, {24{1'b0}}}, - {8'hA0, {24{1'b0}}}, - {8'h90, {24{1'b0}}}, - {8'h80, {24{1'b0}}} -}; - -wire [NS-1:0] slave_sel; - -// Decode Addresseses, then accordingly assign the slave signals -genvar iS; -generate - for (iS = 0; iS < NS; iS = iS + 1) begin - assign slave_sel[iS] = ((wbm_adr_i & ADR_MASK[(iS+1)*AW-1:iS*AW]) == SLAVE_ADR[(iS+1)*AW-1:iS*AW]); - end -endgenerate - -// Plain signal propagation to all target busses -assign wbs_we_o = {NS{wbm_we_i}}; //write enables -assign wbs_sel_o = {NS{wbm_sel_i}}; //write data selects -assign wbs_adr_o = {NS{wbm_adr_i}}; //address busses -assign wbs_dat_o = {NS{wbm_dat_i}}; //write data busses - -// Masked signal propagation to all target busses -assign wbs_cyc_o = slave_sel & {NS{wbm_cyc_i}}; // bus cycle indicators -assign wbs_stb_o = slave_sel & {NS{wbm_cyc_i}}; // access requests - -// Multiplexed signal propagation to the initiator bus -assign wbm_ack_o = |{slave_sel & wbs_ack_i}; - -integer i; -always @* - begin - wbm_dat_o = {DW{1'b0}}; - for (i=0; i<(DW*NS); i=i+1) - wbm_dat_o[i%DW] = wbm_dat_o[i%DW] | (slave_sel[i/DW] & wbs_dat_i[i]); - end - -endmodule \ No newline at end of file
diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v new file mode 100644 index 0000000..0203ede --- /dev/null +++ b/verilog/rtl/chip_io.v
@@ -0,0 +1,300 @@ +module chip_io( + // Package Pins + inout vdd, + inout vdd1v8, + inout vss, + input [15:0] gpio, + inout xi, + output xo, + inout adc0_in, + inout adc1_in, + inout adc_high, + inout adc_low, + inout comp_inn, + inout comp_inp, + inout RSTB, + inout ser_rx, + output ser_tx, + inout irq, + output SDO, + inout SDI, + inout CSB, + inout SCK, + inout xclk, + output flash_csb, + output flash_clk, + output flash_io0, + output flash_io1, + output flash_io2, + output flash_io3, + // Chip Core Interface + input por, + output porb_h, + output ext_clk_core, + output xi_core, + input [15:0] gpio_out_core, + output [15:0] gpio_in_core, + input [15:0] gpio_mode0_core, + input [15:0] gpio_mode1_core, + input [15:0] gpio_outenb_core, + input [15:0] gpio_inenb_core, + output SCK_core, + output ser_rx_core, + inout ser_tx_core, + output irq_pin_core, + input flash_csb_core, + input flash_clk_core, + input flash_csb_oeb_core, + input flash_clk_oeb_core, + input flash_io0_oeb_core, + input flash_io1_oeb_core, + input flash_io2_oeb_core, + input flash_io3_oeb_core, + input flash_csb_ieb_core, + input flash_clk_ieb_core, + input flash_io0_ieb_core, + input flash_io1_ieb_core, + input flash_io2_ieb_core, + input flash_io3_ieb_core, + input flash_io0_do_core, + input flash_io1_do_core, + input flash_io2_do_core, + input flash_io3_do_core, + output flash_io0_di_core, + output flash_io1_di_core, + output flash_io2_di_core, + output flash_io3_di_core, + output SDI_core, + output CSB_core, + input pll_clk16, + input SDO_core, + // Mega-project IOs + input [`MPRJ_IO_PADS-1:0] mprj_io, + input [`MPRJ_IO_PADS-1:0] mprj_io_out, + input [`MPRJ_IO_PADS-1:0] mprj_io_oeb_n, + input [`MPRJ_IO_PADS-1:0] mprj_io_hldh_n, + input [`MPRJ_IO_PADS-1:0] mprj_io_enh, + input [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis, + input [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel, + input [`MPRJ_IO_PADS-1:0] mprj_io_analog_en, + input [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel, + input [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol, + input [`MPRJ_IO_PADS*3-1:0] mprj_io_dm, + output [`MPRJ_IO_PADS-1:0] mprj_io_in +); + wire analog_a, analog_b; + wire vddio_q, vssio_q; + // Instantiate power cells for VDD3V3 domain (8 total; 4 high clamps and + // 4 low clamps) + s8iom0_vdda_hvc_pad vdd3v3hclamp [1:0] ( + `ABUTMENT_PINS + .drn_hvc(), + .src_bdy_hvc() + ); + + s8iom0_vddio_hvc_pad vddiohclamp [1:0] ( + `ABUTMENT_PINS + .drn_hvc(), + .src_bdy_hvc() + ); + + s8iom0_vdda_lvc_pad vdd3v3lclamp [3:0] ( + `ABUTMENT_PINS + .bdy2_b2b(), + .drn_lvc1(), + .drn_lvc2(), + .src_bdy_lvc1(), + .src_bdy_lvc2() + ); + + // Instantiate the core voltage supply (since it is not generated on-chip) + // (1.8V) (4 total, 2 high and 2 low clamps) + s8iom0_vccd_hvc_pad vdd1v8hclamp [1:0] ( + `ABUTMENT_PINS + .drn_hvc(), + .src_bdy_hvc() + ); + + s8iom0_vccd_lvc_pad vdd1v8lclamp [1:0] ( + `ABUTMENT_PINS + .bdy2_b2b(), + .drn_lvc1(), + .drn_lvc2(), + .src_bdy_lvc1(), + .src_bdy_lvc2() + ); + + // Instantiate ground cells (7 total, 4 high clamps and 3 low clamps) + s8iom0_vssa_hvc_pad vsshclamp [3:0] ( + `ABUTMENT_PINS + .drn_hvc(), + .src_bdy_hvc() + ); + + s8iom0_vssa_lvc_pad vssalclamp ( + `ABUTMENT_PINS + .bdy2_b2b(), + .drn_lvc1(), + .drn_lvc2(), + .src_bdy_lvc1(), + .src_bdy_lvc2() + ); + + s8iom0_vssd_lvc_pad vssdlclamp ( + `ABUTMENT_PINS + .bdy2_b2b(), + .drn_lvc1(), + .drn_lvc2(), + .src_bdy_lvc1(), + .src_bdy_lvc2() + ); + + s8iom0_vssio_lvc_pad vssiolclamp ( + `ABUTMENT_PINS + .bdy2_b2b(), + .drn_lvc1(), + .drn_lvc2(), + .src_bdy_lvc1(), + .src_bdy_lvc2() + ); + + wire [47:0] dm_all; + assign dm_all = {gpio_mode1_core[15], gpio_mode1_core[15], gpio_mode0_core[15], + gpio_mode1_core[14], gpio_mode1_core[14], gpio_mode0_core[14], + gpio_mode1_core[13], gpio_mode1_core[13], gpio_mode0_core[13], + gpio_mode1_core[12], gpio_mode1_core[12], gpio_mode0_core[12], + gpio_mode1_core[11], gpio_mode1_core[11], gpio_mode0_core[11], + gpio_mode1_core[10], gpio_mode1_core[10], gpio_mode0_core[10], + gpio_mode1_core[9], gpio_mode1_core[9], gpio_mode0_core[9], + gpio_mode1_core[8], gpio_mode1_core[8], gpio_mode0_core[8], + gpio_mode1_core[7], gpio_mode1_core[7], gpio_mode0_core[7], + gpio_mode1_core[6], gpio_mode1_core[6], gpio_mode0_core[6], + gpio_mode1_core[5], gpio_mode1_core[5], gpio_mode0_core[5], + gpio_mode1_core[4], gpio_mode1_core[4], gpio_mode0_core[4], + gpio_mode1_core[3], gpio_mode1_core[3], gpio_mode0_core[3], + gpio_mode1_core[2], gpio_mode1_core[2], gpio_mode0_core[2], + gpio_mode1_core[1], gpio_mode1_core[1], gpio_mode0_core[1], + gpio_mode1_core[0], gpio_mode1_core[0], gpio_mode0_core[0]}; + + wire[2:0] flash_io0_mode = + {flash_io0_ieb_core, flash_io0_ieb_core, flash_io0_oeb_core}; + wire[2:0] flash_io1_mode = + {flash_io1_ieb_core, flash_io1_ieb_core, flash_io1_oeb_core}; + wire[2:0] flash_io2_mode = + {flash_io2_ieb_core, flash_io2_ieb_core, flash_io2_oeb_core}; + wire[2:0] flash_io3_mode = + {flash_io3_ieb_core, flash_io3_ieb_core, flash_io3_oeb_core}; + + // GPIO pads + `INOUT_PAD_V( + gpio, gpio_in_core, gpio_out_core, 16, + gpio_inenb_core, gpio_outenb_core, dm_all); + + // Flash pads + `INOUT_PAD( + flash_io0, flash_io0_di_core, flash_io0_do_core, + flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode); + `INOUT_PAD( + flash_io1, flash_io1_di_core, flash_io1_do_core, + flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode); + `INOUT_PAD( + flash_io2, flash_io2_di_core, flash_io2_do_core, + flash_io2_ieb_core, flash_io2_oeb_core, flash_io2_mode); + `INOUT_PAD( + flash_io3, flash_io3_di_core, flash_io3_do_core, + flash_io3_ieb_core, flash_io3_oeb_core, flash_io3_mode); + + `INPUT_PAD(xi, xi_core); + `INPUT_PAD(irq, irq_pin_core); + `INPUT_PAD(xclk,ext_clk_core); + `INPUT_PAD(SDI, SDI_core); + `INPUT_PAD(CSB, CSB_core); + `INPUT_PAD(SCK, SCK_core); + + // Analog Pads + `INPUT_PAD_ANALOG(adc0_in,vss,vss); + `INPUT_PAD_ANALOG(adc1_in,vss,vss); + `INPUT_PAD_ANALOG(adc_high,vdd1v8,vdd1v8); + `INPUT_PAD_ANALOG(adc_low,vss,vss); + `INPUT_PAD_ANALOG(comp_inn,vss,vss); + `INPUT_PAD_ANALOG(comp_inp,vdd1v8,vss); + + // Output Pads + `OUTPUT_PAD(xo,pll_clk16,vdd1v8,vss); + `OUTPUT_PAD(SDO,SDO_core,vdd1v8,SDO_enb); + + `OUTPUT_PAD(flash_csb, flash_csb_core, flash_csb_ieb_core, flash_csb_oeb_core); + `OUTPUT_PAD(flash_clk, flash_clk_core, flash_clk_ieb_core, flash_clk_oeb_core); + + // Instantiate GPIO overvoltage (I2C) compliant cell + // (Use this for ser_rx and ser_tx; no reason other than testing + // the use of the cell.) (Might be worth adding in the I2C IP from + // ravenna just to test on a proper I2C channel.) + `I2C_RX(ser_rx, ser_rx_core); + `I2C_TX(ser_tx, ser_tx_core); + + // NOTE: The analog_out pad from the raven chip has been replaced by + // the digital reset input RSTB on striVe due to the lack of an on-board + // power-on-reset circuit. The XRES pad is used for providing a glitch- + // free reset. + s8iom0s8_top_xres4v2 RSTB_pad ( + `ABUTMENT_PINS +`ifndef TOP_ROUTING + .pad(RSTB), +`endif + .tie_weak_hi_h(xresloop), // Loop-back connection to pad through pad_a_esd_h + .tie_hi_esd(), + .tie_lo_esd(), + .pad_a_esd_h(xresloop), + .xres_h_n(porb_h), + .disable_pullup_h(vss), // 0 = enable pull-up on reset pad + .enable_h(vdd), // Power-on-reset to the power-on-reset input?? + .en_vddio_sig_h(vss), // No idea. + .inp_sel_h(vss), // 1 = use filt_in_h else filter the pad input + .filt_in_h(vss), // Alternate input for glitch filter + .pullup_h(vss), // Pullup connection for alternate filter input + .enable_vddio(vdd1v8) + ); + + // Corner cells (These are overlay cells; it is not clear what is normally + // supposed to go under them.) + `ifndef TOP_ROUTING + s8iom0_corner_pad corner [3:0] ( + .vssio(vss), + .vddio(vdd), + .vddio_q(vddio_q), + .vssio_q(vssio_q), + .amuxbus_a(analog_a), + .amuxbus_b(analog_b), + .vssd(vss), + .vssa(vss), + .vswitch(vdd), + .vdda(vdd), + .vccd(vdd1v8), + .vcchib(vdd1v8) + ); +`endif + + mprj_io mprj_pads( + .vdd(vdd), + .vdd1v8(vdd1v8), + .vss(vss), + .vddio_q(vddio_q), + .vssio_q(vssio_q), + .analog_a(analog_a), + .analog_b(analog_b), + .io(mprj_io), + .io_out(mprj_io_out), + .oeb_n(mprj_io_oeb_n), + .hldh_n(mprj_io_hldh_n), + .enh(mprj_io_enh), + .inp_dis(mprj_io_inp_dis), + .ib_mode_sel(mprj_io_ib_mode_sel), + .analog_en(mprj_io_analog_en), + .analog_sel(mprj_io_analog_sel), + .analog_pol(mprj_io_analog_pol), + .dm(mprj_io_dm), + .io_in(mprj_io_in) + ); + +endmodule \ No newline at end of file
diff --git a/verilog/rtl/harness.v b/verilog/rtl/harness.v deleted file mode 100644 index b8403e1..0000000 --- a/verilog/rtl/harness.v +++ /dev/null
@@ -1,1303 +0,0 @@ -/*----------------------------------------------------------*/ -/* striVe, a raven/ravenna-like architecture in SkyWater s8 */ -/* */ -/* 1st edition, test of SkyWater s8 process */ -/* This version is missing all analog functionality, */ -/* including crystal oscillator, voltage regulator, and PLL */ -/* For simplicity, the pad arrangement of Raven has been */ -/* retained, even though many pads have no internal */ -/* connection. */ -/* */ -/* Copyright 2020 efabless, Inc. */ -/* Written by Tim Edwards, December 2019 */ -/* This file is open source hardware released under the */ -/* Apache 2.0 license. See file LICENSE. */ -/* */ -/*----------------------------------------------------------*/ - -`timescale 1 ns / 1 ps - -`define USE_OPENRAM -`define USE_PG_PIN -`define functional - -`ifdef SYNTH_OPENLANE - `include "../stubs/scs8hd_conb_1.v" - `include "../stubs/s8iom0s8.v" - `include "../stubs/power_pads_lib.v" -`else - - `ifndef LVS - `include "/ef/tech/SW/EFS8A/libs.ref/verilog/s8iom0s8/s8iom0s8.v" - `include "/ef/tech/SW/EFS8A/libs.ref/verilog/s8iom0s8/power_pads_lib.v" - `include "/ef/tech/SW/EFS8A/libs.ref/verilog/scs8hd/scs8hd.v" - - `include "lvlshiftdown.v" - `include "mgmt_soc.v" - `include "striVe_spi.v" - `include "digital_pll.v" - `include "striVe_clkrst.v" - `include "../ip/crossbar.v" - `include "../dv/dummy_slave.v" - - `endif -`endif - -`ifdef USE_OPENRAM - `include "sram_1rw1r_32_256_8_sky130.v" -`endif - -//`define TOP_ROUTING -`ifndef TOP_ROUTING - `define ABUTMENT_PINS \ - .amuxbus_a(analog_a),\ - .amuxbus_b(analog_b),\ - .vssa(vss),\ - .vdda(vdd),\ - .vswitch(vdd),\ - .vddio_q(vddio_q),\ - .vcchib(vdd1v8),\ - .vddio(vdd),\ - .vccd(vdd1v8),\ - .vssio(vss),\ - .vssd(vss),\ - .vssio_q(vssio_q), -`else - `define ABUTMENT_PINS -`endif - -// Crossbar Slaves -`ifndef SLAVE_ADR - `define SLAVE_ADR { \ - {8'hB0, {24{1'b0}}},\ - {8'hA0, {24{1'b0}}},\ - {8'h90, {24{1'b0}}},\ - {8'h80, {24{1'b0}}}\ - }\ -`endif - -`ifndef ADR_MASK - `define ADR_MASK { \ - {8'hFF, {24{1'b0}}}, \ - {8'hFF, {24{1'b0}}}, \ - {8'hFF, {24{1'b0}}}, \ - {8'hFF, {24{1'b0}}} \ - }\ -`endif - -`define NM 2 // Crossbar switch number of masters -`define NS 4 // Crossbar switch number of slaves -`define DW 32 -`define AW 32 - -module harness (vdd, vdd1v8, vss, gpio, xi, xo, adc0_in, adc1_in, adc_high, adc_low, - comp_inn, comp_inp, RSTB, ser_rx, ser_tx, irq, SDO, SDI, CSB, SCK, - xclk, flash_csb, flash_clk, flash_io0, flash_io1, flash_io2, flash_io3); - - inout vdd; - inout vdd1v8; - inout vss; - inout [15:0] gpio; - input xi; // CMOS clock input, not a crystal - output xo; // divide-by-16 clock output - input adc0_in; - input adc1_in; - input adc_high; - input adc_low; - input comp_inn; - input comp_inp; - input RSTB; // NOTE: Replaces analog_out pin from raven chip - input ser_rx; - output ser_tx; - input irq; - output SDO; - input SDI; - input CSB; - input SCK; - input xclk; - output flash_csb; - output flash_clk; - output flash_io0; - output flash_io1; - output flash_io2; - output flash_io3; - - wire [15:0] gpio_out_core; - wire [15:0] gpio_in_core; - wire [15:0] gpio_mode0_core; - wire [15:0] gpio_mode1_core; - wire [15:0] gpio_outenb_core; - wire [15:0] gpio_inenb_core; - - wire analog_a, analog_b; /* Placeholders for analog signals */ - - wire porb_h; - wire porb_l; - wire por_h; - wire por; - wire SCK_core; - wire SDI_core; - wire CSB_core; - wire SDO_core; - wire SDO_enb; - wire spi_ro_xtal_ena_core; - wire spi_ro_reg_ena_core; - wire spi_ro_pll_dco_ena_core; - wire [2:0] spi_ro_pll_sel_core; - wire [4:0] spi_ro_pll_div_core; - wire [25:0] spi_ro_pll_trim_core; - wire ext_clk_sel_core; - wire irq_spi_core; - wire ext_reset_core; - wire trap_core; - wire [11:0] spi_ro_mfgr_id_core; - wire [7:0] spi_ro_prod_id_core; - wire [3:0] spi_ro_mask_rev_core; - - // Instantiate power cells for VDD3V3 domain (8 total; 4 high clamps and - // 4 low clamps) - s8iom0_vdda_hvc_pad vdd3v3hclamp [1:0] ( - `ABUTMENT_PINS - .drn_hvc(), - .src_bdy_hvc() - ); - - s8iom0_vddio_hvc_pad vddiohclamp [1:0] ( - `ABUTMENT_PINS - .drn_hvc(), - .src_bdy_hvc() - ); - - - s8iom0_vdda_lvc_pad vdd3v3lclamp [3:0] ( - `ABUTMENT_PINS - .bdy2_b2b(), - .drn_lvc1(), - .drn_lvc2(), - .src_bdy_lvc1(), - .src_bdy_lvc2() - ); - - // Instantiate the core voltage supply (since it is not generated on-chip) - // (1.8V) (4 total, 2 high and 2 low clamps) - - s8iom0_vccd_hvc_pad vdd1v8hclamp [1:0] ( - `ABUTMENT_PINS - .drn_hvc(), - .src_bdy_hvc() - ); - - s8iom0_vccd_lvc_pad vdd1v8lclamp [1:0] ( - `ABUTMENT_PINS - .bdy2_b2b(), - .drn_lvc1(), - .drn_lvc2(), - .src_bdy_lvc1(), - .src_bdy_lvc2() - ); - - // Instantiate ground cells (7 total, 4 high clamps and 3 low clamps) - - s8iom0_vssa_hvc_pad vsshclamp [3:0] ( - `ABUTMENT_PINS - .drn_hvc(), - .src_bdy_hvc() - ); - - s8iom0_vssa_lvc_pad vssalclamp ( - `ABUTMENT_PINS - .bdy2_b2b(), - .drn_lvc1(), - .drn_lvc2(), - .src_bdy_lvc1(), - .src_bdy_lvc2() - ); - - s8iom0_vssd_lvc_pad vssdlclamp ( - `ABUTMENT_PINS - .bdy2_b2b(), - .drn_lvc1(), - .drn_lvc2(), - .src_bdy_lvc1(), - .src_bdy_lvc2() - ); - - s8iom0_vssio_lvc_pad vssiolclamp ( - `ABUTMENT_PINS - .bdy2_b2b(), - .drn_lvc1(), - .drn_lvc2(), - .src_bdy_lvc1(), - .src_bdy_lvc2() - ); - - wire [47:0] dm_all; - - assign dm_all = {gpio_mode1_core[15], gpio_mode1_core[15], gpio_mode0_core[15], - gpio_mode1_core[14], gpio_mode1_core[14], gpio_mode0_core[14], - gpio_mode1_core[13], gpio_mode1_core[13], gpio_mode0_core[13], - gpio_mode1_core[12], gpio_mode1_core[12], gpio_mode0_core[12], - gpio_mode1_core[11], gpio_mode1_core[11], gpio_mode0_core[11], - gpio_mode1_core[10], gpio_mode1_core[10], gpio_mode0_core[10], - gpio_mode1_core[9], gpio_mode1_core[9], gpio_mode0_core[9], - gpio_mode1_core[8], gpio_mode1_core[8], gpio_mode0_core[8], - gpio_mode1_core[7], gpio_mode1_core[7], gpio_mode0_core[7], - gpio_mode1_core[6], gpio_mode1_core[6], gpio_mode0_core[6], - gpio_mode1_core[5], gpio_mode1_core[5], gpio_mode0_core[5], - gpio_mode1_core[4], gpio_mode1_core[4], gpio_mode0_core[4], - gpio_mode1_core[3], gpio_mode1_core[3], gpio_mode0_core[3], - gpio_mode1_core[2], gpio_mode1_core[2], gpio_mode0_core[2], - gpio_mode1_core[1], gpio_mode1_core[1], gpio_mode0_core[1], - gpio_mode1_core[0], gpio_mode1_core[0], gpio_mode0_core[0]}; - - // GPIO pads - s8iom0_gpiov2_pad gpio_pad [15:0] ( - `ABUTMENT_PINS -`ifndef TOP_ROUTING - .pad(gpio), -`endif - .out(gpio_out_core), // Signal from core to pad - .oe_n(gpio_outenb_core), // Output enable (sense inverted) - .hld_h_n(vdd), // Hold signals during deep sleep (sense inverted) - .enable_h(porb_h), // Post-reset enable - .enable_inp_h(loopb0), // Input buffer state when disabled - .enable_vdda_h(porb_h), // - .enable_vswitch_h(vss), // - .enable_vddio(vdd1v8), // - .inp_dis(gpio_inenb_core), // Disable input buffer - .ib_mode_sel(vss), // - .vtrip_sel(vss), // - .slow(vss), // - .hld_ovr(vss), // - .analog_en(vss), // - .analog_sel(vss), // - .analog_pol(vss), // - .dm(dm_all), // (3 bits) Mode control - .pad_a_noesd_h(), // Direct pad connection - .pad_a_esd_0_h(), // Pad connection through 150 ohms - .pad_a_esd_1_h(), // Pad connection through 150 ohms - .in(gpio_in_core), // Signal from pad to core - .in_h(), // VDDA domain signal (unused) - .tie_hi_esd(), - .tie_lo_esd(loopb0) - ); - - s8iom0_gpiov2_pad xi_pad ( - `ABUTMENT_PINS -`ifndef TOP_ROUTING - .pad(xi), -`endif - .out(), // Signal from core to pad - .oe_n(vdd1v8), // Output enable (sense inverted) - .hld_h_n(vdd), // Hold - .enable_h(porb_h), // Enable - .enable_inp_h(loopb1), // Enable input buffer - .enable_vdda_h(porb_h), // - .enable_vswitch_h(vss), // - .enable_vddio(vdd1v8), // - .inp_dis(por), // Disable input buffer - .ib_mode_sel(vss), // - .vtrip_sel(vss), // - .slow(vss), // - .hld_ovr(vss), // - .analog_en(vss), // - .analog_sel(vss), // - .analog_pol(vss), // - .dm({vss, vss, vdd1v8}), // (3 bits) Mode control - .pad_a_noesd_h(), // Direct pad connection - .pad_a_esd_0_h(), // Pad connection through 150 ohms - .pad_a_esd_1_h(), // Pad connection through 150 ohms - .in(xi_core), // Signal from pad to core - .in_h(), - .tie_hi_esd(), - .tie_lo_esd(loopb1) - ); - - s8iom0_gpiov2_pad xo_pad ( - `ABUTMENT_PINS -`ifndef TOP_ROUTING - .pad(xo), -`endif - .out(pll_clk16), // Signal from core to pad - .oe_n(vss), // Output enable (sense inverted) - .hld_h_n(vdd), // Hold - .enable_h(porb_h), // Enable - .enable_inp_h(loopb2), // Enable input buffer - .enable_vdda_h(porb_h), // - .enable_vswitch_h(vss), // - .enable_vddio(vdd1v8), // - .inp_dis(vdd1v8), // Disable input buffer - .ib_mode_sel(vss), // - .vtrip_sel(vss), // - .slow(vss), // - .hld_ovr(vss), // - .analog_en(vss), // - .analog_sel(vss), // - .analog_pol(vss), // - .dm({vdd1v8, vdd1v8, vss}), // (3 bits) Mode control - .pad_a_noesd_h(), // Direct pad connection - .pad_a_esd_0_h(), // Pad connection through 150 ohms - .pad_a_esd_1_h(), // Pad connection through 150 ohms - .in(), // Signal from pad to core - .in_h(), - .tie_hi_esd(), - .tie_lo_esd(loopb2) - ); - - s8iom0_gpiov2_pad adc0_in_pad ( - `ABUTMENT_PINS -`ifndef TOP_ROUTING - .pad(adc0_in), -`endif - .out(vss), // Signal from core to pad - .oe_n(vdd1v8), // Output enable (sense inverted) - .hld_h_n(vdd), // Hold - .enable_h(porb_h), // Enable - .enable_inp_h(loopb3), // Enable input buffer - .enable_vdda_h(porb_h), // - .enable_vswitch_h(vss), // - .enable_vddio(vdd1v8), // - .inp_dis(vdd1v8), // Disable input buffer - .ib_mode_sel(vss), // - .vtrip_sel(vss), // - .slow(vss), // - .hld_ovr(vss), // - .analog_en(vdd1v8), // - .analog_sel(vss), // - .analog_pol(vss), // - .dm({vss, vss, vss}), // (3 bits) Mode control - .pad_a_noesd_h(), // Direct pad connection - .pad_a_esd_0_h(), // Pad connection through 150 ohms - .pad_a_esd_1_h(), // Pad connection through 150 ohms - .in(), // Signal from pad to core - .in_h(), - .tie_hi_esd(), - .tie_lo_esd() - ); - - s8iom0_gpiov2_pad adc1_in_pad ( - `ABUTMENT_PINS -`ifndef TOP_ROUTING - .pad(adc1_in), -`endif - .pad_a_noesd_h(), // Direct pad connection - .out(vss), // Signal from core to pad - .oe_n(vdd1v8), // Output enable (sense inverted) - .hld_h_n(vdd), // Hold - .enable_h(porb_h), // Enable - .enable_inp_h(loopb4), // Enable input buffer - .enable_vdda_h(porb_h), // - .enable_vswitch_h(vss), // - .enable_vddio(vdd1v8), // - .inp_dis(vdd1v8), // Disable input buffer - .ib_mode_sel(vss), // - .vtrip_sel(vss), // - .slow(vss), // - .hld_ovr(vss), // - .analog_en(vdd1v8), // - .analog_sel(vss), // - .analog_pol(vss), // - .dm({vss, vss, vss}), // (3 bits) Mode control - .pad_a_esd_0_h(), // Pad connection through 150 ohms - .pad_a_esd_1_h(), // Pad connection through 150 ohms - .in(), // Signal from pad to core - .in_h(), - .tie_hi_esd(), - .tie_lo_esd() - ); - - s8iom0_gpiov2_pad adc_high_pad ( - `ABUTMENT_PINS -`ifndef TOP_ROUTING - .pad(adc_high), -`endif - .out(vss), // Signal from core to pad - .oe_n(vdd1v8), // Output enable (sense inverted) - .hld_h_n(vdd), // Hold - .enable_h(porb_h), // Enable - .enable_inp_h(loopb5), // Enable input buffer - .enable_vdda_h(porb_h), // - .enable_vswitch_h(vss), // - .enable_vddio(vdd1v8), // - .inp_dis(vdd1v8), // Disable input buffer - .ib_mode_sel(vss), // - .vtrip_sel(vss), // - .slow(vss), // - .hld_ovr(vss), // - .analog_en(vdd1v8), // - .analog_sel(vdd1v8), // - .analog_pol(vdd1v8), // - .dm({vss, vss, vss}), // (3 bits) Mode control - .pad_a_noesd_h(), // Direct pad connection - .pad_a_esd_0_h(), // Pad connection through 150 ohms - .pad_a_esd_1_h(), // Pad connection through 150 ohms - .in(), // Signal from pad to core - .in_h(), - .tie_hi_esd(), - .tie_lo_esd() - ); - - s8iom0_gpiov2_pad adc_low_pad ( - `ABUTMENT_PINS -`ifndef TOP_ROUTING - .pad(adc_low), -`endif - .out(vss), // Signal from core to pad - .oe_n(vdd1v8), // Output enable (sense inverted) - .hld_h_n(vdd), // Hold - .enable_h(porb_h), // Enable - .enable_inp_h(loopb6), // Enable input buffer - .enable_vdda_h(porb_h), // - .enable_vswitch_h(vss), // - .enable_vddio(vdd1v8), // - .inp_dis(vdd1v8), // Disable input buffer - .ib_mode_sel(vss), // - .vtrip_sel(vss), // - .slow(vss), // - .hld_ovr(vss), // - .analog_en(vdd1v8), // - .analog_sel(vss), // - .analog_pol(vss), // - .dm({vss, vss, vss}), // (3 bits) Mode control - .pad_a_noesd_h(), // Direct pad connection - .pad_a_esd_0_h(), // Pad connection through 150 ohms - .pad_a_esd_1_h(), // Pad connection through 150 ohms - .in(), // Signal from pad to core - .in_h(), - .tie_hi_esd(), - .tie_lo_esd() - ); - - s8iom0_gpiov2_pad comp_inn_pad ( - `ABUTMENT_PINS -`ifndef TOP_ROUTING - .pad(comp_inn), -`endif - .out(vss), // Signal from core to pad - .oe_n(vdd1v8), // Output enable (sense inverted) - .hld_h_n(vdd), // Hold - .enable_h(porb_h), // Enable - .enable_inp_h(loopb7), // Enable input buffer - .enable_vdda_h(porb_h), // - .enable_vswitch_h(vss), // - .enable_vddio(vdd1v8), // - .inp_dis(vdd1v8), // Disable input buffer - .ib_mode_sel(vss), // - .vtrip_sel(vss), // - .slow(vss), // - .hld_ovr(vss), // - .analog_en(vdd1v8), // - .analog_sel(vss), // - .analog_pol(vss), // - .dm({vss, vss, vss}), // (3 bits) Mode control - .pad_a_noesd_h(), // Direct pad connection - .pad_a_esd_0_h(), // Pad connection through 150 ohms - .pad_a_esd_1_h(), // Pad connection through 150 ohms - .in(), // Signal from pad to core - .in_h(), - .tie_hi_esd(), - .tie_lo_esd() - ); - - s8iom0_gpiov2_pad comp_inp_pad ( - `ABUTMENT_PINS -`ifndef TOP_ROUTING - .pad(comp_inp), -`endif - .out(vss), // Signal from core to pad - .oe_n(vdd1v8), // Output enable (sense inverted) - .hld_h_n(vdd), // Hold - .enable_h(porb_h), // Enable - .enable_inp_h(loopb8), // Enable input buffer - .enable_vdda_h(porb_h), // - .enable_vswitch_h(vss), // - .enable_vddio(vdd1v8), // - .inp_dis(vdd1v8), // Disable input buffer - .ib_mode_sel(vss), // - .vtrip_sel(vss), // - .slow(vss), // - .hld_ovr(vss), // - .analog_en(vdd1v8), // - .analog_sel(vdd1v8), // - .analog_pol(vss), // - .dm({vss, vss, vss}), // (3 bits) Mode control - .pad_a_noesd_h(), // Direct pad connection - .pad_a_esd_0_h(), // Pad connection through 150 ohms - .pad_a_esd_1_h(), // Pad connection through 150 ohms - .in(), // Signal from pad to core - .in_h(), - .tie_hi_esd(), - .tie_lo_esd() - ); - - // NOTE: The analog_out pad from the raven chip has been replaced by - // the digital reset input RSTB on striVe due to the lack of an on-board - // power-on-reset circuit. The XRES pad is used for providing a glitch- - // free reset. - - s8iom0s8_top_xres4v2 RSTB_pad ( - `ABUTMENT_PINS -`ifndef TOP_ROUTING - .pad(RSTB), -`endif - .tie_weak_hi_h(xresloop), // Loop-back connection to pad through pad_a_esd_h - .tie_hi_esd(), - .tie_lo_esd(), - .pad_a_esd_h(xresloop), - .xres_h_n(porb_h), - .disable_pullup_h(vss), // 0 = enable pull-up on reset pad - .enable_h(vdd), // Power-on-reset to the power-on-reset input?? - .en_vddio_sig_h(vss), // No idea. - .inp_sel_h(vss), // 1 = use filt_in_h else filter the pad input - .filt_in_h(vss), // Alternate input for glitch filter - .pullup_h(vss), // Pullup connection for alternate filter input - .enable_vddio(vdd1v8) - ); - - s8iom0_gpiov2_pad irq_pad ( - `ABUTMENT_PINS -`ifndef TOP_ROUTING - .pad(irq), -`endif - .out(vss), // Signal from core to pad - .oe_n(vdd1v8), // Output enable (sense inverted) - .hld_h_n(vdd), // Hold - .enable_h(porb_h), // Enable - .enable_inp_h(loopb10), // Enable input buffer - .enable_vdda_h(porb_h), // - .enable_vswitch_h(vss), // - .enable_vddio(vdd1v8), // - .inp_dis(por), // Disable input buffer - .ib_mode_sel(vss), // - .vtrip_sel(vss), // - .slow(vss), // - .hld_ovr(vss), // - .analog_en(vss), // - .analog_sel(vss), // - .analog_pol(vss), // - .dm({vss, vss, vdd1v8}), // (3 bits) Mode control - .pad_a_noesd_h(), // Direct pad connection - .pad_a_esd_0_h(), // Pad connection through 150 ohms - .pad_a_esd_1_h(), // Pad connection through 150 ohms - .in(irq_pin_core), // Signal from pad to core - .in_h(), - .tie_hi_esd(), - .tie_lo_esd(loopb10) - ); - - s8iom0_gpiov2_pad SDO_pad ( - `ABUTMENT_PINS -`ifndef TOP_ROUTING - .pad(SDO), -`endif - .out(SDO_core), // Signal from core to pad - .oe_n(SDO_enb), // Output enable (sense inverted) - .hld_h_n(vdd), // Hold - .enable_h(porb_h), // Enable - .enable_inp_h(loopb11), // Enable input buffer - .enable_vdda_h(porb_h), // - .enable_vswitch_h(vss), // - .enable_vddio(vdd1v8), // - .inp_dis(vdd1v8), // Disable input buffer - .ib_mode_sel(vss), // - .vtrip_sel(vss), // - .slow(vss), // - .hld_ovr(vss), // - .analog_en(vss), // - .analog_sel(vss), // - .analog_pol(vss), // - .dm({vdd1v8, vdd1v8, vss}), // (3 bits) Mode control - .pad_a_noesd_h(), // Direct pad connection - .pad_a_esd_0_h(), // Pad connection through 150 ohms - .pad_a_esd_1_h(), // Pad connection through 150 ohms - .in(), // Signal from pad to core - .in_h(), - .tie_hi_esd(), - .tie_lo_esd(loopb11) - ); - - s8iom0_gpiov2_pad SDI_pad ( - `ABUTMENT_PINS -`ifndef TOP_ROUTING - .pad(SDI), -`endif - .out(vss), // Signal from core to pad - .oe_n(vdd1v8), // Output enable (sense inverted) - .hld_h_n(vdd), // Hold - .enable_h(porb_h), // Enable - .enable_inp_h(loopb12), // Enable input buffer - .enable_vdda_h(porb_h), // - .enable_vswitch_h(vss), // - .enable_vddio(vdd1v8), // - .inp_dis(por), // Disable input buffer - .ib_mode_sel(vss), // - .vtrip_sel(vss), // - .slow(vss), // - .hld_ovr(vss), // - .analog_en(vss), // - .analog_sel(vss), // - .analog_pol(vss), // - .dm({vss, vss, vdd1v8}), // (3 bits) Mode control - .pad_a_noesd_h(), // Direct pad connection - .pad_a_esd_0_h(), // Pad connection through 150 ohms - .pad_a_esd_1_h(), // Pad connection through 150 ohms - .in(SDI_core), // Signal from pad to core - .in_h(SDI_core_h), - .tie_hi_esd(), - .tie_lo_esd() - ); - - s8iom0_gpiov2_pad CSB_pad ( - `ABUTMENT_PINS -`ifndef TOP_ROUTING - .pad(CSB), -`endif - .out(vss), // Signal from core to pad - .oe_n(vdd1v8), // Output enable (sense inverted) - .hld_h_n(vdd), // Hold - .enable_h(porb_h), // Enable - .enable_inp_h(loopb13), // Enable input buffer - .enable_vdda_h(porb_h), // - .enable_vswitch_h(vss), // - .enable_vddio(vdd1v8), // - .inp_dis(por), // Disable input buffer - .ib_mode_sel(vss), // - .vtrip_sel(vss), // - .slow(vss), // - .hld_ovr(vss), // - .analog_en(vss), // - .analog_sel(vss), // - .analog_pol(vss), // - .dm({vss, vss, vdd1v8}), // (3 bits) Mode control - .pad_a_noesd_h(), // Direct pad connection - .pad_a_esd_0_h(), // Pad connection through 150 ohms - .pad_a_esd_1_h(), // Pad connection through 150 ohms - .in(CSB_core), // Signal from pad to core - .in_h(CSB_core_h), - .tie_hi_esd(), - .tie_lo_esd(loopb13) - ); - - s8iom0_gpiov2_pad SCK_pad ( - `ABUTMENT_PINS -`ifndef TOP_ROUTING - .pad(SCK), -`endif - .out(vss), // Signal from core to pad - .oe_n(vdd1v8), // Output enable (sense inverted) - .hld_h_n(vdd), // Hold - .enable_h(porb_h), // Enable - .enable_inp_h(loopb14), // Enable input buffer - .enable_vdda_h(porb_h), // - .enable_vswitch_h(vss), // - .enable_vddio(vdd1v8), // - .inp_dis(por), // Disable input buffer - .ib_mode_sel(vss), // - .vtrip_sel(vss), // - .slow(vss), // - .hld_ovr(vss), // - .analog_en(vss), // - .analog_sel(vss), // - .analog_pol(vss), // - .dm({vss, vss, vdd1v8}), // (3 bits) Mode control - .pad_a_noesd_h(), // Direct pad connection - .pad_a_esd_0_h(), // Pad connection through 150 ohms - .pad_a_esd_1_h(), // Pad connection through 150 ohms - .in(SCK_core), // Signal from pad to core - .in_h(SCK_core_h), // Signal in vdda domain (3.3V) - .tie_hi_esd(), - .tie_lo_esd(loopb14) - ); - - s8iom0_gpiov2_pad xclk_pad ( - `ABUTMENT_PINS -`ifndef TOP_ROUTING - .pad(xclk), -`endif - .out(vss), // Signal from core to pad - .oe_n(vdd1v8), // Output enable (sense inverted) - .hld_h_n(vdd), // Hold - .enable_h(porb_h), // Enable - .enable_inp_h(loopb15), // Enable input buffer - .enable_vdda_h(porb_h), // - .enable_vswitch_h(vss), // - .enable_vddio(vdd1v8), // - .inp_dis(por), // Disable input buffer - .ib_mode_sel(vss), // - .vtrip_sel(vss), // - .slow(vss), // - .hld_ovr(vss), // - .analog_en(vss), // - .analog_sel(vss), // - .analog_pol(vss), // - .dm({vss, vss, vdd1v8}), // (3 bits) Mode control - .pad_a_noesd_h(), // Direct pad connection - .pad_a_esd_0_h(), // Pad connection through 150 ohms - .pad_a_esd_1_h(), // Pad connection through 150 ohms - .in(ext_clk_core), // Signal from pad to core - .in_h(), - .tie_hi_esd(), - .tie_lo_esd(loopb15) - ); - - // assign flash_csb = (input) ? - s8iom0_gpiov2_pad flash_csb_pad ( - `ABUTMENT_PINS -`ifndef TOP_ROUTING - .pad(flash_csb), -`endif - .out(flash_csb_core), // Signal from core to pad - .oe_n(flash_csb_oeb_core), // Output enable (sense inverted) - .hld_h_n(vdd), // Hold - .enable_h(porb_h), // Enable - .enable_inp_h(loopb16), // Enable input buffer - .enable_vdda_h(porb_h), // - .enable_vswitch_h(vss), // - .enable_vddio(vdd1v8), // - .inp_dis(flash_csb_ieb_core), // Disable input buffer - .ib_mode_sel(vss), // - .vtrip_sel(vss), // - .slow(vss), // - .hld_ovr(vss), // - .analog_en(vss), // - .analog_sel(vss), // - .analog_pol(vss), // - .dm({vdd1v8, vdd1v8, vss}), // (3 bits) Mode control - .pad_a_noesd_h(), // Direct pad connection - .pad_a_esd_0_h(), // Pad connection through 150 ohms - .pad_a_esd_1_h(), // Pad connection through 150 ohms - .in(), // Signal from pad to core - .in_h(), - .tie_hi_esd(), - .tie_lo_esd() - ); - - s8iom0_gpiov2_pad flash_clk_pad ( - `ABUTMENT_PINS -`ifndef TOP_ROUTING - .pad(flash_clk), -`endif - .out(flash_clk_core), // Signal from core to pad - .oe_n(flash_clk_oeb_core), // Output enable (sense inverted) - .hld_h_n(vdd), // Hold - .enable_h(porb_h), // Enable - .enable_inp_h(loopb17), // Enable input buffer - .enable_vdda_h(porb_h), // - .enable_vswitch_h(vss), // - .enable_vddio(vdd1v8), // - .inp_dis(flash_clk_ieb_core), // Disable input buffer - .ib_mode_sel(vss), // - .vtrip_sel(vss), // - .slow(vss), // - .hld_ovr(vss), // - .analog_en(vss), // - .analog_sel(vss), // - .analog_pol(vss), // - .dm({vdd1v8, vdd1v8, vss}), // (3 bits) Mode control - .pad_a_noesd_h(), // Direct pad connection - .pad_a_esd_0_h(), // Pad connection through 150 ohms - .pad_a_esd_1_h(), // Pad connection through 150 ohms - .in(), // Signal from pad to core - .in_h(), - .tie_hi_esd(), - .tie_lo_esd() - ); - - s8iom0_gpiov2_pad flash_io0_pad ( - `ABUTMENT_PINS -`ifndef TOP_ROUTING - .pad(flash_io0), -`endif - .out(flash_io0_do_core), // Signal from core to pad - .oe_n(flash_io0_oeb_core), // Output enable (sense inverted) - .hld_h_n(vdd), // Hold - .enable_h(porb_h), // Enable - .enable_inp_h(loopb18), // Enable input buffer - .enable_vdda_h(porb_h), // - .enable_vswitch_h(vss), // - .enable_vddio(vdd1v8), // - .inp_dis(flash_io0_ieb_core), // Disable input buffer - .ib_mode_sel(vss), // - .vtrip_sel(vss), // - .slow(vss), // - .hld_ovr(vss), // - .analog_en(vss), // - .analog_sel(vss), // - .analog_pol(vss), // - .dm({flash_io0_ieb_core, flash_io0_ieb_core, flash_io0_oeb_core}), // (3 bits) Mode control - .pad_a_noesd_h(), // Direct pad connection - .pad_a_esd_0_h(), // Pad connection through 150 ohms - .pad_a_esd_1_h(), // Pad connection through 150 ohms - .in(flash_io0_di_core), // Signal from pad to core - .in_h(), - .tie_hi_esd(), - .tie_lo_esd(loopb18) - ); - - s8iom0_gpiov2_pad flash_io1_pad ( - `ABUTMENT_PINS -`ifndef TOP_ROUTING - .pad(flash_io1), -`endif - .out(flash_io1_do_core), // Signal from core to pad - .oe_n(flash_io1_oeb_core), // Output enable (sense inverted) - .hld_h_n(vdd), // Hold - .enable_h(porb_h), // Enable - .enable_inp_h(loopb19), // Enable input buffer - .enable_vdda_h(porb_h), // - .enable_vswitch_h(vss), // - .enable_vddio(vdd1v8), // - .inp_dis(flash_io1_ieb_core), // Disable input buffer - .ib_mode_sel(vss), // - .vtrip_sel(vss), // - .slow(vss), // - .hld_ovr(vss), // - .analog_en(vss), // - .analog_sel(vss), // - .analog_pol(vss), // - .dm({flash_io1_ieb_core, flash_io1_ieb_core, flash_io1_oeb_core}), // (3 bits) Mode control - .pad_a_noesd_h(), // Direct pad connection - .pad_a_esd_0_h(), // Pad connection through 150 ohms - .pad_a_esd_1_h(), // Pad connection through 150 ohms - .in(flash_io1_di_core), // Signal from pad to core - .in_h(), - .tie_hi_esd(), - .tie_lo_esd(loopb19) - ); - - s8iom0_gpiov2_pad flash_io2_pad ( - `ABUTMENT_PINS -`ifndef TOP_ROUTING - .pad(flash_io2), -`endif - .out(flash_io2_do_core), // Signal from core to pad - .oe_n(flash_io2_oeb_core), // Output enable (sense inverted) - .hld_h_n(vdd), // Hold - .enable_h(porb_h), // Enable - .enable_inp_h(loopb20), // Enable input buffer - .enable_vdda_h(porb_h), // - .enable_vswitch_h(vss), // - .enable_vddio(vdd1v8), // - .inp_dis(flash_io2_ieb_core), // Disable input buffer - .ib_mode_sel(vss), // - .vtrip_sel(vss), // - .slow(vss), // - .hld_ovr(vss), // - .analog_en(vss), // - .analog_sel(vss), // - .analog_pol(vss), // - .dm({flash_io2_ieb_core, flash_io2_ieb_core, flash_io2_oeb_core}), // (3 bits) Mode control - .pad_a_noesd_h(), // Direct pad connection - .pad_a_esd_0_h(), // Pad connection through 150 ohms - .pad_a_esd_1_h(), // Pad connection through 150 ohms - .in(flash_io2_di_core), // Signal from pad to core - .in_h(), - .tie_hi_esd(), - .tie_lo_esd(loopb20) - ); - - s8iom0_gpiov2_pad flash_io3_pad ( - `ABUTMENT_PINS -`ifndef TOP_ROUTING - .pad(flash_io3), -`endif - .out(flash_io3_do_core), // Signal from core to pad - .oe_n(flash_io3_oeb_core), // Output enable (sense inverted) - .hld_h_n(vdd), // Hold - .enable_h(porb_h), // Enable - .enable_inp_h(loopb21), // Enable input buffer - .enable_vdda_h(porb_h), // - .enable_vswitch_h(vss), // - .enable_vddio(vdd1v8), // - .inp_dis(flash_io3_ieb_core), // Disable input buffer - .ib_mode_sel(vss), // - .vtrip_sel(vss), // - .slow(vss), // - .hld_ovr(vss), // - .analog_en(vss), // - .analog_sel(vss), // - .analog_pol(vss), // - .dm({flash_io3_ieb_core, flash_io3_ieb_core, flash_io3_oeb_core}), // (3 bits) Mode control - .pad_a_noesd_h(), // Direct pad connection - .pad_a_esd_0_h(), // Pad connection through 150 ohms - .pad_a_esd_1_h(), // Pad connection through 150 ohms - .in(flash_io3_di_core), // Signal from pad to core - .in_h(), - .tie_hi_esd(), - .tie_lo_esd(loopb21) - ); - - // Instantiate GPIO overvoltage (I2C) compliant cell - // (Use this for ser_rx and ser_tx; no reason other than testing - // the use of the cell.) (Might be worth adding in the I2C IP from - // ravenna just to test on a proper I2C channel.) - - s8iom0s8_top_gpio_ovtv2 ser_rx_pad ( - `ABUTMENT_PINS -`ifndef TOP_ROUTING - .pad(ser_rx), -`endif - .out(vss), - .oe_n(vdd1v8), - .hld_h_n(vdd), - .enable_h(porb_h), - .enable_inp_h(loopb22), - .enable_vdda_h(porb_h), - .enable_vddio(vdd1v8), - .enable_vswitch_h(vss), - .inp_dis(por), - .vtrip_sel(vss), - .hys_trim(vdd1v8), - .slow(vss), - .slew_ctl({vss, vss}), // 2 bits - .hld_ovr(vss), - .analog_en(vss), - .analog_sel(vss), - .analog_pol(vss), - .dm({vss, vss, vdd1v8}), // 3 bits - .ib_mode_sel({vss, vss}), // 2 bits - .vinref(vdd1v8), - .pad_a_noesd_h(), - .pad_a_esd_0_h(), - .pad_a_esd_1_h(), - .in(ser_rx_core), - .in_h(), - .tie_hi_esd(), - .tie_lo_esd() - ); - - s8iom0s8_top_gpio_ovtv2 ser_tx_pad ( - `ABUTMENT_PINS -`ifndef TOP_ROUTING - .pad(ser_tx), -`endif - .out(ser_tx_core), - .oe_n(vss), - .hld_h_n(vdd), - .enable_h(porb_h), - .enable_inp_h(loopb23), - .enable_vdda_h(porb_h), - .enable_vddio(vdd1v8), - .enable_vswitch_h(vss), - .inp_dis(vdd1v8), - .vtrip_sel(vss), - .hys_trim(vdd1v8), - .slow(vss), - .slew_ctl({vss, vss}), // 2 bits - .hld_ovr(vss), - .analog_en(vss), - .analog_sel(vss), - .analog_pol(vss), - .dm({vdd1v8, vdd1v8, vss}), // 3 bits - .ib_mode_sel({vss, vss}), // 2 bits - .vinref(vdd1v8), - .pad_a_noesd_h(), - .pad_a_esd_0_h(), - .pad_a_esd_1_h(), - .in(), - .in_h(), - .tie_hi_esd(), - .tie_lo_esd() - ); - - // Corner cells (These are overlay cells; it is not clear what is normally - // supposed to go under them.) - `ifndef TOP_ROUTING - s8iom0_corner_pad corner [3:0] ( - .vssio(vss), - .vddio(vdd), - .vddio_q(vddio_q), - .vssio_q(vssio_q), - .amuxbus_a(analog_a), - .amuxbus_b(analog_b), - .vssd(vss), - .vssa(vss), - .vswitch(vdd), - .vdda(vdd), - .vccd(vdd1v8), - .vcchib(vdd1v8) - //`ABUTMENT_PINS - ); -`endif - - // SoC core - wire [9:0] adc0_data_core; - wire [1:0] adc0_inputsrc_core; - wire [9:0] adc1_data_core; - wire [1:0] adc1_inputsrc_core; - wire [9:0] dac_value_core; - wire [1:0] comp_ninputsrc_core; - wire [1:0] comp_pinputsrc_core; - wire [7:0] spi_ro_config_core; - - wire xbar_cyc_o_core; - wire xbar_stb_o_core; - wire xbar_we_o_core; - wire [3:0] xbar_sel_o_core; - wire [31:0] xbar_adr_o_core; - wire [31:0] xbar_dat_o_core; - wire xbar_ack_i_core; - wire [31:0] xbar_dat_i_core; - - wire striVe_clk, striVe_rstn; - - striVe_clkrst clkrst( - `ifdef LVS - .vdd1v8(vdd1v8), - .vss(vss), - `endif - .ext_clk_sel(ext_clk_sel_core), - .ext_clk(ext_clk_core), - .pll_clk(pll_clk_core), - .reset(por), - .ext_reset(ext_reset_core), - .clk(striVe_clk), - .resetn(striVe_rstn) - ); - - mgmt_soc core ( - `ifdef LVS - .vdd1v8(vdd1v8), - .vss(vss), - `endif - .pll_clk(pll_clk_core), - .ext_clk(ext_clk_core), - .ext_clk_sel(ext_clk_sel_core), - .clk(striVe_clk), - .resetn(striVe_rstn), - .gpio_out_pad(gpio_out_core), - .gpio_in_pad(gpio_in_core), - .gpio_mode0_pad(gpio_mode0_core), - .gpio_mode1_pad(gpio_mode1_core), - .gpio_outenb_pad(gpio_outenb_core), - .gpio_inenb_pad(gpio_inenb_core), - .adc0_ena(adc0_ena_core), - .adc0_convert(adc0_convert_core), - .adc0_data(adc0_data_core), - .adc0_done(adc0_done_core), - .adc0_clk(adc0_clk_core), - .adc0_inputsrc(adc0_inputsrc_core), - .adc1_ena(adc1_ena_core), - .adc1_convert(adc1_convert_core), - .adc1_clk(adc1_clk_core), - .adc1_inputsrc(adc1_inputsrc_core), - .adc1_data(adc1_data_core), - .adc1_done(adc1_done_core), - .xtal_in(xtal_in_core), - .comp_in(comp_in_core), - .spi_sck(SCK_core), - .spi_ro_config(spi_ro_config_core), - .spi_ro_xtal_ena(spi_ro_xtal_ena_core), - .spi_ro_reg_ena(spi_ro_reg_ena_core), - .spi_ro_pll_dco_ena(spi_ro_pll_dco_ena_core), - .spi_ro_pll_div(spi_ro_pll_div_core), - .spi_ro_pll_sel(spi_ro_pll_sel_core), - .spi_ro_pll_trim(spi_ro_pll_trim_core), - .spi_ro_mfgr_id(spi_ro_mfgr_id_core), - .spi_ro_prod_id(spi_ro_prod_id_core), - .spi_ro_mask_rev(spi_ro_mask_rev_core), - .ser_tx(ser_tx_core), - .ser_rx(ser_rx_core), - .irq_pin(irq_pin_core), - .irq_spi(irq_spi_core), - .trap(trap_core), - .flash_csb(flash_csb_core), - .flash_clk(flash_clk_core), - .flash_csb_oeb(flash_csb_oeb_core), - .flash_clk_oeb(flash_clk_oeb_core), - .flash_io0_oeb(flash_io0_oeb_core), - .flash_io1_oeb(flash_io1_oeb_core), - .flash_io2_oeb(flash_io2_oeb_core), - .flash_io3_oeb(flash_io3_oeb_core), - .flash_csb_ieb(flash_csb_ieb_core), - .flash_clk_ieb(flash_clk_ieb_core), - .flash_io0_ieb(flash_io0_ieb_core), - .flash_io1_ieb(flash_io1_ieb_core), - .flash_io2_ieb(flash_io2_ieb_core), - .flash_io3_ieb(flash_io3_ieb_core), - .flash_io0_do(flash_io0_do_core), - .flash_io1_do(flash_io1_do_core), - .flash_io2_do(flash_io2_do_core), - .flash_io3_do(flash_io3_do_core), - .flash_io0_di(flash_io0_di_core), - .flash_io1_di(flash_io1_di_core), - .flash_io2_di(flash_io2_di_core), - .flash_io3_di(flash_io3_di_core), - .xbar_cyc_o(xbar_cyc_o_core), - .xbar_stb_o(xbar_stb_o_core), - .xbar_we_o (xbar_we_o_core), - .xbar_sel_o(xbar_sel_o_core), - .xbar_adr_o(xbar_adr_o_core), - .xbar_dat_o(xbar_dat_o_core), - .xbar_ack_i(xbar_ack_i_core), - .xbar_dat_i(xbar_dat_i_core) - ); - - // Mega-Project - wire mega_cyc_o; - wire mega_stb_o; - wire mega_we_o; - wire [3:0] mega_sel_o; - wire [31:0] mega_adr_o; - wire [31:0] mega_dat_o; - wire mega_ack_i; - wire [31:0] mega_dat_i; - - // Masters interface - wire [`NM-1:0] wbm_cyc_i; - wire [`NM-1:0] wbm_stb_i; - wire [`NM-1:0] wbm_we_i; - wire [(`NM*(`DW/8))-1:0] wbm_sel_i; - wire [(`NM*`AW)-1:0] wbm_adr_i; - wire [(`NM*`DW)-1:0] wbm_dat_i; - - wire [`NM-1:0] wbm_ack_o; - wire [(`NM*`DW)-1:0] wbm_dat_o; - - // Slaves interfaces - wire [`NS-1:0] wbs_ack_o; - wire [(`NS*`DW)-1:0] wbs_dat_i; - wire [`NS-1:0] wbs_cyc_o; - wire [`NS-1:0] wbs_stb_o; - wire [`NS-1:0] wbs_we_o; - wire [(`NS*(`DW/8))-1:0] wbs_sel_o; - wire [(`NS*`AW)-1:0] wbs_adr_o; - wire [(`NS*`DW)-1:0] wbs_dat_o; - - assign wbm_cyc_i = {mega_cyc_o, xbar_cyc_o_core}; - assign wbm_stb_i = {mega_stb_o, xbar_stb_o_core}; - assign wbm_we_i = {mega_we_o , xbar_we_o_core}; - assign wbm_sel_i = {mega_sel_o, xbar_sel_o_core}; - assign wbm_adr_i = {mega_adr_o, xbar_adr_o_core}; - assign wbm_dat_i = {mega_dat_o, xbar_dat_o_core}; - - assign xbar_ack_i_core = wbm_ack_o[0]; - assign mega_ack_i = wbm_ack_o[1]; - assign xbar_dat_i_core = wbm_dat_o[`DW-1:0]; - assign mega_dat_i = wbm_dat_o[`DW*2-1:`DW]; - - // Instantiate four dummy slaves for testing (TO-BE-REMOVED) - dummy_slave dummy_slaves [`NS-1:0]( - .wb_clk_i({`NS{striVe_clk}}), - .wb_rst_i({`NS{~striVe_rstn}}), - .wb_stb_i(wbs_stb_o), - .wb_cyc_i(wbs_cyc_o), - .wb_we_i(wbs_we_o), - .wb_sel_i(wbs_sel_o), - .wb_adr_i(wbs_adr_o), - .wb_dat_i(wbs_dat_i), - .wb_dat_o(wbs_dat_o), - .wb_ack_o(wbs_ack_o) - ); - // Crossbar Switch - wb_xbar #( - .NM(`NM), - .NS(`NS), - .AW(`AW), - .DW(`DW), - .SLAVE_ADR(`SLAVE_ADR), - .ADR_MASK(`ADR_MASK) - ) - wb_xbar( - .wb_clk_i(striVe_clk), - .wb_rst_i(~striVe_rstn), - - // Masters interface - .wbm_cyc_i(wbm_cyc_i), - .wbm_stb_i(wbm_stb_i), - .wbm_we_i (wbm_we_i), - .wbm_sel_i(wbm_sel_i), - .wbm_adr_i(wbm_adr_i), - .wbm_dat_i(wbm_dat_i), - .wbm_ack_o(wbm_ack_o), - .wbm_dat_o(wbm_dat_o), - - // Slaves interfaces - .wbs_ack_i(wbs_ack_o), - .wbs_dat_i(wbs_dat_o), - .wbs_cyc_o(wbs_cyc_o), - .wbs_stb_o(wbs_stb_o), - .wbs_we_o (wbs_we_o), - .wbs_sel_o(wbs_sel_o), - .wbs_adr_o(wbs_adr_o), - .wbs_dat_o(wbs_dat_i) - ); - - // For the mask revision input, use an array of digital constant logic cells - wire [3:0] mask_rev; - wire [3:0] no_connect; - scs8hd_conb_1 mask_rev_value [3:0] ( - `ifdef LVS - .vpwr(vdd1v8), - .vpb(vdd1v8), - .vnb(vss), - .vgnd(vss), - `endif - .HI({no_connect[3:1], mask_rev[0]}), - .LO({mask_rev[3:1], no_connect[0]}) - ); - - // Housekeeping SPI at 1.8V. - - striVe_spi housekeeping ( - `ifdef LVS - .vdd(vdd1v8), - .vss(vss), - `endif - .RSTB(porb_l), - .SCK(SCK_core), - .SDI(SDI_core), - .CSB(CSB_core), - .SDO(SDO_core), - .sdo_enb(SDO_enb), - - .xtal_ena(spi_ro_xtal_ena_core), - .reg_ena(spi_ro_reg_ena_core), - .pll_dco_ena(spi_ro_pll_dco_ena_core), - .pll_sel(spi_ro_pll_sel_core), - .pll_div(spi_ro_pll_div_core), - .pll_trim(spi_ro_pll_trim_core), - .pll_bypass(ext_clk_sel_core), - .irq(irq_spi_core), - .RST(por), - .reset(ext_reset_core), - .trap(trap_core), - .mfgr_id(spi_ro_mfgr_id_core), - .prod_id(spi_ro_prod_id_core), - .mask_rev_in(mask_rev), - .mask_rev(spi_ro_mask_rev_core) - ); - - lvlshiftdown porb_level_shift ( - `ifdef LVS - .vpwr(vdd1v8), - .vpb(vdd1v8), - .vnb(vss), - .vgnd(vss), - `endif - .A(porb_h), - .X(porb_l) - ); - - // On-board experimental digital PLL - // Use xi_core, assumed to be a CMOS digital clock signal. xo_core - // is used as an output and set from pll_clk16. - - digital_pll pll ( - `ifdef LVS - .vdd(vdd1v8), - .vss(vss), - `endif - .reset(por), - .extclk_sel(ext_clk_sel_core), - .osc(xi_core), - .clockc(pll_clk_core), - .clockp({pll_clk_core0, pll_clk_core90}), - .clockd({pll_clk2, pll_clk4, pll_clk8, pll_clk16}), - .div(spi_ro_pll_div_core), - .sel(spi_ro_pll_sel_core), - .dco(spi_ro_pll_dco_ena_core), - .ext_trim(spi_ro_pll_trim_core) - ); - -endmodule
diff --git a/verilog/rtl/harness_chip.v b/verilog/rtl/harness_chip.v new file mode 100644 index 0000000..52992eb --- /dev/null +++ b/verilog/rtl/harness_chip.v
@@ -0,0 +1,378 @@ +/*----------------------------------------------------------*/ +/* striVe, a raven/ravenna-like architecture in SkyWater s8 */ +/* */ +/* 1st edition, test of SkyWater s8 process */ +/* This version is missing all analog functionality, */ +/* including crystal oscillator, voltage regulator, and PLL */ +/* For simplicity, the pad arrangement of Raven has been */ +/* retained, even though many pads have no internal */ +/* connection. */ +/* */ +/* Copyright 2020 efabless, Inc. */ +/* Written by Tim Edwards, December 2019 */ +/* This file is open source hardware released under the */ +/* Apache 2.0 license. See file LICENSE. */ +/* */ +/*----------------------------------------------------------*/ + +`timescale 1 ns / 1 ps + +`define USE_OPENRAM +`define USE_PG_PIN +`define functional + +`define MPRJ_IO_PADS 32 + +`include "pads.v" + +`include "/ef/tech/SW/EFS8A/libs.ref/verilog/s8iom0s8/s8iom0s8.v" +`include "/ef/tech/SW/EFS8A/libs.ref/verilog/s8iom0s8/power_pads_lib.v" +`include "/ef/tech/SW/EFS8A/libs.ref/verilog/scs8hd/scs8hd.v" + +`include "lvlshiftdown.v" +`include "mgmt_soc.v" +`include "striVe_spi.v" +`include "digital_pll.v" +`include "striVe_clkrst.v" +`include "mprj_counter.v" +`include "mgmt_core.v" +`include "mprj_io.v" +`include "chip_io.v" + +`ifdef USE_OPENRAM + `include "sram_1rw1r_32_8192_8_sky130.v" +`endif + +module harness_chip ( + inout vdd, + inout vdd1v8, + inout vss, + inout [15:0] gpio, + inout [`MPRJ_IO_PADS-1:0] mprj_io, + input xi, // CMOS clock input, not a crystal + output xo, // divide-by-16 clock output + input adc0_in, + input adc1_in, + input adc_high, + input adc_low, + input comp_inn, + input comp_inp, + input RSTB, // NOTE: Replaces analog_out pin from raven chip + input ser_rx, + output ser_tx, + input irq, + output SDO, + input SDI, + input CSB, + input SCK, + input xclk, + output flash_csb, + output flash_clk, + output flash_io0, + output flash_io1, + output flash_io2, + output flash_io3 +); + + wire [15:0] gpio_out_core; + wire [15:0] gpio_in_core; + wire [15:0] gpio_mode0_core; + wire [15:0] gpio_mode1_core; + wire [15:0] gpio_outenb_core; + wire [15:0] gpio_inenb_core; + + // Mega-Project Control + wire [`MPRJ_IO_PADS-1:0] mprj_io_oeb_n; + wire [`MPRJ_IO_PADS-1:0] mprj_io_hldh_n; + wire [`MPRJ_IO_PADS-1:0] mprj_io_enh; + wire [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis; + wire [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel; + wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_en; + wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel; + wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol; + wire [`MPRJ_IO_PADS*3-1:0] mprj_io_dm; + wire [`MPRJ_IO_PADS-1:0] mprj_io_in; + wire [`MPRJ_IO_PADS-1:0] mprj_io_out; + + wire porb_h; + wire porb_l; + wire por; + wire SCK_core; + wire SDI_core; + wire CSB_core; + wire SDO_core; + wire SDO_enb; + + chip_io padframe( + // Package Pins + .vdd(vdd), + .vdd1v8(vdd1v8), + .vss(vss), + .gpio(gpio), + .mprj_io(mprj_io), + .xi(xi), + .xo(xo), + .adc0_in(adc0_in), + .adc1_in(adc1_in), + .adc_high(adc_high), + .adc_low(adc_low), + .comp_inn(comp_inn), + .comp_inp(comp_inp), + .RSTB(RSTB), + .ser_rx(ser_rx), + .ser_tx(ser_tx), + .irq(irq), + .SDO(SDO), + .SDI(SDI), + .CSB(CSB), + .SCK(SCK), + .xclk(xclk), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .flash_io2(flash_io2), + .flash_io3(flash_io3), + // SoC Core Interface + .por(por), + .porb_h(porb_h), + .ext_clk_core(ext_clk_core), + .xi_core(xi_core), + .gpio_out_core(gpio_out_core), + .gpio_in_core(gpio_in_core), + .gpio_mode0_core(gpio_mode0_core), + .gpio_mode1_core(gpio_mode1_core), + .gpio_outenb_core(gpio_outenb_core), + .gpio_inenb_core(gpio_inenb_core), + .SCK_core(SCK_core), + .ser_rx_core(ser_rx_core), + .ser_tx_core(ser_tx_core), + .irq_pin_core(irq_pin_core), + .flash_csb_core(flash_csb_core), + .flash_clk_core(flash_clk_core), + .flash_csb_oeb_core(flash_csb_oeb_core), + .flash_clk_oeb_core(flash_clk_oeb_core), + .flash_io0_oeb_core(flash_io0_oeb_core), + .flash_io1_oeb_core(flash_io1_oeb_core), + .flash_io2_oeb_core(flash_io2_oeb_core), + .flash_io3_oeb_core(flash_io3_oeb_core), + .flash_csb_ieb_core(flash_csb_ieb_core), + .flash_clk_ieb_core(flash_clk_ieb_core), + .flash_io0_ieb_core(flash_io0_ieb_core), + .flash_io1_ieb_core(flash_io1_ieb_core), + .flash_io2_ieb_core(flash_io2_ieb_core), + .flash_io3_ieb_core(flash_io3_ieb_core), + .flash_io0_do_core(flash_io0_do_core), + .flash_io1_do_core(flash_io1_do_core), + .flash_io2_do_core(flash_io2_do_core), + .flash_io3_do_core(flash_io3_do_core), + .flash_io0_di_core(flash_io0_di_core), + .flash_io1_di_core(flash_io1_di_core), + .flash_io2_di_core(flash_io2_di_core), + .flash_io3_di_core(flash_io3_di_core), + .SDI_core(SDI_core), + .CSB_core(CSB_core), + .pll_clk16(pll_clk16), + .SDO_core(SDO_core), + .mprj_io_in(mprj_io_in), + .mprj_io_out(mprj_io_out), + .mprj_io_oeb_n(mprj_io_oeb_n), + .mprj_io_hldh_n(mprj_io_hldh_n), + .mprj_io_enh(mprj_io_enh), + .mprj_io_inp_dis(mprj_io_inp_dis), + .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel), + .mprj_io_analog_en(mprj_io_analog_en), + .mprj_io_analog_sel(mprj_io_analog_sel), + .mprj_io_analog_pol(mprj_io_analog_pol), + .mprj_io_dm(mprj_io_dm) + ); + + // SoC core + wire striVe_clk; + wire striVe_rstn; + + wire [9:0] adc0_data_core; + wire [1:0] adc0_inputsrc_core; + wire [9:0] adc1_data_core; + wire [1:0] adc1_inputsrc_core; + wire [9:0] dac_value_core; + wire [1:0] comp_ninputsrc_core; + wire [1:0] comp_pinputsrc_core; + wire [7:0] spi_ro_config_core; + + // LA signals + wire [127:0] la_output_core; // From CPU to MPRJ + wire [127:0] la_data_in_mprj; // From CPU to MPRJ + wire [127:0] la_data_out_mprj; // From CPU to MPRJ + wire [127:0] la_output_mprj; // From MPRJ to CPU + wire [127:0] la_oen; // LA output enable from CPU perspective (active-low) + + // WB MI A (Mega Project) + wire mprj_cyc_o_core; + wire mprj_stb_o_core; + wire mprj_we_o_core; + wire [3:0] mprj_sel_o_core; + wire [31:0] mprj_adr_o_core; + wire [31:0] mprj_dat_o_core; + wire mprj_ack_i_core; + wire [31:0] mprj_dat_i_core; + + // WB MI B (xbar) + wire xbar_cyc_o_core; + wire xbar_stb_o_core; + wire xbar_we_o_core; + wire [3:0] xbar_sel_o_core; + wire [31:0] xbar_adr_o_core; + wire [31:0] xbar_dat_o_core; + wire xbar_ack_i_core; + wire [31:0] xbar_dat_i_core; + + mgmt_core soc ( + `ifdef LVS + .vdd1v8(vdd1v8), + .vss(vss), + `endif + .ext_clk(ext_clk_core), + .gpio_out_pad(gpio_out_core), + .gpio_in_pad(gpio_in_core), + .gpio_mode0_pad(gpio_mode0_core), + .gpio_mode1_pad(gpio_mode1_core), + .gpio_outenb_pad(gpio_outenb_core), + .gpio_inenb_pad(gpio_inenb_core), + .adc0_ena(adc0_ena_core), + .adc0_convert(adc0_convert_core), + .adc0_data(adc0_data_core), + .adc0_done(adc0_done_core), + .adc0_clk(adc0_clk_core), + .adc0_inputsrc(adc0_inputsrc_core), + .adc1_ena(adc1_ena_core), + .adc1_convert(adc1_convert_core), + .adc1_clk(adc1_clk_core), + .adc1_inputsrc(adc1_inputsrc_core), + .adc1_data(adc1_data_core), + .adc1_done(adc1_done_core), + .dac_ena(dac_ena_core), + .dac_value(dac_value_core), + .analog_out_sel(analog_out_sel_core), + .opamp_ena(opamp_ena_core), + .opamp_bias_ena(opamp_bias_ena_core), + .bg_ena(bg_ena_core), + .comp_ena(comp_ena_core), + .comp_ninputsrc(comp_ninputsrc_core), + .comp_pinputsrc(comp_pinputsrc_core), + .rcosc_ena(rcosc_ena_core), + .overtemp_ena(overtemp_ena_core), + .overtemp(overtemp_core), + .rcosc_in(rcosc_in_core), + .xtal_in(xtal_in_core), + .comp_in(comp_in_core), + .spi_sck(SCK_core), + .spi_ro_config(spi_ro_config_core), + .ser_tx(ser_tx_core), + .ser_rx(ser_rx_core), + .irq_pin(irq_pin_core), + .flash_csb(flash_csb_core), + .flash_clk(flash_clk_core), + .flash_csb_oeb(flash_csb_oeb_core), + .flash_clk_oeb(flash_clk_oeb_core), + .flash_io0_oeb(flash_io0_oeb_core), + .flash_io1_oeb(flash_io1_oeb_core), + .flash_io2_oeb(flash_io2_oeb_core), + .flash_io3_oeb(flash_io3_oeb_core), + .flash_csb_ieb(flash_csb_ieb_core), + .flash_clk_ieb(flash_clk_ieb_core), + .flash_io0_ieb(flash_io0_ieb_core), + .flash_io1_ieb(flash_io1_ieb_core), + .flash_io2_ieb(flash_io2_ieb_core), + .flash_io3_ieb(flash_io3_ieb_core), + .flash_io0_do(flash_io0_do_core), + .flash_io1_do(flash_io1_do_core), + .flash_io2_do(flash_io2_do_core), + .flash_io3_do(flash_io3_do_core), + .flash_io0_di(flash_io0_di_core), + .flash_io1_di(flash_io1_di_core), + .flash_io2_di(flash_io2_di_core), + .flash_io3_di(flash_io3_di_core), + .por(por), + .porb_l(porb_l), + .xi(xi_core), + .pll_clk16(pll_clk16), + .SDI_core(SDI_core), + .CSB_core(CSB_core), + .SDO_core(SDO_core), + .SDO_enb(SDO_enb), + .striVe_clk(striVe_clk), + .striVe_rstn(striVe_rstn), + // Logic Analyzer + .la_input(la_data_out_mprj), + .la_output(la_output_core), + .la_oen(la_oen), + // Mega Project IO Control + .mprj_io_oeb_n(mprj_io_oeb_n), + .mprj_io_enh(mprj_io_enh), + .mprj_io_hldh_n(mprj_io_hldh_n), + .mprj_io_inp_dis(mprj_io_inp_dis), + .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel), + .mprj_io_analog_en(mprj_io_analog_en), + .mprj_io_analog_sel(mprj_io_analog_sel), + .mprj_io_analog_pol(mprj_io_analog_pol), + .mprj_io_dm(mprj_io_dm), + // Mega Project Slave ports (WB MI A) + .mprj_cyc_o(mprj_cyc_o_core), + .mprj_stb_o(mprj_stb_o_core), + .mprj_we_o(mprj_we_o_core), + .mprj_sel_o(mprj_sel_o_core), + .mprj_adr_o(mprj_adr_o_core), + .mprj_dat_o(mprj_dat_o_core), + .mprj_ack_i(mprj_ack_i_core), + .mprj_dat_i(mprj_dat_i_core), + // Xbar Switch (WB MI B) + .xbar_cyc_o(xbar_cyc_o_core), + .xbar_stb_o(xbar_stb_o_core), + .xbar_we_o (xbar_we_o_core), + .xbar_sel_o(xbar_sel_o_core), + .xbar_adr_o(xbar_adr_o_core), + .xbar_dat_o(xbar_dat_o_core), + .xbar_ack_i(xbar_ack_i_core), + .xbar_dat_i(xbar_dat_i_core) + ); + + scs8hd_ebufn_8 la_buf[127:0]( + .Z(la_data_in_mprj), + .A(la_output_core), + .TEB(la_oen) + ); + + mega_project mprj ( + .wb_clk_i(striVe_clk), + .wb_rst_i(!striVe_rstn), + // MGMT SoC Wishbone Slave + .wbs_cyc_i(mprj_cyc_o_core), + .wbs_stb_i(mprj_stb_o_core), + .wbs_we_i(mprj_we_o_core), + .wbs_sel_i(mprj_sel_o_core), + .wbs_adr_i(mprj_adr_o_core), + .wbs_dat_i(mprj_dat_o_core), + .wbs_ack_o(mprj_ack_i_core), + .wbs_dat_o(mprj_dat_i_core), + // Logic Analyzer + .la_data_in(la_data_in_mprj), + .la_data_out(la_data_out_mprj), + .la_oen (la_oen), + // IO Pads + .io_out(mprj_io_out), + .io_in (mprj_io_in) + ); + + lvlshiftdown porb_level_shift ( + `ifdef LVS + .vpwr(vdd1v8), + .vpb(vdd1v8), + .vnb(vss), + .vgnd(vss), + `endif + .A(porb_h), + .X(porb_l) + ); + +endmodule
diff --git a/verilog/rtl/la_wb.v b/verilog/rtl/la_wb.v index fd713a4..68e0cc0 100644 --- a/verilog/rtl/la_wb.v +++ b/verilog/rtl/la_wb.v
@@ -22,8 +22,9 @@ output [31:0] wb_dat_o, output wb_ack_o, + input [127:0] la_data_in, // From MPRJ output [127:0] la_data, - output [127:0] la_ena + output [127:0] la_oen ); wire resetn; @@ -56,8 +57,9 @@ .iomem_wdata(wb_dat_i), .iomem_rdata(wb_dat_o), .iomem_ready(ready), + .la_data_in(la_data_in), .la_data(la_data), - .la_ena(la_ena) + .la_oen(la_oen) ); endmodule @@ -84,8 +86,9 @@ output reg [31:0] iomem_rdata, output reg iomem_ready, - output [127:0] la_data, - output [127:0] la_ena + input [127:0] la_data_in, // From MPRJ + output [127:0] la_data, // To MPRJ + output [127:0] la_oen ); reg [31:0] la_data_0; @@ -102,7 +105,7 @@ wire [3:0] la_ena_sel; assign la_data = {la_data_3, la_data_2, la_data_1, la_data_0}; - assign la_ena = {la_ena_3, la_ena_2, la_ena_1, la_ena_0}; + assign la_oen = {la_ena_3, la_ena_2, la_ena_1, la_ena_0}; assign la_data_sel = { (iomem_addr[7:0] == LA_DATA_3), @@ -125,17 +128,17 @@ la_data_1 <= 0; la_data_2 <= 0; la_data_3 <= 0; - la_ena_0 <= 0; - la_ena_1 <= 0; - la_ena_2 <= 0; - la_ena_3 <= 0; + la_ena_0 <= 32'hFFFF_FFFF; // default is tri-state buff disabled + la_ena_1 <= 32'hFFFF_FFFF; + la_ena_2 <= 32'hFFFF_FFFF; + la_ena_3 <= 32'hFFFF_FFFF; end else begin iomem_ready <= 0; if (iomem_valid && !iomem_ready && iomem_addr[31:8] == BASE_ADR[31:8]) begin iomem_ready <= 1'b 1; if (la_data_sel[0]) begin - iomem_rdata <= la_data_0; + iomem_rdata <= la_data_0 | (la_data_in[31:0] & la_ena_0); if (iomem_wstrb[0]) la_data_0[ 7: 0] <= iomem_wdata[ 7: 0]; if (iomem_wstrb[1]) la_data_0[15: 8] <= iomem_wdata[15: 8]; @@ -143,7 +146,7 @@ if (iomem_wstrb[3]) la_data_0[31:24] <= iomem_wdata[31:24]; end else if (la_data_sel[1]) begin - iomem_rdata <= la_data_1; + iomem_rdata <= la_data_1 | (la_data_in[63:32] & la_ena_1); if (iomem_wstrb[0]) la_data_1[ 7: 0] <= iomem_wdata[ 7: 0]; if (iomem_wstrb[1]) la_data_1[15: 8] <= iomem_wdata[15: 8]; @@ -151,7 +154,7 @@ if (iomem_wstrb[3]) la_data_1[31:24] <= iomem_wdata[31:24]; end else if (la_data_sel[2]) begin - iomem_rdata <= la_data_2; + iomem_rdata <= la_data_2 | (la_data_in[95:64] & la_ena_2); if (iomem_wstrb[0]) la_data_2[ 7: 0] <= iomem_wdata[ 7: 0]; if (iomem_wstrb[1]) la_data_2[15: 8] <= iomem_wdata[15: 8]; @@ -159,7 +162,7 @@ if (iomem_wstrb[3]) la_data_2[31:24] <= iomem_wdata[31:24]; end else if (la_data_sel[3]) begin - iomem_rdata <= la_data_3; + iomem_rdata <= la_data_3 | (la_data_in[127:96] & la_ena_3); if (iomem_wstrb[0]) la_data_3[ 7: 0] <= iomem_wdata[ 7: 0]; if (iomem_wstrb[1]) la_data_3[15: 8] <= iomem_wdata[15: 8];
diff --git a/verilog/rtl/mem_wb.v b/verilog/rtl/mem_wb.v index e0b6599..bacf52c 100644 --- a/verilog/rtl/mem_wb.v +++ b/verilog/rtl/mem_wb.v
@@ -34,15 +34,17 @@ - read transaction : asserted one clock cycle after receiving the adr_i & dat_i */ - reg [2:0] wb_ack_read; - - assign wb_ack_o = wb_we_i ? valid : &wb_ack_read; + reg wb_ack_read; + reg wb_ack_o; always @(posedge wb_clk_i) begin if (wb_rst_i == 1'b 1) begin - wb_ack_read <= 3'b 00; + wb_ack_read <= 1'b0; + wb_ack_o <= 1'b0; end else begin - wb_ack_read <= {3{valid}} & {1'b1, wb_ack_read[2:1]}; + // wb_ack_read <= {2{valid}} & {1'b1, wb_ack_read[1]}; + wb_ack_o <= wb_we_i? (valid & !wb_ack_o): wb_ack_read; + wb_ack_read <= (valid & !wb_ack_o) & !wb_ack_read; end end @@ -62,7 +64,7 @@ module soc_mem `ifndef USE_OPENRAM #( - parameter integer WORDS = 256 + parameter integer WORDS = 8192 ) `endif ( @@ -91,12 +93,12 @@ /* Using Port 0 Only - Size: 1KB, 256x32 bits */ //sram_1rw1r_32_256_8_scn4m_subm - sram_1rw1r_32_256_8_sky130 SRAM( + sram_1rw1r_32_8192_8_sky130 SRAM( .clk0(clk), .csb0(~ena), .web0(~|wen), .wmask0(wen), - .addr0(addr[7:0]), + .addr0(addr[12:0]), .din0(wdata), .dout0(rdata) );
diff --git a/verilog/rtl/mgmt_core.v b/verilog/rtl/mgmt_core.v new file mode 100644 index 0000000..9fe3a79 --- /dev/null +++ b/verilog/rtl/mgmt_core.v
@@ -0,0 +1,326 @@ +module mgmt_core( +`ifdef LVS + inout vdd1v8, + inout vss, +`endif + input ext_clk, + output[ 15:0] gpio_out_pad, // Connect to out on gpio pad + input [15:0] gpio_in_pad, // Connect to in on gpio pad + output [15:0] gpio_mode0_pad, // Connect to dm[0] on gpio pad + output [15:0] gpio_mode1_pad, // Connect to dm[2] on gpio pad + output [15:0] gpio_outenb_pad, // Connect to oe_n on gpio pad + output [15:0] gpio_inenb_pad, // Connect to inp_dis on gpio pad + output adc0_ena, + output adc0_convert, + input [9:0] adc0_data, + input adc0_done, + output adc0_clk, + output [1:0] adc0_inputsrc, + output adc1_ena, + output adc1_convert, + output adc1_clk, + output [1:0] adc1_inputsrc, + input [9:0] adc1_data, + input adc1_done, + output dac_ena, + output [9:0] dac_value, + output analog_out_sel, // Analog output select (DAC or bandgap) + output opamp_ena, // Op-amp enable for analog output + output opamp_bias_ena, // Op-amp bias enable for analog output + output bg_ena, // Bandgap enable + output comp_ena, + output [1:0] comp_ninputsrc, + output [1:0] comp_pinputsrc, + output rcosc_ena, + output overtemp_ena, + input overtemp, + input rcosc_in, // RC oscillator output + input xtal_in, // crystal oscillator output + input comp_in, // comparator output + input spi_sck, + input [7:0] spi_ro_config, + output ser_tx, + input ser_rx, + // IRQ + input irq_pin, // dedicated IRQ pin + // Flash memory control (SPI master) + output flash_csb, + output flash_clk, + output flash_csb_oeb, + output flash_clk_oeb, + output flash_io0_oeb, + output flash_io1_oeb, + output flash_io2_oeb, + output flash_io3_oeb, + output flash_csb_ieb, + output flash_clk_ieb, + output flash_io0_ieb, + output flash_io1_ieb, + output flash_io2_ieb, + output flash_io3_ieb, + output flash_io0_do, + output flash_io1_do, + output flash_io2_do, + output flash_io3_do, + input flash_io0_di, + input flash_io1_di, + input flash_io2_di, + input flash_io3_di, + output por, + input porb_l, + input xi, + output pll_clk16, + input SDI_core, + input CSB_core, + output SDO_core, + output SDO_enb, + // LA signals + input [127:0] la_input, // From Mega-Project to cpu + output [127:0] la_output, // From CPU to Mega-Project + output [127:0] la_oen, // LA output enable + // Mega-Project Control Signals + output [`MPRJ_IO_PADS-1:0] mprj_io_oeb_n, + output [`MPRJ_IO_PADS-1:0] mprj_io_hldh_n, + output [`MPRJ_IO_PADS-1:0] mprj_io_enh, + output [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis, + output [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel, + output [`MPRJ_IO_PADS-1:0] mprj_io_analog_en, + output [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel, + output [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol, + output [`MPRJ_IO_PADS*3-1:0] mprj_io_dm, + // WB MI A (Mega project) + input mprj_ack_i, + input [31:0] mprj_dat_i, + output mprj_cyc_o, + output mprj_stb_o, + output mprj_we_o, + output [3:0] mprj_sel_o, + output [31:0] mprj_adr_o, + output [31:0] mprj_dat_o, + // WB MI B Switch + input xbar_ack_i, + input [31:0] xbar_dat_i, + output xbar_cyc_o, + output xbar_stb_o, + output xbar_we_o, + output [3:0] xbar_sel_o, + output [31:0] xbar_adr_o, + output [31:0] xbar_dat_o, + + output striVe_clk, + output striVe_rstn +); + wire ext_clk_sel; + wire ext_clk; + wire pll_clk; + wire ext_reset; + + striVe_clkrst clkrst( + `ifdef LVS + .vdd1v8(vdd1v8), + .vss(vss), + `endif + .ext_clk_sel(ext_clk_sel), + .ext_clk(ext_clk), + .pll_clk(pll_clk), + .reset(por), + .ext_reset(ext_reset), + .clk(striVe_clk), + .resetn(striVe_rstn) + ); + + // SoC core + wire [9:0] adc0_data_core; + wire [1:0] adc0_inputsrc_core; + wire [9:0] adc1_data_core; + wire [1:0] adc1_inputsrc_core; + wire [9:0] dac_value_core; + wire [1:0] comp_ninputsrc_core; + wire [1:0] comp_pinputsrc_core; + wire [7:0] spi_ro_config_core; + + // HKSPI + wire [11:0] spi_ro_mfgr_id; + wire [7:0] spi_ro_prod_id; + wire [3:0] spi_ro_mask_rev; + wire [2:0] spi_ro_pll_sel; + wire [4:0] spi_ro_pll_div; + wire [25:0] spi_ro_pll_trim; + + mgmt_soc soc ( + `ifdef LVS + .vdd1v8(vdd1v8), + .vss(vss), + `endif + .pll_clk(pll_clk), + .ext_clk(ext_clk), + .ext_clk_sel(ext_clk_sel), + .clk(striVe_clk), + .resetn(striVe_rstn), + .gpio_out_pad(gpio_out_pad), + .gpio_in_pad(gpio_in_pad), + .gpio_mode0_pad(gpio_mode0_pad), + .gpio_mode1_pad(gpio_mode1_pad), + .gpio_outenb_pad(gpio_outenb_pad), + .gpio_inenb_pad(gpio_inenb_pad), + .adc0_ena(adc0_ena), + .adc0_convert(adc0_convert), + .adc0_data(adc0_data), + .adc0_done(adc0_done), + .adc0_clk(adc0_clk), + .adc0_inputsrc(adc0_inputsrc), + .adc1_ena(adc1_ena), + .adc1_convert(adc1_convert), + .adc1_clk(adc1_clk), + .adc1_inputsrc(adc1_inputsrc), + .adc1_data(adc1_data), + .adc1_done(adc1_done), + .dac_ena(dac_ena), + .dac_value(dac_value), + .analog_out_sel(analog_out_sel), + .opamp_ena(opamp_ena), + .opamp_bias_ena(opamp_bias_ena), + .bg_ena(bg_ena), + .comp_ena(comp_ena), + .comp_ninputsrc(comp_ninputsrc), + .comp_pinputsrc(comp_pinputsrc), + .rcosc_ena(rcosc_ena), + .overtemp_ena(overtemp_ena), + .overtemp(overtemp), + .rcosc_in(rcosc_in), + .xtal_in(xtal_in), + .comp_in(comp_in), + .spi_sck(spi_sck), + .spi_ro_config(spi_ro_config), + .spi_ro_xtal_ena(spi_ro_xtal_ena), + .spi_ro_reg_ena(spi_ro_reg_ena), + .spi_ro_pll_dco_ena(spi_ro_pll_dco_ena), + .spi_ro_pll_div(spi_ro_pll_div), + .spi_ro_pll_sel(spi_ro_pll_sel), + .spi_ro_pll_trim(spi_ro_pll_trim), + .spi_ro_mfgr_id(spi_ro_mfgr_id), + .spi_ro_prod_id(spi_ro_prod_id), + .spi_ro_mask_rev(spi_ro_mask_rev), + .ser_tx(ser_tx), + .ser_rx(ser_rx), + .irq_pin(irq_pin), + .irq_spi(irq_spi), + .trap(trap), + // Flash + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_csb_oeb(flash_csb_oeb), + .flash_clk_oeb(flash_clk_oeb), + .flash_io0_oeb(flash_io0_oeb), + .flash_io1_oeb(flash_io1_oeb), + .flash_io2_oeb(flash_io2_oeb), + .flash_io3_oeb(flash_io3_oeb), + .flash_csb_ieb(flash_csb_ieb), + .flash_clk_ieb(flash_clk_ieb), + .flash_io0_ieb(flash_io0_ieb), + .flash_io1_ieb(flash_io1_ieb), + .flash_io2_ieb(flash_io2_ieb), + .flash_io3_ieb(flash_io3_ieb), + .flash_io0_do(flash_io0_do), + .flash_io1_do(flash_io1_do), + .flash_io2_do(flash_io2_do), + .flash_io3_do(flash_io3_do), + .flash_io0_di(flash_io0_di), + .flash_io1_di(flash_io1_di), + .flash_io2_di(flash_io2_di), + .flash_io3_di(flash_io3_di), + // Logic Analyzer + .la_input(la_input), + .la_output(la_output), + .la_oen(la_oen), + // Mega-Project Control + .mprj_io_oeb_n(mprj_io_oeb_n), + .mprj_io_hldh_n(mprj_io_hldh_n), + .mprj_io_enh(mprj_io_enh), + .mprj_io_inp_dis(mprj_io_inp_dis), + .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel), + .mprj_io_analog_en(mprj_io_analog_en), + .mprj_io_analog_sel(mprj_io_analog_sel), + .mprj_io_analog_pol(mprj_io_analog_pol), + .mprj_io_dm(mprj_io_dm), + // Mega Project Slave ports (WB MI A) + .mprj_cyc_o(mprj_cyc_o), + .mprj_stb_o(mprj_stb_o), + .mprj_we_o(mprj_we_o), + .mprj_sel_o(mprj_sel_o), + .mprj_adr_o(mprj_adr_o), + .mprj_dat_o(mprj_dat_o), + .mprj_ack_i(mprj_ack_i), + .mprj_dat_i(mprj_dat_i), + // Crossbar Switch + .xbar_cyc_o(xbar_cyc_o), + .xbar_stb_o(xbar_stb_o), + .xbar_we_o (xbar_we_o), + .xbar_sel_o(xbar_sel_o), + .xbar_adr_o(xbar_adr_o), + .xbar_dat_o(xbar_dat_o), + .xbar_ack_i(xbar_ack_i), + .xbar_dat_i(xbar_dat_i) + ); + + digital_pll pll ( + `ifdef LVS + .vdd(vdd1v8), + .vss(vss), + `endif + .reset(por), + .extclk_sel(ext_clk_sel), + .osc(xi), + .clockc(pll_clk), + .clockp({pll_clk_core0, pll_clk_core90}), + .clockd({pll_clk2, pll_clk4, pll_clk8, pll_clk16}), + .div(spi_ro_pll_div), + .sel(spi_ro_pll_sel), + .dco(spi_ro_pll_dco_ena), + .ext_trim(spi_ro_pll_trim) + ); + + // For the mask revision input, use an array of digital constant logic cells + wire [3:0] mask_rev; + wire [3:0] no_connect; + scs8hd_conb_1 mask_rev_value [3:0] ( + `ifdef LVS + .vpwr(vdd1v8), + .vpb(vdd1v8), + .vnb(vss), + .vgnd(vss), + `endif + .HI({no_connect[3:1], mask_rev[0]}), + .LO({mask_rev[3:1], no_connect[0]}) + ); + + // Housekeeping SPI at 1.8V. + striVe_spi housekeeping ( + `ifdef LVS + .vdd(vdd1v8), + .vss(vss), + `endif + .RSTB(porb_l), + .SCK(spi_sck), + .SDI(SDI_core), + .CSB(CSB_core), + .SDO(SDO_core), + .sdo_enb(SDO_enb), + .xtal_ena(spi_ro_xtal_ena), + .reg_ena(spi_ro_reg_ena), + .pll_dco_ena(spi_ro_pll_dco_ena), + .pll_sel(spi_ro_pll_sel), + .pll_div(spi_ro_pll_div), + .pll_trim(spi_ro_pll_trim), + .pll_bypass(ext_clk_sel), + .irq(irq_spi), + .RST(por), + .reset(ext_reset), + .trap(trap), + .mfgr_id(spi_ro_mfgr_id), + .prod_id(spi_ro_prod_id), + .mask_rev_in(mask_rev), + .mask_rev(spi_ro_mask_rev) + ); + +endmodule \ No newline at end of file
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v index 007ca0f..af27f99 100644 --- a/verilog/rtl/mgmt_soc.v +++ b/verilog/rtl/mgmt_soc.v
@@ -38,6 +38,7 @@ `include "spi_sysctrl.v" `include "sysctrl.v" `include "la_wb.v" +`include "mprj_ctrl.v" module mgmt_soc ( `ifdef LVS @@ -62,7 +63,18 @@ // LA signals input [127:0] la_input, // From Mega-Project to cpu output [127:0] la_output, // From CPU to Mega-Project - output [127:0] la_oe, // LA output enable (sensitiviy according to tri-state ?) + output [127:0] la_oen, // LA output enable (active low) + + // Mega-Project Control + output [MPRJ_IO_PADS-1:0] mprj_io_oeb_n, + output [MPRJ_IO_PADS-1:0] mprj_io_hldh_n, + output [MPRJ_IO_PADS-1:0] mprj_io_enh, + output [MPRJ_IO_PADS-1:0] mprj_io_inp_dis, + output [MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel, + output [MPRJ_IO_PADS-1:0] mprj_io_analog_en, + output [MPRJ_IO_PADS-1:0] mprj_io_analog_sel, + output [MPRJ_IO_PADS-1:0] mprj_io_analog_pol, + output [MPRJ_IO_PADS*3-1:0] mprj_io_dm, output adc0_ena, output adc0_convert, @@ -149,7 +161,17 @@ input flash_io2_di, input flash_io3_di, - // Crossbar Switch Slaves + // WB MI A (Mega project) + input mprj_ack_i, + input [31:0] mprj_dat_i, + output mprj_cyc_o, + output mprj_stb_o, + output mprj_we_o, + output [3:0] mprj_sel_o, + output [31:0] mprj_adr_o, + output [31:0] mprj_dat_o, + + // WB MI B (xbar) input [31:0] xbar_dat_i, input xbar_ack_i, output xbar_cyc_o, @@ -160,7 +182,7 @@ output [31:0] xbar_dat_o ); /* Memory reverted back to 256 words while memory has to be synthesized */ - parameter integer MEM_WORDS = 256; + parameter integer MEM_WORDS = 8192; parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory parameter [31:0] PROGADDR_RESET = 32'h 1000_0000; parameter [31:0] PROGADDR_IRQ = 32'h 0000_0000; @@ -170,7 +192,9 @@ parameter FLASH_BASE_ADR = 32'h 1000_0000; parameter UART_BASE_ADR = 32'h 2000_0000; parameter GPIO_BASE_ADR = 32'h 2100_0000; - parameter LA_BASE_ADR = 32'h 2200_0000; + parameter LA_BASE_ADR = 32'h 2200_0000; + parameter MPRJ_CTRL_ADR = 32'h 2300_0000; + parameter MPRJ_BASE_ADR = 32'h 3000_0000; // WB MI A parameter SYS_BASE_ADR = 32'h 2F00_0000; parameter SPI_BASE_ADR = 32'h 2E00_0000; parameter FLASH_CTRL_CFG = 32'h 2D00_0000; @@ -186,7 +210,7 @@ parameter GPIO_PU = 8'h08; parameter GPIO_PD = 8'h0c; - // LDO + // LA parameter LA_DATA_0 = 8'h00; parameter LA_DATA_1 = 8'h04; parameter LA_DATA_2 = 8'h08; @@ -196,6 +220,10 @@ parameter LA_ENA_2 = 8'h18; parameter LA_ENA_3 = 8'h1c; + // Mega-Project Control + parameter MPRJ_IO_PADS = 32; + parameter MPRJ_PWR_CTRL = 32; + // SPI-Controlled Registers parameter SPI_CFG = 8'h00; parameter SPI_ENA = 8'h04; @@ -220,7 +248,7 @@ // Wishbone Interconnect localparam ADR_WIDTH = 32; localparam DAT_WIDTH = 32; - localparam NUM_SLAVES = 9; + localparam NUM_SLAVES = 11; parameter [NUM_SLAVES*ADR_WIDTH-1: 0] ADR_MASK = { {8'h80, {ADR_WIDTH-8{1'b0}}}, @@ -231,13 +259,18 @@ {8'hFF, {ADR_WIDTH-8{1'b0}}}, {8'hFF, {ADR_WIDTH-8{1'b0}}}, {8'hFF, {ADR_WIDTH-8{1'b0}}}, + {8'hFF, {ADR_WIDTH-8{1'b0}}}, + {8'hFF, {ADR_WIDTH-8{1'b0}}}, {8'hFF, {ADR_WIDTH-8{1'b0}}} }; + parameter [NUM_SLAVES*ADR_WIDTH-1: 0] SLAVE_ADR = { {XBAR_BASE_ADR}, {SYS_BASE_ADR}, {SPI_BASE_ADR}, {FLASH_CTRL_CFG}, + {MPRJ_BASE_ADR}, + {MPRJ_CTRL_ADR}, {LA_BASE_ADR}, {GPIO_BASE_ADR}, {UART_BASE_ADR}, @@ -281,9 +314,9 @@ reg [1:0] comp_output_dest; // Comparator output destination reg analog_out_sel; // Analog output select - reg opamp_ena; // Analog output op-amp enable - reg opamp_bias_ena; // Analog output op-amp bias enable - reg bg_ena; // Bandgap enable + reg opamp_ena; // Analog output op-amp enable + reg opamp_bias_ena; // Analog output op-amp bias enable + reg bg_ena; // Bandgap enable wire adc0_clk; // ADC0 clock (multiplexed) wire adc1_clk; // ADC1 clock (multiplexed) @@ -380,6 +413,19 @@ .gpio_mode0_pad(gpio_mode0_pad) ); + wire [7:0] mprj_io_oeb; + convert_gpio_sigs convert_io_bit [7:0] ( + .gpio_out(), + .gpio_outenb(mprj_io_oeb), + .gpio_pu(mprj_io_pu), + .gpio_pd(mprj_io_pd), + .gpio_out_pad(), + .gpio_outenb_pad(mprj_io_outenb_pad), + .gpio_inenb_pad(mprj_io_inenb_pad), + .gpio_mode1_pad(mprj_io_mode1_pad), + .gpio_mode0_pad(mprj_io_mode0_pad) + ); + reg [31:0] irq; wire irq_7; wire irq_8; @@ -596,18 +642,15 @@ ) gpio_wb ( .wb_clk_i(wb_clk_i), .wb_rst_i(wb_rst_i), - .wb_adr_i(cpu_adr_o), .wb_dat_i(cpu_dat_o), .wb_sel_i(cpu_sel_o), .wb_we_i(cpu_we_o), .wb_cyc_i(cpu_cyc_o), - .wb_stb_i(gpio_stb_i), .wb_ack_o(gpio_ack_o), .wb_dat_o(gpio_dat_o), .gpio_in_pad(gpio_in_pad), - .gpio(gpio), .gpio_oeb(gpio_oeb), .gpio_pu(gpio_pu), @@ -729,9 +772,43 @@ .wb_dat_o(la_dat_o), .la_data(la_output), - .la_ena(la_oe) + .la_data_in(la_input), + .la_oen(la_oen) ); + // WB Slave Mega-Project Control + wire mprj_ctrl_stb_i; + wire mprj_ctrl_ack_o; + wire [31:0] mprj_ctrl_dat_o; + + mprj_ctrl_wb #( + .BASE_ADR(MPRJ_CTRL_ADR), + .IO_PADS(MPRJ_IO_PADS), + .PWR_CTRL(MPRJ_PWR_CTRL) + ) mprj_ctrl ( + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + + .wb_adr_i(cpu_adr_o), + .wb_dat_i(cpu_dat_o), + .wb_sel_i(cpu_sel_o), + .wb_we_i(cpu_we_o), + .wb_cyc_i(cpu_cyc_o), + .wb_stb_i(mprj_ctrl_stb_i), + .wb_ack_o(mprj_ctrl_ack_o), + .wb_dat_o(mprj_ctrl_dat_o), + + .output_en_n(mprj_io_oeb_n), + .holdh_n(mprj_io_hldh_n), + .enableh(mprj_io_enh), + .input_dis(mprj_io_inp_dis), + .ib_mode_sel(mprj_io_ib_mode_sel), + .analog_en(mprj_io_analog_en), + .analog_sel(mprj_io_analog_sel), + .analog_pol(mprj_io_analog_pol), + .digital_mode(mprj_io_dm) + ); + // Wishbone Slave RAM wire mem_stb_i; wire mem_ack_o; @@ -769,9 +846,9 @@ .wbm_ack_o(cpu_ack_i), // Slaves Interface - .wbs_stb_o({ xbar_stb_o, sys_stb_i, spi_sys_stb_i, spimemio_cfg_stb_i, la_stb_i, gpio_stb_i, uart_stb_i, spimemio_flash_stb_i, mem_stb_i }), - .wbs_dat_i({ xbar_dat_i, sys_dat_o, spi_sys_dat_o, spimemio_cfg_dat_o, la_dat_o, gpio_dat_o, uart_dat_o, spimemio_flash_dat_o, mem_dat_o }), - .wbs_ack_i({ xbar_ack_i, sys_ack_o, spi_sys_ack_o, spimemio_cfg_ack_o, la_ack_o, gpio_ack_o, uart_ack_o, spimemio_flash_ack_o, mem_ack_o }) + .wbs_stb_o({ xbar_stb_o, sys_stb_i, spi_sys_stb_i, spimemio_cfg_stb_i, mprj_stb_o, mprj_ctrl_stb_i, la_stb_i, gpio_stb_i, uart_stb_i, spimemio_flash_stb_i, mem_stb_i }), + .wbs_dat_i({ xbar_dat_i, sys_dat_o, spi_sys_dat_o, spimemio_cfg_dat_o, mprj_dat_i, mprj_ctrl_dat_o, la_dat_o, gpio_dat_o, uart_dat_o, spimemio_flash_dat_o, mem_dat_o }), + .wbs_ack_i({ xbar_ack_i, sys_ack_o, spi_sys_ack_o, spimemio_cfg_ack_o, mprj_ack_i, mprj_ctrl_ack_o, la_ack_o, gpio_ack_o, uart_ack_o, spimemio_flash_ack_o, mem_ack_o }) ); // Akin to ram ack
diff --git a/verilog/rtl/mprj_counter.v b/verilog/rtl/mprj_counter.v new file mode 100644 index 0000000..924a52c --- /dev/null +++ b/verilog/rtl/mprj_counter.v
@@ -0,0 +1,116 @@ +module mega_project #( + parameter IO_PADS = 32, + parameter BITS = 32 +)( + // Wishbone Slave ports (WB MI A) + input wb_clk_i, + input wb_rst_i, + input wbs_stb_i, + input wbs_cyc_i, + input wbs_we_i, + input [3:0] wbs_sel_i, + input [31:0] wbs_dat_i, + input [31:0] wbs_adr_i, + output wbs_ack_o, + output [31:0] wbs_dat_o, + // Logic Analyzer Signals + input [127:0] la_data_in, + output [127:0] la_data_out, + input [127:0] la_oen, + // IOs + input [IO_PADS-1:0] io_in, + output [IO_PADS-1:0] io_out +); + wire clk; + wire rst; + + wire [31:0] rdata; + wire [31:0] wdata; + wire [BITS-1:0] count; + + wire valid; + wire [3:0] wstrb; + wire [31:0] la_write; + + // WB MI A + assign valid = wbs_cyc_i && wbs_stb_i; + assign wstrb = wbs_sel_i & {4{wbs_we_i}}; + assign wbs_dat_o = rdata; + assign wdata = wbs_dat_i; + + // IO + assign io_out = count; + + // LA + assign la_data_out = {{(127-BITS){1'b0}}, count}; + // Assuming LA probes [63:32] are for controlling the count register + assign la_write = ~la_oen[63:32] & ~{BITS{valid}}; + // Assuming LA probes [65:64] are for controlling the count clk & reset + assign clk = (~la_oen[64]) ? la_data_in[64]: wb_clk_i; + assign rst = (~la_oen[65]) ? la_data_in[65]: wb_rst_i; + + counter #( + .BITS(BITS) + ) counter( + .clk(clk), + .reset(rst), + .ready(wbs_ack_i), + .valid(valid), + .rdata(rdata), + .wdata(wbs_dat_i), + .wstrb(wstrb), + .la_write(la_write), + .la_input(la_data_in[63:32]), + .count(count) + ); + +endmodule + +module counter #( + parameter BITS = 32 +)( + input clk, + input reset, + input valid, + input [3:0] wstrb, + input [BITS-1:0] wdata, + input [BITS-1:0] la_write, + input [BITS-1:0] la_input, + output ready, + output [BITS-1:0] rdata, + output [BITS-1:0] count +); + reg ready; + reg [BITS-1:0] count; + reg [BITS-1:0] rdata; + + always @(posedge clk) begin + if (reset) begin + count <= 0; + ready <= 0; + end else begin + ready <= 1'b0; + if (~|la_write) begin + count <= count + 1; + end + if (valid && !ready) begin + ready <= 1'b1; + rdata <= count; + if (wstrb[0]) count[7:0] <= wdata[7:0]; + if (wstrb[1]) count[15:8] <= wdata[15:8]; + if (wstrb[2]) count[23:16] <= wdata[23:16]; + if (wstrb[3]) count[31:24] <= wdata[31:24]; + end + end + end + + genvar i; + generate + for(i=0; i<BITS; i=i+1) begin + always @(posedge clk) begin + if (la_write[i]) count[i] <= la_input[i]; + end + end + endgenerate + +endmodule \ No newline at end of file
diff --git a/verilog/rtl/mprj_ctrl.v b/verilog/rtl/mprj_ctrl.v new file mode 100644 index 0000000..9236beb --- /dev/null +++ b/verilog/rtl/mprj_ctrl.v
@@ -0,0 +1,193 @@ +module mprj_ctrl_wb #( + parameter BASE_ADR = 32'h 2300_0000, + parameter IO_PADS = 32, // Number of IO control registers + parameter PWR_CTRL = 32 // Number of power control registers +)( + input wb_clk_i, + input wb_rst_i, + + input [31:0] wb_dat_i, + input [31:0] wb_adr_i, + input [3:0] wb_sel_i, + input wb_cyc_i, + input wb_stb_i, + input wb_we_i, + + output [31:0] wb_dat_o, + output wb_ack_o, + + output [IO_PADS-1:0] output_en_n, + output [IO_PADS-1:0] holdh_n, + output [IO_PADS-1:0] enableh, + output [IO_PADS-1:0] input_dis, + output [IO_PADS-1:0] ib_mode_sel, + output [IO_PADS-1:0] analog_en, + output [IO_PADS-1:0] analog_sel, + output [IO_PADS-1:0] analog_pol, + output [IO_PADS*3-1:0] digital_mode +); + + wire resetn; + wire valid; + wire ready; + wire [3:0] iomem_we; + + assign resetn = ~wb_rst_i; + assign valid = wb_stb_i && wb_cyc_i; + + assign iomem_we = wb_sel_i & {4{wb_we_i}}; + assign wb_ack_o = ready; + + mprj_ctrl #( + .BASE_ADR(BASE_ADR), + .IO_PADS(IO_PADS), + .PWR_CTRL(PWR_CTRL) + ) mprj_ctrl ( + .clk(wb_clk_i), + .resetn(resetn), + .iomem_addr(wb_adr_i), + .iomem_valid(valid), + .iomem_wstrb(iomem_we), + .iomem_wdata(wb_dat_i), + .iomem_rdata(wb_dat_o), + .iomem_ready(ready), + .output_en_n(output_en_n), + .holdh_n(holdh_n), + .enableh(enableh), + .input_dis(input_dis), + .ib_mode_sel(ib_mode_sel), + .analog_en(analog_en), + .analog_sel(analog_sel), + .analog_pol(analog_pol), + .digital_mode(digital_mode) + ); + +endmodule + +module mprj_ctrl #( + parameter BASE_ADR = 32'h 2300_0000, + parameter IO_PADS = 32, + parameter PWR_CTRL = 32 +)( + input clk, + input resetn, + + input [31:0] iomem_addr, + input iomem_valid, + input [3:0] iomem_wstrb, + input [31:0] iomem_wdata, + + output reg [31:0] iomem_rdata, + output reg iomem_ready, + + output [IO_PADS-1:0] output_en_n, + output [IO_PADS-1:0] holdh_n, + output [IO_PADS-1:0] enableh, + output [IO_PADS-1:0] input_dis, + output [IO_PADS-1:0] ib_mode_sel, + output [IO_PADS-1:0] analog_en, + output [IO_PADS-1:0] analog_sel, + output [IO_PADS-1:0] analog_pol, + output [IO_PADS*3-1:0] digital_mode +); + + localparam PWR_BASE_ADR = BASE_ADR + IO_PADS*4; + localparam OEB = 0; + localparam HLDH = 1; + localparam ENH = 2; + localparam INP_DIS = 3; + localparam MOD_SEL = 4; + localparam AN_EN = 5; + localparam AN_SEL = 6; + localparam AN_POL = 7; + localparam DM = 8; + + reg [IO_PADS*32-1:0] io_ctrl; + reg [PWR_CTRL*32-1:0] pwr_ctrl; + + wire [IO_PADS-1:0] io_ctrl_sel; + wire [PWR_CTRL-1:0] pwr_ctrl_sel; + + genvar i; + generate + for (i=0; i<IO_PADS; i=i+1) begin + assign io_ctrl_sel[i] = (iomem_addr[7:0] == (BASE_ADR[7:0] + i*4)); + assign output_en_n[i] = io_ctrl[i*32+OEB]; + assign holdh_n[i] = io_ctrl[i*32+HLDH]; + assign enableh[i] = io_ctrl[i*32+ENH]; + assign input_dis[i] = io_ctrl[i*32+INP_DIS]; + assign ib_mode_sel[i] = io_ctrl[i*32+MOD_SEL]; + assign analog_en[i] = io_ctrl[i*32+AN_EN]; + assign analog_sel[i] = io_ctrl[i*32+AN_SEL]; + assign analog_pol[i] = io_ctrl[i*32+AN_POL]; + assign digital_mode[(i+1)*3-1:i*3] = io_ctrl[i*32+DM+3-1:i*32+DM]; + end + endgenerate + + generate + for (i=0; i<PWR_CTRL; i=i+1) begin + assign pwr_ctrl_sel[i] = (iomem_addr[7:0] == (PWR_BASE_ADR[7:0] + i*4)); + end + endgenerate + + generate + for (i=0; i<IO_PADS; i=i+1) begin + always @(posedge clk) begin + if (!resetn) begin + io_ctrl[i*32+: 32] <= 0; + end else begin + iomem_ready <= 0; + if (iomem_valid && !iomem_ready && iomem_addr[31:8] == BASE_ADR[31:8]) begin + iomem_ready <= 1'b 1; + + if (io_ctrl_sel[i]) begin + iomem_rdata <= io_ctrl[i*32+: 32]; + if (iomem_wstrb[0]) + io_ctrl[(i+1)*32-1-24:i*32] <= iomem_wdata[7:0]; + + if (iomem_wstrb[1]) + io_ctrl[(i+1)*32-1-16:i*32+8] <= iomem_wdata[15:8]; + + if (iomem_wstrb[2]) + io_ctrl[(i+1)*32-1-8:i*32+16] <= iomem_wdata[23:16]; + + if (iomem_wstrb[3]) + io_ctrl[(i+1)*32-1:i*32+24] <= iomem_wdata[31:24]; + end + end + end + end + end + endgenerate + + generate + for (i=0; i<PWR_CTRL; i=i+1) begin + always @(posedge clk) begin + if (!resetn) begin + pwr_ctrl[i*32+: 32] <= 0; + end else begin + iomem_ready <= 0; + if (iomem_valid && !iomem_ready && iomem_addr[31:8] == BASE_ADR[31:8]) begin + iomem_ready <= 1'b 1; + + if (pwr_ctrl_sel[i]) begin + iomem_rdata <= pwr_ctrl[i*32+: 32]; + if (iomem_wstrb[0]) + pwr_ctrl[(i+1)*32-1-24:i*32] <= iomem_wdata[7:0]; + + if (pwr_ctrl_sel[1]) + pwr_ctrl[(i+1)*32-1-16:i*32+8] <= iomem_wdata[15:8]; + + if (pwr_ctrl_sel[2]) + pwr_ctrl[(i+1)*32-1-8:i*32+16] <= iomem_wdata[23:16]; + + if (pwr_ctrl_sel[3]) + pwr_ctrl[(i+1)*32-1:i*32+24] <= iomem_wdata[31:24]; + end + end + end + end + end + endgenerate + +endmodule \ No newline at end of file
diff --git a/verilog/rtl/mprj_io.v b/verilog/rtl/mprj_io.v new file mode 100644 index 0000000..e168b67 --- /dev/null +++ b/verilog/rtl/mprj_io.v
@@ -0,0 +1,27 @@ +module mprj_io( + inout vdd, + inout vdd1v8, + inout vss, + input vddio_q, + input vssio_q, + input analog_a, + input analog_b, + input [`MPRJ_IO_PADS-1:0] io, + input [`MPRJ_IO_PADS-1:0] io_out, + input [`MPRJ_IO_PADS-1:0] oeb_n, + input [`MPRJ_IO_PADS-1:0] hldh_n, + input [`MPRJ_IO_PADS-1:0] enh, + input [`MPRJ_IO_PADS-1:0] inp_dis, + input [`MPRJ_IO_PADS-1:0] ib_mode_sel, + input [`MPRJ_IO_PADS-1:0] analog_en, + input [`MPRJ_IO_PADS-1:0] analog_sel, + input [`MPRJ_IO_PADS-1:0] analog_pol, + input [`MPRJ_IO_PADS*3-1:0] dm, + output [`MPRJ_IO_PADS-1:0] io_in +); + + `MPRJ_IO_PAD_V(io, io_in, io_out, `MPRJ_IO_PADS, + oeb_n, hldh_n, enh, inp_dis, ib_mode_sel, + analog_en, analog_sel, analog_pol, dm); + +endmodule \ No newline at end of file
diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v new file mode 100644 index 0000000..640216b --- /dev/null +++ b/verilog/rtl/pads.v
@@ -0,0 +1,310 @@ +`ifndef TOP_ROUTING + `define ABUTMENT_PINS \ + .amuxbus_a(analog_a),\ + .amuxbus_b(analog_b),\ + .vssa(vss),\ + .vdda(vdd),\ + .vswitch(vdd),\ + .vddio_q(vddio_q),\ + .vcchib(vdd1v8),\ + .vddio(vdd),\ + .vccd(vdd1v8),\ + .vssio(vss),\ + .vssd(vss),\ + .vssio_q(vssio_q), +`else + `define ABUTMENT_PINS +`endif + +`define INPUT_PAD(X,Y) \ + wire loop_``X; \ + s8iom0_gpiov2_pad X``_pad ( \ + `ABUTMENT_PINS \ + `ifndef TOP_ROUTING \ + .pad(X), \ + `endif \ + .out(vss), \ + .oe_n(vdd1v8), \ + .hld_h_n(vdd), \ + .enable_h(porb_h), \ + .enable_inp_h(loop_``X), \ + .enable_vdda_h(porb_h), \ + .enable_vswitch_h(vss), \ + .enable_vddio(vdd1v8), \ + .inp_dis(por), \ + .ib_mode_sel(vss), \ + .vtrip_sel(vss), \ + .slow(vss), \ + .hld_ovr(vss), \ + .analog_en(vss), \ + .analog_sel(vss), \ + .analog_pol(vss), \ + .dm({vss, vss, vdd1v8}), \ + .pad_a_noesd_h(), \ + .pad_a_esd_0_h(), \ + .pad_a_esd_1_h(), \ + .in(Y), \ + .in_h(), \ + .tie_hi_esd(), \ + .tie_lo_esd(loop_``X) ) + +`define INPUT_PAD_ANALOG(X,SEL,POL) \ + wire loop_``X; \ + s8iom0_gpiov2_pad X``_pad ( \ + `ABUTMENT_PINS \ + `ifndef TOP_ROUTING \ + .pad(X), \ + `endif \ + .out(vss), \ + .oe_n(vdd1v8), \ + .hld_h_n(vdd), \ + .enable_h(porb_h), \ + .enable_inp_h(loop_``X), \ + .enable_vdda_h(porb_h), \ + .enable_vswitch_h(vss), \ + .enable_vddio(vdd1v8), \ + .inp_dis(vdd1v8), \ + .ib_mode_sel(vss), \ + .vtrip_sel(vss), \ + .slow(vss), \ + .hld_ovr(vss), \ + .analog_en(vdd1v8), \ + .analog_sel(SEL), \ + .analog_pol(POL), \ + .dm({vss, vss, vss}), \ + .pad_a_noesd_h(), \ + .pad_a_esd_0_h(), \ + .pad_a_esd_1_h(), \ + .in(), \ + .in_h(), \ + .tie_hi_esd(), \ + .tie_lo_esd() ) + +`define INPUT_PAD_V(X,Y,V) \ + wire [V-1:0] loop_``X; \ + s8iom0_gpiov2_pad X``_pad [V-1:0] ( \ + `ABUTMENT_PINS \ + `ifndef TOP_ROUTING \ + .pad(X),\ + `endif \ + .out(), \ + .oe_n(vdd1v8), \ + .hld_h_n(vdd), \ + .enable_h(vdd), \ + .enable_inp_h(loop_``X), \ + .enable_vdda_h(vdd), \ + .enable_vswitch_h(vss), \ + .enable_vddio(vdd1v8), \ + .inp_dis(por), \ + .ib_mode_sel(vss), \ + .vtrip_sel(vss), \ + .slow(vss), \ + .hld_ovr(vss), \ + .analog_en(vss), \ + .analog_sel(vss), \ + .analog_pol(vss), \ + .dm({vss, vss, vdd1v8}), \ + .pad_a_noesd_h(), \ + .pad_a_esd_0_h(), \ + .pad_a_esd_1_h(), \ + .in(Y), \ + .in_h(), \ + .tie_hi_esd(), \ + .tie_lo_esd(loop_``X) ) + +`define OUTPUT_PAD(X,Y,INP_DIS,OUT_EN_N) \ + wire loop_``X; \ + s8iom0_gpiov2_pad X``_pad ( \ + `ABUTMENT_PINS \ + `ifndef TOP_ROUTING \ + .pad(X), \ + `endif \ + .out(Y), \ + .oe_n(OUT_EN_N), \ + .hld_h_n(vdd), \ + .enable_h(porb_h), \ + .enable_inp_h(loop_``X), \ + .enable_vdda_h(porb_h), \ + .enable_vswitch_h(vss), \ + .enable_vddio(vdd1v8), \ + .inp_dis(INP_DIS), \ + .ib_mode_sel(vss), \ + .vtrip_sel(vss), \ + .slow(vss), \ + .hld_ovr(vss), \ + .analog_en(vss), \ + .analog_sel(vss), \ + .analog_pol(vss), \ + .dm({vdd1v8, vdd1v8, vss}), \ + .pad_a_noesd_h(), \ + .pad_a_esd_0_h(), \ + .pad_a_esd_1_h(), \ + .in(), \ + .in_h(), \ + .tie_hi_esd(), \ + .tie_lo_esd(loop_``X)) + +`define INOUT_PAD_V(X,Y,Y_OUT,V,INP_DIS,OUT_EN_N,MODE) \ + wire [V-1:0] loop_``X; \ + s8iom0_gpiov2_pad X``_pad [V-1:0] ( \ + `ABUTMENT_PINS \ + `ifndef TOP_ROUTING \ + .pad(X),\ + `endif \ + .out(Y_OUT), \ + .oe_n(OUT_EN_N), \ + .hld_h_n(vdd), \ + .enable_h(porb_h), \ + .enable_inp_h(loop_``X), \ + .enable_vdda_h(porb_h), \ + .enable_vswitch_h(vss), \ + .enable_vddio(vdd1v8), \ + .inp_dis(INP_DIS), \ + .ib_mode_sel(vss), \ + .vtrip_sel(vss), \ + .slow(vss), \ + .hld_ovr(vss), \ + .analog_en(vss), \ + .analog_sel(vss), \ + .analog_pol(vss), \ + .dm(MODE), \ + .pad_a_noesd_h(), \ + .pad_a_esd_0_h(), \ + .pad_a_esd_1_h(), \ + .in(Y), \ + .in_h(), \ + .tie_hi_esd(), \ + .tie_lo_esd(loop_``X) ) + +`define INOUT_PAD(X,Y,Y_OUT,INP_DIS,OUT_EN_N,MODE) \ + s8iom0_gpiov2_pad X``_pad ( \ + `ABUTMENT_PINS \ + `ifndef TOP_ROUTING \ + .pad(X),\ + `endif \ + .out(Y_OUT), \ + .oe_n(OUT_EN_N), \ + .hld_h_n(vdd), \ + .enable_h(porb_h), \ + .enable_inp_h(loop_``X), \ + .enable_vdda_h(porb_h), \ + .enable_vswitch_h(vss), \ + .enable_vddio(vdd1v8), \ + .inp_dis(INP_DIS), \ + .ib_mode_sel(vss), \ + .vtrip_sel(vss), \ + .slow(vss), \ + .hld_ovr(vss), \ + .analog_en(vss), \ + .analog_sel(vss), \ + .analog_pol(vss), \ + .dm(MODE), \ + .pad_a_noesd_h(), \ + .pad_a_esd_0_h(), \ + .pad_a_esd_1_h(), \ + .in(Y), \ + .in_h(), \ + .tie_hi_esd(), \ + .tie_lo_esd(loop_``X) ) + +`define MPRJ_IO_PAD_V(X,Y,Y_OUT,V,OUT_EN_N,HLD_N, ENH, INP_DIS, MODE_SEL, AN_EN, AN_SEL, AN_POL, MODE) \ + wire [V-1:0] loop_``X; \ + s8iom0_gpiov2_pad X``_pad [V-1:0] ( \ + `ABUTMENT_PINS \ + `ifndef TOP_ROUTING \ + .pad(X),\ + `endif \ + .out(Y_OUT), \ + .oe_n(OUT_EN_N), \ + .hld_h_n(HLD_N), \ + .enable_h(ENH), \ + .enable_inp_h(loop_``X), \ + .enable_vdda_h(porb_h), \ + .enable_vswitch_h(vss), \ + .enable_vddio(vdd1v8), \ + .inp_dis(INP_DIS), \ + .ib_mode_sel(MODE_SEL), \ + .vtrip_sel(vss), \ + .slow(vss), \ + .hld_ovr(vss), \ + .analog_en(AN_EN), \ + .analog_sel(AN_SEL), \ + .analog_pol(AN_POL), \ + .dm(MODE), \ + .pad_a_noesd_h(), \ + .pad_a_esd_0_h(), \ + .pad_a_esd_1_h(), \ + .in(Y), \ + .in_h(), \ + .tie_hi_esd(), \ + .tie_lo_esd(loop_``X) ) + +`define I2C_RX(X,Y) \ + wire loop_``X; \ + s8iom0s8_top_gpio_ovtv2 X``_pad ( \ + `ABUTMENT_PINS \ + `ifndef TOP_ROUTING \ + .pad(X), \ + `endif \ + .out(vss), \ + .oe_n(vdd1v8), \ + .hld_h_n(vdd), \ + .enable_h(porb_h), \ + .enable_inp_h(loop_``X), \ + .enable_vdda_h(porb_h), \ + .enable_vddio(vdd1v8), \ + .enable_vswitch_h(vss), \ + .inp_dis(por), \ + .vtrip_sel(vss), \ + .hys_trim(vdd1v8), \ + .slow(vss), \ + .slew_ctl({vss, vss}), \ // 2 bits + .hld_ovr(vss), \ + .analog_en(vss), \ + .analog_sel(vss), \ + .analog_pol(vss), \ + .dm({vss, vss, vdd1v8}), \ // 3 bits + .ib_mode_sel({vss, vss}), \ // 2 bits + .vinref(vdd1v8), \ + .pad_a_noesd_h(), \ + .pad_a_esd_0_h(), \ + .pad_a_esd_1_h(), \ + .in(Y), \ + .in_h(), \ + .tie_hi_esd(), \ + .tie_lo_esd() ) + +`define I2C_TX(X,Y) \ + wire loop_``X; \ + s8iom0s8_top_gpio_ovtv2 X``_pad ( \ + `ABUTMENT_PINS \ + `ifndef TOP_ROUTING \ + .pad(X), \ + `endif \ + .out(Y), \ + .oe_n(vss), \ + .hld_h_n(vdd), \ + .enable_h(porb_h), \ + .enable_inp_h(loop_``X), \ + .enable_vdda_h(porb_h), \ + .enable_vddio(vdd1v8), \ + .enable_vswitch_h(vss), \ + .inp_dis(vdd1v8), \ + .vtrip_sel(vss), \ + .hys_trim(vdd1v8), \ + .slow(vss), \ + .slew_ctl({vss, vss}), \ // 2 bits + .hld_ovr(vss), \ + .analog_en(vss), \ + .analog_sel(vss), \ + .analog_pol(vss), \ + .dm({vdd1v8, vdd1v8, vss}), \ // 3 bits + .ib_mode_sel({vss, vss}), \ // 2 bits + .vinref(vdd1v8), \ + .pad_a_noesd_h(), \ + .pad_a_esd_0_h(), \ + .pad_a_esd_1_h(), \ + .in(), \ + .in_h(), \ + .tie_hi_esd(), \ + .tie_lo_esd())
diff --git a/verilog/rtl/sram_1rw1r_32_256_8_sky130.v b/verilog/rtl/sram_1rw1r_32_8192_8_sky130.v similarity index 96% rename from verilog/rtl/sram_1rw1r_32_256_8_sky130.v rename to verilog/rtl/sram_1rw1r_32_8192_8_sky130.v index 2dd1c62..dfd9a45 100644 --- a/verilog/rtl/sram_1rw1r_32_256_8_sky130.v +++ b/verilog/rtl/sram_1rw1r_32_8192_8_sky130.v
@@ -1,9 +1,9 @@ // OpenRAM SRAM model -// Words: 256 +// Words: 8192 // Word size: 32 // Write size: 8 -module sram_1rw1r_32_256_8_sky130( +module sram_1rw1r_32_8192_8_sky130( // Port 0: RW clk0,csb0,web0,wmask0,addr0,din0,dout0, // Port 1: R @@ -12,7 +12,7 @@ parameter NUM_WMASKS = 4 ; parameter DATA_WIDTH = 32 ; - parameter ADDR_WIDTH = 8 ; + parameter ADDR_WIDTH = 13 ; parameter RAM_DEPTH = 1 << ADDR_WIDTH; // FIXME: This delay is arbitrary. parameter DELAY = 1 ;
