| module ibex_if_stage ( |
| clk_i, |
| rst_ni, |
| boot_addr_i, |
| req_i, |
| instr_req_o, |
| instr_addr_o, |
| instr_gnt_i, |
| instr_rvalid_i, |
| instr_rdata_i, |
| instr_err_i, |
| instr_pmp_err_i, |
| instr_valid_id_o, |
| instr_new_id_o, |
| instr_rdata_id_o, |
| instr_rdata_alu_id_o, |
| instr_rdata_c_id_o, |
| instr_is_compressed_id_o, |
| instr_bp_taken_o, |
| instr_fetch_err_o, |
| instr_fetch_err_plus2_o, |
| illegal_c_insn_id_o, |
| dummy_instr_id_o, |
| pc_if_o, |
| pc_id_o, |
| instr_valid_clear_i, |
| pc_set_i, |
| pc_set_spec_i, |
| pc_mux_i, |
| nt_branch_mispredict_i, |
| exc_pc_mux_i, |
| exc_cause, |
| dummy_instr_en_i, |
| dummy_instr_mask_i, |
| dummy_instr_seed_en_i, |
| dummy_instr_seed_i, |
| icache_enable_i, |
| icache_inval_i, |
| branch_target_ex_i, |
| csr_mepc_i, |
| csr_depc_i, |
| csr_mtvec_i, |
| csr_mtvec_init_o, |
| id_in_ready_i, |
| pc_mismatch_alert_o, |
| if_busy_o |
| ); |
| parameter [31:0] DmHaltAddr = 32'h1a110800; |
| parameter [31:0] DmExceptionAddr = 32'h1a110808; |
| parameter [0:0] DummyInstructions = 1'b0; |
| parameter [0:0] ICache = 1'b0; |
| parameter [0:0] ICacheECC = 1'b0; |
| parameter [0:0] PCIncrCheck = 1'b0; |
| parameter [0:0] BranchPredictor = 1'b0; |
| input wire clk_i; |
| input wire rst_ni; |
| input wire [31:0] boot_addr_i; |
| input wire req_i; |
| output wire instr_req_o; |
| output wire [31:0] instr_addr_o; |
| input wire instr_gnt_i; |
| input wire instr_rvalid_i; |
| input wire [31:0] instr_rdata_i; |
| input wire instr_err_i; |
| input wire instr_pmp_err_i; |
| output wire instr_valid_id_o; |
| output wire instr_new_id_o; |
| output reg [31:0] instr_rdata_id_o; |
| output reg [31:0] instr_rdata_alu_id_o; |
| output reg [15:0] instr_rdata_c_id_o; |
| output reg instr_is_compressed_id_o; |
| output wire instr_bp_taken_o; |
| output reg instr_fetch_err_o; |
| output reg instr_fetch_err_plus2_o; |
| output reg illegal_c_insn_id_o; |
| output reg dummy_instr_id_o; |
| output wire [31:0] pc_if_o; |
| output reg [31:0] pc_id_o; |
| input wire instr_valid_clear_i; |
| input wire pc_set_i; |
| input wire pc_set_spec_i; |
| input wire [2:0] pc_mux_i; |
| input wire nt_branch_mispredict_i; |
| input wire [1:0] exc_pc_mux_i; |
| input wire [5:0] exc_cause; |
| input wire dummy_instr_en_i; |
| input wire [2:0] dummy_instr_mask_i; |
| input wire dummy_instr_seed_en_i; |
| input wire [31:0] dummy_instr_seed_i; |
| input wire icache_enable_i; |
| input wire icache_inval_i; |
| input wire [31:0] branch_target_ex_i; |
| input wire [31:0] csr_mepc_i; |
| input wire [31:0] csr_depc_i; |
| input wire [31:0] csr_mtvec_i; |
| output wire csr_mtvec_init_o; |
| input wire id_in_ready_i; |
| output wire pc_mismatch_alert_o; |
| output wire if_busy_o; |
| localparam integer RegFileFF = 0; |
| localparam integer RegFileFPGA = 1; |
| localparam integer RegFileLatch = 2; |
| localparam integer RV32MNone = 0; |
| localparam integer RV32MSlow = 1; |
| localparam integer RV32MFast = 2; |
| localparam integer RV32MSingleCycle = 3; |
| localparam integer RV32BNone = 0; |
| localparam integer RV32BBalanced = 1; |
| localparam integer RV32BFull = 2; |
| localparam [6:0] OPCODE_LOAD = 7'h03; |
| localparam [6:0] OPCODE_MISC_MEM = 7'h0f; |
| localparam [6:0] OPCODE_OP_IMM = 7'h13; |
| localparam [6:0] OPCODE_AUIPC = 7'h17; |
| localparam [6:0] OPCODE_STORE = 7'h23; |
| localparam [6:0] OPCODE_OP = 7'h33; |
| localparam [6:0] OPCODE_LUI = 7'h37; |
| localparam [6:0] OPCODE_BRANCH = 7'h63; |
| localparam [6:0] OPCODE_JALR = 7'h67; |
| localparam [6:0] OPCODE_JAL = 7'h6f; |
| localparam [6:0] OPCODE_SYSTEM = 7'h73; |
| localparam [5:0] ALU_ADD = 0; |
| localparam [5:0] ALU_SUB = 1; |
| localparam [5:0] ALU_XOR = 2; |
| localparam [5:0] ALU_OR = 3; |
| localparam [5:0] ALU_AND = 4; |
| localparam [5:0] ALU_XNOR = 5; |
| localparam [5:0] ALU_ORN = 6; |
| localparam [5:0] ALU_ANDN = 7; |
| localparam [5:0] ALU_SRA = 8; |
| localparam [5:0] ALU_SRL = 9; |
| localparam [5:0] ALU_SLL = 10; |
| localparam [5:0] ALU_SRO = 11; |
| localparam [5:0] ALU_SLO = 12; |
| localparam [5:0] ALU_ROR = 13; |
| localparam [5:0] ALU_ROL = 14; |
| localparam [5:0] ALU_GREV = 15; |
| localparam [5:0] ALU_GORC = 16; |
| localparam [5:0] ALU_SHFL = 17; |
| localparam [5:0] ALU_UNSHFL = 18; |
| localparam [5:0] ALU_LT = 19; |
| localparam [5:0] ALU_LTU = 20; |
| localparam [5:0] ALU_GE = 21; |
| localparam [5:0] ALU_GEU = 22; |
| localparam [5:0] ALU_EQ = 23; |
| localparam [5:0] ALU_NE = 24; |
| localparam [5:0] ALU_MIN = 25; |
| localparam [5:0] ALU_MINU = 26; |
| localparam [5:0] ALU_MAX = 27; |
| localparam [5:0] ALU_MAXU = 28; |
| localparam [5:0] ALU_PACK = 29; |
| localparam [5:0] ALU_PACKU = 30; |
| localparam [5:0] ALU_PACKH = 31; |
| localparam [5:0] ALU_SEXTB = 32; |
| localparam [5:0] ALU_SEXTH = 33; |
| localparam [5:0] ALU_CLZ = 34; |
| localparam [5:0] ALU_CTZ = 35; |
| localparam [5:0] ALU_PCNT = 36; |
| localparam [5:0] ALU_SLT = 37; |
| localparam [5:0] ALU_SLTU = 38; |
| localparam [5:0] ALU_CMOV = 39; |
| localparam [5:0] ALU_CMIX = 40; |
| localparam [5:0] ALU_FSL = 41; |
| localparam [5:0] ALU_FSR = 42; |
| localparam [5:0] ALU_SBSET = 43; |
| localparam [5:0] ALU_SBCLR = 44; |
| localparam [5:0] ALU_SBINV = 45; |
| localparam [5:0] ALU_SBEXT = 46; |
| localparam [5:0] ALU_BEXT = 47; |
| localparam [5:0] ALU_BDEP = 48; |
| localparam [5:0] ALU_BFP = 49; |
| localparam [5:0] ALU_CLMUL = 50; |
| localparam [5:0] ALU_CLMULR = 51; |
| localparam [5:0] ALU_CLMULH = 52; |
| localparam [5:0] ALU_CRC32_B = 53; |
| localparam [5:0] ALU_CRC32C_B = 54; |
| localparam [5:0] ALU_CRC32_H = 55; |
| localparam [5:0] ALU_CRC32C_H = 56; |
| localparam [5:0] ALU_CRC32_W = 57; |
| localparam [5:0] ALU_CRC32C_W = 58; |
| localparam [1:0] MD_OP_MULL = 0; |
| localparam [1:0] MD_OP_MULH = 1; |
| localparam [1:0] MD_OP_DIV = 2; |
| localparam [1:0] MD_OP_REM = 3; |
| localparam [1:0] CSR_OP_READ = 0; |
| localparam [1:0] CSR_OP_WRITE = 1; |
| localparam [1:0] CSR_OP_SET = 2; |
| localparam [1:0] CSR_OP_CLEAR = 3; |
| localparam [1:0] PRIV_LVL_M = 2'b11; |
| localparam [1:0] PRIV_LVL_H = 2'b10; |
| localparam [1:0] PRIV_LVL_S = 2'b01; |
| localparam [1:0] PRIV_LVL_U = 2'b00; |
| localparam [3:0] XDEBUGVER_NO = 4'd0; |
| localparam [3:0] XDEBUGVER_STD = 4'd4; |
| localparam [3:0] XDEBUGVER_NONSTD = 4'd15; |
| localparam [1:0] WB_INSTR_LOAD = 0; |
| localparam [1:0] WB_INSTR_STORE = 1; |
| localparam [1:0] WB_INSTR_OTHER = 2; |
| localparam [1:0] OP_A_REG_A = 0; |
| localparam [1:0] OP_A_FWD = 1; |
| localparam [1:0] OP_A_CURRPC = 2; |
| localparam [1:0] OP_A_IMM = 3; |
| localparam [0:0] IMM_A_Z = 0; |
| localparam [0:0] IMM_A_ZERO = 1; |
| localparam [0:0] OP_B_REG_B = 0; |
| localparam [0:0] OP_B_IMM = 1; |
| localparam [2:0] IMM_B_I = 0; |
| localparam [2:0] IMM_B_S = 1; |
| localparam [2:0] IMM_B_B = 2; |
| localparam [2:0] IMM_B_U = 3; |
| localparam [2:0] IMM_B_J = 4; |
| localparam [2:0] IMM_B_INCR_PC = 5; |
| localparam [2:0] IMM_B_INCR_ADDR = 6; |
| localparam [0:0] RF_WD_EX = 0; |
| localparam [0:0] RF_WD_CSR = 1; |
| localparam [2:0] PC_BOOT = 0; |
| localparam [2:0] PC_JUMP = 1; |
| localparam [2:0] PC_EXC = 2; |
| localparam [2:0] PC_ERET = 3; |
| localparam [2:0] PC_DRET = 4; |
| localparam [2:0] PC_BP = 5; |
| localparam [1:0] EXC_PC_EXC = 0; |
| localparam [1:0] EXC_PC_IRQ = 1; |
| localparam [1:0] EXC_PC_DBD = 2; |
| localparam [1:0] EXC_PC_DBG_EXC = 3; |
| localparam [5:0] EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd3}; |
| localparam [5:0] EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd7}; |
| localparam [5:0] EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11}; |
| localparam [5:0] EXC_CAUSE_IRQ_NM = {1'b1, 5'd31}; |
| localparam [5:0] EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd0}; |
| localparam [5:0] EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd1}; |
| localparam [5:0] EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd2}; |
| localparam [5:0] EXC_CAUSE_BREAKPOINT = {1'b0, 5'd3}; |
| localparam [5:0] EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd5}; |
| localparam [5:0] EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd7}; |
| localparam [5:0] EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd8}; |
| localparam [5:0] EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11}; |
| localparam [2:0] DBG_CAUSE_NONE = 3'h0; |
| localparam [2:0] DBG_CAUSE_EBREAK = 3'h1; |
| localparam [2:0] DBG_CAUSE_TRIGGER = 3'h2; |
| localparam [2:0] DBG_CAUSE_HALTREQ = 3'h3; |
| localparam [2:0] DBG_CAUSE_STEP = 3'h4; |
| localparam [31:0] PMP_MAX_REGIONS = 16; |
| localparam [31:0] PMP_CFG_W = 8; |
| localparam [31:0] PMP_I = 0; |
| localparam [31:0] PMP_D = 1; |
| localparam [1:0] PMP_ACC_EXEC = 2'b00; |
| localparam [1:0] PMP_ACC_WRITE = 2'b01; |
| localparam [1:0] PMP_ACC_READ = 2'b10; |
| localparam [1:0] PMP_MODE_OFF = 2'b00; |
| localparam [1:0] PMP_MODE_TOR = 2'b01; |
| localparam [1:0] PMP_MODE_NA4 = 2'b10; |
| localparam [1:0] PMP_MODE_NAPOT = 2'b11; |
| localparam [11:0] CSR_MHARTID = 12'hf14; |
| localparam [11:0] CSR_MSTATUS = 12'h300; |
| localparam [11:0] CSR_MISA = 12'h301; |
| localparam [11:0] CSR_MIE = 12'h304; |
| localparam [11:0] CSR_MTVEC = 12'h305; |
| localparam [11:0] CSR_MSCRATCH = 12'h340; |
| localparam [11:0] CSR_MEPC = 12'h341; |
| localparam [11:0] CSR_MCAUSE = 12'h342; |
| localparam [11:0] CSR_MTVAL = 12'h343; |
| localparam [11:0] CSR_MIP = 12'h344; |
| localparam [11:0] CSR_PMPCFG0 = 12'h3a0; |
| localparam [11:0] CSR_PMPCFG1 = 12'h3a1; |
| localparam [11:0] CSR_PMPCFG2 = 12'h3a2; |
| localparam [11:0] CSR_PMPCFG3 = 12'h3a3; |
| localparam [11:0] CSR_PMPADDR0 = 12'h3b0; |
| localparam [11:0] CSR_PMPADDR1 = 12'h3b1; |
| localparam [11:0] CSR_PMPADDR2 = 12'h3b2; |
| localparam [11:0] CSR_PMPADDR3 = 12'h3b3; |
| localparam [11:0] CSR_PMPADDR4 = 12'h3b4; |
| localparam [11:0] CSR_PMPADDR5 = 12'h3b5; |
| localparam [11:0] CSR_PMPADDR6 = 12'h3b6; |
| localparam [11:0] CSR_PMPADDR7 = 12'h3b7; |
| localparam [11:0] CSR_PMPADDR8 = 12'h3b8; |
| localparam [11:0] CSR_PMPADDR9 = 12'h3b9; |
| localparam [11:0] CSR_PMPADDR10 = 12'h3ba; |
| localparam [11:0] CSR_PMPADDR11 = 12'h3bb; |
| localparam [11:0] CSR_PMPADDR12 = 12'h3bc; |
| localparam [11:0] CSR_PMPADDR13 = 12'h3bd; |
| localparam [11:0] CSR_PMPADDR14 = 12'h3be; |
| localparam [11:0] CSR_PMPADDR15 = 12'h3bf; |
| localparam [11:0] CSR_TSELECT = 12'h7a0; |
| localparam [11:0] CSR_TDATA1 = 12'h7a1; |
| localparam [11:0] CSR_TDATA2 = 12'h7a2; |
| localparam [11:0] CSR_TDATA3 = 12'h7a3; |
| localparam [11:0] CSR_MCONTEXT = 12'h7a8; |
| localparam [11:0] CSR_SCONTEXT = 12'h7aa; |
| localparam [11:0] CSR_DCSR = 12'h7b0; |
| localparam [11:0] CSR_DPC = 12'h7b1; |
| localparam [11:0] CSR_DSCRATCH0 = 12'h7b2; |
| localparam [11:0] CSR_DSCRATCH1 = 12'h7b3; |
| localparam [11:0] CSR_MCOUNTINHIBIT = 12'h320; |
| localparam [11:0] CSR_MHPMEVENT3 = 12'h323; |
| localparam [11:0] CSR_MHPMEVENT4 = 12'h324; |
| localparam [11:0] CSR_MHPMEVENT5 = 12'h325; |
| localparam [11:0] CSR_MHPMEVENT6 = 12'h326; |
| localparam [11:0] CSR_MHPMEVENT7 = 12'h327; |
| localparam [11:0] CSR_MHPMEVENT8 = 12'h328; |
| localparam [11:0] CSR_MHPMEVENT9 = 12'h329; |
| localparam [11:0] CSR_MHPMEVENT10 = 12'h32a; |
| localparam [11:0] CSR_MHPMEVENT11 = 12'h32b; |
| localparam [11:0] CSR_MHPMEVENT12 = 12'h32c; |
| localparam [11:0] CSR_MHPMEVENT13 = 12'h32d; |
| localparam [11:0] CSR_MHPMEVENT14 = 12'h32e; |
| localparam [11:0] CSR_MHPMEVENT15 = 12'h32f; |
| localparam [11:0] CSR_MHPMEVENT16 = 12'h330; |
| localparam [11:0] CSR_MHPMEVENT17 = 12'h331; |
| localparam [11:0] CSR_MHPMEVENT18 = 12'h332; |
| localparam [11:0] CSR_MHPMEVENT19 = 12'h333; |
| localparam [11:0] CSR_MHPMEVENT20 = 12'h334; |
| localparam [11:0] CSR_MHPMEVENT21 = 12'h335; |
| localparam [11:0] CSR_MHPMEVENT22 = 12'h336; |
| localparam [11:0] CSR_MHPMEVENT23 = 12'h337; |
| localparam [11:0] CSR_MHPMEVENT24 = 12'h338; |
| localparam [11:0] CSR_MHPMEVENT25 = 12'h339; |
| localparam [11:0] CSR_MHPMEVENT26 = 12'h33a; |
| localparam [11:0] CSR_MHPMEVENT27 = 12'h33b; |
| localparam [11:0] CSR_MHPMEVENT28 = 12'h33c; |
| localparam [11:0] CSR_MHPMEVENT29 = 12'h33d; |
| localparam [11:0] CSR_MHPMEVENT30 = 12'h33e; |
| localparam [11:0] CSR_MHPMEVENT31 = 12'h33f; |
| localparam [11:0] CSR_MCYCLE = 12'hb00; |
| localparam [11:0] CSR_MINSTRET = 12'hb02; |
| localparam [11:0] CSR_MHPMCOUNTER3 = 12'hb03; |
| localparam [11:0] CSR_MHPMCOUNTER4 = 12'hb04; |
| localparam [11:0] CSR_MHPMCOUNTER5 = 12'hb05; |
| localparam [11:0] CSR_MHPMCOUNTER6 = 12'hb06; |
| localparam [11:0] CSR_MHPMCOUNTER7 = 12'hb07; |
| localparam [11:0] CSR_MHPMCOUNTER8 = 12'hb08; |
| localparam [11:0] CSR_MHPMCOUNTER9 = 12'hb09; |
| localparam [11:0] CSR_MHPMCOUNTER10 = 12'hb0a; |
| localparam [11:0] CSR_MHPMCOUNTER11 = 12'hb0b; |
| localparam [11:0] CSR_MHPMCOUNTER12 = 12'hb0c; |
| localparam [11:0] CSR_MHPMCOUNTER13 = 12'hb0d; |
| localparam [11:0] CSR_MHPMCOUNTER14 = 12'hb0e; |
| localparam [11:0] CSR_MHPMCOUNTER15 = 12'hb0f; |
| localparam [11:0] CSR_MHPMCOUNTER16 = 12'hb10; |
| localparam [11:0] CSR_MHPMCOUNTER17 = 12'hb11; |
| localparam [11:0] CSR_MHPMCOUNTER18 = 12'hb12; |
| localparam [11:0] CSR_MHPMCOUNTER19 = 12'hb13; |
| localparam [11:0] CSR_MHPMCOUNTER20 = 12'hb14; |
| localparam [11:0] CSR_MHPMCOUNTER21 = 12'hb15; |
| localparam [11:0] CSR_MHPMCOUNTER22 = 12'hb16; |
| localparam [11:0] CSR_MHPMCOUNTER23 = 12'hb17; |
| localparam [11:0] CSR_MHPMCOUNTER24 = 12'hb18; |
| localparam [11:0] CSR_MHPMCOUNTER25 = 12'hb19; |
| localparam [11:0] CSR_MHPMCOUNTER26 = 12'hb1a; |
| localparam [11:0] CSR_MHPMCOUNTER27 = 12'hb1b; |
| localparam [11:0] CSR_MHPMCOUNTER28 = 12'hb1c; |
| localparam [11:0] CSR_MHPMCOUNTER29 = 12'hb1d; |
| localparam [11:0] CSR_MHPMCOUNTER30 = 12'hb1e; |
| localparam [11:0] CSR_MHPMCOUNTER31 = 12'hb1f; |
| localparam [11:0] CSR_MCYCLEH = 12'hb80; |
| localparam [11:0] CSR_MINSTRETH = 12'hb82; |
| localparam [11:0] CSR_MHPMCOUNTER3H = 12'hb83; |
| localparam [11:0] CSR_MHPMCOUNTER4H = 12'hb84; |
| localparam [11:0] CSR_MHPMCOUNTER5H = 12'hb85; |
| localparam [11:0] CSR_MHPMCOUNTER6H = 12'hb86; |
| localparam [11:0] CSR_MHPMCOUNTER7H = 12'hb87; |
| localparam [11:0] CSR_MHPMCOUNTER8H = 12'hb88; |
| localparam [11:0] CSR_MHPMCOUNTER9H = 12'hb89; |
| localparam [11:0] CSR_MHPMCOUNTER10H = 12'hb8a; |
| localparam [11:0] CSR_MHPMCOUNTER11H = 12'hb8b; |
| localparam [11:0] CSR_MHPMCOUNTER12H = 12'hb8c; |
| localparam [11:0] CSR_MHPMCOUNTER13H = 12'hb8d; |
| localparam [11:0] CSR_MHPMCOUNTER14H = 12'hb8e; |
| localparam [11:0] CSR_MHPMCOUNTER15H = 12'hb8f; |
| localparam [11:0] CSR_MHPMCOUNTER16H = 12'hb90; |
| localparam [11:0] CSR_MHPMCOUNTER17H = 12'hb91; |
| localparam [11:0] CSR_MHPMCOUNTER18H = 12'hb92; |
| localparam [11:0] CSR_MHPMCOUNTER19H = 12'hb93; |
| localparam [11:0] CSR_MHPMCOUNTER20H = 12'hb94; |
| localparam [11:0] CSR_MHPMCOUNTER21H = 12'hb95; |
| localparam [11:0] CSR_MHPMCOUNTER22H = 12'hb96; |
| localparam [11:0] CSR_MHPMCOUNTER23H = 12'hb97; |
| localparam [11:0] CSR_MHPMCOUNTER24H = 12'hb98; |
| localparam [11:0] CSR_MHPMCOUNTER25H = 12'hb99; |
| localparam [11:0] CSR_MHPMCOUNTER26H = 12'hb9a; |
| localparam [11:0] CSR_MHPMCOUNTER27H = 12'hb9b; |
| localparam [11:0] CSR_MHPMCOUNTER28H = 12'hb9c; |
| localparam [11:0] CSR_MHPMCOUNTER29H = 12'hb9d; |
| localparam [11:0] CSR_MHPMCOUNTER30H = 12'hb9e; |
| localparam [11:0] CSR_MHPMCOUNTER31H = 12'hb9f; |
| localparam [11:0] CSR_CPUCTRL = 12'h7c0; |
| localparam [11:0] CSR_SECURESEED = 12'h7c1; |
| localparam [11:0] CSR_OFF_PMP_CFG = 12'h3a0; |
| localparam [11:0] CSR_OFF_PMP_ADDR = 12'h3b0; |
| localparam [31:0] CSR_MSTATUS_MIE_BIT = 3; |
| localparam [31:0] CSR_MSTATUS_MPIE_BIT = 7; |
| localparam [31:0] CSR_MSTATUS_MPP_BIT_LOW = 11; |
| localparam [31:0] CSR_MSTATUS_MPP_BIT_HIGH = 12; |
| localparam [31:0] CSR_MSTATUS_MPRV_BIT = 17; |
| localparam [31:0] CSR_MSTATUS_TW_BIT = 21; |
| localparam [1:0] CSR_MISA_MXL = 2'd1; |
| localparam [31:0] CSR_MSIX_BIT = 3; |
| localparam [31:0] CSR_MTIX_BIT = 7; |
| localparam [31:0] CSR_MEIX_BIT = 11; |
| localparam [31:0] CSR_MFIX_BIT_LOW = 16; |
| localparam [31:0] CSR_MFIX_BIT_HIGH = 30; |
| wire instr_valid_id_d; |
| reg instr_valid_id_q; |
| wire instr_new_id_d; |
| reg instr_new_id_q; |
| wire prefetch_busy; |
| wire branch_req; |
| wire branch_spec; |
| wire predicted_branch; |
| reg [31:0] fetch_addr_n; |
| wire unused_fetch_addr_n0; |
| wire fetch_valid; |
| wire fetch_ready; |
| wire [31:0] fetch_rdata; |
| wire [31:0] fetch_addr; |
| wire fetch_err; |
| wire fetch_err_plus2; |
| wire if_instr_valid; |
| wire [31:0] if_instr_rdata; |
| wire [31:0] if_instr_addr; |
| wire if_instr_err; |
| reg [31:0] exc_pc; |
| wire [5:0] irq_id; |
| wire unused_irq_bit; |
| wire if_id_pipe_reg_we; |
| wire stall_dummy_instr; |
| wire [31:0] instr_out; |
| wire instr_is_compressed_out; |
| wire illegal_c_instr_out; |
| wire instr_err_out; |
| wire predict_branch_taken; |
| wire [31:0] predict_branch_pc; |
| wire [2:0] pc_mux_internal; |
| wire [7:0] unused_boot_addr; |
| wire [7:0] unused_csr_mtvec; |
| assign unused_boot_addr = boot_addr_i[7:0]; |
| assign unused_csr_mtvec = csr_mtvec_i[7:0]; |
| assign irq_id = exc_cause; |
| assign unused_irq_bit = irq_id[5]; |
| always @(*) begin : exc_pc_mux |
| case (exc_pc_mux_i) |
| EXC_PC_EXC: exc_pc = {csr_mtvec_i[31:8], 8'h00}; |
| EXC_PC_IRQ: exc_pc = {csr_mtvec_i[31:8], 1'b0, irq_id[4:0], 2'b00}; |
| EXC_PC_DBD: exc_pc = DmHaltAddr; |
| EXC_PC_DBG_EXC: exc_pc = DmExceptionAddr; |
| default: exc_pc = {csr_mtvec_i[31:8], 8'h00}; |
| endcase |
| end |
| assign pc_mux_internal = ((BranchPredictor && predict_branch_taken) && !pc_set_i ? PC_BP : pc_mux_i); |
| always @(*) begin : fetch_addr_mux |
| case (pc_mux_internal) |
| PC_BOOT: fetch_addr_n = {boot_addr_i[31:8], 8'h80}; |
| PC_JUMP: fetch_addr_n = branch_target_ex_i; |
| PC_EXC: fetch_addr_n = exc_pc; |
| PC_ERET: fetch_addr_n = csr_mepc_i; |
| PC_DRET: fetch_addr_n = csr_depc_i; |
| PC_BP: fetch_addr_n = (BranchPredictor ? predict_branch_pc : {boot_addr_i[31:8], 8'h80}); |
| default: fetch_addr_n = {boot_addr_i[31:8], 8'h80}; |
| endcase |
| end |
| assign csr_mtvec_init_o = (pc_mux_i == PC_BOOT) & pc_set_i; |
| generate |
| if (ICache) begin : gen_icache |
| ibex_icache #(.ICacheECC(ICacheECC)) icache_i( |
| .clk_i(clk_i), |
| .rst_ni(rst_ni), |
| .req_i(req_i), |
| .branch_i(branch_req), |
| .branch_spec_i(branch_spec), |
| .addr_i({fetch_addr_n[31:1], 1'b0}), |
| .ready_i(fetch_ready), |
| .valid_o(fetch_valid), |
| .rdata_o(fetch_rdata), |
| .addr_o(fetch_addr), |
| .err_o(fetch_err), |
| .err_plus2_o(fetch_err_plus2), |
| .instr_req_o(instr_req_o), |
| .instr_addr_o(instr_addr_o), |
| .instr_gnt_i(instr_gnt_i), |
| .instr_rvalid_i(instr_rvalid_i), |
| .instr_rdata_i(instr_rdata_i), |
| .instr_err_i(instr_err_i), |
| .instr_pmp_err_i(instr_pmp_err_i), |
| .icache_enable_i(icache_enable_i), |
| .icache_inval_i(icache_inval_i), |
| .busy_o(prefetch_busy) |
| ); |
| wire unused_nt_branch_mispredict; |
| wire unused_predicted_branch; |
| assign unused_nt_branch_mispredict = nt_branch_mispredict_i; |
| assign unused_predicted_branch = predicted_branch; |
| end |
| else begin : gen_prefetch_buffer |
| ibex_prefetch_buffer #(.BranchPredictor(BranchPredictor)) prefetch_buffer_i( |
| .clk_i(clk_i), |
| .rst_ni(rst_ni), |
| .req_i(req_i), |
| .branch_i(branch_req), |
| .branch_spec_i(branch_spec), |
| .predicted_branch_i(predicted_branch), |
| .branch_mispredict_i(nt_branch_mispredict_i), |
| .addr_i({fetch_addr_n[31:1], 1'b0}), |
| .ready_i(fetch_ready), |
| .valid_o(fetch_valid), |
| .rdata_o(fetch_rdata), |
| .addr_o(fetch_addr), |
| .err_o(fetch_err), |
| .err_plus2_o(fetch_err_plus2), |
| .instr_req_o(instr_req_o), |
| .instr_addr_o(instr_addr_o), |
| .instr_gnt_i(instr_gnt_i), |
| .instr_rvalid_i(instr_rvalid_i), |
| .instr_rdata_i(instr_rdata_i), |
| .instr_err_i(instr_err_i), |
| .instr_pmp_err_i(instr_pmp_err_i), |
| .busy_o(prefetch_busy) |
| ); |
| wire unused_icen; |
| wire unused_icinv; |
| assign unused_icen = icache_enable_i; |
| assign unused_icinv = icache_inval_i; |
| end |
| endgenerate |
| assign unused_fetch_addr_n0 = fetch_addr_n[0]; |
| assign branch_req = pc_set_i | predict_branch_taken; |
| assign branch_spec = pc_set_spec_i | predict_branch_taken; |
| assign pc_if_o = if_instr_addr; |
| assign if_busy_o = prefetch_busy; |
| wire [31:0] instr_decompressed; |
| wire illegal_c_insn; |
| wire instr_is_compressed; |
| ibex_compressed_decoder compressed_decoder_i( |
| .clk_i(clk_i), |
| .rst_ni(rst_ni), |
| .valid_i(fetch_valid & ~fetch_err), |
| .instr_i(if_instr_rdata), |
| .instr_o(instr_decompressed), |
| .is_compressed_o(instr_is_compressed), |
| .illegal_instr_o(illegal_c_insn) |
| ); |
| generate |
| if (DummyInstructions) begin : gen_dummy_instr |
| wire insert_dummy_instr; |
| wire [31:0] dummy_instr_data; |
| ibex_dummy_instr dummy_instr_i( |
| .clk_i(clk_i), |
| .rst_ni(rst_ni), |
| .dummy_instr_en_i(dummy_instr_en_i), |
| .dummy_instr_mask_i(dummy_instr_mask_i), |
| .dummy_instr_seed_en_i(dummy_instr_seed_en_i), |
| .dummy_instr_seed_i(dummy_instr_seed_i), |
| .fetch_valid_i(fetch_valid), |
| .id_in_ready_i(id_in_ready_i), |
| .insert_dummy_instr_o(insert_dummy_instr), |
| .dummy_instr_data_o(dummy_instr_data) |
| ); |
| assign instr_out = (insert_dummy_instr ? dummy_instr_data : instr_decompressed); |
| assign instr_is_compressed_out = (insert_dummy_instr ? 1'b0 : instr_is_compressed); |
| assign illegal_c_instr_out = (insert_dummy_instr ? 1'b0 : illegal_c_insn); |
| assign instr_err_out = (insert_dummy_instr ? 1'b0 : if_instr_err); |
| assign stall_dummy_instr = insert_dummy_instr; |
| always @(posedge clk_i or negedge rst_ni) |
| if (!rst_ni) |
| dummy_instr_id_o <= 1'b0; |
| else if (if_id_pipe_reg_we) |
| dummy_instr_id_o <= insert_dummy_instr; |
| end |
| else begin : gen_no_dummy_instr |
| wire unused_dummy_en; |
| wire [2:0] unused_dummy_mask; |
| wire unused_dummy_seed_en; |
| wire [31:0] unused_dummy_seed; |
| assign unused_dummy_en = dummy_instr_en_i; |
| assign unused_dummy_mask = dummy_instr_mask_i; |
| assign unused_dummy_seed_en = dummy_instr_seed_en_i; |
| assign unused_dummy_seed = dummy_instr_seed_i; |
| assign instr_out = instr_decompressed; |
| assign instr_is_compressed_out = instr_is_compressed; |
| assign illegal_c_instr_out = illegal_c_insn; |
| assign instr_err_out = if_instr_err; |
| assign stall_dummy_instr = 1'b0; |
| initial dummy_instr_id_o = 1'b0; |
| end |
| endgenerate |
| assign instr_valid_id_d = ((if_instr_valid & id_in_ready_i) & ~pc_set_i) | (instr_valid_id_q & ~instr_valid_clear_i); |
| assign instr_new_id_d = if_instr_valid & id_in_ready_i; |
| always @(posedge clk_i or negedge rst_ni) |
| if (!rst_ni) begin |
| instr_valid_id_q <= 1'b0; |
| instr_new_id_q <= 1'b0; |
| end |
| else begin |
| instr_valid_id_q <= instr_valid_id_d; |
| instr_new_id_q <= instr_new_id_d; |
| end |
| assign instr_valid_id_o = instr_valid_id_q; |
| assign instr_new_id_o = instr_new_id_q; |
| assign if_id_pipe_reg_we = instr_new_id_d; |
| always @(posedge clk_i) |
| if (if_id_pipe_reg_we) begin |
| instr_rdata_id_o <= instr_out; |
| instr_rdata_alu_id_o <= instr_out; |
| instr_fetch_err_o <= instr_err_out; |
| instr_fetch_err_plus2_o <= fetch_err_plus2; |
| instr_rdata_c_id_o <= if_instr_rdata[15:0]; |
| instr_is_compressed_id_o <= instr_is_compressed_out; |
| illegal_c_insn_id_o <= illegal_c_instr_out; |
| pc_id_o <= pc_if_o; |
| end |
| generate |
| if (PCIncrCheck) begin : g_secure_pc |
| wire [31:0] prev_instr_addr_incr; |
| reg prev_instr_seq_q; |
| wire prev_instr_seq_d; |
| assign prev_instr_seq_d = ((prev_instr_seq_q | instr_new_id_d) & ~branch_req) & ~stall_dummy_instr; |
| always @(posedge clk_i or negedge rst_ni) |
| if (!rst_ni) |
| prev_instr_seq_q <= 1'b0; |
| else |
| prev_instr_seq_q <= prev_instr_seq_d; |
| assign prev_instr_addr_incr = pc_id_o + (instr_is_compressed_id_o && !instr_fetch_err_o ? 32'd2 : 32'd4); |
| assign pc_mismatch_alert_o = prev_instr_seq_q & (pc_if_o != prev_instr_addr_incr); |
| end |
| else begin : g_no_secure_pc |
| assign pc_mismatch_alert_o = 1'b0; |
| end |
| endgenerate |
| generate |
| if (BranchPredictor) begin : g_branch_predictor |
| reg [31:0] instr_skid_data_q; |
| reg [31:0] instr_skid_addr_q; |
| reg instr_skid_bp_taken_q; |
| reg instr_skid_valid_q; |
| wire instr_skid_valid_d; |
| wire instr_skid_en; |
| reg instr_bp_taken_q; |
| wire instr_bp_taken_d; |
| wire predict_branch_taken_raw; |
| always @(posedge clk_i) |
| if (if_id_pipe_reg_we) |
| instr_bp_taken_q <= instr_bp_taken_d; |
| assign instr_skid_en = (predicted_branch & ~id_in_ready_i) & ~instr_skid_valid_q; |
| assign instr_skid_valid_d = ((instr_skid_valid_q & ~id_in_ready_i) & ~stall_dummy_instr) | instr_skid_en; |
| always @(posedge clk_i or negedge rst_ni) |
| if (!rst_ni) |
| instr_skid_valid_q <= 1'b0; |
| else |
| instr_skid_valid_q <= instr_skid_valid_d; |
| always @(posedge clk_i) |
| if (instr_skid_en) begin |
| instr_skid_bp_taken_q <= predict_branch_taken; |
| instr_skid_data_q <= fetch_rdata; |
| instr_skid_addr_q <= fetch_addr; |
| end |
| ibex_branch_predict branch_predict_i( |
| .clk_i(clk_i), |
| .rst_ni(rst_ni), |
| .fetch_rdata_i(fetch_rdata), |
| .fetch_pc_i(fetch_addr), |
| .fetch_valid_i(fetch_valid), |
| .predict_branch_taken_o(predict_branch_taken_raw), |
| .predict_branch_pc_o(predict_branch_pc) |
| ); |
| assign predict_branch_taken = (predict_branch_taken_raw & ~instr_skid_valid_q) & ~fetch_err; |
| assign predicted_branch = predict_branch_taken & ~pc_set_i; |
| assign if_instr_valid = fetch_valid | instr_skid_valid_q; |
| assign if_instr_rdata = (instr_skid_valid_q ? instr_skid_data_q : fetch_rdata); |
| assign if_instr_addr = (instr_skid_valid_q ? instr_skid_addr_q : fetch_addr); |
| assign if_instr_err = ~instr_skid_valid_q & fetch_err; |
| assign instr_bp_taken_d = (instr_skid_valid_q ? instr_skid_bp_taken_q : predict_branch_taken); |
| assign fetch_ready = (id_in_ready_i & ~stall_dummy_instr) & ~instr_skid_valid_q; |
| assign instr_bp_taken_o = instr_bp_taken_q; |
| end |
| else begin : g_no_branch_predictor |
| assign instr_bp_taken_o = 1'b0; |
| assign predict_branch_taken = 1'b0; |
| assign predicted_branch = 1'b0; |
| assign predict_branch_pc = 32'b00000000000000000000000000000000; |
| assign if_instr_valid = fetch_valid; |
| assign if_instr_rdata = fetch_rdata; |
| assign if_instr_addr = fetch_addr; |
| assign if_instr_err = fetch_err; |
| assign fetch_ready = id_in_ready_i & ~stall_dummy_instr; |
| end |
| endgenerate |
| endmodule |