| module ibex_id_stage ( |
| clk_i, |
| rst_ni, |
| ctrl_busy_o, |
| illegal_insn_o, |
| instr_valid_i, |
| instr_rdata_i, |
| instr_rdata_alu_i, |
| instr_rdata_c_i, |
| instr_is_compressed_i, |
| instr_bp_taken_i, |
| instr_req_o, |
| instr_first_cycle_id_o, |
| instr_valid_clear_o, |
| id_in_ready_o, |
| icache_inval_o, |
| branch_decision_i, |
| pc_set_o, |
| pc_set_spec_o, |
| pc_mux_o, |
| nt_branch_mispredict_o, |
| exc_pc_mux_o, |
| exc_cause_o, |
| illegal_c_insn_i, |
| instr_fetch_err_i, |
| instr_fetch_err_plus2_i, |
| pc_id_i, |
| ex_valid_i, |
| lsu_resp_valid_i, |
| alu_operator_ex_o, |
| alu_operand_a_ex_o, |
| alu_operand_b_ex_o, |
| imd_val_we_ex_i, |
| imd_val_d_ex_i, |
| imd_val_q_ex_o, |
| bt_a_operand_o, |
| bt_b_operand_o, |
| mult_en_ex_o, |
| div_en_ex_o, |
| mult_sel_ex_o, |
| div_sel_ex_o, |
| multdiv_operator_ex_o, |
| multdiv_signed_mode_ex_o, |
| multdiv_operand_a_ex_o, |
| multdiv_operand_b_ex_o, |
| multdiv_ready_id_o, |
| csr_access_o, |
| csr_op_o, |
| csr_op_en_o, |
| csr_save_if_o, |
| csr_save_id_o, |
| csr_save_wb_o, |
| csr_restore_mret_id_o, |
| csr_restore_dret_id_o, |
| csr_save_cause_o, |
| csr_mtval_o, |
| priv_mode_i, |
| csr_mstatus_tw_i, |
| illegal_csr_insn_i, |
| data_ind_timing_i, |
| lsu_req_o, |
| lsu_we_o, |
| lsu_type_o, |
| lsu_sign_ext_o, |
| lsu_wdata_o, |
| lsu_req_done_i, |
| lsu_addr_incr_req_i, |
| lsu_addr_last_i, |
| csr_mstatus_mie_i, |
| irq_pending_i, |
| irqs_i, |
| irq_nm_i, |
| nmi_mode_o, |
| lsu_load_err_i, |
| lsu_store_err_i, |
| debug_mode_o, |
| debug_cause_o, |
| debug_csr_save_o, |
| debug_req_i, |
| debug_single_step_i, |
| debug_ebreakm_i, |
| debug_ebreaku_i, |
| trigger_match_i, |
| result_ex_i, |
| csr_rdata_i, |
| rf_raddr_a_o, |
| rf_rdata_a_i, |
| rf_raddr_b_o, |
| rf_rdata_b_i, |
| rf_ren_a_o, |
| rf_ren_b_o, |
| rf_waddr_id_o, |
| rf_wdata_id_o, |
| rf_we_id_o, |
| rf_rd_a_wb_match_o, |
| rf_rd_b_wb_match_o, |
| rf_waddr_wb_i, |
| rf_wdata_fwd_wb_i, |
| rf_write_wb_i, |
| en_wb_o, |
| instr_type_wb_o, |
| instr_perf_count_id_o, |
| ready_wb_i, |
| outstanding_load_wb_i, |
| outstanding_store_wb_i, |
| perf_jump_o, |
| perf_branch_o, |
| perf_tbranch_o, |
| perf_dside_wait_o, |
| perf_mul_wait_o, |
| perf_div_wait_o, |
| instr_id_done_o |
| ); |
| parameter [0:0] RV32E = 0; |
| localparam integer ibex_pkg_RV32MFast = 2; |
| parameter integer RV32M = ibex_pkg_RV32MFast; |
| localparam integer ibex_pkg_RV32BNone = 0; |
| parameter integer RV32B = ibex_pkg_RV32BNone; |
| parameter [0:0] DataIndTiming = 1'b0; |
| parameter [0:0] BranchTargetALU = 0; |
| parameter [0:0] SpecBranch = 0; |
| parameter [0:0] WritebackStage = 0; |
| parameter [0:0] BranchPredictor = 0; |
| input wire clk_i; |
| input wire rst_ni; |
| output wire ctrl_busy_o; |
| output wire illegal_insn_o; |
| input wire instr_valid_i; |
| input wire [31:0] instr_rdata_i; |
| input wire [31:0] instr_rdata_alu_i; |
| input wire [15:0] instr_rdata_c_i; |
| input wire instr_is_compressed_i; |
| input wire instr_bp_taken_i; |
| output wire instr_req_o; |
| output wire instr_first_cycle_id_o; |
| output wire instr_valid_clear_o; |
| output wire id_in_ready_o; |
| output wire icache_inval_o; |
| input wire branch_decision_i; |
| output wire pc_set_o; |
| output wire pc_set_spec_o; |
| output wire [2:0] pc_mux_o; |
| output wire nt_branch_mispredict_o; |
| output wire [1:0] exc_pc_mux_o; |
| output wire [5:0] exc_cause_o; |
| input wire illegal_c_insn_i; |
| input wire instr_fetch_err_i; |
| input wire instr_fetch_err_plus2_i; |
| input wire [31:0] pc_id_i; |
| input wire ex_valid_i; |
| input wire lsu_resp_valid_i; |
| output wire [5:0] alu_operator_ex_o; |
| output wire [31:0] alu_operand_a_ex_o; |
| output wire [31:0] alu_operand_b_ex_o; |
| input wire [1:0] imd_val_we_ex_i; |
| input wire [67:0] imd_val_d_ex_i; |
| output wire [67:0] imd_val_q_ex_o; |
| output reg [31:0] bt_a_operand_o; |
| output reg [31:0] bt_b_operand_o; |
| output wire mult_en_ex_o; |
| output wire div_en_ex_o; |
| output wire mult_sel_ex_o; |
| output wire div_sel_ex_o; |
| output wire [1:0] multdiv_operator_ex_o; |
| output wire [1:0] multdiv_signed_mode_ex_o; |
| output wire [31:0] multdiv_operand_a_ex_o; |
| output wire [31:0] multdiv_operand_b_ex_o; |
| output wire multdiv_ready_id_o; |
| output wire csr_access_o; |
| output wire [1:0] csr_op_o; |
| output wire csr_op_en_o; |
| output wire csr_save_if_o; |
| output wire csr_save_id_o; |
| output wire csr_save_wb_o; |
| output wire csr_restore_mret_id_o; |
| output wire csr_restore_dret_id_o; |
| output wire csr_save_cause_o; |
| output wire [31:0] csr_mtval_o; |
| input wire [1:0] priv_mode_i; |
| input wire csr_mstatus_tw_i; |
| input wire illegal_csr_insn_i; |
| input wire data_ind_timing_i; |
| output wire lsu_req_o; |
| output wire lsu_we_o; |
| output wire [1:0] lsu_type_o; |
| output wire lsu_sign_ext_o; |
| output wire [31:0] lsu_wdata_o; |
| input wire lsu_req_done_i; |
| input wire lsu_addr_incr_req_i; |
| input wire [31:0] lsu_addr_last_i; |
| input wire csr_mstatus_mie_i; |
| input wire irq_pending_i; |
| input wire [17:0] irqs_i; |
| input wire irq_nm_i; |
| output wire nmi_mode_o; |
| input wire lsu_load_err_i; |
| input wire lsu_store_err_i; |
| output wire debug_mode_o; |
| output wire [2:0] debug_cause_o; |
| output wire debug_csr_save_o; |
| input wire debug_req_i; |
| input wire debug_single_step_i; |
| input wire debug_ebreakm_i; |
| input wire debug_ebreaku_i; |
| input wire trigger_match_i; |
| input wire [31:0] result_ex_i; |
| input wire [31:0] csr_rdata_i; |
| output wire [4:0] rf_raddr_a_o; |
| input wire [31:0] rf_rdata_a_i; |
| output wire [4:0] rf_raddr_b_o; |
| input wire [31:0] rf_rdata_b_i; |
| output wire rf_ren_a_o; |
| output wire rf_ren_b_o; |
| output wire [4:0] rf_waddr_id_o; |
| output reg [31:0] rf_wdata_id_o; |
| output wire rf_we_id_o; |
| output wire rf_rd_a_wb_match_o; |
| output wire rf_rd_b_wb_match_o; |
| input wire [4:0] rf_waddr_wb_i; |
| input wire [31:0] rf_wdata_fwd_wb_i; |
| input wire rf_write_wb_i; |
| output wire en_wb_o; |
| output wire [1:0] instr_type_wb_o; |
| output wire instr_perf_count_id_o; |
| input wire ready_wb_i; |
| input wire outstanding_load_wb_i; |
| input wire outstanding_store_wb_i; |
| output wire perf_jump_o; |
| output reg perf_branch_o; |
| output wire perf_tbranch_o; |
| output wire perf_dside_wait_o; |
| output wire perf_mul_wait_o; |
| output wire perf_div_wait_o; |
| output wire instr_id_done_o; |
| localparam integer RegFileFF = 0; |
| localparam integer RegFileFPGA = 1; |
| localparam integer RegFileLatch = 2; |
| localparam integer RV32MNone = 0; |
| localparam integer RV32MSlow = 1; |
| localparam integer RV32MFast = 2; |
| localparam integer RV32MSingleCycle = 3; |
| localparam integer RV32BNone = 0; |
| localparam integer RV32BBalanced = 1; |
| localparam integer RV32BFull = 2; |
| localparam [6:0] OPCODE_LOAD = 7'h03; |
| localparam [6:0] OPCODE_MISC_MEM = 7'h0f; |
| localparam [6:0] OPCODE_OP_IMM = 7'h13; |
| localparam [6:0] OPCODE_AUIPC = 7'h17; |
| localparam [6:0] OPCODE_STORE = 7'h23; |
| localparam [6:0] OPCODE_OP = 7'h33; |
| localparam [6:0] OPCODE_LUI = 7'h37; |
| localparam [6:0] OPCODE_BRANCH = 7'h63; |
| localparam [6:0] OPCODE_JALR = 7'h67; |
| localparam [6:0] OPCODE_JAL = 7'h6f; |
| localparam [6:0] OPCODE_SYSTEM = 7'h73; |
| localparam [5:0] ALU_ADD = 0; |
| localparam [5:0] ALU_SUB = 1; |
| localparam [5:0] ALU_XOR = 2; |
| localparam [5:0] ALU_OR = 3; |
| localparam [5:0] ALU_AND = 4; |
| localparam [5:0] ALU_XNOR = 5; |
| localparam [5:0] ALU_ORN = 6; |
| localparam [5:0] ALU_ANDN = 7; |
| localparam [5:0] ALU_SRA = 8; |
| localparam [5:0] ALU_SRL = 9; |
| localparam [5:0] ALU_SLL = 10; |
| localparam [5:0] ALU_SRO = 11; |
| localparam [5:0] ALU_SLO = 12; |
| localparam [5:0] ALU_ROR = 13; |
| localparam [5:0] ALU_ROL = 14; |
| localparam [5:0] ALU_GREV = 15; |
| localparam [5:0] ALU_GORC = 16; |
| localparam [5:0] ALU_SHFL = 17; |
| localparam [5:0] ALU_UNSHFL = 18; |
| localparam [5:0] ALU_LT = 19; |
| localparam [5:0] ALU_LTU = 20; |
| localparam [5:0] ALU_GE = 21; |
| localparam [5:0] ALU_GEU = 22; |
| localparam [5:0] ALU_EQ = 23; |
| localparam [5:0] ALU_NE = 24; |
| localparam [5:0] ALU_MIN = 25; |
| localparam [5:0] ALU_MINU = 26; |
| localparam [5:0] ALU_MAX = 27; |
| localparam [5:0] ALU_MAXU = 28; |
| localparam [5:0] ALU_PACK = 29; |
| localparam [5:0] ALU_PACKU = 30; |
| localparam [5:0] ALU_PACKH = 31; |
| localparam [5:0] ALU_SEXTB = 32; |
| localparam [5:0] ALU_SEXTH = 33; |
| localparam [5:0] ALU_CLZ = 34; |
| localparam [5:0] ALU_CTZ = 35; |
| localparam [5:0] ALU_PCNT = 36; |
| localparam [5:0] ALU_SLT = 37; |
| localparam [5:0] ALU_SLTU = 38; |
| localparam [5:0] ALU_CMOV = 39; |
| localparam [5:0] ALU_CMIX = 40; |
| localparam [5:0] ALU_FSL = 41; |
| localparam [5:0] ALU_FSR = 42; |
| localparam [5:0] ALU_SBSET = 43; |
| localparam [5:0] ALU_SBCLR = 44; |
| localparam [5:0] ALU_SBINV = 45; |
| localparam [5:0] ALU_SBEXT = 46; |
| localparam [5:0] ALU_BEXT = 47; |
| localparam [5:0] ALU_BDEP = 48; |
| localparam [5:0] ALU_BFP = 49; |
| localparam [5:0] ALU_CLMUL = 50; |
| localparam [5:0] ALU_CLMULR = 51; |
| localparam [5:0] ALU_CLMULH = 52; |
| localparam [5:0] ALU_CRC32_B = 53; |
| localparam [5:0] ALU_CRC32C_B = 54; |
| localparam [5:0] ALU_CRC32_H = 55; |
| localparam [5:0] ALU_CRC32C_H = 56; |
| localparam [5:0] ALU_CRC32_W = 57; |
| localparam [5:0] ALU_CRC32C_W = 58; |
| localparam [1:0] MD_OP_MULL = 0; |
| localparam [1:0] MD_OP_MULH = 1; |
| localparam [1:0] MD_OP_DIV = 2; |
| localparam [1:0] MD_OP_REM = 3; |
| localparam [1:0] CSR_OP_READ = 0; |
| localparam [1:0] CSR_OP_WRITE = 1; |
| localparam [1:0] CSR_OP_SET = 2; |
| localparam [1:0] CSR_OP_CLEAR = 3; |
| localparam [1:0] PRIV_LVL_M = 2'b11; |
| localparam [1:0] PRIV_LVL_H = 2'b10; |
| localparam [1:0] PRIV_LVL_S = 2'b01; |
| localparam [1:0] PRIV_LVL_U = 2'b00; |
| localparam [3:0] XDEBUGVER_NO = 4'd0; |
| localparam [3:0] XDEBUGVER_STD = 4'd4; |
| localparam [3:0] XDEBUGVER_NONSTD = 4'd15; |
| localparam [1:0] WB_INSTR_LOAD = 0; |
| localparam [1:0] WB_INSTR_STORE = 1; |
| localparam [1:0] WB_INSTR_OTHER = 2; |
| localparam [1:0] OP_A_REG_A = 0; |
| localparam [1:0] OP_A_FWD = 1; |
| localparam [1:0] OP_A_CURRPC = 2; |
| localparam [1:0] OP_A_IMM = 3; |
| localparam [0:0] IMM_A_Z = 0; |
| localparam [0:0] IMM_A_ZERO = 1; |
| localparam [0:0] OP_B_REG_B = 0; |
| localparam [0:0] OP_B_IMM = 1; |
| localparam [2:0] IMM_B_I = 0; |
| localparam [2:0] IMM_B_S = 1; |
| localparam [2:0] IMM_B_B = 2; |
| localparam [2:0] IMM_B_U = 3; |
| localparam [2:0] IMM_B_J = 4; |
| localparam [2:0] IMM_B_INCR_PC = 5; |
| localparam [2:0] IMM_B_INCR_ADDR = 6; |
| localparam [0:0] RF_WD_EX = 0; |
| localparam [0:0] RF_WD_CSR = 1; |
| localparam [2:0] PC_BOOT = 0; |
| localparam [2:0] PC_JUMP = 1; |
| localparam [2:0] PC_EXC = 2; |
| localparam [2:0] PC_ERET = 3; |
| localparam [2:0] PC_DRET = 4; |
| localparam [2:0] PC_BP = 5; |
| localparam [1:0] EXC_PC_EXC = 0; |
| localparam [1:0] EXC_PC_IRQ = 1; |
| localparam [1:0] EXC_PC_DBD = 2; |
| localparam [1:0] EXC_PC_DBG_EXC = 3; |
| localparam [5:0] EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd3}; |
| localparam [5:0] EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd7}; |
| localparam [5:0] EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11}; |
| localparam [5:0] EXC_CAUSE_IRQ_NM = {1'b1, 5'd31}; |
| localparam [5:0] EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd0}; |
| localparam [5:0] EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd1}; |
| localparam [5:0] EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd2}; |
| localparam [5:0] EXC_CAUSE_BREAKPOINT = {1'b0, 5'd3}; |
| localparam [5:0] EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd5}; |
| localparam [5:0] EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd7}; |
| localparam [5:0] EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd8}; |
| localparam [5:0] EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11}; |
| localparam [2:0] DBG_CAUSE_NONE = 3'h0; |
| localparam [2:0] DBG_CAUSE_EBREAK = 3'h1; |
| localparam [2:0] DBG_CAUSE_TRIGGER = 3'h2; |
| localparam [2:0] DBG_CAUSE_HALTREQ = 3'h3; |
| localparam [2:0] DBG_CAUSE_STEP = 3'h4; |
| localparam [31:0] PMP_MAX_REGIONS = 16; |
| localparam [31:0] PMP_CFG_W = 8; |
| localparam [31:0] PMP_I = 0; |
| localparam [31:0] PMP_D = 1; |
| localparam [1:0] PMP_ACC_EXEC = 2'b00; |
| localparam [1:0] PMP_ACC_WRITE = 2'b01; |
| localparam [1:0] PMP_ACC_READ = 2'b10; |
| localparam [1:0] PMP_MODE_OFF = 2'b00; |
| localparam [1:0] PMP_MODE_TOR = 2'b01; |
| localparam [1:0] PMP_MODE_NA4 = 2'b10; |
| localparam [1:0] PMP_MODE_NAPOT = 2'b11; |
| localparam [11:0] CSR_MHARTID = 12'hf14; |
| localparam [11:0] CSR_MSTATUS = 12'h300; |
| localparam [11:0] CSR_MISA = 12'h301; |
| localparam [11:0] CSR_MIE = 12'h304; |
| localparam [11:0] CSR_MTVEC = 12'h305; |
| localparam [11:0] CSR_MSCRATCH = 12'h340; |
| localparam [11:0] CSR_MEPC = 12'h341; |
| localparam [11:0] CSR_MCAUSE = 12'h342; |
| localparam [11:0] CSR_MTVAL = 12'h343; |
| localparam [11:0] CSR_MIP = 12'h344; |
| localparam [11:0] CSR_PMPCFG0 = 12'h3a0; |
| localparam [11:0] CSR_PMPCFG1 = 12'h3a1; |
| localparam [11:0] CSR_PMPCFG2 = 12'h3a2; |
| localparam [11:0] CSR_PMPCFG3 = 12'h3a3; |
| localparam [11:0] CSR_PMPADDR0 = 12'h3b0; |
| localparam [11:0] CSR_PMPADDR1 = 12'h3b1; |
| localparam [11:0] CSR_PMPADDR2 = 12'h3b2; |
| localparam [11:0] CSR_PMPADDR3 = 12'h3b3; |
| localparam [11:0] CSR_PMPADDR4 = 12'h3b4; |
| localparam [11:0] CSR_PMPADDR5 = 12'h3b5; |
| localparam [11:0] CSR_PMPADDR6 = 12'h3b6; |
| localparam [11:0] CSR_PMPADDR7 = 12'h3b7; |
| localparam [11:0] CSR_PMPADDR8 = 12'h3b8; |
| localparam [11:0] CSR_PMPADDR9 = 12'h3b9; |
| localparam [11:0] CSR_PMPADDR10 = 12'h3ba; |
| localparam [11:0] CSR_PMPADDR11 = 12'h3bb; |
| localparam [11:0] CSR_PMPADDR12 = 12'h3bc; |
| localparam [11:0] CSR_PMPADDR13 = 12'h3bd; |
| localparam [11:0] CSR_PMPADDR14 = 12'h3be; |
| localparam [11:0] CSR_PMPADDR15 = 12'h3bf; |
| localparam [11:0] CSR_TSELECT = 12'h7a0; |
| localparam [11:0] CSR_TDATA1 = 12'h7a1; |
| localparam [11:0] CSR_TDATA2 = 12'h7a2; |
| localparam [11:0] CSR_TDATA3 = 12'h7a3; |
| localparam [11:0] CSR_MCONTEXT = 12'h7a8; |
| localparam [11:0] CSR_SCONTEXT = 12'h7aa; |
| localparam [11:0] CSR_DCSR = 12'h7b0; |
| localparam [11:0] CSR_DPC = 12'h7b1; |
| localparam [11:0] CSR_DSCRATCH0 = 12'h7b2; |
| localparam [11:0] CSR_DSCRATCH1 = 12'h7b3; |
| localparam [11:0] CSR_MCOUNTINHIBIT = 12'h320; |
| localparam [11:0] CSR_MHPMEVENT3 = 12'h323; |
| localparam [11:0] CSR_MHPMEVENT4 = 12'h324; |
| localparam [11:0] CSR_MHPMEVENT5 = 12'h325; |
| localparam [11:0] CSR_MHPMEVENT6 = 12'h326; |
| localparam [11:0] CSR_MHPMEVENT7 = 12'h327; |
| localparam [11:0] CSR_MHPMEVENT8 = 12'h328; |
| localparam [11:0] CSR_MHPMEVENT9 = 12'h329; |
| localparam [11:0] CSR_MHPMEVENT10 = 12'h32a; |
| localparam [11:0] CSR_MHPMEVENT11 = 12'h32b; |
| localparam [11:0] CSR_MHPMEVENT12 = 12'h32c; |
| localparam [11:0] CSR_MHPMEVENT13 = 12'h32d; |
| localparam [11:0] CSR_MHPMEVENT14 = 12'h32e; |
| localparam [11:0] CSR_MHPMEVENT15 = 12'h32f; |
| localparam [11:0] CSR_MHPMEVENT16 = 12'h330; |
| localparam [11:0] CSR_MHPMEVENT17 = 12'h331; |
| localparam [11:0] CSR_MHPMEVENT18 = 12'h332; |
| localparam [11:0] CSR_MHPMEVENT19 = 12'h333; |
| localparam [11:0] CSR_MHPMEVENT20 = 12'h334; |
| localparam [11:0] CSR_MHPMEVENT21 = 12'h335; |
| localparam [11:0] CSR_MHPMEVENT22 = 12'h336; |
| localparam [11:0] CSR_MHPMEVENT23 = 12'h337; |
| localparam [11:0] CSR_MHPMEVENT24 = 12'h338; |
| localparam [11:0] CSR_MHPMEVENT25 = 12'h339; |
| localparam [11:0] CSR_MHPMEVENT26 = 12'h33a; |
| localparam [11:0] CSR_MHPMEVENT27 = 12'h33b; |
| localparam [11:0] CSR_MHPMEVENT28 = 12'h33c; |
| localparam [11:0] CSR_MHPMEVENT29 = 12'h33d; |
| localparam [11:0] CSR_MHPMEVENT30 = 12'h33e; |
| localparam [11:0] CSR_MHPMEVENT31 = 12'h33f; |
| localparam [11:0] CSR_MCYCLE = 12'hb00; |
| localparam [11:0] CSR_MINSTRET = 12'hb02; |
| localparam [11:0] CSR_MHPMCOUNTER3 = 12'hb03; |
| localparam [11:0] CSR_MHPMCOUNTER4 = 12'hb04; |
| localparam [11:0] CSR_MHPMCOUNTER5 = 12'hb05; |
| localparam [11:0] CSR_MHPMCOUNTER6 = 12'hb06; |
| localparam [11:0] CSR_MHPMCOUNTER7 = 12'hb07; |
| localparam [11:0] CSR_MHPMCOUNTER8 = 12'hb08; |
| localparam [11:0] CSR_MHPMCOUNTER9 = 12'hb09; |
| localparam [11:0] CSR_MHPMCOUNTER10 = 12'hb0a; |
| localparam [11:0] CSR_MHPMCOUNTER11 = 12'hb0b; |
| localparam [11:0] CSR_MHPMCOUNTER12 = 12'hb0c; |
| localparam [11:0] CSR_MHPMCOUNTER13 = 12'hb0d; |
| localparam [11:0] CSR_MHPMCOUNTER14 = 12'hb0e; |
| localparam [11:0] CSR_MHPMCOUNTER15 = 12'hb0f; |
| localparam [11:0] CSR_MHPMCOUNTER16 = 12'hb10; |
| localparam [11:0] CSR_MHPMCOUNTER17 = 12'hb11; |
| localparam [11:0] CSR_MHPMCOUNTER18 = 12'hb12; |
| localparam [11:0] CSR_MHPMCOUNTER19 = 12'hb13; |
| localparam [11:0] CSR_MHPMCOUNTER20 = 12'hb14; |
| localparam [11:0] CSR_MHPMCOUNTER21 = 12'hb15; |
| localparam [11:0] CSR_MHPMCOUNTER22 = 12'hb16; |
| localparam [11:0] CSR_MHPMCOUNTER23 = 12'hb17; |
| localparam [11:0] CSR_MHPMCOUNTER24 = 12'hb18; |
| localparam [11:0] CSR_MHPMCOUNTER25 = 12'hb19; |
| localparam [11:0] CSR_MHPMCOUNTER26 = 12'hb1a; |
| localparam [11:0] CSR_MHPMCOUNTER27 = 12'hb1b; |
| localparam [11:0] CSR_MHPMCOUNTER28 = 12'hb1c; |
| localparam [11:0] CSR_MHPMCOUNTER29 = 12'hb1d; |
| localparam [11:0] CSR_MHPMCOUNTER30 = 12'hb1e; |
| localparam [11:0] CSR_MHPMCOUNTER31 = 12'hb1f; |
| localparam [11:0] CSR_MCYCLEH = 12'hb80; |
| localparam [11:0] CSR_MINSTRETH = 12'hb82; |
| localparam [11:0] CSR_MHPMCOUNTER3H = 12'hb83; |
| localparam [11:0] CSR_MHPMCOUNTER4H = 12'hb84; |
| localparam [11:0] CSR_MHPMCOUNTER5H = 12'hb85; |
| localparam [11:0] CSR_MHPMCOUNTER6H = 12'hb86; |
| localparam [11:0] CSR_MHPMCOUNTER7H = 12'hb87; |
| localparam [11:0] CSR_MHPMCOUNTER8H = 12'hb88; |
| localparam [11:0] CSR_MHPMCOUNTER9H = 12'hb89; |
| localparam [11:0] CSR_MHPMCOUNTER10H = 12'hb8a; |
| localparam [11:0] CSR_MHPMCOUNTER11H = 12'hb8b; |
| localparam [11:0] CSR_MHPMCOUNTER12H = 12'hb8c; |
| localparam [11:0] CSR_MHPMCOUNTER13H = 12'hb8d; |
| localparam [11:0] CSR_MHPMCOUNTER14H = 12'hb8e; |
| localparam [11:0] CSR_MHPMCOUNTER15H = 12'hb8f; |
| localparam [11:0] CSR_MHPMCOUNTER16H = 12'hb90; |
| localparam [11:0] CSR_MHPMCOUNTER17H = 12'hb91; |
| localparam [11:0] CSR_MHPMCOUNTER18H = 12'hb92; |
| localparam [11:0] CSR_MHPMCOUNTER19H = 12'hb93; |
| localparam [11:0] CSR_MHPMCOUNTER20H = 12'hb94; |
| localparam [11:0] CSR_MHPMCOUNTER21H = 12'hb95; |
| localparam [11:0] CSR_MHPMCOUNTER22H = 12'hb96; |
| localparam [11:0] CSR_MHPMCOUNTER23H = 12'hb97; |
| localparam [11:0] CSR_MHPMCOUNTER24H = 12'hb98; |
| localparam [11:0] CSR_MHPMCOUNTER25H = 12'hb99; |
| localparam [11:0] CSR_MHPMCOUNTER26H = 12'hb9a; |
| localparam [11:0] CSR_MHPMCOUNTER27H = 12'hb9b; |
| localparam [11:0] CSR_MHPMCOUNTER28H = 12'hb9c; |
| localparam [11:0] CSR_MHPMCOUNTER29H = 12'hb9d; |
| localparam [11:0] CSR_MHPMCOUNTER30H = 12'hb9e; |
| localparam [11:0] CSR_MHPMCOUNTER31H = 12'hb9f; |
| localparam [11:0] CSR_CPUCTRL = 12'h7c0; |
| localparam [11:0] CSR_SECURESEED = 12'h7c1; |
| localparam [11:0] CSR_OFF_PMP_CFG = 12'h3a0; |
| localparam [11:0] CSR_OFF_PMP_ADDR = 12'h3b0; |
| localparam [31:0] CSR_MSTATUS_MIE_BIT = 3; |
| localparam [31:0] CSR_MSTATUS_MPIE_BIT = 7; |
| localparam [31:0] CSR_MSTATUS_MPP_BIT_LOW = 11; |
| localparam [31:0] CSR_MSTATUS_MPP_BIT_HIGH = 12; |
| localparam [31:0] CSR_MSTATUS_MPRV_BIT = 17; |
| localparam [31:0] CSR_MSTATUS_TW_BIT = 21; |
| localparam [1:0] CSR_MISA_MXL = 2'd1; |
| localparam [31:0] CSR_MSIX_BIT = 3; |
| localparam [31:0] CSR_MTIX_BIT = 7; |
| localparam [31:0] CSR_MEIX_BIT = 11; |
| localparam [31:0] CSR_MFIX_BIT_LOW = 16; |
| localparam [31:0] CSR_MFIX_BIT_HIGH = 30; |
| wire illegal_insn_dec; |
| wire ebrk_insn; |
| wire mret_insn_dec; |
| wire dret_insn_dec; |
| wire ecall_insn_dec; |
| wire wfi_insn_dec; |
| wire wb_exception; |
| wire branch_in_dec; |
| reg branch_spec; |
| wire branch_set_spec; |
| wire branch_set; |
| reg branch_set_d; |
| reg branch_not_set; |
| wire branch_taken; |
| wire jump_in_dec; |
| wire jump_set_dec; |
| reg jump_set; |
| wire instr_first_cycle; |
| wire instr_executing; |
| wire instr_done; |
| wire controller_run; |
| wire stall_ld_hz; |
| wire stall_mem; |
| reg stall_multdiv; |
| reg stall_branch; |
| reg stall_jump; |
| wire stall_id; |
| wire stall_wb; |
| wire flush_id; |
| wire multicycle_done; |
| wire [31:0] imm_i_type; |
| wire [31:0] imm_s_type; |
| wire [31:0] imm_b_type; |
| wire [31:0] imm_u_type; |
| wire [31:0] imm_j_type; |
| wire [31:0] zimm_rs1_type; |
| wire [31:0] imm_a; |
| reg [31:0] imm_b; |
| wire rf_wdata_sel; |
| wire rf_we_dec; |
| reg rf_we_raw; |
| wire rf_ren_a; |
| wire rf_ren_b; |
| assign rf_ren_a_o = rf_ren_a; |
| assign rf_ren_b_o = rf_ren_b; |
| wire [31:0] rf_rdata_a_fwd; |
| wire [31:0] rf_rdata_b_fwd; |
| wire [5:0] alu_operator; |
| wire [1:0] alu_op_a_mux_sel; |
| wire [1:0] alu_op_a_mux_sel_dec; |
| wire alu_op_b_mux_sel; |
| wire alu_op_b_mux_sel_dec; |
| wire alu_multicycle_dec; |
| reg stall_alu; |
| reg [67:0] imd_val_q; |
| wire [1:0] bt_a_mux_sel; |
| wire [2:0] bt_b_mux_sel; |
| wire imm_a_mux_sel; |
| wire [2:0] imm_b_mux_sel; |
| wire [2:0] imm_b_mux_sel_dec; |
| wire mult_en_id; |
| wire mult_en_dec; |
| wire div_en_id; |
| wire div_en_dec; |
| wire multdiv_en_dec; |
| wire [1:0] multdiv_operator; |
| wire [1:0] multdiv_signed_mode; |
| wire lsu_we; |
| wire [1:0] lsu_type; |
| wire lsu_sign_ext; |
| wire lsu_req; |
| wire lsu_req_dec; |
| wire data_req_allowed; |
| reg csr_pipe_flush; |
| reg [31:0] alu_operand_a; |
| wire [31:0] alu_operand_b; |
| assign alu_op_a_mux_sel = (lsu_addr_incr_req_i ? OP_A_FWD : alu_op_a_mux_sel_dec); |
| assign alu_op_b_mux_sel = (lsu_addr_incr_req_i ? OP_B_IMM : alu_op_b_mux_sel_dec); |
| assign imm_b_mux_sel = (lsu_addr_incr_req_i ? IMM_B_INCR_ADDR : imm_b_mux_sel_dec); |
| assign imm_a = (imm_a_mux_sel == IMM_A_Z ? zimm_rs1_type : {32 {1'sb0}}); |
| always @(*) begin : alu_operand_a_mux |
| case (alu_op_a_mux_sel) |
| OP_A_REG_A: alu_operand_a = rf_rdata_a_fwd; |
| OP_A_FWD: alu_operand_a = lsu_addr_last_i; |
| OP_A_CURRPC: alu_operand_a = pc_id_i; |
| OP_A_IMM: alu_operand_a = imm_a; |
| default: alu_operand_a = pc_id_i; |
| endcase |
| end |
| generate |
| if (BranchTargetALU) begin : g_btalu_muxes |
| always @(*) begin : bt_operand_a_mux |
| case (bt_a_mux_sel) |
| OP_A_REG_A: bt_a_operand_o = rf_rdata_a_fwd; |
| OP_A_CURRPC: bt_a_operand_o = pc_id_i; |
| default: bt_a_operand_o = pc_id_i; |
| endcase |
| end |
| always @(*) begin : bt_immediate_b_mux |
| case (bt_b_mux_sel) |
| IMM_B_I: bt_b_operand_o = imm_i_type; |
| IMM_B_B: bt_b_operand_o = imm_b_type; |
| IMM_B_J: bt_b_operand_o = imm_j_type; |
| IMM_B_INCR_PC: bt_b_operand_o = (instr_is_compressed_i ? 32'h00000002 : 32'h00000004); |
| default: bt_b_operand_o = (instr_is_compressed_i ? 32'h00000002 : 32'h00000004); |
| endcase |
| end |
| always @(*) begin : immediate_b_mux |
| case (imm_b_mux_sel) |
| IMM_B_I: imm_b = imm_i_type; |
| IMM_B_S: imm_b = imm_s_type; |
| IMM_B_U: imm_b = imm_u_type; |
| IMM_B_INCR_PC: imm_b = (instr_is_compressed_i ? 32'h00000002 : 32'h00000004); |
| IMM_B_INCR_ADDR: imm_b = 32'h00000004; |
| default: imm_b = 32'h00000004; |
| endcase |
| end |
| end |
| else begin : g_nobtalu |
| wire [1:0] unused_a_mux_sel; |
| wire [2:0] unused_b_mux_sel; |
| assign unused_a_mux_sel = bt_a_mux_sel; |
| assign unused_b_mux_sel = bt_b_mux_sel; |
| initial bt_a_operand_o = {32 {1'sb0}}; |
| initial bt_b_operand_o = {32 {1'sb0}}; |
| always @(*) begin : immediate_b_mux |
| case (imm_b_mux_sel) |
| IMM_B_I: imm_b = imm_i_type; |
| IMM_B_S: imm_b = imm_s_type; |
| IMM_B_B: imm_b = imm_b_type; |
| IMM_B_U: imm_b = imm_u_type; |
| IMM_B_J: imm_b = imm_j_type; |
| IMM_B_INCR_PC: imm_b = (instr_is_compressed_i ? 32'h00000002 : 32'h00000004); |
| IMM_B_INCR_ADDR: imm_b = 32'h00000004; |
| default: imm_b = 32'h00000004; |
| endcase |
| end |
| end |
| endgenerate |
| assign alu_operand_b = (alu_op_b_mux_sel == OP_B_IMM ? imm_b : rf_rdata_b_fwd); |
| generate |
| genvar i; |
| for (i = 0; i < 2; i = i + 1) begin : gen_intermediate_val_reg |
| always @(posedge clk_i or negedge rst_ni) begin : intermediate_val_reg |
| if (!rst_ni) |
| imd_val_q[(1 - i) * 34+:34] <= {34 {1'sb0}}; |
| else if (imd_val_we_ex_i[i]) |
| imd_val_q[(1 - i) * 34+:34] <= imd_val_d_ex_i[(1 - i) * 34+:34]; |
| end |
| end |
| endgenerate |
| assign imd_val_q_ex_o = imd_val_q; |
| assign rf_we_id_o = (rf_we_raw & instr_executing) & ~illegal_csr_insn_i; |
| always @(*) begin : rf_wdata_id_mux |
| case (rf_wdata_sel) |
| RF_WD_EX: rf_wdata_id_o = result_ex_i; |
| RF_WD_CSR: rf_wdata_id_o = csr_rdata_i; |
| default: rf_wdata_id_o = result_ex_i; |
| endcase |
| end |
| ibex_decoder #( |
| .RV32E(RV32E), |
| .RV32M(RV32M), |
| .RV32B(RV32B), |
| .BranchTargetALU(BranchTargetALU) |
| ) decoder_i( |
| .clk_i(clk_i), |
| .rst_ni(rst_ni), |
| .illegal_insn_o(illegal_insn_dec), |
| .ebrk_insn_o(ebrk_insn), |
| .mret_insn_o(mret_insn_dec), |
| .dret_insn_o(dret_insn_dec), |
| .ecall_insn_o(ecall_insn_dec), |
| .wfi_insn_o(wfi_insn_dec), |
| .jump_set_o(jump_set_dec), |
| .branch_taken_i(branch_taken), |
| .icache_inval_o(icache_inval_o), |
| .instr_first_cycle_i(instr_first_cycle), |
| .instr_rdata_i(instr_rdata_i), |
| .instr_rdata_alu_i(instr_rdata_alu_i), |
| .illegal_c_insn_i(illegal_c_insn_i), |
| .imm_a_mux_sel_o(imm_a_mux_sel), |
| .imm_b_mux_sel_o(imm_b_mux_sel_dec), |
| .bt_a_mux_sel_o(bt_a_mux_sel), |
| .bt_b_mux_sel_o(bt_b_mux_sel), |
| .imm_i_type_o(imm_i_type), |
| .imm_s_type_o(imm_s_type), |
| .imm_b_type_o(imm_b_type), |
| .imm_u_type_o(imm_u_type), |
| .imm_j_type_o(imm_j_type), |
| .zimm_rs1_type_o(zimm_rs1_type), |
| .rf_wdata_sel_o(rf_wdata_sel), |
| .rf_we_o(rf_we_dec), |
| .rf_raddr_a_o(rf_raddr_a_o), |
| .rf_raddr_b_o(rf_raddr_b_o), |
| .rf_waddr_o(rf_waddr_id_o), |
| .rf_ren_a_o(rf_ren_a), |
| .rf_ren_b_o(rf_ren_b), |
| .alu_operator_o(alu_operator), |
| .alu_op_a_mux_sel_o(alu_op_a_mux_sel_dec), |
| .alu_op_b_mux_sel_o(alu_op_b_mux_sel_dec), |
| .alu_multicycle_o(alu_multicycle_dec), |
| .mult_en_o(mult_en_dec), |
| .div_en_o(div_en_dec), |
| .mult_sel_o(mult_sel_ex_o), |
| .div_sel_o(div_sel_ex_o), |
| .multdiv_operator_o(multdiv_operator), |
| .multdiv_signed_mode_o(multdiv_signed_mode), |
| .csr_access_o(csr_access_o), |
| .csr_op_o(csr_op_o), |
| .data_req_o(lsu_req_dec), |
| .data_we_o(lsu_we), |
| .data_type_o(lsu_type), |
| .data_sign_extension_o(lsu_sign_ext), |
| .jump_in_dec_o(jump_in_dec), |
| .branch_in_dec_o(branch_in_dec) |
| ); |
| function automatic [11:0] sv2v_cast_12; |
| input reg [11:0] inp; |
| sv2v_cast_12 = inp; |
| endfunction |
| always @(*) begin : csr_pipeline_flushes |
| csr_pipe_flush = 1'b0; |
| if ((csr_op_en_o == 1'b1) && ((csr_op_o == CSR_OP_WRITE) || (csr_op_o == CSR_OP_SET))) begin |
| if ((sv2v_cast_12(instr_rdata_i[31:20]) == CSR_MSTATUS) || (sv2v_cast_12(instr_rdata_i[31:20]) == CSR_MIE)) |
| csr_pipe_flush = 1'b1; |
| end |
| else if ((csr_op_en_o == 1'b1) && (csr_op_o != CSR_OP_READ)) |
| if ((((sv2v_cast_12(instr_rdata_i[31:20]) == CSR_DCSR) || (sv2v_cast_12(instr_rdata_i[31:20]) == CSR_DPC)) || (sv2v_cast_12(instr_rdata_i[31:20]) == CSR_DSCRATCH0)) || (sv2v_cast_12(instr_rdata_i[31:20]) == CSR_DSCRATCH1)) |
| csr_pipe_flush = 1'b1; |
| end |
| assign illegal_insn_o = instr_valid_i & (illegal_insn_dec | illegal_csr_insn_i); |
| ibex_controller #( |
| .WritebackStage(WritebackStage), |
| .BranchPredictor(BranchPredictor) |
| ) controller_i( |
| .clk_i(clk_i), |
| .rst_ni(rst_ni), |
| .ctrl_busy_o(ctrl_busy_o), |
| .illegal_insn_i(illegal_insn_o), |
| .ecall_insn_i(ecall_insn_dec), |
| .mret_insn_i(mret_insn_dec), |
| .dret_insn_i(dret_insn_dec), |
| .wfi_insn_i(wfi_insn_dec), |
| .ebrk_insn_i(ebrk_insn), |
| .csr_pipe_flush_i(csr_pipe_flush), |
| .instr_valid_i(instr_valid_i), |
| .instr_i(instr_rdata_i), |
| .instr_compressed_i(instr_rdata_c_i), |
| .instr_is_compressed_i(instr_is_compressed_i), |
| .instr_bp_taken_i(instr_bp_taken_i), |
| .instr_fetch_err_i(instr_fetch_err_i), |
| .instr_fetch_err_plus2_i(instr_fetch_err_plus2_i), |
| .pc_id_i(pc_id_i), |
| .instr_valid_clear_o(instr_valid_clear_o), |
| .id_in_ready_o(id_in_ready_o), |
| .controller_run_o(controller_run), |
| .instr_req_o(instr_req_o), |
| .pc_set_o(pc_set_o), |
| .pc_set_spec_o(pc_set_spec_o), |
| .pc_mux_o(pc_mux_o), |
| .nt_branch_mispredict_o(nt_branch_mispredict_o), |
| .exc_pc_mux_o(exc_pc_mux_o), |
| .exc_cause_o(exc_cause_o), |
| .lsu_addr_last_i(lsu_addr_last_i), |
| .load_err_i(lsu_load_err_i), |
| .store_err_i(lsu_store_err_i), |
| .wb_exception_o(wb_exception), |
| .branch_set_i(branch_set), |
| .branch_set_spec_i(branch_set_spec), |
| .branch_not_set_i(branch_not_set), |
| .jump_set_i(jump_set), |
| .csr_mstatus_mie_i(csr_mstatus_mie_i), |
| .irq_pending_i(irq_pending_i), |
| .irqs_i(irqs_i), |
| .irq_nm_i(irq_nm_i), |
| .nmi_mode_o(nmi_mode_o), |
| .csr_save_if_o(csr_save_if_o), |
| .csr_save_id_o(csr_save_id_o), |
| .csr_save_wb_o(csr_save_wb_o), |
| .csr_restore_mret_id_o(csr_restore_mret_id_o), |
| .csr_restore_dret_id_o(csr_restore_dret_id_o), |
| .csr_save_cause_o(csr_save_cause_o), |
| .csr_mtval_o(csr_mtval_o), |
| .priv_mode_i(priv_mode_i), |
| .csr_mstatus_tw_i(csr_mstatus_tw_i), |
| .debug_mode_o(debug_mode_o), |
| .debug_cause_o(debug_cause_o), |
| .debug_csr_save_o(debug_csr_save_o), |
| .debug_req_i(debug_req_i), |
| .debug_single_step_i(debug_single_step_i), |
| .debug_ebreakm_i(debug_ebreakm_i), |
| .debug_ebreaku_i(debug_ebreaku_i), |
| .trigger_match_i(trigger_match_i), |
| .stall_id_i(stall_id), |
| .stall_wb_i(stall_wb), |
| .flush_id_o(flush_id), |
| .ready_wb_i(ready_wb_i), |
| .perf_jump_o(perf_jump_o), |
| .perf_tbranch_o(perf_tbranch_o) |
| ); |
| assign multdiv_en_dec = mult_en_dec | div_en_dec; |
| assign lsu_req = (instr_executing ? data_req_allowed & lsu_req_dec : 1'b0); |
| assign mult_en_id = (instr_executing ? mult_en_dec : 1'b0); |
| assign div_en_id = (instr_executing ? div_en_dec : 1'b0); |
| assign lsu_req_o = lsu_req; |
| assign lsu_we_o = lsu_we; |
| assign lsu_type_o = lsu_type; |
| assign lsu_sign_ext_o = lsu_sign_ext; |
| assign lsu_wdata_o = rf_rdata_b_fwd; |
| assign csr_op_en_o = (csr_access_o & instr_executing) & instr_id_done_o; |
| assign alu_operator_ex_o = alu_operator; |
| assign alu_operand_a_ex_o = alu_operand_a; |
| assign alu_operand_b_ex_o = alu_operand_b; |
| assign mult_en_ex_o = mult_en_id; |
| assign div_en_ex_o = div_en_id; |
| assign multdiv_operator_ex_o = multdiv_operator; |
| assign multdiv_signed_mode_ex_o = multdiv_signed_mode; |
| assign multdiv_operand_a_ex_o = rf_rdata_a_fwd; |
| assign multdiv_operand_b_ex_o = rf_rdata_b_fwd; |
| generate |
| if (BranchTargetALU && !DataIndTiming) begin : g_branch_set_direct |
| assign branch_set = branch_set_d; |
| assign branch_set_spec = branch_spec; |
| end |
| else begin : g_branch_set_flop |
| reg branch_set_q; |
| always @(posedge clk_i or negedge rst_ni) |
| if (!rst_ni) |
| branch_set_q <= 1'b0; |
| else |
| branch_set_q <= branch_set_d; |
| assign branch_set = (BranchTargetALU && !data_ind_timing_i ? branch_set_d : branch_set_q); |
| assign branch_set_spec = (BranchTargetALU && !data_ind_timing_i ? branch_spec : branch_set_q); |
| end |
| endgenerate |
| generate |
| if (DataIndTiming) begin : g_sec_branch_taken |
| reg branch_taken_q; |
| always @(posedge clk_i or negedge rst_ni) |
| if (!rst_ni) |
| branch_taken_q <= 1'b0; |
| else |
| branch_taken_q <= branch_decision_i; |
| assign branch_taken = ~data_ind_timing_i | branch_taken_q; |
| end |
| else begin : g_nosec_branch_taken |
| assign branch_taken = 1'b1; |
| end |
| endgenerate |
| reg id_fsm_q; |
| reg id_fsm_d; |
| localparam [0:0] FIRST_CYCLE = 0; |
| always @(posedge clk_i or negedge rst_ni) begin : id_pipeline_reg |
| if (!rst_ni) |
| id_fsm_q <= FIRST_CYCLE; |
| else |
| id_fsm_q <= id_fsm_d; |
| end |
| localparam [0:0] MULTI_CYCLE = 1; |
| always @(*) begin |
| id_fsm_d = id_fsm_q; |
| rf_we_raw = rf_we_dec; |
| stall_multdiv = 1'b0; |
| stall_jump = 1'b0; |
| stall_branch = 1'b0; |
| stall_alu = 1'b0; |
| branch_set_d = 1'b0; |
| branch_spec = 1'b0; |
| branch_not_set = 1'b0; |
| jump_set = 1'b0; |
| perf_branch_o = 1'b0; |
| if (instr_executing) |
| case (id_fsm_q) |
| FIRST_CYCLE: |
| case (1'b1) |
| lsu_req_dec: |
| if (!WritebackStage) |
| id_fsm_d = MULTI_CYCLE; |
| else if (~lsu_req_done_i) |
| id_fsm_d = MULTI_CYCLE; |
| multdiv_en_dec: |
| if (~ex_valid_i) begin |
| id_fsm_d = MULTI_CYCLE; |
| rf_we_raw = 1'b0; |
| stall_multdiv = 1'b1; |
| end |
| branch_in_dec: begin |
| id_fsm_d = (data_ind_timing_i || (!BranchTargetALU && branch_decision_i) ? MULTI_CYCLE : FIRST_CYCLE); |
| stall_branch = (~BranchTargetALU & branch_decision_i) | data_ind_timing_i; |
| branch_set_d = branch_decision_i | data_ind_timing_i; |
| if (BranchPredictor) |
| branch_not_set = ~branch_decision_i; |
| branch_spec = (SpecBranch ? 1'b1 : branch_decision_i); |
| perf_branch_o = 1'b1; |
| end |
| jump_in_dec: begin |
| id_fsm_d = (BranchTargetALU ? FIRST_CYCLE : MULTI_CYCLE); |
| stall_jump = ~BranchTargetALU; |
| jump_set = jump_set_dec; |
| end |
| alu_multicycle_dec: begin |
| stall_alu = 1'b1; |
| id_fsm_d = MULTI_CYCLE; |
| rf_we_raw = 1'b0; |
| end |
| default: id_fsm_d = FIRST_CYCLE; |
| endcase |
| MULTI_CYCLE: begin |
| if (multdiv_en_dec) |
| rf_we_raw = rf_we_dec & ex_valid_i; |
| if (multicycle_done & ready_wb_i) |
| id_fsm_d = FIRST_CYCLE; |
| else begin |
| stall_multdiv = multdiv_en_dec; |
| stall_branch = branch_in_dec; |
| stall_jump = jump_in_dec; |
| end |
| end |
| default: id_fsm_d = FIRST_CYCLE; |
| endcase |
| end |
| assign multdiv_ready_id_o = ready_wb_i; |
| assign stall_id = ((((stall_ld_hz | stall_mem) | stall_multdiv) | stall_jump) | stall_branch) | stall_alu; |
| assign instr_done = (~stall_id & ~flush_id) & instr_executing; |
| assign instr_first_cycle = instr_valid_i & (id_fsm_q == FIRST_CYCLE); |
| assign instr_first_cycle_id_o = instr_first_cycle; |
| generate |
| if (WritebackStage) begin : gen_stall_mem |
| wire rf_rd_a_wb_match; |
| wire rf_rd_b_wb_match; |
| wire rf_rd_a_hz; |
| wire rf_rd_b_hz; |
| wire outstanding_memory_access; |
| wire instr_kill; |
| assign multicycle_done = (lsu_req_dec ? ~stall_mem : ex_valid_i); |
| assign outstanding_memory_access = (outstanding_load_wb_i | outstanding_store_wb_i) & ~lsu_resp_valid_i; |
| assign data_req_allowed = ~outstanding_memory_access; |
| assign instr_kill = (instr_fetch_err_i | wb_exception) | ~controller_run; |
| assign instr_executing = ((instr_valid_i & ~instr_kill) & ~stall_ld_hz) & ~outstanding_memory_access; |
| assign stall_mem = instr_valid_i & (outstanding_memory_access | (lsu_req_dec & ~lsu_req_done_i)); |
| assign rf_rd_a_wb_match = (rf_waddr_wb_i == rf_raddr_a_o) & |rf_raddr_a_o; |
| assign rf_rd_b_wb_match = (rf_waddr_wb_i == rf_raddr_b_o) & |rf_raddr_b_o; |
| assign rf_rd_a_wb_match_o = rf_rd_a_wb_match; |
| assign rf_rd_b_wb_match_o = rf_rd_b_wb_match; |
| assign rf_rd_a_hz = rf_rd_a_wb_match & rf_ren_a; |
| assign rf_rd_b_hz = rf_rd_b_wb_match & rf_ren_b; |
| assign rf_rdata_a_fwd = (rf_rd_a_wb_match & rf_write_wb_i ? rf_wdata_fwd_wb_i : rf_rdata_a_i); |
| assign rf_rdata_b_fwd = (rf_rd_b_wb_match & rf_write_wb_i ? rf_wdata_fwd_wb_i : rf_rdata_b_i); |
| assign stall_ld_hz = outstanding_load_wb_i & (rf_rd_a_hz | rf_rd_b_hz); |
| assign instr_type_wb_o = (~lsu_req_dec ? WB_INSTR_OTHER : (lsu_we ? WB_INSTR_STORE : WB_INSTR_LOAD)); |
| assign instr_id_done_o = en_wb_o & ready_wb_i; |
| assign stall_wb = en_wb_o & ~ready_wb_i; |
| assign perf_dside_wait_o = (instr_valid_i & ~instr_kill) & (outstanding_memory_access | stall_ld_hz); |
| end |
| else begin : gen_no_stall_mem |
| assign multicycle_done = (lsu_req_dec ? lsu_resp_valid_i : ex_valid_i); |
| assign data_req_allowed = instr_first_cycle; |
| assign stall_mem = instr_valid_i & (lsu_req_dec & (~lsu_resp_valid_i | instr_first_cycle)); |
| assign stall_ld_hz = 1'b0; |
| assign instr_executing = (instr_valid_i & ~instr_fetch_err_i) & controller_run; |
| assign rf_rdata_a_fwd = rf_rdata_a_i; |
| assign rf_rdata_b_fwd = rf_rdata_b_i; |
| assign rf_rd_a_wb_match_o = 1'b0; |
| assign rf_rd_b_wb_match_o = 1'b0; |
| wire unused_data_req_done_ex; |
| wire [4:0] unused_rf_waddr_wb; |
| wire unused_rf_write_wb; |
| wire unused_outstanding_load_wb; |
| wire unused_outstanding_store_wb; |
| wire unused_wb_exception; |
| wire [31:0] unused_rf_wdata_fwd_wb; |
| assign unused_data_req_done_ex = lsu_req_done_i; |
| assign unused_rf_waddr_wb = rf_waddr_wb_i; |
| assign unused_rf_write_wb = rf_write_wb_i; |
| assign unused_outstanding_load_wb = outstanding_load_wb_i; |
| assign unused_outstanding_store_wb = outstanding_store_wb_i; |
| assign unused_wb_exception = wb_exception; |
| assign unused_rf_wdata_fwd_wb = rf_wdata_fwd_wb_i; |
| assign instr_type_wb_o = WB_INSTR_OTHER; |
| assign stall_wb = 1'b0; |
| assign perf_dside_wait_o = (instr_executing & lsu_req_dec) & ~lsu_resp_valid_i; |
| assign instr_id_done_o = instr_done; |
| end |
| endgenerate |
| assign instr_perf_count_id_o = (((~ebrk_insn & ~ecall_insn_dec) & ~illegal_insn_dec) & ~illegal_csr_insn_i) & ~instr_fetch_err_i; |
| assign en_wb_o = instr_done; |
| assign perf_mul_wait_o = stall_multdiv & mult_en_dec; |
| assign perf_div_wait_o = stall_multdiv & div_en_dec; |
| endmodule |
