Updated scff_test
diff --git a/verilog/dv/caravel/user_proj_example/io_ports_scff_test/io_ports_tb.v b/verilog/dv/caravel/user_proj_example/io_ports_scff_test/io_ports_tb.v
index 3032743..1e3808a 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports_scff_test/io_ports_tb.v
+++ b/verilog/dv/caravel/user_proj_example/io_ports_scff_test/io_ports_tb.v
@@ -24,12 +24,12 @@
`define FPGA_SCANCHAIN_SIZE 1024
`define POWER_UP_TIME_PERIOD 200
+`define SOC_RESET_TIME_PERIOD 2000
`define SOC_SETUP_TIME_PERIOD 200*2001
`define SOC_CLOCK_PERIOD 12.5
-`define FPGA_PROG_CLOCK_PERIOD 12.5
`define FPGA_CLOCK_PERIOD 12.5
-module io_ports;
+module scff_test_post_pnr_caravel_autocheck_top_tb;
reg clock;
reg RSTB;
reg power1, power2;
@@ -52,7 +52,7 @@
reg [0:0] greset;
// ---- Configuration-chain head -----
- reg [0:0] ccff_head;
+ wire [0:0] ccff_head;
// ---- Configuration-chain tail -----
wire [0:0] ccff_tail;
@@ -63,34 +63,33 @@
wire [0:0] IO_ISOL_N;
- // ----- Counters for error checking -----
- integer num_clock_cycles = 0;
- integer num_errors = 0;
- integer num_checked_points = 0;
+ // ----- Counters for error checking -----
+ integer num_clock_cycles = 0;
+ integer num_errors = 0;
+ integer num_checked_points = 0;
// Indicate when SoC setup phase should be finished
reg soc_setup_done = 0;
// Indicate when configuration should be finished
- reg config_done = 0;
+ reg scan_done = 0;
initial
begin
- config_done = 1'b0;
+ scan_done = 1'b0;
soc_setup_done = 1'b0;
end
-// Indicate when configuration should be finished
-reg scan_done = 0;
+ // ----- Begin raw programming clock signal generation -----
+ initial
+ begin
+ prog_clock_reg[0] = 1'b0;
+ end
+ // ----- End raw programming clock signal generation -----
-initial
- begin
- scan_done = 1'b0;
- end
-
- initial
+ // ----- Begin raw operating clock signal generation -----
+ initial
begin
op_clock_reg[0] = 1'b0;
- prog_clock_reg[0] = 1'b0;
end
always
begin
@@ -118,29 +117,13 @@
end
// ----- End operating reset signal generation -----
- // ----- Begin programming reset signal generation -----
- initial
- begin
- prog_reset[0] = 1'b1;
- #(`SOC_SETUP_TIME_PERIOD + 2 * `FPGA_PROG_CLOCK_PERIOD) prog_reset[0] = 1'b0;
- end
-
- // ----- End programming reset signal generation -----
-
- // ----- Begin operating reset signal generation -----
- // ----- Reset signal is disabled always -----
- initial
- begin
- greset[0] = 1'b1;
- end
- // ----- End operating reset signal generation -----
-
// ----- Begin connecting global ports of FPGA fabric to stimuli -----
assign op_clk[0] = op_clock[0];
assign prog_clk[0] = prog_clock[0];
assign pReset[0] = ~prog_reset[0];
assign Reset[0] = ~greset[0];
- assign Test_en[0] = ~greset;
+ assign Test_en[0] = ~greset;
+ assign ccff_head[0] = 1'b0;
assign IO_ISOL_N[0] = ~greset;
// ----- End connecting global ports of FPGA fabric to stimuli -----
@@ -154,8 +137,6 @@
assign mprj_io[36] = op_clk;
assign mprj_io[37] = prog_clk;
- // ----- End connecting global ports of FPGA fabric to stimuli -----
- // ----- FPGA top-level module to be capsulated -----
assign sc_tail = mprj_io[11];
assign ccff_tail = mprj_io[35];
@@ -163,48 +144,49 @@
assign mprj_io[24:13] = {12{1'b0}};
assign mprj_io[34:27] = {8{1'b0}};
- // Generate a pulse after operating reset is disabled (in the 2nd clock
- // cycle). Then the head of scan chain should be always zero
- always @(negedge op_clock[0]) begin
- sc_head = 1'b1;
- if (0 != num_clock_cycles) begin
- sc_head = 1'b0;
- end
+// Generate a pulse after operating reset is disabled (in the 2nd clock
+// cycle). Then the head of scan chain should be always zero
+ always @(negedge op_clock[0]) begin
+ sc_head = 1'b1;
+ if (0 != num_clock_cycles) begin
+ sc_head = 1'b0;
+ end
+ end
+
+// ----- Count the number of programming cycles -------
+ always @(posedge op_clock[0]) begin
+ num_clock_cycles = num_clock_cycles + 1;
+ // Indicate when scan chain loading is suppose to end
+ if (`FPGA_SCANCHAIN_SIZE + 1 == num_clock_cycles) begin
+ scan_done = 1'b1;
end
- // ----- Count the number of programming cycles -------
- always @(posedge op_clock[0]) begin
- num_clock_cycles = num_clock_cycles + 1;
- // Indicate when scan chain loading is suppose to end
- if (`FPGA_SCANCHAIN_SIZE + 1 == num_clock_cycles) begin
- scan_done = 1'b1;
+ // Check the tail of scan-chain when configuration is done
+ if (1'b1 == scan_done) begin
+ // The tail should spit a pulse after configuration is done
+ // So it should be at logic '1' and then pulled down to logic '0'
+ if (0 == num_checked_points) begin
+ if (sc_tail !== 1'b1) begin
+ $display("Error: sc_tail = %b", sc_tail);
+ num_errors = num_errors + 1;
end
+ end
+ if (1 <= num_checked_points) begin
+ if (sc_tail !== 1'b0) begin
+ $display("Error: sc_tail = %b", sc_tail);
+ num_errors = num_errors + 1;
+ end
+ end
+ num_checked_points = num_checked_points + 1;
+ end
- // Check the tail of scan-chain when configuration is done
- if (1'b1 == scan_done) begin
- // The tail should spit a pulse after configuration is done
- // So it should be at logic '1' and then pulled down to logic '0'
- if (0 == num_checked_points) begin
- if (sc_tail !== 1'b1) begin
- $display("Error: sc_tail = %b", sc_tail);
- num_errors = num_errors + 1;
- end
- end
- if (1 <= num_checked_points) begin
- if (sc_tail !== 1'b0) begin
- $display("Error: sc_tail = %b", sc_tail);
- num_errors = num_errors + 1;
- end
- end
- num_checked_points = num_checked_points + 1;
- end
+ if (2 < num_checked_points) begin
+ $display("Simulation finish with %d errors", num_errors);
- if (2 < num_checked_points) begin
- $display("Simulation finish with %d errors", num_errors);
- // End simulation
- $finish;
- end
- end
+ // End simulation
+ $finish;
+ end
+ end
// External clock is used by default. Make this artificially fast for the
// simulation. Normally this would be a slow clock and the digital PLL
@@ -219,23 +201,11 @@
initial begin
RSTB <= 1'b0;
soc_setup_done <= 1'b1;
- #(`SOC_SETUP_TIME_PERIOD);
+ #(`SOC_RESET_TIME_PERIOD);
RSTB <= 1'b1; // Release reset
soc_setup_done <= 1'b1; // We can start scff test
end
- initial begin
- $dumpfile("io_ports.vcd");
- $dumpvars(0, io_ports);
- repeat (10) begin
- repeat (`FPGA_SCANCHAIN_SIZE + 1) @(posedge op_clock);
- end
- $display("%c[1;31m",27);
- $display ("Monitor: Timeout, Test Mega-Project IO (scff_test) Failed");
- $display("%c[0m",27);
- $finish;
- end
-
initial begin // Power-up sequence
power1 <= 1'b0;
power2 <= 1'b0;
@@ -263,7 +233,6 @@
wire VSS = 1'b0;
caravel uut (
-
.vddio (VDD3V3),
.vssio (VSS),
.vdda (VDD3V3),
