| caldrc-put: caravel_0001001e.gds 2e753679d8fc69bdf1c742532abfa647ef75dfa5 2021-01-21.08:25:50.UTC md5=a4745abc5e7fdb89cc6df3069f3c6e69 /mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/gds/caravel_0001001e.gds.gz [no-git-push] |
| caldrc-put: caravel_0001001e.gds 6c28895256952f957ae9d81d1be6ccdd4dc8effb 2021-01-22.08:40:03.UTC md5=a4745abc5e7fdb89cc6df3069f3c6e69 /mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/gds/caravel_0001001e.gds.gz [no-git-push] |
| caldrc-put: caravel_0001001e.gds a33639512f10f7c2b875773948f0251646357ffb 2021-01-23.03:59:51.UTC md5=264fcc9b81be069099c6a62515f10640 /mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/gds/caravel_0001001e.gds.gz [no-git-push] |
| caldrc-post: caravel_0001001e.gds put=a336395 2021-01-23.05:55:42.UTC md5=(no-gds-file) output423_pdk79-ge1e7d3aa3_drc344-g4be006c_prj342-ga336395_caravel_0001001e |
| caldrc-put: caravel_0001001e.gds f495c2e9221d0aa944a2204f48cd03c9958b32dc 2021-01-29.06:10:38.UTC md5=4f93fffbe1c9567a641b6fb77d87880c /mnt/share/open_mpw/shuttle/slot-030/Caravel-OpenFPGA-EF/gds/caravel_0001001e.gds.gz [no-git-push] |
| caldrc-post: caravel_0001001e.gds put=f495c2e 2021-01-29.22:26:31.UTC md5=(no-gds-file) output458_pdk79-ge1e7d3aa3_drc379-gd4c995f_prj377-gf495c2e_caravel_0001001e |
| caldrc-post: caravel_0001001e.gds put=f495c2e 2021-01-30.08:43:05.UTC md5=(no-gds-file) output459_pdk79-ge1e7d3aa3_drc380-g81a5dbd_prj377-gf495c2e_caravel_0001001e |
