| ,design,design_name,config,runtime,DIEAREA_mm^2,CellPer_mm^2,(Cell/mm^2)/Core_Util,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/ef/openfpga/openlane/input/user_project_wrapper/,user_project_wrapper,user_project_wrapper,0h16m28s,10.2784,17.70703611457036,35.41407222914072,0,1199.88,182,0,0,0,0,0,0,0,22,0,-1,352880,3012,0.0,0.0,0.0,-0.72,0.0,0.0,0.0,0.0,-18.15,0.0,352828215,0.0,3.85,1.73,0.7,0.0,0.0,156,774,156,774,0,0,0,182,0,0,0,0,0,0,0,0,-1,-1,-1,4694,37810,0,42504,100.0,10.0,10,2,5,50,1,153.6,153.18,0.1,0,sky130_fd_sc_hd,8,4 |
