| //------------------------------------------- |
| // FPGA Synthesizable Verilog Netlist |
| // Description: Verilog modules for pb_type: io |
| // Author: Xifan TANG |
| // Organization: University of Utah |
| // Date: Tue Nov 24 18:04:19 2020 |
| //------------------------------------------- |
| //----- Time scale ----- |
| `timescale 1ns / 1ps |
| |
| // ----- BEGIN Physical programmable logic block Verilog module: io ----- |
| // ----- Verilog module for logical_tile_io_mode_io_ ----- |
| module logical_tile_io_mode_io_(IO_ISOL_N, |
| prog_clk, |
| gfpga_pad_EMBEDDED_IO_HD_SOC_IN, |
| gfpga_pad_EMBEDDED_IO_HD_SOC_OUT, |
| gfpga_pad_EMBEDDED_IO_HD_SOC_DIR, |
| io_outpad, |
| ccff_head, |
| io_inpad, |
| ccff_tail); |
| //----- GLOBAL PORTS ----- |
| input [0:0] IO_ISOL_N; |
| //----- GLOBAL PORTS ----- |
| input [0:0] prog_clk; |
| //----- GPIN PORTS ----- |
| input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN; |
| //----- GPOUT PORTS ----- |
| output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; |
| //----- GPOUT PORTS ----- |
| output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; |
| //----- INPUT PORTS ----- |
| input [0:0] io_outpad; |
| //----- INPUT PORTS ----- |
| input [0:0] ccff_head; |
| //----- OUTPUT PORTS ----- |
| output [0:0] io_inpad; |
| //----- OUTPUT PORTS ----- |
| output [0:0] ccff_tail; |
| |
| //----- BEGIN wire-connection ports ----- |
| wire [0:0] io_outpad; |
| wire [0:0] io_inpad; |
| //----- END wire-connection ports ----- |
| |
| |
| //----- BEGIN Registered ports ----- |
| //----- END Registered ports ----- |
| |
| |
| wire [0:0] direct_interc_1_out; |
| wire [0:0] ltile_phy_iopad_0_iopad_inpad; |
| |
| // ----- BEGIN Local short connections ----- |
| // ----- END Local short connections ----- |
| // ----- BEGIN Local output short connections ----- |
| // ----- END Local output short connections ----- |
| |
| ltile_phy_iopad ltile_phy_iopad_0 ( |
| .IO_ISOL_N(IO_ISOL_N[0]), |
| .prog_clk(prog_clk[0]), |
| .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0]), |
| .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0]), |
| .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0]), |
| .iopad_outpad(direct_interc_1_out[0]), |
| .ccff_head(ccff_head[0]), |
| .iopad_inpad(ltile_phy_iopad_0_iopad_inpad[0]), |
| .ccff_tail(ccff_tail[0])); |
| |
| direct_interc direct_interc_0_ ( |
| .in(ltile_phy_iopad_0_iopad_inpad[0]), |
| .out(io_inpad[0])); |
| |
| direct_interc direct_interc_1_ ( |
| .in(io_outpad[0]), |
| .out(direct_interc_1_out[0])); |
| |
| endmodule |
| // ----- END Verilog module for logical_tile_io_mode_io_ ----- |
| |
| |
| // ----- END Physical programmable logic block Verilog module: io ----- |